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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allyesconfig
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discards 91d42d237 0: update: llvm-linux: 17816
new 0709a344e 0: update: llvm-9f992c238abb34ead73318633da38f80153eef2d: 17816
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-stable-allnoconfig
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from e07bdcfb0e Automatic date update in version.in
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discards 0e285707e 0: update: binutils-gcc-linux: boot
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unknown user pushed a change to branch master
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from f3b2d689fe3 AMDGPU/GlobalISel: RegBankSelect for DS ordered add/swap
new 8af834bc792 AMDGPU: Support GDS atomics
new 0a05eaccbd5 AMDGPU/GFX10: implement ds_ordered_count changes
new b82c63f999a GlobalISel: Implement lower for min/max
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include/llvm/CodeGen/GlobalISel/LegalizerHelper.h | 1 +
include/llvm/IR/IntrinsicsAMDGPU.td | 1 +
lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 36 ++++++
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 17 ++-
lib/Target/AMDGPU/AMDGPUInstructions.td | 21 ++++
lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp | 5 +-
lib/Target/AMDGPU/DSInstructions.td | 88 +++++++-------
lib/Target/AMDGPU/SIISelLowering.cpp | 29 ++++-
lib/Target/AMDGPU/SIInstrInfo.td | 2 +
lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 7 +-
lib/Target/AMDGPU/SIMachineFunctionInfo.h | 5 +
test/CodeGen/AMDGPU/gds-atomic.ll | 128 +++++++++++++++++++++
.../AMDGPU/llvm.amdgcn.ds.ordered.add.gfx10.ll | 23 ++++
.../CodeGen/GlobalISel/LegalizerHelperTest.cpp | 78 +++++++++++++
14 files changed, 386 insertions(+), 55 deletions(-)
create mode 100644 test/CodeGen/AMDGPU/gds-atomic.ll
create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx10.ll
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-next-allnoconfig
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from 01056071c28 Daily bump.
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from e07bdcfb0e Automatic date update in version.in
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bfd/version.h | 2 +-
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discards f3e6e0bc3 0: update: binutils-gcc-linux: boot
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03-build_abe-binutils/console.log | 10749 +++++++--------
04-build_abe-stage1/console.log | 13845 +++++++++----------
05-build_linux/console.log | 615 +-
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unknown user pushed a change to branch master
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from 914425994ea AArch64/GlobalISel: Fix trying to select invalid MIR
new f3b2d689fe3 AMDGPU/GlobalISel: RegBankSelect for DS ordered add/swap
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include/llvm/IR/IntrinsicsAMDGPU.td | 1 +
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 33 +++++++++-
.../regbankselect-amdgcn.ds.ordered.add.mir | 71 ++++++++++++++++++++++
.../regbankselect-amdgcn.ds.ordered.swap.mir | 71 ++++++++++++++++++++++
4 files changed, 174 insertions(+), 2 deletions(-)
create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered. [...]
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