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from 60d7d138646 2019-07-01 Sandra Loosemore <sandra(a)codesourcery.com>
new d9f9a289e04 PR middle-end/64242 * config/sparc/sparc.md (nonlocal_got [...]
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unknown user pushed a change to branch gcc-9-branch
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from bbb9b7ce301 Daily bump.
new 0ea79e478db PR middle-end/64242 * config/sparc/sparc.md (nonlocal_got [...]
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-allmodconfig
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from 01056071c28 Daily bump.
adds 824376db1f2 Daily bump.
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-allmodconfig
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from e07bdcfb0e Automatic date update in version.in
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discards b71c93ab7 0: update: binutils-gcc-linux: all
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unknown user pushed a change to branch master
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from 60235d0ed6b [X86] Add widenSubVector to size in bits helper. NFCI.
new a7bea5605ca AMDGPU/GlobalISel: Try to select VOP3 form of add
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discards 0c80247fe 0: update: llvm-linux: boot
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unknown user pushed a change to branch master
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from 962c2a67ea8 AMDGPU/GlobalISel: Implement select for 32-bit G_ADD
new a1ebca4b3e7 [docs][llvm-readelf] Expand llvm-readelf documentation
new 8d62be14dc5 AMDGPU/GlobalISel: RegBankSelect for readlane/readfirstlane
new 60235d0ed6b [X86] Add widenSubVector to size in bits helper. NFCI.
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.../{llvm-readobj.rst => llvm-readelf.rst} | 231 +++++++--------------
docs/CommandGuide/llvm-readobj.rst | 24 +++
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 75 +++++++
lib/Target/AMDGPU/AMDGPURegisterBankInfo.h | 7 +
lib/Target/X86/X86ISelLowering.cpp | 20 +-
....mir => regbankselect-amdgcn.readfirstlane.mir} | 17 +-
.../GlobalISel/regbankselect-amdgcn.readlane.mir | 71 +++++++
7 files changed, 274 insertions(+), 171 deletions(-)
copy docs/CommandGuide/{llvm-readobj.rst => llvm-readelf.rst} (57%)
copy test/CodeGen/AMDGPU/GlobalISel/{regbankselect-amdgcn.wwm.mir => regbankselect [...]
create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
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