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[PATCH net 1/2] tls: fix handling of zero-length records on the rx_list

by Jakub Kicinski

Each recvmsg() call must process either - only contiguous DATA records (any number of them) - one non-DATA record If the next record has different type than what has already been processed we break out of the main processing loop. If the record has already been decrypted (which may be the case for TLS 1.3 where we don't know type until decryption) we queue the pending record to the rx_list. Next recvmsg() will pick it up from there. Queuing the skb to rx_list after zero-copy decrypt is not possible, since in that case we decrypted directly to the user space buffer, and we don't have an skb to queue (darg.skb points to the ciphertext skb for access to metadata like length). Only data records are allowed zero-copy, and we break the processing loop after each non-data record. So we should never zero-copy and then find out that the record type has changed. The corner case we missed is when the initial record comes from rx_list, and it's zero length. Reported-by: Muhammad Alifa Ramdhan <ramdhan(a)starlabs.sg> Reported-by: Billy Jheng Bing-Jhong <billy(a)starlabs.sg> Fixes: 84c61fe1a75b ("tls: rx: do not use the standard strparser") Reviewed-by: Sabrina Dubroca <sd(a)queasysnail.net> Signed-off-by: Jakub Kicinski <kuba(a)kernel.org> --- net/tls/tls_sw.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/net/tls/tls_sw.c b/net/tls/tls_sw.c index 51c98a007dda..bac65d0d4e3e 100644 --- a/net/tls/tls_sw.c +++ b/net/tls/tls_sw.c @@ -1808,6 +1808,9 @@ int decrypt_skb(struct sock *sk, struct scatterlist *sgout) return tls_decrypt_sg(sk, NULL, sgout, &darg); } +/* All records returned from a recvmsg() call must have the same type. + * 0 is not a valid content type. Use it as "no type reported, yet". + */ static int tls_record_content_type(struct msghdr *msg, struct tls_msg *tlm, u8 *control) { @@ -2051,8 +2054,10 @@ int tls_sw_recvmsg(struct sock *sk, if (err < 0) goto end; + /* process_rx_list() will set @control if it processed any records */ copied = err; - if (len <= copied || (copied && control != TLS_RECORD_TYPE_DATA) || rx_more) + if (len <= copied || rx_more || + (control && control != TLS_RECORD_TYPE_DATA)) goto end; target = sock_rcvlowat(sk, flags & MSG_WAITALL, len); -- 2.50.1

4 months, 2 weeks

[PATCH bpf-next v12 0/2] libbpf: fix USDT SIB argument handling causing unrecognized register error

by Jiawei Zhao

When using GCC on x86-64 to compile an usdt prog with -O1 or higher optimization, the compiler will generate SIB addressing mode for global array and PC-relative addressing mode for global variable, e.g. "1@-96(%rbp,%rax,8)" and "-1@4+t1(%rip)". The current USDT implementation in libbpf cannot parse these two formats, causing `bpf_program__attach_usdt()` to fail with -ENOENT (unrecognized register). This patch series adds support for SIB addressing mode in USDT probes. The main changes include: - add correct handling logic for SIB-addressed arguments in `parse_usdt_arg`. - add an usdt_o2 test case to cover SIB addressing mode. Testing shows that the SIB probe correctly generates 8@(%rcx,%rax,8) argument spec and passes all validation checks. The modification history of this patch series: Change since v1: - refactor the code to make it more readable - modify the commit message to explain why and how Change since v2: - fix the `scale` uninitialized error Change since v3: - force -O2 optimization for usdt.test.o to generate SIB addressing usdt and pass all test cases. Change since v4: - split the patch into two parts, one for the fix and the other for the test Change since v5: - Only enable optimization for x86 architecture to generate SIB addressing usdt argument spec. Change since v6: - Add an usdt_o2 test case to cover SIB addressing mode. - Reinstate the usdt.c test case. Change since v7: - Refactor modifications to __bpf_usdt_arg_spec to avoid increasing its size, achieving better compatibility - Fix some minor code style issues - Refactor the usdt_o2 test case, removing semaphore and adding GCC attribute to force -O2 optimization Change since v8: - Refactor the usdt_o2 test case, using assembly to force SIB addressing mode. Change since v9: - Only enable the usdt_o2 test case on x86_64 and i386 architectures since the SIB addressing mode is only supported on x86_64 and i386. Change since v10: - Replace `__attribute__((optimize("O2")))` with `#pragma GCC optimize("O1")` to fix the issue where the optimized compilation condition works improperly. - Renamed test case usdt_o2 and relevant files name to usdt_o1 in that O1 level optimization is enough to generate SIB addressing usdt argument spec. Change since v11: - Replace `STAP_PROBE1` with `STAP_PROBE_ASM` - Use bit fields instead of bit shifting operations - Merge the usdt_o1 test case into the usdt test case Jiawei Zhao (2): libbpf: fix USDT SIB argument handling causing unrecognized register error selftests/bpf: Enrich subtest_basic_usdt case in selftests to cover SIB handling logic tools/lib/bpf/usdt.bpf.h | 47 ++++++++++++++- tools/lib/bpf/usdt.c | 58 +++++++++++++++++-- tools/testing/selftests/bpf/prog_tests/usdt.c | 30 ++++++++++ tools/testing/selftests/bpf/progs/test_usdt.c | 28 +++++++++ 4 files changed, 156 insertions(+), 7 deletions(-) -- 2.43.0

4 months, 2 weeks

[PATCH 0/5] RISC-V: Add Zilsd/Zclsd support in hwprobe and KVM

by Pincheng Wang

Hi all, This patch series adds support for the recently ratified Zilsd (Load/Store pair instructions) and Zclsd (Compressed Load/Store pair instructions) extensions to the RISC-V Linux kernel. It covers device tree binding,ISA string parsing, hwprobe exposure, KVM guest handling and selftests. Zilsd and Zclsd allow more efficient memory access sequences on RV32. My goal is to enable glibc and other user-space libraries to detect these extensions via hwprobe and make use of them for optimized implementations of common routines. To achieve this, the Linux kernel needs to recognize and expose the availability of these extensions through the device tree bindings, ISA string parsing and hwprobe interfaces. KVM support is also required to correctly virtualize these features for guest environments. The series is structured as follows: - Patch 1: Add device tree bindings documentation for Zilsd and Zclsd - Patch 2: Extend RISC-V ISA extension string parsing to recognize them. - Patch 3: Export Zilsd and Zclsd via riscv_hwprobe - Patch 4: Allow KVM guests to use them. - Patch 5: Add KVM selftests. This series of patches is a preparatory step toward enabling user-space optimizations in glibc that leverage Zilsd and Zclsd, by providing the necessary kernel-side support. Please review, and let me know if any adjustments are needed. Thanks, Pincheng Wang Pincheng Wang (5): dt-bidings: riscv: add Zilsd and Zclsd extension descriptions riscv: add ISA extension parsing for Zilsd and Zclsd riscv: hwprobe: export Zilsd and Zclsd ISA extensions riscv: KVM: allow Zilsd and Zclsd extensions for Guest/VM KVM: riscv: selftests: add Zilsd and Zclsd extension to get-reg-list test Documentation/arch/riscv/hwprobe.rst | 8 ++++ .../devicetree/bindings/riscv/extensions.yaml | 39 +++++++++++++++++++ arch/riscv/include/asm/hwcap.h | 2 + arch/riscv/include/uapi/asm/hwprobe.h | 2 + arch/riscv/include/uapi/asm/kvm.h | 2 + arch/riscv/kernel/cpufeature.c | 24 ++++++++++++ arch/riscv/kernel/sys_hwprobe.c | 2 + arch/riscv/kvm/vcpu_onereg.c | 2 + .../selftests/kvm/riscv/get-reg-list.c | 6 +++ 9 files changed, 87 insertions(+) -- 2.39.5

4 months, 2 weeks

[PATCH v13 00/21] Enable CET Virtualization

by Chao Gao

The FPU support for CET virtualization has already been merged into 6.17-rc1. Building on that, this series introduces Intel CET virtualization support for KVM. Changes in v13 1. Add "arch" and "size" fields to the register ID used in KVM_GET/SET_ONE_REG ioctls 2. Add a kselftest for KVM_GET/SET_ONE_REG ioctls 3. Advertise KVM_CAP_ONE_REG 4. Document how the emulation of SSP MSRs is flawed for 32-bit guests 5. Don't pass-thru MSR_IA32_INT_SSP_TAB and report it as unsupported for 32-bit guests 6. Refine changelog to clarify why CET MSRs are pass-thru'd. 7. Limit SHSTK to 64-bit kernels 8. Retain CET state if L1 doesn't set VM_EXIT_LOAD_CET_STATE 9. Rename a new functions for clarity --- Control-flow Enforcement Technology (CET) is a kind of CPU feature used to prevent Return/CALL/Jump-Oriented Programming (ROP/COP/JOP) attacks. It provides two sub-features(SHSTK,IBT) to defend against ROP/COP/JOP style control-flow subversion attacks. Shadow Stack (SHSTK): A shadow stack is a second stack used exclusively for control transfer operations. The shadow stack is separate from the data/normal stack and can be enabled individually in user and kernel mode. When shadow stack is enabled, CALL pushes the return address on both the data and shadow stack. RET pops the return address from both stacks and compares them. If the return addresses from the two stacks do not match, the processor generates a #CP. Indirect Branch Tracking (IBT): IBT introduces new instruction(ENDBRANCH)to mark valid target addresses of indirect branches (CALL, JMP etc...). If an indirect branch is executed and the next instruction is _not_ an ENDBRANCH, the processor generates a #CP. These instruction behaves as a NOP on platforms that doesn't support CET. CET states management ===================== KVM cooperates with host kernel FPU framework to manage guest CET registers. With CET supervisor mode state support in this series, KVM can save/restore full guest CET xsave-managed states. CET user mode and supervisor mode xstates, i.e., MSR_IA32_{U_CET,PL3_SSP} and MSR_IA32_PL{0,1,2}, depend on host FPU framework to swap guest and host xstates. On VM-Exit, guest CET xstates are saved to guest fpu area and host CET xstates are loaded from task/thread context before vCPU returns to userspace, vice-versa on VM-Entry. See details in kvm_{load,put}_guest_fpu(). CET supervisor mode states are grouped into two categories : XSAVE-managed and non-XSAVE-managed, the former includes MSR_IA32_PL{0,1,2}_SSP and are controlled by CET supervisor mode bit(S_CET bit) in XSS, the later consists of MSR_IA32_S_CET and MSR_IA32_INTR_SSP_TBL. VMX introduces new VMCS fields, {GUEST|HOST}_{S_CET,SSP,INTR_SSP_TABL}, to facilitate guest/host non-XSAVES-managed states. When VMX CET entry/exit load bits are set, guest/host MSR_IA32_{S_CET,INTR_SSP_TBL,SSP} are loaded from equivalent fields at VM-Exit/Entry. With these new fields, such supervisor states require no addtional KVM save/reload actions. Tests ====== This series has successfully passed the basic CET user shadow stack test and kernel IBT test in both L1 and L2 guests. The newly added KVM-unit-tests [2] also passed, and its v11 has been tested with the AMD CET series by John [3]. For your convenience, you can use my WIP QEMU [1] for testing. [1]: https://github.com/gaochaointel/qemu-dev qemu-cet [2]: https://lore.kernel.org/kvm/20250626073459.12990-1-minipli@grsecurity.net/ [3]: https://lore.kernel.org/kvm/aH6CH+x5mCDrvtoz@AUSJOHALLEN.amd.com/ Chao Gao (4): KVM: nVMX: Add consistency checks for CR0.WP and CR4.CET KVM: nVMX: Add consistency checks for CET states KVM: nVMX: Advertise new VM-Entry/Exit control bits for CET state KVM: selftest: Add tests for KVM_{GET,SET}_ONE_REG Sean Christopherson (2): KVM: x86: Report XSS as to-be-saved if there are supported features KVM: x86: Load guest FPU state when access XSAVE-managed MSRs Yang Weijiang (15): KVM: x86: Introduce KVM_{G,S}ET_ONE_REG uAPIs support KVM: x86: Refresh CPUID on write to guest MSR_IA32_XSS KVM: x86: Initialize kvm_caps.supported_xss KVM: x86: Add fault checks for guest CR4.CET setting KVM: x86: Report KVM supported CET MSRs as to-be-saved KVM: VMX: Introduce CET VMCS fields and control bits KVM: x86: Enable guest SSP read/write interface with new uAPIs KVM: VMX: Emulate read and write to CET MSRs KVM: x86: Save and reload SSP to/from SMRAM KVM: VMX: Set up interception for CET MSRs KVM: VMX: Set host constant supervisor states to VMCS fields KVM: x86: Don't emulate instructions guarded by CET KVM: x86: Enable CET virtualization for VMX and advertise to userspace KVM: nVMX: Virtualize NO_HW_ERROR_CODE_CC for L1 event injection to L2 KVM: nVMX: Prepare for enabling CET support for nested guest arch/x86/include/asm/kvm_host.h | 5 +- arch/x86/include/asm/vmx.h | 9 + arch/x86/include/uapi/asm/kvm.h | 24 ++ arch/x86/kvm/cpuid.c | 17 +- arch/x86/kvm/emulate.c | 46 ++- arch/x86/kvm/smm.c | 8 + arch/x86/kvm/smm.h | 2 +- arch/x86/kvm/svm/svm.c | 4 + arch/x86/kvm/vmx/capabilities.h | 9 + arch/x86/kvm/vmx/nested.c | 163 ++++++++++- arch/x86/kvm/vmx/nested.h | 5 + arch/x86/kvm/vmx/vmcs12.c | 6 + arch/x86/kvm/vmx/vmcs12.h | 14 +- arch/x86/kvm/vmx/vmx.c | 84 +++++- arch/x86/kvm/vmx/vmx.h | 9 +- arch/x86/kvm/x86.c | 267 +++++++++++++++++- arch/x86/kvm/x86.h | 61 ++++ tools/arch/x86/include/uapi/asm/kvm.h | 24 ++ tools/testing/selftests/kvm/Makefile.kvm | 1 + .../selftests/kvm/x86/get_set_one_reg.c | 35 +++ 20 files changed, 752 insertions(+), 41 deletions(-) create mode 100644 tools/testing/selftests/kvm/x86/get_set_one_reg.c -- 2.47.3

4 months, 2 weeks

[PATCH] selftests: proc: mark vsyscall strings maybe-unused

by Bala-Vignesh-Reddy

The str_vsyscall_* constants in proc-pid-vm.c triggers -Wunused-const-variable warnings with gcc-13.32 and clang 18.1. Define and apply __maybe_unused locally to suppress the warnings. No functional change Fixes compiler warning: warning: ‘str_vsyscall_*’ defined but not used[-Wunused-const-variable] Signed-off-by: Bala-Vignesh-Reddy <reddybalavignesh9979(a)gmail.com> --- tools/testing/selftests/proc/proc-pid-vm.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/tools/testing/selftests/proc/proc-pid-vm.c b/tools/testing/selftests/proc/proc-pid-vm.c index d04685771952..978cbcb3eb11 100644 --- a/tools/testing/selftests/proc/proc-pid-vm.c +++ b/tools/testing/selftests/proc/proc-pid-vm.c @@ -47,6 +47,10 @@ #include <sys/resource.h> #include <linux/fs.h> +#ifndef __maybe_unused +#define __maybe_unused __attribute__((__unused__)) +#endif + #include "../kselftest.h" static inline long sys_execveat(int dirfd, const char *pathname, char **argv, char **envp, int flags) @@ -218,12 +222,12 @@ static int make_exe(const uint8_t *payload, size_t len) * 2: vsyscall VMA is r-xp vsyscall=emulate */ static volatile int g_vsyscall; -static const char *str_vsyscall; +static const char *str_vsyscall __maybe_unused; -static const char str_vsyscall_0[] = ""; -static const char str_vsyscall_1[] = +static const char str_vsyscall_0[] __maybe_unused = ""; +static const char str_vsyscall_1[] __maybe_unused = "ffffffffff600000-ffffffffff601000 --xp 00000000 00:00 0 [vsyscall]\n"; -static const char str_vsyscall_2[] = +static const char str_vsyscall_2[] __maybe_unused = "ffffffffff600000-ffffffffff601000 r-xp 00000000 00:00 0 [vsyscall]\n"; #ifdef __x86_64__ -- 2.43.0

4 months, 2 weeks

[PATCH v6 24/24] tracing: selftests: Add pKVM trace remote tests

by Vincent Donnefort

Run the trace remote selftests with the pKVM trace remote "hypervisor". Cc: Shuah Khan <skhan(a)linuxfoundation.org> Cc: linux-kselftest(a)vger.kernel.org Signed-off-by: Vincent Donnefort <vdonnefort(a)google.com> diff --git a/tools/testing/selftests/ftrace/test.d/remotes/pkvm/buffer_size.tc b/tools/testing/selftests/ftrace/test.d/remotes/pkvm/buffer_size.tc new file mode 100644 index 000000000000..383ef7a84274 --- /dev/null +++ b/tools/testing/selftests/ftrace/test.d/remotes/pkvm/buffer_size.tc @@ -0,0 +1,10 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# description: Test pkvm hypervisor tracing buffer size + +SOURCE_REMOTE_TEST=1 +. $TEST_DIR/remotes/buffer_size.tc + +set -e +setup_remote "hypervisor" +test_buffer_size diff --git a/tools/testing/selftests/ftrace/test.d/remotes/pkvm/reset.tc b/tools/testing/selftests/ftrace/test.d/remotes/pkvm/reset.tc new file mode 100644 index 000000000000..679e31257d0b --- /dev/null +++ b/tools/testing/selftests/ftrace/test.d/remotes/pkvm/reset.tc @@ -0,0 +1,10 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# description: Test pkvm hypervisor tracing reset + +SOURCE_REMOTE_TEST=1 +. $TEST_DIR/remotes/reset.tc + +set -e +setup_remote "hypervisor" +test_reset diff --git a/tools/testing/selftests/ftrace/test.d/remotes/pkvm/trace_pipe.tc b/tools/testing/selftests/ftrace/test.d/remotes/pkvm/trace_pipe.tc new file mode 100644 index 000000000000..4c77431e884f --- /dev/null +++ b/tools/testing/selftests/ftrace/test.d/remotes/pkvm/trace_pipe.tc @@ -0,0 +1,10 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# description: Test pkvm hypervisor tracing pipe + +SOURCE_REMOTE_TEST=1 +. $TEST_DIR/remotes/trace_pipe.tc + +set -e +setup_remote "hypervisor" +test_trace_pipe diff --git a/tools/testing/selftests/ftrace/test.d/remotes/pkvm/unloading.tc b/tools/testing/selftests/ftrace/test.d/remotes/pkvm/unloading.tc new file mode 100644 index 000000000000..059c7ad1c008 --- /dev/null +++ b/tools/testing/selftests/ftrace/test.d/remotes/pkvm/unloading.tc @@ -0,0 +1,10 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# description: Test pkvm hypervisor tracing buffer unloading + +SOURCE_REMOTE_TEST=1 +. $TEST_DIR/remotes/unloading.tc + +set -e +setup_remote "hypervisor" +test_unloading -- 2.51.0.rc2.233.g662b1ed5c5-goog

4 months, 2 weeks

[PATCHv3 net 0/3] bonding: fix negotiation flapping in 802.3ad passive mode

by Hangbin Liu

This patch fixes unstable LACP negotiation when bonding is configured in passive mode (`lacp_active=off`). Previously, the actor would stop sending LACPDUs after initial negotiation succeeded, leading to the partner timing out and restarting the negotiation cycle. This resulted in continuous LACP state flapping. The fix ensures the passive actor starts sending periodic LACPDUs after receiving the first LACPDU from the partner, in accordance with IEEE 802.1AX-2020 section 6.4.1. v3: a) const bond_params for ad_initialize_port (Paolo Abeni) b) add comment about why we need to sleep in test script (Paolo Abeni) v2: a) Split the patch in to 2 parts. One for lacp_active setting. One for passive mode negotiation flapping issue. (Nikolay Aleksandrov) b) Update fixes tags and some comments (Nikolay Aleksandrov) c) Update selftest to pass on normal kernel (Jakub Kicinski) Hangbin Liu (3): bonding: update LACP activity flag after setting lacp_active bonding: send LACPDUs periodically in passive mode after receiving partner's LACPDU selftests: bonding: add test for passive LACP mode drivers/net/bonding/bond_3ad.c | 67 ++++++++--- drivers/net/bonding/bond_options.c | 1 + include/net/bond_3ad.h | 1 + .../selftests/drivers/net/bonding/Makefile | 3 +- .../drivers/net/bonding/bond_passive_lacp.sh | 105 ++++++++++++++++++ .../selftests/drivers/net/bonding/config | 1 + 6 files changed, 159 insertions(+), 19 deletions(-) create mode 100755 tools/testing/selftests/drivers/net/bonding/bond_passive_lacp.sh -- 2.50.1

4 months, 2 weeks

[PATCH] Fix typo in comment, amd-pstate selftest gitsource script

by Abhishek Jadhav

Signed-off-by: Abhishek Jadhav <abhijadhav.dev(a)gmail.com> --- tools/testing/selftests/amd-pstate/gitsource.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/amd-pstate/gitsource.sh b/tools/testing/selftests/amd-pstate/gitsource.sh index 4cde62f90468..9b7323b1d0a6 100755 --- a/tools/testing/selftests/amd-pstate/gitsource.sh +++ b/tools/testing/selftests/amd-pstate/gitsource.sh @@ -121,7 +121,7 @@ parse_gitsource() en_sum=$(awk 'BEGIN {sum=0};{sum += $1};END {print sum}' $OUTFILE_GIT-energy-$1-$2.log) printf "Gitsource-$1-#$2 power consumption(J): $en_sum\n" | tee -a $OUTFILE_GIT.result - # Permance is the number of run gitsource per second, denoted 1/t, where 1 is the number of run gitsource in t + # Performance is the number of run gitsource per second, denoted 1/t, where 1 is the number of run gitsource in t # seconds. It is well known that P=E/t, where P is power measured in watts(W), E is energy measured in joules(J), # and t is time measured in seconds(s). This means that performance per watt becomes # 1/t 1/t 1 @@ -179,7 +179,7 @@ gather_gitsource() avg_en=$(awk 'BEGIN {sum=0};{sum += $1};END {print sum/'$LOOP_TIMES'}' $OUTFILE_GIT-energy-$1.log) printf "Gitsource-$1 avg power consumption(J): $avg_en\n" | tee -a $OUTFILE_GIT.result - # Permance is the number of run gitsource per second, denoted 1/t, where 1 is the number of run gitsource in t + # Performance is the number of run gitsource per second, denoted 1/t, where 1 is the number of run gitsource in t # seconds. It is well known that P=E/t, where P is power measured in watts(W), E is energy measured in joules(J), # and t is time measured in seconds(s). This means that performance per watt becomes # 1/t 1/t 1 -- 2.50.1

4 months, 2 weeks

[PATCH 0/6] ONE_REG interface for SBI FWFT extension

by Anup Patel

This series adds ONE_REG interface for SBI FWFT extension implemented by KVM RISC-V. This was missed out in accepted SBI FWFT patches for KVM RISC-V. These patches can also be found in the riscv_kvm_fwft_one_reg_v1 branch at: https://github.com/avpatel/linux.git Anup Patel (6): RISC-V: KVM: Set initial value of hedeleg in kvm_arch_vcpu_create() RISC-V: KVM: Introduce feature specific reset for SBI FWFT RISC-V: KVM: Introduce optional ONE_REG callbacks for SBI extensions RISC-V: KVM: Move copy_sbi_ext_reg_indices() to SBI implementation RISC-V: KVM: Implement ONE_REG interface for SBI FWFT state KVM: riscv: selftests: Add SBI FWFT to get-reg-list test arch/riscv/include/asm/kvm_vcpu_sbi.h | 23 +- arch/riscv/include/uapi/asm/kvm.h | 14 ++ arch/riscv/kvm/vcpu.c | 3 +- arch/riscv/kvm/vcpu_onereg.c | 60 +----- arch/riscv/kvm/vcpu_sbi.c | 172 ++++++++++++--- arch/riscv/kvm/vcpu_sbi_fwft.c | 199 ++++++++++++++++-- arch/riscv/kvm/vcpu_sbi_sta.c | 64 ++++-- .../selftests/kvm/riscv/get-reg-list.c | 28 +++ 8 files changed, 436 insertions(+), 127 deletions(-) -- 2.43.0

4 months, 2 weeks

[PATCH] selftests/powerpc: fix typos in tm

by Rakuram Eswaran

Fixed multiple typos in powerpc/tm reported by Codespell Signed-off-by: Rakuram Eswaran <rakuram.e96(a)gmail.com> --- tools/testing/selftests/powerpc/tm/tm-signal-msr-resv.c | 2 +- tools/testing/selftests/powerpc/tm/tm-signal-stack.c | 4 ++-- tools/testing/selftests/powerpc/tm/tm-sigreturn.c | 2 +- tools/testing/selftests/powerpc/tm/tm-tar.c | 2 +- tools/testing/selftests/powerpc/tm/tm-tmspr.c | 2 +- tools/testing/selftests/powerpc/tm/tm-trap.c | 4 ++-- 6 files changed, 8 insertions(+), 8 deletions(-) diff --git a/tools/testing/selftests/powerpc/tm/tm-signal-msr-resv.c b/tools/testing/selftests/powerpc/tm/tm-signal-msr-resv.c index 4a61e9bd12b4..8aee18819603 100644 --- a/tools/testing/selftests/powerpc/tm/tm-signal-msr-resv.c +++ b/tools/testing/selftests/powerpc/tm/tm-signal-msr-resv.c @@ -42,7 +42,7 @@ void signal_usr1(int signum, siginfo_t *info, void *uc) #else ucp->uc_mcontext.uc_regs->gregs[PT_MSR] |= (7ULL); #endif - /* Should segv on return becuase of invalid context */ + /* Should segv on return because of invalid context */ segv_expected = 1; } diff --git a/tools/testing/selftests/powerpc/tm/tm-signal-stack.c b/tools/testing/selftests/powerpc/tm/tm-signal-stack.c index 68807aac8dd3..e793b5d97c48 100644 --- a/tools/testing/selftests/powerpc/tm/tm-signal-stack.c +++ b/tools/testing/selftests/powerpc/tm/tm-signal-stack.c @@ -2,7 +2,7 @@ /* * Copyright 2015, Michael Neuling, IBM Corp. * - * Test the kernel's signal delievery code to ensure that we don't + * Test the kernel's signal delivery code to ensure that we don't * trelaim twice in the kernel signal delivery code. This can happen * if we trigger a signal when in a transaction and the stack pointer * is bogus. @@ -52,7 +52,7 @@ int tm_signal_stack() /* * The flow here is: - * 1) register a signal handler (so signal delievery occurs) + * 1) register a signal handler (so signal delivery occurs) * 2) make stack pointer (r1) = NULL * 3) start transaction * 4) cause segv diff --git a/tools/testing/selftests/powerpc/tm/tm-sigreturn.c b/tools/testing/selftests/powerpc/tm/tm-sigreturn.c index ffe4e5515f33..4dfb25409393 100644 --- a/tools/testing/selftests/powerpc/tm/tm-sigreturn.c +++ b/tools/testing/selftests/powerpc/tm/tm-sigreturn.c @@ -5,7 +5,7 @@ * * Test the kernel's signal returning code to check reclaim is done if the * sigreturn() is called while in a transaction (suspended since active is - * already dropped trough the system call path). + * already dropped through the system call path). * * The kernel must discard the transaction when entering sigreturn, since * restoring the potential TM SPRS from the signal frame is requiring to not be diff --git a/tools/testing/selftests/powerpc/tm/tm-tar.c b/tools/testing/selftests/powerpc/tm/tm-tar.c index f2a9137f3c1e..ea420caa3961 100644 --- a/tools/testing/selftests/powerpc/tm/tm-tar.c +++ b/tools/testing/selftests/powerpc/tm/tm-tar.c @@ -50,7 +50,7 @@ int test_tar(void) "bne 2b;" "tend.;" - /* Transaction sucess! TAR should be 3 */ + /* Transaction success! TAR should be 3 */ "mfspr 7, %[tar];" "ori %[res], 7, 4;" // res = 3|4 = 7 "b 4f;" diff --git a/tools/testing/selftests/powerpc/tm/tm-tmspr.c b/tools/testing/selftests/powerpc/tm/tm-tmspr.c index dd5ddffa28b7..e2c3ae7c9035 100644 --- a/tools/testing/selftests/powerpc/tm/tm-tmspr.c +++ b/tools/testing/selftests/powerpc/tm/tm-tmspr.c @@ -9,7 +9,7 @@ * - TFIAR - stores address of location of transaction failure * - TFHAR - stores address of software failure handler (if transaction * fails) - * - TEXASR - lots of info about the transacion(s) + * - TEXASR - lots of info about the transaction(s) * * (1) create more threads than cpus * (2) in each thread: diff --git a/tools/testing/selftests/powerpc/tm/tm-trap.c b/tools/testing/selftests/powerpc/tm/tm-trap.c index 97cb74768e30..99acb7c78403 100644 --- a/tools/testing/selftests/powerpc/tm/tm-trap.c +++ b/tools/testing/selftests/powerpc/tm/tm-trap.c @@ -91,9 +91,9 @@ void trap_signal_handler(int signo, siginfo_t *si, void *uc) * LE endianness does in effect nothing, instruction (2) * is then executed again as 'trap', generating a second * trap event (note that in that case 'trap' is caught - * not in transacional mode). On te other hand, if after + * not in transactional mode). On the other hand, if after * the return from the signal handler the endianness in- - * advertently flipped, instruction (1) is tread as a + * advertently flipped, instruction (1) is thread as a * branch instruction, i.e. b .+8, hence instruction (3) * and (4) are executed (tbegin.; trap;) and we get sim- * ilaly on the trap signal handler, but now in TM mode. -- 2.43.0

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