- Linux-kselftest-mirror - lists.linaro.org

[PATCH v4 4/4] selftests/resctrl: Fix non-contiguous CBM check for Hygon

by Xiaochen Shen

The resctrl selftest currently fails on Hygon CPUs that always supports non-contiguous CBM, printing the error: "# Hardware and kernel differ on non-contiguous CBM support!" This occurs because the arch_supports_noncont_cat() function lacks vendor detection for Hygon CPUs, preventing proper identification of their non-contiguous CBM capability. Fix this by adding Hygon vendor ID detection to arch_supports_noncont_cat(). Signed-off-by: Xiaochen Shen <shenxiaochen(a)open-hieco.net> Reviewed-by: Reinette Chatre <reinette.chatre(a)intel.com> Reviewed-by: Fenghua Yu <fenghuay(a)nvidia.com> --- tools/testing/selftests/resctrl/cat_test.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/selftests/resctrl/cat_test.c index 94cfdba5308d..f00b622c1460 100644 --- a/tools/testing/selftests/resctrl/cat_test.c +++ b/tools/testing/selftests/resctrl/cat_test.c @@ -290,8 +290,10 @@ static int cat_run_test(const struct resctrl_test *test, const struct user_param static bool arch_supports_noncont_cat(const struct resctrl_test *test) { - /* AMD always supports non-contiguous CBM. */ - if (get_vendor() == ARCH_AMD) + unsigned int vendor_id = get_vendor(); + + /* AMD and Hygon always support non-contiguous CBM. */ + if (vendor_id == ARCH_AMD || vendor_id == ARCH_HYGON) return true; #if defined(__i386__) || defined(__x86_64__) /* arch */ -- 2.47.3

7 hours, 21 minutes

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[PATCH v4 3/4] selftests/resctrl: Add CPU vendor detection for Hygon

by Xiaochen Shen

The resctrl selftest currently fails on Hygon CPUs that support Platform QoS features, printing the error: "# Can not get vendor info..." This occurs because vendor detection is missing for Hygon CPUs. Fix this by extending the CPU vendor detection logic to include Hygon's vendor ID. Signed-off-by: Xiaochen Shen <shenxiaochen(a)open-hieco.net> Reviewed-by: Reinette Chatre <reinette.chatre(a)intel.com> --- tools/testing/selftests/resctrl/resctrl.h | 1 + tools/testing/selftests/resctrl/resctrl_tests.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/tools/testing/selftests/resctrl/resctrl.h b/tools/testing/selftests/resctrl/resctrl.h index 4f9c7d04c98d..afe635b6e48d 100644 --- a/tools/testing/selftests/resctrl/resctrl.h +++ b/tools/testing/selftests/resctrl/resctrl.h @@ -39,6 +39,7 @@ */ #define ARCH_INTEL BIT(0) #define ARCH_AMD BIT(1) +#define ARCH_HYGON BIT(2) #define END_OF_TESTS 1 diff --git a/tools/testing/selftests/resctrl/resctrl_tests.c b/tools/testing/selftests/resctrl/resctrl_tests.c index 980ecf2bcf10..78626bbae976 100644 --- a/tools/testing/selftests/resctrl/resctrl_tests.c +++ b/tools/testing/selftests/resctrl/resctrl_tests.c @@ -50,6 +50,8 @@ static unsigned int detect_vendor(void) vendor_id = ARCH_INTEL; else if (s && !strcmp(s, ": AuthenticAMD\n")) vendor_id = ARCH_AMD; + else if (s && !strcmp(s, ": HygonGenuine\n")) + vendor_id = ARCH_HYGON; fclose(inf); free(res); -- 2.47.3

7 hours, 21 minutes

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[PATCH v4 2/4] selftests/resctrl: Define CPU vendor IDs as bits to match usage

by Xiaochen Shen

The CPU vendor IDs are required to be unique bits because they're used for vendor_specific bitmask in the struct resctrl_test. Consider for example their usage in test_vendor_specific_check(): return get_vendor() & test->vendor_specific However, the definitions of CPU vendor IDs in file resctrl.h is quite subtle as a bitmask value: #define ARCH_INTEL 1 #define ARCH_AMD 2 A clearer and more maintainable approach is to define these CPU vendor IDs using BIT(). This ensures each vendor corresponds to a distinct bit and makes it obvious when adding new vendor IDs. Accordingly, update the return types of detect_vendor() and get_vendor() from 'int' to 'unsigned int' to align with their usage as bitmask values and to prevent potentially risky type conversions. Furthermore, introduce a bool flag 'initialized' to simplify the get_vendor() -> detect_vendor() logic. This ensures the vendor ID is detected only once and resolves the ambiguity of using the same variable 'vendor' both as a value and as a state. Suggested-by: Reinette Chatre <reinette.chatre(a)intel.com> Suggested-by: Fenghua Yu <fenghuay(a)nvidia.com> Signed-off-by: Xiaochen Shen <shenxiaochen(a)open-hieco.net> --- tools/testing/selftests/resctrl/resctrl.h | 7 ++--- .../testing/selftests/resctrl/resctrl_tests.c | 26 +++++++++++++------ 2 files changed, 22 insertions(+), 11 deletions(-) diff --git a/tools/testing/selftests/resctrl/resctrl.h b/tools/testing/selftests/resctrl/resctrl.h index 3c51bdac2dfa..4f9c7d04c98d 100644 --- a/tools/testing/selftests/resctrl/resctrl.h +++ b/tools/testing/selftests/resctrl/resctrl.h @@ -23,6 +23,7 @@ #include <asm/unistd.h> #include <linux/perf_event.h> #include <linux/compiler.h> +#include <linux/bits.h> #include "kselftest.h" #define MB (1024 * 1024) @@ -36,8 +37,8 @@ * Define as bits because they're used for vendor_specific bitmask in * the struct resctrl_test. */ -#define ARCH_INTEL 1 -#define ARCH_AMD 2 +#define ARCH_INTEL BIT(0) +#define ARCH_AMD BIT(1) #define END_OF_TESTS 1 @@ -163,7 +164,7 @@ extern int snc_unreliable; extern char llc_occup_path[1024]; int snc_nodes_per_l3_cache(void); -int get_vendor(void); +unsigned int get_vendor(void); bool check_resctrlfs_support(void); int filter_dmesg(void); int get_domain_id(const char *resource, int cpu_no, int *domain_id); diff --git a/tools/testing/selftests/resctrl/resctrl_tests.c b/tools/testing/selftests/resctrl/resctrl_tests.c index 5154ffd821c4..980ecf2bcf10 100644 --- a/tools/testing/selftests/resctrl/resctrl_tests.c +++ b/tools/testing/selftests/resctrl/resctrl_tests.c @@ -23,16 +23,24 @@ static struct resctrl_test *resctrl_tests[] = { &l2_noncont_cat_test, }; -static int detect_vendor(void) +static unsigned int detect_vendor(void) { - FILE *inf = fopen("/proc/cpuinfo", "r"); - int vendor_id = 0; + FILE *inf; + static unsigned int vendor_id; char *s = NULL; char *res; + static bool initialized; - if (!inf) + if (initialized) return vendor_id; + inf = fopen("/proc/cpuinfo", "r"); + if (!inf) { + vendor_id = 0; + initialized = true; + return vendor_id; + } + res = fgrep(inf, "vendor_id"); if (res) @@ -45,15 +53,17 @@ static int detect_vendor(void) fclose(inf); free(res); + + initialized = true; return vendor_id; } -int get_vendor(void) +unsigned int get_vendor(void) { - static int vendor = -1; + unsigned int vendor; + + vendor = detect_vendor(); - if (vendor == -1) - vendor = detect_vendor(); if (vendor == 0) ksft_print_msg("Can not get vendor info...\n"); -- 2.47.3

7 hours, 21 minutes

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[PATCH v4 1/4] selftests/resctrl: Fix a division by zero error on Hygon

by Xiaochen Shen

Commit a1cd99e700ec ("selftests/resctrl: Adjust effective L3 cache size with SNC enabled") introduced the snc_nodes_per_l3_cache() function to detect the Intel Sub-NUMA Clustering (SNC) feature by comparing #CPUs in node0 with #CPUs sharing LLC with CPU0. The function was designed to return: (1) >1: SNC mode is enabled. (2) 1: SNC mode is not enabled or not supported. However, on certain Hygon CPUs, #CPUs sharing LLC with CPU0 is actually less than #CPUs in node0. This results in snc_nodes_per_l3_cache() returning 0 (calculated as cache_cpus / node_cpus). This leads to a division by zero error in get_cache_size(): *cache_size /= snc_nodes_per_l3_cache(); Causing the resctrl selftest to fail with: "Floating point exception (core dumped)" Fix the issue by ensuring snc_nodes_per_l3_cache() returns 1 when SNC mode is not supported on the platform. Fixes: a1cd99e700ec ("selftests/resctrl: Adjust effective L3 cache size with SNC enabled") Signed-off-by: Xiaochen Shen <shenxiaochen(a)open-hieco.net> Reviewed-by: Reinette Chatre <reinette.chatre(a)intel.com> Reviewed-by: Fenghua Yu <fenghuay(a)nvidia.com> --- tools/testing/selftests/resctrl/resctrlfs.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/tools/testing/selftests/resctrl/resctrlfs.c b/tools/testing/selftests/resctrl/resctrlfs.c index 195f04c4d158..b9c1bfb6cc02 100644 --- a/tools/testing/selftests/resctrl/resctrlfs.c +++ b/tools/testing/selftests/resctrl/resctrlfs.c @@ -243,6 +243,16 @@ int snc_nodes_per_l3_cache(void) } snc_mode = cache_cpus / node_cpus; + /* + * On some platforms (e.g. Hygon), + * cache_cpus < node_cpus, the calculated snc_mode is 0. + * + * Set snc_mode = 1 to indicate that SNC mode is not + * supported on the platform. + */ + if (!snc_mode) + snc_mode = 1; + if (snc_mode > 1) ksft_print_msg("SNC-%d mode discovered.\n", snc_mode); } -- 2.47.3

7 hours, 21 minutes

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[PATCH v4 0/4] selftests/resctrl: Add Hygon CPUs support and bug fixes

by Xiaochen Shen

The resctrl selftest currently exhibits several failures on Hygon CPUs due to missing vendor detection and edge-case handling specific to Hygon's architecture. This patch series addresses three distinct issues: 1. A division-by-zero crash in SNC detection on some platforms (e.g., Hygon). 2. Missing CPU vendor detection, causing the test to fail with "# Can not get vendor info..." on Hygon CPUs. 3. Incorrect handling of non-contiguous CBM support on Hygon CPUs. These changes enable resctrl selftest to run successfully on Hygon CPUs that support Platform QoS features. Maintainer notes: ----------------- Patch 1: selftests/resctrl: Fix a division by zero error on Hygon - This is a candidate for backport with "Fixes:" tag. Patch 2: selftests/resctrl: Define CPU vendor IDs as bits to match usage - This is *not* a candidate for backport since it is an enhancement and preparatory patch for patch 3. Patch 3: selftests/resctrl: Add CPU vendor detection for Hygon Patch 4: selftests/resctrl: Fix non-contiguous CBM check for Hygon - Even though they are fixes they are *not* candidates for backport since they are based on another patch series (x86/resctrl: Fix Platform QoS issues for Hygon) which is in process of being added to resctrl. ----------------- Changelog: v4: - Cover letter: add maintainer notes outlining how these patches to be handled (Reinette). - Re-organize the patch series to move original patch 3 to the beginning of series. The patch order has changed between v3 and v4 (Reinette): v3 -> v4 patch #3 -> patch #1 patch #1 -> patch #2 patch #2 -> patch #3 patch #4 -> patch #4 - Patch 2: 1. Resolve a conflict against latest upstream kernel (Reinette). 2. Fix a nit to maintain the reverse fir ordering of variables in detect_vendor() (Reinette). - Patch 3: add Reviewed-by: Reinette Chatre <reinette.chatre(a)intel.com> - Patch 4: move the maintainer note into the cover letter (Reinette). v3: - Patch 1: 1. Update the return types of detect_vendor() and get_vendor() from 'int' to 'unsigned int' to align with their usage as bitmask values and to prevent potentially risky type conversions (Fenghua). 2. Split the code changes of "define CPU vendor IDs as bits to match usage" from original patch 1 into a separate patch (this patch, suggested by Fenghua and Reinette). 3. Introduce the flag 'initialized' to simplify the get_vendor() -> detect_vendor() logic (Reinette). - Patch 2 (original patch 1): 1. Move the code changes of "define CPU vendor IDs as bits to match usage" into patch 1. - Patch 3 (original patch 2): 1. Fix a nit of code comment for affected platforms (Fenghua). 2. Add Reviewed-by: Fenghua Yu <fenghuay(a)nvidia.com>. - Patch 4 (original patch 3): 1. Fix a nit to avoid calling get_vendor() twice (Fenghua). 2. Add Reviewed-by: Fenghua Yu <fenghuay(a)nvidia.com>. v2: - Patch 1: switch all of the vendor id bitmasks to use BIT() (Reinette) - Patch 2: add Reviewed-by: Reinette Chatre <reinette.chatre(a)intel.com> - Patch 3: add Reviewed-by: Reinette Chatre <reinette.chatre(a)intel.com> add a maintainer note to highlight it is not a candidate for backport (Reinette) Xiaochen Shen (4): selftests/resctrl: Fix a division by zero error on Hygon selftests/resctrl: Define CPU vendor IDs as bits to match usage selftests/resctrl: Add CPU vendor detection for Hygon selftests/resctrl: Fix non-contiguous CBM check for Hygon tools/testing/selftests/resctrl/cat_test.c | 6 ++-- tools/testing/selftests/resctrl/resctrl.h | 8 ++++-- .../testing/selftests/resctrl/resctrl_tests.c | 28 +++++++++++++------ tools/testing/selftests/resctrl/resctrlfs.c | 10 +++++++ 4 files changed, 39 insertions(+), 13 deletions(-) -- 2.47.3

7 hours, 21 minutes

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[PATCH v3 0/1] cpuset: relax the overlap check for cgroup-v2

by Sun Shaojie

In cgroup v2, a mutual overlap check is required when at least one of two cpusets is exclusive. However, this check should be relaxed and limited to cases where both cpusets are exclusive. This patch ensures that for sibling cpusets A1 (exclusive) and B1 (non-exclusive), change B1 cannot affect A1's exclusivity. for example. Assume a machine has 4 CPUs (0-3). root cgroup / \ A1 B1 Case 1: Table 1.1: Before applying the patch Step | A1's prstate | B1'sprstate | #1> echo "0-1" > A1/cpuset.cpus | member | member | #2> echo "root" > A1/cpuset.cpus.partition | root | member | #3> echo "0" > B1/cpuset.cpus | root invalid | member | After step #3, A1 changes from "root" to "root invalid" because its CPUs (0-1) overlap with those requested by B1 (0-3). However, B1 can actually use CPUs 2-3(from B1's parent), so it would be more reasonable for A1 to remain as "root." Table 1.2: After applying the patch Step | A1's prstate | B1'sprstate | #1> echo "0-1" > A1/cpuset.cpus | member | member | #2> echo "root" > A1/cpuset.cpus.partition | root | member | #3> echo "0" > B1/cpuset.cpus | root | member | Case 2: (This situation remains unchanged from before) Table 2.1: Before applying the patch Step | A1's prstate | B1'sprstate | #1> echo "0-1" > A1/cpuset.cpus | member | member | #3> echo "1-2" > B1/cpuset.cpus | member | member | #2> echo "root" > A1/cpuset.cpus.partition | root invalid | member | Table 2.2: After applying the patch Step | A1's prstate | B1'sprstate | #1> echo "0-1" > A1/cpuset.cpus | member | member | #3> echo "1-2" > B1/cpuset.cpus | member | member | #2> echo "root" > A1/cpuset.cpus.partition | root invalid | member | All other cases remain unaffected. For example, cgroup-v1, both A1 and B1 are exclusive or non-exlusive. --- v3 -> v4: - Adjust the test_cpuset_prt.sh test file to align with the current behavior. v2 -> v3: - Ensure compliance with constraints such as cpuset.cpus.exclusive. - Link: https://lore.kernel.org/cgroups/20251113131434.606961-1-sunshaojie@kylinos.… v1 -> v2: - Keeps the current cgroup v1 behavior unchanged - Link: https://lore.kernel.org/cgroups/c8e234f4-2c27-4753-8f39-8ae83197efd3@redhat… --- kernel/cgroup/cpuset-internal.h | 3 ++ kernel/cgroup/cpuset-v1.c | 20 +++++++++ kernel/cgroup/cpuset.c | 43 ++++++++++++++----- .../selftests/cgroup/test_cpuset_prs.sh | 5 ++- 4 files changed, 58 insertions(+), 13 deletions(-) -- 2.25.1

10 hours, 1 minute

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[PATCH bpf-next v3 0/6] Add cryptographic hash and signature verification kfuncs to BPF

by Daniel Hodges

This series extends BPF's cryptographic capabilities by adding kfuncs for SHA hashing and ECDSA signature verification. These functions enable BPF programs to perform cryptographic operations for use cases such as content verification, integrity checking, and data authentication. BPF programs increasingly need to verify data integrity and authenticity in networking, security, and observability contexts. While BPF already supports symmetric encryption/decryption, it lacks support for: 1. Cryptographic hashing - needed for content verification, fingerprinting, and preparing message digests for signature operations 2. Asymmetric signature verification - needed to verify signed data without requiring the signing key in the datapath These capabilities enable use cases such as: - Verifying signed network packets or application data in XDP/TC programs - Implementing integrity checks in tracing and security monitoring - Building zero-trust security models where BPF programs verify credentials - Content-addressed storage and deduplication in BPF-based filesystems Implementation: The implementation follows BPF's existing crypto patterns: 1. Uses bpf_dynptr for safe memory access without page fault risks 2. Leverages the kernel's existing crypto library (lib/crypto/sha256.c and crypto/ecdsa.c) rather than reimplementing algorithms 3. Provides context-based API for ECDSA to enable key reuse and support multiple program types (syscall, XDP, TC) 4. Includes comprehensive selftests with NIST test vectors Patch 1: bpf: Extend bpf_crypto_type with hash operations - Adds hash operation callbacks to bpf_crypto_type structure - Adds hash() and digestsize() function pointers - Must come before crypto module to maintain bisectability Patch 2: crypto: Add BPF hash algorithm type registration module - Adds bpf_crypto_shash module in crypto/ subsystem - Registers hash type with BPF crypto infrastructure - Enables hash algorithm access through unified bpf_crypto_type interface - Implements callbacks: alloc_tfm, free_tfm, hash, digestsize, get_flags - Manages shash_desc lifecycle internally Patch 3: bpf: Add SHA hash kfunc for cryptographic hashing - Adds bpf_crypto_hash() kfunc for SHA-256/384/512 - Updates bpf_crypto_ctx_create() to support keyless operations - Protected by CONFIG_CRYPTO_HASH2 guards - Uses kernel's crypto library implementations - Fixed u64 types for dynptr sizes to prevent truncation Patch 4: selftests/bpf: Add tests for bpf_crypto_hash kfunc - Tests basic functionality with NIST "abc" test vectors - Validates error handling for invalid parameters (zero-length input) - Ensures correct hash output for SHA-256, SHA-384, and SHA-512 - Adds CONFIG_CRYPTO_HASH2 and CONFIG_CRYPTO_SHA512 to selftest config - Refactored test setup code to reduce duplication Patch 5: bpf: Add ECDSA signature verification kfuncs - Context-based API: bpf_ecdsa_ctx_create/acquire/release pattern - Supports NIST curves (P-256, P-384, P-521) - Adds bpf_ecdsa_verify() for signature verification - Includes size query functions: keysize, digestsize, maxsize - Enables use in non-sleepable contexts via pre-allocated contexts - Uses crypto_sig API with p1363 format (r || s signatures) Patch 6: selftests/bpf: Add tests for ECDSA signature verification - Tests valid signature acceptance with RFC 6979 test vectors for P-256 - Tests invalid signature rejection - Tests size query functions (keysize, digestsize, maxsize) - Uses well-known NIST test vectors with "sample" message - Adds CONFIG_CRYPTO_ECDSA to selftest config v2: - Fixed redundant __bpf_dynptr_is_rdonly() checks (Vadim) - Added BPF hash algorithm type registration module in crypto/ subsystem - Added CONFIG_CRYPTO_HASH2 guards around bpf_crypto_hash() kfunc and its BTF registration, matching the pattern used for CONFIG_CRYPTO_ECDSA - Added mandatory digestsize validation for hash operations v3: - Fixed patch ordering - header changes now in separate first commit before crypto module to ensure bisectability (bot+bpf-ci) - Fixed type mismatch - changed u32 to u64 for dynptr sizes in bpf_crypto_hash() to match __bpf_dynptr_size() return type (Mykyta) - Added CONFIG_CRYPTO_ECDSA to selftest config (Song) - Refactored test code duplication with setup_skel() helper (Song) - Added copyright notices to all new files Daniel Hodges (6): bpf: Extend bpf_crypto_type with hash operations crypto: Add BPF hash algorithm type registration module bpf: Add SHA hash kfunc for cryptographic hashing selftests/bpf: Add tests for bpf_crypto_hash kfunc bpf: Add ECDSA signature verification kfuncs selftests/bpf: Add tests for ECDSA signature verification kfuncs crypto/Makefile | 3 + crypto/bpf_crypto_shash.c | 95 ++++++ include/linux/bpf_crypto.h | 2 + kernel/bpf/crypto.c | 306 +++++++++++++++++- tools/testing/selftests/bpf/config | 3 + .../selftests/bpf/prog_tests/crypto_hash.c | 147 +++++++++ .../selftests/bpf/prog_tests/ecdsa_verify.c | 75 +++++ .../testing/selftests/bpf/progs/crypto_hash.c | 142 ++++++++ .../selftests/bpf/progs/ecdsa_verify.c | 160 +++++++++ 9 files changed, 925 insertions(+), 8 deletions(-) create mode 100644 crypto/bpf_crypto_shash.c create mode 100644 tools/testing/selftests/bpf/prog_tests/crypto_hash.c create mode 100644 tools/testing/selftests/bpf/prog_tests/ecdsa_verify.c create mode 100644 tools/testing/selftests/bpf/progs/crypto_hash.c create mode 100644 tools/testing/selftests/bpf/progs/ecdsa_verify.c -- 2.51.0

10 hours, 51 minutes

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[PATCH 00/46] Allow inlining C helpers into Rust when using LTO

by Alice Ryhl

This patch series adds __rust_helper to every single rust helper. The patches do not depend on each other, so maintainers please go ahead and pick up any patches relevant to your subsystem! Or provide your Acked-by so that Miguel can pick them up. These changes were generated by adding __rust_helper and running ClangFormat. Unrelated formatting changes were removed manually. Why is __rust_helper needed? ============================ Currently, C helpers cannot be inlined into Rust even when using LTO because LLVM detects slightly different options on the codegen units. * LLVM doesn't want to inline functions compiled with `-fno-delete-null-pointer-checks` with code compiled without. The C CGUs all have this enabled and Rust CGUs don't. Inlining is okay since this is one of the hardening features that does not change the ABI, and we shouldn't have null pointer dereferences in these helpers. * LLVM doesn't want to inline functions with different list of builtins. C side has `-fno-builtin-wcslen`; `wcslen` is not a Rust builtin, so they should be compatible, but LLVM does not perform inlining due to attributes mismatch. * clang and Rust doesn't have the exact target string. Clang generates `+cmov,+cx8,+fxsr` but Rust doesn't enable them (in fact, Rust will complain if `-Ctarget-feature=+cmov,+cx8,+fxsr` is used). x86-64 always enable these features, so they are in fact the same target string, but LLVM doesn't understand this and so inlining is inhibited. This can be bypassed with `--ignore-tti-inline-compatible`, but this is a hidden option. (This analysis was written by Gary Guo.) How is this fixed? ================== To fix this we need to add __always_inline to all helpers when compiling with LTO. However, it should not be added when running bindgen as bindgen will ignore functions marked inline. To achieve this, we are using a #define called __rust_helper that is defined differently depending on whether bindgen is running or not. Note that __rust_helper is currently always #defined to nothing. Changing it to __always_inline will happen separately in another patch series. Signed-off-by: Alice Ryhl <aliceryhl(a)google.com> --- Alice Ryhl (46): rust: auxiliary: add __rust_helper to helpers rust: barrier: add __rust_helper to helpers rust: binder: add __rust_helper to helpers rust: bitmap: add __rust_helper to helpers rust: bitops: add __rust_helper to helpers rust: blk: add __rust_helper to helpers rust: bug: add __rust_helper to helpers rust: clk: add __rust_helper to helpers rust: completion: add __rust_helper to helpers rust: cpu: add __rust_helper to helpers rust: cpufreq: add __rust_helper to helpers rust: cpumask: add __rust_helper to helpers rust: cred: add __rust_helper to helpers rust: device: add __rust_helper to helpers rust: dma: add __rust_helper to helpers rust: drm: add __rust_helper to helpers rust: err: add __rust_helper to helpers rust: fs: add __rust_helper to helpers rust: io: add __rust_helper to helpers rust: irq: add __rust_helper to helpers rust: jump_label: add __rust_helper to helpers rust: kunit: add __rust_helper to helpers rust: maple_tree: add __rust_helper to helpers rust: mm: add __rust_helper to helpers rust: of: add __rust_helper to helpers rust: pci: add __rust_helper to helpers rust: pid_namespace: add __rust_helper to helpers rust: platform: add __rust_helper to helpers rust: poll: add __rust_helper to helpers rust: processor: add __rust_helper to helpers rust: property: add __rust_helper to helpers rust: rbtree: add __rust_helper to helpers rust: rcu: add __rust_helper to helpers rust: refcount: add __rust_helper to helpers rust: regulator: add __rust_helper to helpers rust: scatterlist: add __rust_helper to helpers rust: security: add __rust_helper to helpers rust: slab: add __rust_helper to helpers rust: sync: add __rust_helper to helpers rust: task: add __rust_helper to helpers rust: time: add __rust_helper to helpers rust: uaccess: add __rust_helper to helpers rust: usb: add __rust_helper to helpers rust: wait: add __rust_helper to helpers rust: workqueue: add __rust_helper to helpers rust: xarray: add __rust_helper to helpers rust/helpers/auxiliary.c | 6 +++-- rust/helpers/barrier.c | 6 ++--- rust/helpers/binder.c | 13 ++++----- rust/helpers/bitmap.c | 6 +++-- rust/helpers/bitops.c | 11 +++++--- rust/helpers/blk.c | 4 +-- rust/helpers/bug.c | 4 +-- rust/helpers/build_bug.c | 2 +- rust/helpers/clk.c | 24 +++++++++-------- rust/helpers/completion.c | 2 +- rust/helpers/cpu.c | 2 +- rust/helpers/cpufreq.c | 3 ++- rust/helpers/cpumask.c | 32 +++++++++++++--------- rust/helpers/cred.c | 4 +-- rust/helpers/device.c | 16 +++++------ rust/helpers/dma.c | 15 ++++++----- rust/helpers/drm.c | 7 ++--- rust/helpers/err.c | 6 ++--- rust/helpers/fs.c | 2 +- rust/helpers/io.c | 64 +++++++++++++++++++++++--------------------- rust/helpers/irq.c | 6 +++-- rust/helpers/jump_label.c | 2 +- rust/helpers/kunit.c | 2 +- rust/helpers/maple_tree.c | 3 ++- rust/helpers/mm.c | 20 +++++++------- rust/helpers/mutex.c | 13 ++++----- rust/helpers/of.c | 2 +- rust/helpers/page.c | 9 ++++--- rust/helpers/pci.c | 13 +++++---- rust/helpers/pid_namespace.c | 8 +++--- rust/helpers/platform.c | 2 +- rust/helpers/poll.c | 5 ++-- rust/helpers/processor.c | 2 +- rust/helpers/property.c | 2 +- rust/helpers/rbtree.c | 5 ++-- rust/helpers/rcu.c | 4 +-- rust/helpers/refcount.c | 10 +++---- rust/helpers/regulator.c | 24 ++++++++++------- rust/helpers/scatterlist.c | 12 +++++---- rust/helpers/security.c | 26 ++++++++++-------- rust/helpers/signal.c | 2 +- rust/helpers/slab.c | 14 +++++----- rust/helpers/spinlock.c | 13 ++++----- rust/helpers/sync.c | 4 +-- rust/helpers/task.c | 24 ++++++++--------- rust/helpers/time.c | 12 ++++----- rust/helpers/uaccess.c | 8 +++--- rust/helpers/usb.c | 3 ++- rust/helpers/vmalloc.c | 7 ++--- rust/helpers/wait.c | 2 +- rust/helpers/workqueue.c | 8 +++--- rust/helpers/xarray.c | 10 +++---- 52 files changed, 280 insertions(+), 226 deletions(-) --- base-commit: 54e3eae855629702c566bd2e130d9f40e7f35bde change-id: 20251202-define-rust-helper-f7b531813007 Best regards, -- Alice Ryhl <aliceryhl(a)google.com>

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[PATCH net-next v7 0/9] Add support for providers with large rx buffer

by Pavel Begunkov

Note: it's net/ only bits and doesn't include changes, which shoulf be merged separately and are posted separately. The full branch for convenience is at [1], and the patch is here: https://lore.kernel.org/io-uring/7486ab32e99be1f614b3ef8d0e9bc77015b173f7.1… Many modern NICs support configurable receive buffer lengths, and zcrx and memory providers can use buffers larger than 4K/PAGE_SIZE on x86 to improve performance. When paired with hw-gro larger rx buffer sizes can drastically reduce the number of buffers traversing the stack and save a lot of processing time. It also allows to give to users larger contiguous chunks of data. The idea was first floated around by Saeed during netdev conf 2024 and was asked about by a few folks. Single stream benchmarks showed up to ~30% CPU util improvement. E.g. comparison for 4K vs 32K buffers using a 200Gbit NIC: packets=23987040 (MB=2745098), rps=199559 (MB/s=22837) CPU %usr %nice %sys %iowait %irq %soft %idle 0 1.53 0.00 27.78 2.72 1.31 66.45 0.22 packets=24078368 (MB=2755550), rps=200319 (MB/s=22924) CPU %usr %nice %sys %iowait %irq %soft %idle 0 0.69 0.00 8.26 31.65 1.83 57.00 0.57 This series adds net infrastructure for memory providers configuring the size and implements it for bnxt. It's an opt-in feature for drivers, they should advertise support for the parameter in the qops and must check if the hardware supports the given size. It's limited to memory providers as it drastically simplifies implementation. It doesn't affect the fast path zcrx uAPI, and the sizes is defined in zcrx terms, which allows it to be flexible and adjusted in the future, see Patch 8 for details. A liburing example can be found at [2] full branch: [1] https://github.com/isilence/linux.git zcrx/large-buffers-v7 Liburing example: [2] https://github.com/isilence/liburing.git zcrx/rx-buf-len v7: - Add xa_destroy - Rebase v6: - Update docs and add a selftest v5: https://lore.kernel.org/netdev/cover.1760440268.git.asml.silence@gmail.com/ - Remove all unnecessary bits like configuration via netlink, and multi-stage queue configuration. v4: https://lore.kernel.org/all/cover.1760364551.git.asml.silence@gmail.com/ - Update fbnic qops - Propagate max buf len for hns3 - Use configured buf size in __bnxt_alloc_rx_netmem - Minor stylistic changes v3: https://lore.kernel.org/all/cover.1755499375.git.asml.silence@gmail.com/ - Rebased, excluded zcrx specific patches - Set agg_size_fac to 1 on warning v2: https://lore.kernel.org/all/cover.1754657711.git.asml.silence@gmail.com/ - Add MAX_PAGE_ORDER check on pp init - Applied comments rewording - Adjust pp.max_len based on order - Patch up mlx5 queue callbacks after rebase - Minor ->queue_mgmt_ops refactoring - Rebased to account for both fill level and agg_size_fac - Pass providers buf length in struct pp_memory_provider_params and apply it in __netdev_queue_confi(). - Use ->supported_ring_params to validate drivers support of set qcfg parameters. Jakub Kicinski (1): eth: bnxt: adjust the fill level of agg queues with larger buffers Pavel Begunkov (8): net: page pool: xa init with destroy on pp init net: page_pool: sanitise allocation order net: memzero mp params when closing a queue net: let pp memory provider to specify rx buf len eth: bnxt: store rx buffer size per queue eth: bnxt: allow providers to set rx buf size io_uring/zcrx: document area chunking parameter selftests: iou-zcrx: test large chunk sizes Documentation/networking/iou-zcrx.rst | 20 +++ drivers/net/ethernet/broadcom/bnxt/bnxt.c | 118 ++++++++++++++---- drivers/net/ethernet/broadcom/bnxt/bnxt.h | 2 + drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c | 6 +- drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.h | 2 +- include/net/netdev_queues.h | 9 ++ include/net/page_pool/types.h | 1 + net/core/netdev_rx_queue.c | 14 ++- net/core/page_pool.c | 4 + .../selftests/drivers/net/hw/iou-zcrx.c | 72 +++++++++-- .../selftests/drivers/net/hw/iou-zcrx.py | 37 ++++++ 11 files changed, 236 insertions(+), 49 deletions(-) -- 2.52.0

14 hours, 55 minutes

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[PATCH v5 00/24] ARM64 PMU Partitioning

by Colton Lewis

This series creates a new PMU scheme on ARM, a partitioned PMU that allows reserving a subset of counters for more direct guest access, significantly reducing overhead. More details, including performance benchmarks, can be read in the v1 cover letter linked below. An overview of what this series accomplishes was presented at KVM Forum 2025. Slides [1] and video [2] are linked below. The long duration between v4 and v5 is due to time spent on this project being monopolized preparing this feature for internal production. As a result, there are too many improvements to fully list here, but I will cover the notable ones. v5: * Rebase onto v6.18-rc7. This required pulling some reorganization patches from Anish and Sean that were dependencies from previous versions based on kvm/queue but never made it to upstream. * Ensure FGTs (fine-grained traps) are correctly programmed at vCPU load using kvm_vcpu_load_fgt() and helpers introduced by Oliver Upton. * Cleanly separate concerns of whether the partitioned PMU is enabled for the guest and whether FGT should be enabled. This allows that the capability can be VM-scoped while the implementation detail of whether FGT and context switching are in effect can remain vCPU-scoped. * Shrink the uAPI change. Instead of a cap and corresponding ioctl, the feature can be controlled by just a cap with an argument. The cap is now also VM-scoped and enforces ordering that it should be decided before vCPUs are created. Whether the cap is enabled is now tracked by the new flag KVM_ARCH_ARM_PARTITIONED_PMU_ENABLED. * Improve log messages when partitioning in the PMUv3 driver. * Introduce a global variable armv8pmu_hpmn_max in the PMUv3 driver so KVM code can read if a value was set before the PMU is probed. This is needed to properly test if we have the capability before vCPUs are created. * Make it possible for a VMM to filter the HPMN0 feature bit. * Fix event filter problems with PMEVTYPER handling in writethrough_pmevtyper() and kvm_pmu_apply_event_filter() by using kvm_pmu_event_mask() in the right spots. And if an event is filtered, write the physical register with the appropriate exclude bits set but keep the virtual register exactly what the guest wrote. * Fix register access problems with the PMU register fast path handler by lifting some static PMU access checks from sys_regs.c to use them in the fast path too and make bit masking more strict for better ARM compliance. * Fix the readability and logic of programming the MDCR_EL2 register when entering the guest. Make sure to set the HPME bit to allow host counters to count guest events. Set TPM and TPMCR by default and clear them if partitioning is enabled rather than the previous inverted logic of leaving them clear and setting them if partitioning is not enabled. Make the HPMN field computation more clear. * As part of lazy context switching, do a load when the guest is switching to physical access to ensure any previous writes that only reached the virtual registers reach the physical ones as well and are not clobbered by the next vcpu_put(). * Other fixes and improvements that are too small to mention or left out from my personal notes. v4: https://lore.kernel.org/kvmarm/20250714225917.1396543-1-coltonlewis@google.… v3: https://lore.kernel.org/kvm/20250626200459.1153955-1-coltonlewis@google.com/ v2: https://lore.kernel.org/kvm/20250620221326.1261128-1-coltonlewis@google.com/ v1: https://lore.kernel.org/kvm/20250602192702.2125115-1-coltonlewis@google.com/ [1] https://gitlab.com/qemu-project/kvm-forum/-/raw/main/_attachments/2025/Opti… [2] https://www.youtube.com/watch?v=YRzZ8jMIA6M&list=PLW3ep1uCIRfxwmllXTOA2txfD… Anish Ghulati (1): KVM: arm64: Move arm_{psci,hypercalls}.h to an internal KVM path Colton Lewis (20): arm64: cpufeature: Add cpucap for HPMN0 KVM: arm64: Reorganize PMU functions perf: arm_pmuv3: Introduce method to partition the PMU perf: arm_pmuv3: Generalize counter bitmasks perf: arm_pmuv3: Keep out of guest counter partition KVM: arm64: Set up FGT for Partitioned PMU KVM: arm64: Writethrough trapped PMEVTYPER register KVM: arm64: Use physical PMSELR for PMXEVTYPER if partitioned KVM: arm64: Writethrough trapped PMOVS register KVM: arm64: Write fast path PMU register handlers KVM: arm64: Setup MDCR_EL2 to handle a partitioned PMU KVM: arm64: Account for partitioning in PMCR_EL0 access KVM: arm64: Context swap Partitioned PMU guest registers KVM: arm64: Enforce PMU event filter at vcpu_load() KVM: arm64: Implement lazy PMU context swaps perf: arm_pmuv3: Handle IRQs for Partitioned PMU guest counters KVM: arm64: Inject recorded guest interrupts KVM: arm64: Add KVM_CAP to partition the PMU KVM: selftests: Add find_bit to KVM library KVM: arm64: selftests: Add test case for partitioned PMU Marc Zyngier (1): KVM: arm64: Reorganize PMU includes Sean Christopherson (2): KVM: arm64: Include KVM headers to get forward declarations KVM: arm64: Move ARM specific headers in include/kvm to arch directory Documentation/virt/kvm/api.rst | 24 + arch/arm/include/asm/arm_pmuv3.h | 28 + arch/arm64/include/asm/arm_pmuv3.h | 61 +- .../arm64/include/asm/kvm_arch_timer.h | 2 + arch/arm64/include/asm/kvm_host.h | 24 +- .../arm64/include/asm/kvm_pmu.h | 142 ++++ arch/arm64/include/asm/kvm_types.h | 7 +- .../arm64/include/asm/kvm_vgic.h | 0 arch/arm64/kernel/cpufeature.c | 8 + arch/arm64/kvm/Makefile | 2 +- arch/arm64/kvm/arch_timer.c | 5 +- arch/arm64/kvm/arm.c | 23 +- {include => arch/arm64}/kvm/arm_hypercalls.h | 0 {include => arch/arm64}/kvm/arm_psci.h | 0 arch/arm64/kvm/config.c | 34 +- arch/arm64/kvm/debug.c | 31 +- arch/arm64/kvm/guest.c | 2 +- arch/arm64/kvm/handle_exit.c | 2 +- arch/arm64/kvm/hyp/Makefile | 6 +- arch/arm64/kvm/hyp/include/hyp/switch.h | 211 ++++- arch/arm64/kvm/hyp/nvhe/switch.c | 4 +- arch/arm64/kvm/hyp/vhe/switch.c | 4 +- arch/arm64/kvm/hypercalls.c | 4 +- arch/arm64/kvm/pmu-direct.c | 464 +++++++++++ arch/arm64/kvm/pmu-emul.c | 678 +--------------- arch/arm64/kvm/pmu.c | 726 ++++++++++++++++++ arch/arm64/kvm/psci.c | 4 +- arch/arm64/kvm/pvtime.c | 2 +- arch/arm64/kvm/reset.c | 3 +- arch/arm64/kvm/sys_regs.c | 110 +-- arch/arm64/kvm/trace_arm.h | 2 +- arch/arm64/kvm/trng.c | 2 +- arch/arm64/kvm/vgic/vgic-debug.c | 2 +- arch/arm64/kvm/vgic/vgic-init.c | 2 +- arch/arm64/kvm/vgic/vgic-irqfd.c | 2 +- arch/arm64/kvm/vgic/vgic-kvm-device.c | 2 +- arch/arm64/kvm/vgic/vgic-mmio-v2.c | 2 +- arch/arm64/kvm/vgic/vgic-mmio-v3.c | 2 +- arch/arm64/kvm/vgic/vgic-mmio.c | 4 +- arch/arm64/kvm/vgic/vgic-v2.c | 2 +- arch/arm64/kvm/vgic/vgic-v3-nested.c | 3 +- arch/arm64/kvm/vgic/vgic-v3.c | 2 +- arch/arm64/kvm/vgic/vgic-v5.c | 2 +- arch/arm64/tools/cpucaps | 1 + arch/arm64/tools/sysreg | 6 +- drivers/perf/arm_pmuv3.c | 137 +++- include/linux/perf/arm_pmu.h | 1 + include/linux/perf/arm_pmuv3.h | 14 +- include/uapi/linux/kvm.h | 1 + tools/include/uapi/linux/kvm.h | 1 + tools/testing/selftests/kvm/Makefile.kvm | 1 + .../selftests/kvm/arm64/vpmu_counter_access.c | 77 +- tools/testing/selftests/kvm/lib/find_bit.c | 1 + 53 files changed, 2049 insertions(+), 831 deletions(-) rename include/kvm/arm_arch_timer.h => arch/arm64/include/asm/kvm_arch_timer.h (98%) rename include/kvm/arm_pmu.h => arch/arm64/include/asm/kvm_pmu.h (61%) rename include/kvm/arm_vgic.h => arch/arm64/include/asm/kvm_vgic.h (100%) rename {include => arch/arm64}/kvm/arm_hypercalls.h (100%) rename {include => arch/arm64}/kvm/arm_psci.h (100%) create mode 100644 arch/arm64/kvm/pmu-direct.c create mode 100644 tools/testing/selftests/kvm/lib/find_bit.c base-commit: ac3fd01e4c1efce8f2c054cdeb2ddd2fc0fb150d -- 2.52.0.239.gd5f0c6e74e-goog

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