From: Geliang Tang <tanggeliang(a)kylinos.cn>
v4:
- add more patches using make_sockaddr and get_socket_local_port
helpers.
v3:
- address comments of Martin and Eduard in v2. (thanks)
- move "int type" to the first argument of start_server_addr and
connect_to_addr.
- add start_server_addr_opts.
- using "sockaddr_storage" instead of "sockaddr".
- move start_server_setsockopt patches out of this series.
v2:
- update patch 6 only, fix errors reported by CI.
This patchset uses public helpers start_server_* and connect_to_* defined
in network_helpers.c to drop duplicate code.
Geliang Tang (14):
selftests/bpf: Update arguments of connect_to_addr
selftests/bpf: Add start_server_addr* helpers
selftests/bpf: Use start_server_addr in cls_redirect
selftests/bpf: Use connect_to_addr in cls_redirect
selftests/bpf: Use start_server_addr in sk_assign
selftests/bpf: Use connect_to_addr in sk_assign
selftests/bpf: Use get_socket_local_port in sk_assign
selftests/bpf: Use make_sockaddr in sk_assign
selftests/bpf: Use log_err in network_helpers
selftests/bpf: Use start_server_addr in test_sock_addr
selftests/bpf: Use connect_to_addr in test_sock_addr
selftests/bpf: Use make_sockaddr in test_sock_addr
selftests/bpf: Use make_sockaddr in test_sock
selftests/bpf: Use make_sockaddr in ip_check_defrag
tools/testing/selftests/bpf/Makefile | 4 +-
tools/testing/selftests/bpf/network_helpers.c | 37 ++++-
tools/testing/selftests/bpf/network_helpers.h | 6 +-
.../selftests/bpf/prog_tests/cls_redirect.c | 38 +----
.../selftests/bpf/prog_tests/empty_skb.c | 2 +
.../bpf/prog_tests/ip_check_defrag.c | 20 +--
.../selftests/bpf/prog_tests/sk_assign.c | 92 ++----------
.../selftests/bpf/prog_tests/sock_addr.c | 6 +-
.../selftests/bpf/prog_tests/tc_redirect.c | 2 +-
.../selftests/bpf/prog_tests/test_tunnel.c | 4 +
.../selftests/bpf/prog_tests/xdp_metadata.c | 16 +++
tools/testing/selftests/bpf/test_sock.c | 28 +---
tools/testing/selftests/bpf/test_sock_addr.c | 136 +++---------------
13 files changed, 104 insertions(+), 287 deletions(-)
--
2.40.1
This patch series ended up much larger than expected, please bear with
me! The goal here is to support vendor extensions, starting at probing
the device tree and ending with reporting to userspace.
The main design objective was to allow vendors to operate independently
of each other. This has been achieved by delegating vendor extensions to
a new struct "hart_isa_vendor" which is a counterpart to "hart_isa".
Each vendor will have their own list of extensions they support. Each
vendor will have a "namespace" to themselves which is set at the key
values of 0x8000 - 0x8080. It is up to the vendor's disgression how they
wish to allocate keys in the range for their vendor extensions.
Reporting to userspace follows a similar story, leveraging the hwprobe
syscall. There is a new hwprobe key RISCV_HWPROBE_KEY_VENDOR_EXT_0 that
is used to request supported vendor extensions. The vendor extension
keys are disambiguated by the vendor associated with the cpumask passed
into hwprobe. The entire 64-bit key space is available to each vendor.
On to the xtheadvector specific code. xtheadvector is a custom extension
that is based upon riscv vector version 0.7.1 [1]. All of the vector
routines have been modified to support this alternative vector version
based upon whether xtheadvector was determined to be supported at boot.
I have tested this with an Allwinner Nezha board. I ran into issues
booting the board on 6.9-rc1 so I applied these patches to 6.8. There
are a couple of minor merge conflicts that do arrise when doing that, so
please let me know if you have been able to boot this board with a 6.9
kernel. I used SkiffOS [2] to manage building the image, but upgraded
the U-Boot version to Samuel Holland's more up-to-date version [3] and
changed out the device tree used by U-Boot with the device trees that
are present in upstream linux and this series. Thank you Samuel for all
of the work you did to make this task possible.
To test the integration, I used the riscv vector kselftests. I modified
the test cases to be able to more easily extend them, and then added a
xtheadvector target that works by calling hwprobe and swapping out the
vector asm if needed.
[1] https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361…
[2] https://github.com/skiffos/SkiffOS/tree/master/configs/allwinner/nezha
[3] https://github.com/smaeul/u-boot/commit/2e89b706f5c956a70c989cd31665f1429e9…
Signed-off-by: Charlie Jenkins <charlie(a)rivosinc.com>
---
Changes in v2:
- Added commit hash to xtheadvector
- Simplified riscv,isa vector removal fix to not mess with the DT
riscv,vendorid
- Moved riscv,vendorid parsing into a different patch and cache the
value to be used by alternative patching
- Reduce riscv,vendorid missing severity to "info"
- Separate vendor extension list to vendor files
- xtheadvector no longer puts v in the elf_hwcap
- Only patch vendor extension if all harts are associated with the same
vendor. This is the best chance the kernel has for working properly if
there are multiple vendors.
- Split hwprobe vendor keys out into vendor file
- Add attribution for Heiko's patches
- Link to v1: https://lore.kernel.org/r/20240411-dev-charlie-support_thead_vector_6_9-v1-…
---
Charlie Jenkins (16):
riscv: cpufeature: Fix thead vector hwcap removal
dt-bindings: riscv: Add xtheadvector ISA extension description
dt-bindings: riscv: Add vendorid
riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree
riscv: Fix extension subset checking
riscv: Extend cpufeature.c to detect vendor extensions
riscv: Introduce vendor variants of extension helpers
riscv: drivers: Convert xandespmu to use the vendor extension framework
riscv: uaccess: Add alternative for xtheadvector uaccess
riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT
riscv: Create xtheadvector file
riscv: vector: Support xtheadvector save/restore
riscv: hwprobe: Add vendor extension probing
riscv: hwprobe: Document vendor extensions and xtheadvector extension
selftests: riscv: Fix vector tests
selftests: riscv: Support xtheadvector in vector tests
Heiko Stuebner (1):
RISC-V: define the elements of the VCSR vector CSR
Documentation/arch/riscv/hwprobe.rst | 12 +
Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +
.../devicetree/bindings/riscv/extensions.yaml | 10 +
arch/riscv/Kconfig | 2 +
arch/riscv/Kconfig.vendor | 11 +
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 +-
arch/riscv/errata/sifive/errata.c | 2 +
arch/riscv/errata/thead/errata.c | 2 +
arch/riscv/include/asm/cpufeature.h | 170 +++++++++---
arch/riscv/include/asm/csr.h | 13 +
arch/riscv/include/asm/hwcap.h | 27 +-
arch/riscv/include/asm/hwprobe.h | 7 +-
arch/riscv/include/asm/sbi.h | 2 +
arch/riscv/include/asm/switch_to.h | 2 +-
arch/riscv/include/asm/vector.h | 246 +++++++++++++----
arch/riscv/include/asm/vendor_extensions.h | 18 ++
arch/riscv/include/asm/xtheadvector.h | 25 ++
arch/riscv/include/uapi/asm/hwprobe.h | 11 +-
arch/riscv/include/uapi/asm/vendor/thead.h | 3 +
arch/riscv/kernel/Makefile | 2 +
arch/riscv/kernel/cpu.c | 36 ++-
arch/riscv/kernel/cpufeature.c | 204 ++++++++++----
arch/riscv/kernel/kernel_mode_vector.c | 8 +-
arch/riscv/kernel/process.c | 4 +-
arch/riscv/kernel/signal.c | 6 +-
arch/riscv/kernel/sys_hwprobe.c | 54 +++-
arch/riscv/kernel/vector.c | 35 ++-
arch/riscv/kernel/vendor_extensions.c | 36 +++
arch/riscv/kernel/vendor_extensions/Makefile | 4 +
.../kernel/vendor_extensions/andes_extensions.c | 13 +
.../kernel/vendor_extensions/thead_extensions.c | 13 +
arch/riscv/lib/uaccess.S | 2 +
drivers/perf/riscv_pmu_sbi.c | 7 +-
tools/testing/selftests/riscv/vector/.gitignore | 3 +-
tools/testing/selftests/riscv/vector/Makefile | 17 +-
.../selftests/riscv/vector/v_exec_initval_nolibc.c | 93 +++++++
tools/testing/selftests/riscv/vector/v_helpers.c | 74 ++++++
tools/testing/selftests/riscv/vector/v_helpers.h | 7 +
tools/testing/selftests/riscv/vector/v_initval.c | 22 ++
.../selftests/riscv/vector/v_initval_nolibc.c | 68 -----
.../selftests/riscv/vector/vstate_exec_nolibc.c | 20 +-
.../testing/selftests/riscv/vector/vstate_prctl.c | 295 ++++++++++++---------
42 files changed, 1226 insertions(+), 368 deletions(-)
---
base-commit: 4cece764965020c22cff7665b18a012006359095
change-id: 20240411-dev-charlie-support_thead_vector_6_9-1591fc2a431d
--
- Charlie
This patch series ended up much larger than expected, please bear with
me! The goal here is to support vendor extensions, starting at probing
the device tree and ending with reporting to userspace.
The main design objective was to allow vendors to operate independently
of each other. This has been achieved by delegating vendor extensions to
a new struct "hart_isa_vendor" which is a counterpart to "hart_isa".
Each vendor will have their own list of extensions they support. Each
vendor will have a "namespace" to themselves which is set at the key
values of 0x8000 - 0x8080. It is up to the vendor's disgression how they
wish to allocate keys in the range for their vendor extensions.
Reporting to userspace follows a similar story, leveraging the hwprobe
syscall. There is a new hwprobe key RISCV_HWPROBE_KEY_VENDOR_EXT_0 that
is used to request supported vendor extensions. The vendor extension
keys are disambiguated by the vendor associated with the cpumask passed
into hwprobe. The entire 64-bit key space is available to each vendor.
On to the xtheadvector specific code. xtheadvector is a custom extension
that is based upon riscv vector version 0.7.1 [1]. All of the vector
routines have been modified to support this alternative vector version
based upon whether xtheadvector was determined to be supported at boot.
I have tested this with an Allwinner Nezha board. I ran into issues
booting the board on 6.9-rc1 so I applied these patches to 6.8. There
are a couple of minor merge conflicts that do arrise when doing that, so
please let me know if you have been able to boot this board with a 6.9
kernel. I used SkiffOS [2] to manage building the image, but upgraded
the U-Boot version to Samuel Holland's more up-to-date version [3] and
changed out the device tree used by U-Boot with the device trees that
are present in upstream linux and this series. Thank you Samuel for all
of the work you did to make this task possible.
To test the integration, I used the riscv vector kselftests. I modified
the test cases to be able to more easily extend them, and then added a
xtheadvector target that works by calling hwprobe and swapping out the
vector asm if needed.
[1] https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361…
[2] https://github.com/skiffos/SkiffOS/tree/master/configs/allwinner/nezha
[3] https://github.com/smaeul/u-boot/commit/2e89b706f5c956a70c989cd31665f1429e9…
Signed-off-by: Charlie Jenkins <charlie(a)rivosinc.com>
---
Charlie Jenkins (18):
dt-bindings: riscv: Add vendorid and archid
riscv: cpufeature: Fix thead vector hwcap removal
dt-bindings: riscv: Add xtheadvector ISA extension description
riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree
riscv: Fix extension subset checking
riscv: Extend cpufeature.c to detect vendor extensions
riscv: Optimize riscv_cpu_isa_extension_(un)likely()
riscv: Introduce vendor variants of extension helpers
riscv: uaccess: Add alternative for xtheadvector uaccess
riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT
riscv: Create xtheadvector file
riscv: vector: Support xtheadvector save/restore
riscv: hwprobe: Disambiguate vector and xtheadvector in hwprobe
riscv: hwcap: Add v to hwcap if xtheadvector enabled
riscv: hwprobe: Add vendor extension probing
riscv: hwprobe: Document vendor extensions and xtheadvector extension
selftests: riscv: Fix vector tests
selftests: riscv: Support xtheadvector in vector tests
Heiko Stuebner (1):
RISC-V: define the elements of the VCSR vector CSR
Documentation/arch/riscv/hwprobe.rst | 12 +
Documentation/devicetree/bindings/riscv/cpus.yaml | 11 +
.../devicetree/bindings/riscv/extensions.yaml | 9 +
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 4 +-
arch/riscv/include/asm/cpufeature.h | 143 +++++++---
arch/riscv/include/asm/csr.h | 13 +
arch/riscv/include/asm/hwcap.h | 23 ++
arch/riscv/include/asm/hwprobe.h | 4 +-
arch/riscv/include/asm/sbi.h | 2 +
arch/riscv/include/asm/vector.h | 228 ++++++++++++----
arch/riscv/include/asm/xtheadvector.h | 25 ++
arch/riscv/include/uapi/asm/hwprobe.h | 10 +-
arch/riscv/kernel/cpu.c | 20 ++
arch/riscv/kernel/cpufeature.c | 264 +++++++++++++++---
arch/riscv/kernel/kernel_mode_vector.c | 4 +-
arch/riscv/kernel/sys_hwprobe.c | 59 ++++-
arch/riscv/kernel/vector.c | 22 +-
arch/riscv/lib/uaccess.S | 1 +
tools/testing/selftests/riscv/vector/.gitignore | 3 +-
tools/testing/selftests/riscv/vector/Makefile | 17 +-
.../selftests/riscv/vector/v_exec_initval_nolibc.c | 93 +++++++
tools/testing/selftests/riscv/vector/v_helpers.c | 66 +++++
tools/testing/selftests/riscv/vector/v_helpers.h | 7 +
tools/testing/selftests/riscv/vector/v_initval.c | 22 ++
.../selftests/riscv/vector/v_initval_nolibc.c | 68 -----
.../selftests/riscv/vector/vstate_exec_nolibc.c | 20 +-
.../testing/selftests/riscv/vector/vstate_prctl.c | 295 ++++++++++++---------
27 files changed, 1114 insertions(+), 331 deletions(-)
---
base-commit: 4cece764965020c22cff7665b18a012006359095
change-id: 20240411-dev-charlie-support_thead_vector_6_9-1591fc2a431d
--
- Charlie
Add support for (yet again) more RVA23U64 missing extensions. Add
support for Zcmop, Zca, Zcf, Zcd and Zcb extensions isa string parsing,
hwprobe and kvm support. Zce, Zcmt and Zcmp extensions have been left
out since they target microcontrollers/embedded CPUs and are not needed
by RVA23U64
This series is based on the Zimop one [1].
Link: https://lore.kernel.org/linux-riscv/20240404103254.1752834-1-cleger@rivosin… [1]
Clément Léger (10):
dt-bindings: riscv: add Zca, Zcf, Zcd and Zcb ISA extension
description
riscv: add ISA parsing for Zca, Zcf, Zcd and Zcb
riscv: hwprobe: export Zca, Zcf, Zcd and Zcb ISA extensions
RISC-V: KVM: Allow Zca, Zcf, Zcd and Zcb extensions for Guest/VM
KVM: riscv: selftests: Add some Zc* extensions to get-reg-list test
dt-bindings: riscv: add Zcmop ISA extension description
riscv: add ISA extension parsing for Zcmop
riscv: hwprobe: export Zcmop ISA extension
RISC-V: KVM: Allow Zcmop extension for Guest/VM
KVM: riscv: selftests: Add Zcmop extension to get-reg-list test
Documentation/arch/riscv/hwprobe.rst | 24 ++++++++++++
.../devicetree/bindings/riscv/extensions.yaml | 37 +++++++++++++++++++
arch/riscv/include/asm/hwcap.h | 5 +++
arch/riscv/include/uapi/asm/hwprobe.h | 5 +++
arch/riscv/include/uapi/asm/kvm.h | 5 +++
arch/riscv/kernel/cpufeature.c | 5 +++
arch/riscv/kernel/sys_hwprobe.c | 5 +++
arch/riscv/kvm/vcpu_onereg.c | 10 +++++
.../selftests/kvm/riscv/get-reg-list.c | 20 ++++++++++
9 files changed, 116 insertions(+)
--
2.43.0
Fix the error reported by clang:
In file included from mdwe_test.c:17:
./../kselftest_harness.h:1169:2: error: call to undeclared function
'asprintf'; ISO C99 and later do not support implicit function
declarations [-Wimplicit-function-declaration]
1169 | asprintf(&test_name, "%s%s%s.%s", f->name,
| ^
1 warning generated.
The gcc reports it as warning:
In file included from mdwe_test.c:17:
../kselftest_harness.h: In function ‘__run_test’:
../kselftest_harness.h:1169:9: warning: implicit declaration of function
‘asprintf’; did you mean ‘vsprintf’? [-Wimplicit-function-declaration]
1169 | asprintf(&test_name, "%s%s%s.%s", f->name,
| ^~~~~~~~
| vsprintf
Fix this by setting _GNU_SOURCE macro needed to get exposure to the
asprintf().
Signed-off-by: Muhammad Usama Anjum <usama.anjum(a)collabora.com>
---
tools/testing/selftests/mm/mdwe_test.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/testing/selftests/mm/mdwe_test.c b/tools/testing/selftests/mm/mdwe_test.c
index 200bedcdc32e9..1e01d3ddc11c5 100644
--- a/tools/testing/selftests/mm/mdwe_test.c
+++ b/tools/testing/selftests/mm/mdwe_test.c
@@ -7,6 +7,7 @@
#include <linux/mman.h>
#include <linux/prctl.h>
+#define _GNU_SOURCE
#include <stdio.h>
#include <stdlib.h>
#include <sys/auxv.h>
--
2.39.2