* 2 days off
== Progress ==
* GCC upstream validation:
- reported several regressions/new failures
* GCC
- PR96767: patch accepted
- PR96770: patch accepted
- patch for C++ thunks with -mpure-code and cortex-m0: iterating, almost OK
- Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: no feedback
* benchmarking:
- Scripts to run coremark on stm32 now merged, debugging issues.
* infra:
- debugging issues with our docker containers
- added monitoring for disk space on dev machines
== Next ==
* GCC/cortex-M testing improvements & fixes
* cortex-m benchmarking
* MVE intrinsics improvements
[VIRT-327 # Richard's upstream QEMU work ]
More time than I expected on float128_muladd, adjusting the codebase to share
code with float64_muladd.
[VIRT-339 # ARMv8.5-BTI, Branch Target Identification ]
Posted v12, adjusting one of the smoke tests vs a distro linker bug (fixed in
mainline).
r~
VirtIO Initiative ([STR-9])
===========================
VirtIO RPMB ([STR-5])
=====================
- Synced with with Ulf/Illias on enhancements for eMMC stacks
- need to support 512 frames somehow for the CSD, everything else
should be fine
[STR-5] <https://projects.linaro.org/browse/STR-5>
VirtIO Portability Demo ([STR-13])
==================================
- More work on trying to get Xen working on MB
- more failures, this time GIC related. Might just stick to KVM
- Created a [branch with the experimental ioreq (virtio-mmio) support]
- Got Virgl based acceleration working on both TCG and KVM - so now
fast graphics!
- posted [PATCH v1 0/4] add guest-loader (for direct Xen boot)
Message-Id: <20201021170842.25762-1-alex.bennee(a)linaro.org>
[STR-13] <https://projects.linaro.org/browse/STR-13>
[branch with the experimental ioreq (virtio-mmio) support]
<http://git.linaro.org/people/alex.bennee/linux.git/shortlog/refs/heads/expe…>
Upstream Work ([QEMU-109])
==========================
- Some discussion on converting the final bits of 96/128 bit softfloat
- posted [RFC PATCH 0/8] fpu: experimental conversion of
float128_addsub Message-Id:
<20201020163738.27700-1-alex.bennee(a)linaro.org>
- partial reviewed [RFC PATCH 00/15] softfloat: alternate conversion
of float128_addsub Message-Id:
<20201021045149.1582203-1-richard.henderson(a)linaro.org>
- posted [PATCH v1 0/6] testing/next (gitdm, acceptance, docker,
gitlab) Message-Id: <20201021163136.27324-5-alex.bennee(a)linaro.org>
Other
=====
- reclaiming space for my gmail (98.5% used!)
Completed Reviews [1/1]
=======================
[PATCH 0/2] tcg: optimize across branches
Message-Id: <20201013222330.173525-1-richard.henderson(a)linaro.org>
Absences
========
- Welsh lockdown next week
- Children at home
Current Review Queue
====================
* [PATCH v3 0/4] GitLab Custom Runners and Jobs (was: QEMU Gating CI)
Message-Id: <20201014052140.1146924-1-crosa(a)redhat.com>
Added: <2020-10-14 Wed>
* [PATCH v6 0/5] Enable plugin support on msys2/mingw
Message-Id: <20201013002806.1447-1-luoyonggang(a)gmail.com>
Added: <2020-10-13 Tue>
* [PATCH v7 0/4] Improve cirrus msys2
Message-Id: <20201012233740.190-1-luoyonggang(a)gmail.com>
Added: <2020-10-13 Tue>
* [PATCH RFC 00/22] Support of Virtual CPU Hotplug for ARMv8 Arch
Message-Id: <20200613213629.21984-1-salil.mehta(a)huawei.com>
Added: <2020-09-23 Wed>
--
Alex Bennée
* 2 days off
== Progress ==
* GCC upstream validation:
- identified several regressions, but they had already been reported
* GCC
- PR96767: no feedback
- PR96770: no feedback
- patch for C++ thunks with -mpure-code and cortex-m0: handling
further feedback
- Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: no feedback
* benchmarking:
- Scripts to run coremark on stm32 now merged, debugging issues. No
progress this week.
* infra:
- debugging issues with our docker containers
== Next ==
* GCC/cortex-M testing improvements & fixes
* cortex-m benchmarking
* MVE intrinsics improvements
Hi,
I am new to toolchains. I would like to know information on building
toolchains for different architectures.
My objective is to build a cross compiling toolchain for AARCH64 BE
target on the RHEL7.6 build system. It would be great if you can give me
pointers on how to compile toolchains. Do we have any Wiki pages on
building linaro toolchains for different architectures?
Appreciate your help.
Regards
Suresh
== Progress ==
* GCC upstream validation:
- reported several regressions
- committed minor cleanup fixes
- fixed broken trunk build with gcc-4.8
* GCC
- PR96767: no feedback
- PR96770: no feedback
- patch for C++ thunks with -mpure-code and cortex-m0: sent updated patch
- Neon intrinsics: sent patch to implement vceqq, vceqz and vceqzq for p64.
* benchmarking:
- Scripts to run coremark on stm32 now merged, debugging issues. No
progress this week.
* infra:
- debugging issues with our docker containers
== Next ==
* GCC/cortex-M testing improvements & fixes
* cortex-m benchmarking
* MVE intrinsics improvements
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ another round of code review and target-arm queue wrangling
+ found and fixed an edge-case bug in setting Q flag in SMLAD insn
+ fixed a GICv3 emulation bug where we didn't ever raise
maintenance interrupts
* VIRT-364 [QEMU support for ARMv8.1-M extensions]
+ went through Arm ARM and identified exactly what the "v8.1M changes
which aren't part of a named architectural feature" are (for
QEMU-409 subtask)
+ implemented some parts of NOCP handling that were left as TODO comments
for being v8.1M-specific
+ implemented conditional-select insns (CSEL, CSINC, CSINV, CSNEG)
+ implemented low-overhead-loops and branch-future (in the 'trivial'
don't-cache-anything way the architecture permits)
thanks
-- PMM