linaro-toolchain

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5578 discussions

No arm-eabi builds on latest Linaro Android 4.9 toolchain?

by 박주형

I was using arm-eabi builds on Linaro Android 4.9 toolchain 2014.06. I've just downloaded 2014.07 and found out there is not an arm-eabi toolchain. I need arm-eabi to build Linux kernels and arm-none-eabi toolchain from here: http://releases.linaro.org/14.07/components/toolchain/binaries/gcc-linaro-a… is not capable of building LTO kernels. Error pops up : "cc1: error: -fno-fat-lto-objects are supported only with linker plugin" TL;DR, I need arm-eabi builds from Linaro Android toolchains. arm-none-eabi builds are not built with linker plugin enabled.

10 years, 9 months

[ACTIVITY] 28-31 July

by Christophe Lyon

Short week (Friday off) == Progress == * GCC trunk cross-validation (2/10) - catch up with backlog, reported newly introduced FAILs - analyzed logs of spurious failures, improved reporting of such cases - the script will know send a separate email with the svn ids it has selected for validation, to help fill the backports spreadsheet * Infrastructure (2/10) - started deployment of past releases to help us quickly reproduce/investigate bug reports - 14.* binary releases deployed on toolchain64 (/work/toolchains) - automation not yet possible because of problem with the lab internal squid proxy preventing the download of http://releases.linaro.org/14.07/components/toolchain/binaries for parsing - started deployment of past toolchains built from the source releases using cbuild2 but ran into build problems * Neon intrinsics tests (1/10) * Misc (conf calls, meetings) (3/10) - 1-1 calls to get feedback after Cauldron+Sprint - a bit of bugzilla triage - backports reviews for 14.08 release == Next == Holidays, back on Aug 18th

10 years, 9 months

Linaro toolchain binary allowing soft-float?

by Joel (Xi Zhou) Zhou

Hi Linaro-toolchain team, I notice that the Linaro toolchain binary only support hard-float. We have a platform which is ARMv7 based does not support VFP. Could you generate toolchain binary for ARmv7 that allows soft-float? Thanks, Joel

10 years, 9 months

[ACTIVITY] Week 28 - 29 - 30

by Yvan Roux

-------------------------------------------------------------------------------- Week 28 -------------------------------------------------------------------------------- == Issues == * none. == Progress == * TCWG-496 : Linaro GCC 4.9 2014.07 (7/10) - FSF branch merge. - Backports validation results gathering. * Misc: (3/10) - Various meetings. -------------------------------------------------------------------------------- Week 29 -------------------------------------------------------------------------------- == Issues == * none. == Progress == * TCWG-496 : Linaro GCC 4.9 2014.07 (7/10) - Compared all the validation results. - Released 2014.07. * Misc: (3/10) - Various meetings. - Travel to Cambridge -------------------------------------------------------------------------------- Week 30 -------------------------------------------------------------------------------- == Issues == * none. == Progress == * TCWG-496 : Linaro GCC 4.9 2014.07 (1/14) - Release had to be respinned. - Reverted unwanted backport. - Merged FSF 4.9 branch up to 4.9.1 release. * GNU Tools Cauldron (4/14) * Linaro TCWG sprint (7/14) * Travel (2/14) == Next == * Complete release respin * Prepare 4.9-2014.08 release (backports, ...).

10 years, 9 months

[ANNOUNCE] Linaro GCC 4.9 2014.07-1 released

by Yvan Roux

The Linaro Toolchain Working Group (TCWG) announces the 2014.07-1 release of the Linaro GCC 4.9 source package. This is a respin of the 2014.07 release which contained a backport of a revision that is only relevant to trunk. Changes in this GCC source package release are: * Updates to GCC 4.9.1 (svn212635) * Revert backport of [AArch32] Fix PR target/61154. Please find the original 2014.07 release notes below: The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2014.07 stable release of the Linaro GCC 4.9 source package. Linaro GCC 4.9 2014.07 is the fourth Linaro GCC source package release in the 4.9 series. It is based on FSF GCC 4.9.1+svn212419 and includes performance improvements and bug fixes. With the imminent release of ARMv8 hardware and the recent release of the GCC 4.9 compiler the Linaro TCWG will be focusing on stabilization and performance of the compiler as the FSF GCC compiler approaches version 4.9.1. The Linaro TCWG will provide monthly stable[1] source package releases until FSF GCC 4.9.1 is released. At that point Linaro GCC 4.9 will merge in FSF GCC 4.9.1 and, release Linaro GCC 4.9.1, and then return to a schedule of stable quarterly releases and monthly engineering[2] releases. Interesting changes in this GCC source package release include: * Updates to GCC 4.9.1-pre+svn212419 * Backport of [AArch32] Wrap long literals in HOST_WIDE_INT_C in aarch-common.c * Backport of [AArch32] Rewrite TLC Intrinsics. * Backport of [AArch32] Remove vzip, vuzp, vtrn builtins and cleanup * Backport of [AArch32] Use enum name instead of integer value for PARAM_SCHED_PRESSURE_ALGORITHM. * Backport of [AArch32] Vectorise bswap* * Backport of [AArch32] Fix PR/61331 * Backport of [AArch32] Fix PR target/61154 * Backport of [AArch32] Use mov_imm type for movw operations consistently * Backport of [AArch32] Remove XFmode from ARM backend. * Backport of [AArch64] Rewrite REV Intrinsics. * Backport of [AArch64] Implement HARD_REGNO_CALLER_SAVE_MODE. * Backport of [AArch64] Support tail indirect function call. * Backport of [AArch64] Fix stack protector for ILP32 * Backport of [AArch64] ILP32 dynamic linker * Backport of [AArch64] Correct signedness of builtins, remove casts from arm_neon.h * Backport of [AArch64] clarify stack layout diagram * Backport of [AArch64] Implement movmem for the benefit of inline memcpy * Backport of [AArch64] Fix REG_CFA_RESTORE mode. * Backport of [AArch64] Fix layout of frame layout code. * Backport of [AArch64] Fix some reg-to-reg move scheduler types. * Backport of [AArch64] Implement CRC32 ACLE intrinsics + testsuite. * Backport of [AArch64] Implement ADD in vector registers for 32-bit scalar values. * Backport of [AArch32/AArch64] TARGET_ATOMIC_ASSIGN_EXPAND_FENV AArch64 * Backport of [AArch32/AArch64] Use signed chars in gcc.dg/pr60114.c. * Backport of [AArch32/AArch64] Rewrite UZP Intrinsics. * Backport of [AArch32/AArch64] Rewrite TRN Intrinsics. * Backport of [AArch32/AArch64] Rewrite EXT Intrinsics. * Backport of [genattrtab] Fix memory corruption, allocate enough memory for all bypassed reservations * Backport of Fix PR c/60114 Feedback and Support Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list": http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in Launchpad against "Linaro GCC project": http://bugs.launchpad.net/gcc-linaro/+filebug. * Questions? "ask Linaro": http://ask.linaro.org/. * Interested in commercial support? inquire at "Linaro support":mailto: support(a)linaro.org [1] Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed. [2] Engineering source package releases are defined as releases where the compiler is only put through unit-testing and full validation is not performed.

10 years, 9 months

[ACTIVITY] July 19th - 25th

by Bernie Ogden

=Progress= GNU Cauldron TCWG Sprint [8/10] * Really helpful to meet (almost) everybody * Some useful discussion, too memcpy on A15 - TCWG-390 [1/10] * Should have let this lie but I had an odd 1/2 day and some data begging to be looked at * Turned out I'd fat-fingered the wrong data * But I gained more evidence suggesting that cortex-strings benchmark is too noisy (Non-sprint) meetings/mail etc [1/10] =Plan= cbuild2 benchmarking * Fit what I have into Rob's worldview * Hopefully convert it into some reviewable patches Follow up on some notes from Cauldron, sprint

10 years, 9 months

[ACTIVITY] Week 30

by Renato Golin

== Progress == * GNU Cauldron (4/10) - GCC+LLVM presentation had some positive reviews - Discussed sanitizers roadmap - Very interesting meeting with QuIC * TCWG Sprint (4/10) - Mostly about GNU tools - Team Mission streamlined, looking good - LLVM roadmap attracted some attention - We could have some bite-sized work from other team members? * Release 3.5 testing (TCWG-476 2/10) - No test regressions - Spotted some benchmark regressions - ARMv7 is overall the same on EEMBC - AArch64 is overall 10% faster on EEMBC * Weekend working, Friday off == Plan == * Release week! - Investigate 3.5 performance regressions on v7 - Work around the lack of perf on v8? - Run SPEC on both v7 and v8 and spot regressions

10 years, 9 months

[Activity] 19-25 JULY 2014

by Venkataramanan Kumar

== Progress == * Attend GNU Cauldron. * TCWG Sprint (8/10) - Participated in Discussions about TCWG/GNU tools. - Partcipated in Discussions with ARM mainatiners. - Discussed about Connect plans. - LLVM status. - Attend Backport Demo by Yvan / some Bug fix Activity. * Friday off traveling back home (2/10) == Plan == * Continue LTO bootstrap issue * Benchmark Core mark with LTO * Upstream patch review. == Issues == * Large Memory Model put on hold now. * Waiting on ARM on Aarch64 SYS V ABI.

10 years, 9 months

[Weekly] 21-25 JULY 2014

by Michael Collison

== This week == * TCWG Sprint (8/10) - Validation process greatly clarified including roadmap * Launchpad 1318831 - Invalid unpoisoning of stack redzones on ARM (2/10) - Finished validating and working thru git review isses with Launchpad == Next week == * Begin neon intrinsic testing * I will be off on Monday and Tuesday

10 years, 9 months

help, here is a armV8 32bit question for linaro 4.8: the code I given below adopt sembedding ARMV8 assembly , but the compile result with Linaro GCC 4.8 aarch32 is not correct

by Panshilin (Peter)

Hi all concerned: this test code I given below: AARCH32 [https://email-cn04.huawei.com/owa/14.3.158.1/themes/base/pgrs-sm.gif] Test function[X][X] { volatile unsigned int val0 = 0; volatile unsigned int val1 = 0; asm volatile(“mrrc p15, 1, %0, %1, c15” : “=r”(val0), “=r”(val1)) val0 &= ~(1<<6); val1 &= ~(1<<6); asm volatile(“mcrr p15, 1, %0, %1, c15” : “=r”(val0), “=r”(val1)); } After compiling, the result is: mrrc 15, 1, r2, r3, cr15 str r2, [fp, #-28] str r3, [fp, #-24] ldr r3, [fp, #-28] bic r3, r3, #64; str r3, [fp, #-28] ldr r3, [fp, #-24] bic r3, r3, #64 str r3, [fp, #-24] mcrr 15, 1, r2, r3, cr15 obviously , it is not what I expect. I have val0 an vl1 two vars, but the compiling result is only one val takes effect. especia I have to mention is AARCH32. thanks. Peter

10 years, 9 months

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