== Progress ==
* Automation Framework (CARD-1378 1/10)
- Setting up Junos with ARM
* Toolchain (CARD-862 1/10)
- Some progress on fpu parser issue
- Produced a lot more work for the near future
* Buildbots (TCWG-76 4/10)
- Setting up a libc++ buildbot, working on reducing failures
- Some bots broken, bisecting
* Background (4/10)
- Code review, meetings, discussions, etc.
- Annual review
- More lab move planning
- EuroLLVM meetings and planning
== Plan ==
* US LLVM whole next week
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2014.10
release of the Linaro GCC 4.9 source package.
Linaro GCC 4.9 2014.10 is the seventh Linaro GCC source package release. It is
based on FSF GCC 4.9.2-pre+svn216130 and includes performance improvements and
bug fixes.
With the imminent release of ARMv8 hardware and the recent release of the
GCC 4.9 compiler the Linaro TCWG will be focusing on stabilization and
performance of the compiler as the FSF GCC compiler. The Linaro TCWG provides
stable[1] quarterly releases and monthly enginering[2] releases.
Interesting changes in this GCC source package release include
* Updates to GCC 4.9.2-pre+svn216130
* Backport of [AArch64] Define TARGET_FLAGS_REGNUM
* Backport of PR target/61565
* Backport of [AArch64] libitm: Improve _ITM_beginTransaction
* Backport of [AArch64] Fix *extr_insv_lower_reg<mode> pattern
* Backport of [AArch64] Use CC_Z and CC_NZ with csinc and similar instructions
* Backport of [AArch32] Implement and vectorize lceil, lfloor, lround optabs
with new ARMv8-A instructions
* Backport of [AArch64] Improve epilogue unwind info rth
* Backport of [AArch64] Add a mode to operand 1 of sibcall_value_insn
* Backport of [AArch64] Add a builtin for rbit(q?)_p8; add intrinsics and tests
* Backport of [AArch32/AArch64] Schedule alu_ext for Cortex-A53
* Backport of [AArch64] Remove varargs from aarch64_simd_expand_args
* Backport of [AArch64] Tidy: remove unused qualifier_const_pointer
* Backport of [AArch32/AArch64] Add scheduling info for ARMv8-A FPU new
instructions in Cortex-A53
* Backport of [AArch32] Convert FP mnemonics to UAL.
* Backport of [AArch32] Enable auto-vectorization for copysignf
* Backport of [AArch32][tests] Make input and output arrays 128-bit aligned in
vectorisation tests
* Backport of [AArch64] Add crtfastmath
* Backport of PR target/56846 libstdc++
* Backport of PR target/63209
* Backport of [Ree] Ensure inserted copy don't change the number of hard
registers
* Backport of [AArch64] Fix force_simd macro in vdup_lane_2
* Backport of [AArch32] Disallow -mfpu=neon for unsuitable architectures
* Backport of [AArch32] movmisalign<mode>_neon_load
* Backport of [AArch64] Add constraint letter for stack_protect_test pattern
* Backport of [AArch64] Auto-generate the "BUILTIN_" macros
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Questions? "ask Linaro":
http://ask.linaro.org/.
* Interested in commercial support? inquire at "Linaro support":mailto:
support(a)linaro.org
[1] Stable source package releases are defined as releases where the full Linaro
Toolchain validation plan is executed.
[2] Engineering source package releases are defined as releases where the
compiler is only put through unit-testing and full validation is not
performed.
Hi,
I start to use Linary AArch64 toolchain recently and just joined this maillist. I went through some of the archived threads but didn't read all of them. So bear me if I'm asking dumb question or old question which had been answered before.
For our use case, we are running the gdb client at early state of boot. So the ARMv8 target might be running into any EL and into either AArch64 or AArch32 state. My questions are:
1) Is the aarch64-none-elf-gdb.exe good for both AArch64 and AArch32 or I have to run the arm-none-eabi-gdb.exe if the target running in AArch32 state?
2) If the target is in AArch64 state, can I use the aarch64-none-elf-gdb.exe to load binary built for AArch32 to the target?
I'm really appreciated if anybody can help me on these two questions.
Thanks in advance,
StrongQ
cbuild2 benchmarking - TCWG-360 [3/10]
* A few small enhancements and bug-fixes
* Tried to run spec2006 on Juno, looks tricky
libm profiling - CARD-1693 [3/10]
* Pulled together lapack + blas
* Looked a bit at how it exercises libm on x86
* Tried to look at how it exercises libm on Juno, looks tricky
Meetings/mail/etc [4/10]
* Featuring some fun with backups and ARM performance review season
=Plan=
* cbuild2 benchmarking - keep chipping away at spec/juno
* libm profiling - attempt to assemble an AArch64 setup that works for me
* further performance review/corporate admin will take up extra time
this week, but should then fall back to normal levels
=Issues=
State of the setup on our Junos
== Progress ==
* Part way through integrating Cbuild2/Jenkins with Gerrit. (#1692,
8/10)
- Implemented functions to use the REST API to Gerrit via SSH.
- Integrated into build and test processes.
* Meetings and Misc (2/10)
- Ordered 10 Snapdragon boards
== Plan ==
* Finish Gerrit integration with Cbuild2 and Jenkins. (#1692)
- Find a way the buildslave user can use the SSH connection to Gerrit.
* Start merging the linaro branch in DejaGnu to master to get
ready for the next release.
* Start getting ready for the lab move, do what I can ahead of time.
== Issues ==
* Gerrit comments via REST strip out all newlines, so I need to
limit the message size after a test run.
= Progress ==
* Core mark benchmark and report for PGO and PGO + LTO (TCWG-544) (6/10)
Going by CPU cycles adding LTO gains in x86 and degrades in Aarch64 .
Looked at hot functions and examining assembly the code generation seems to
be same. X86_64 does alignment of code. Also branch misses decreased in
X86_64 compared to Aarch64 with -flto + -O3.
Also profiled for instruction counts on Aarch64 with linaro compiler. These
profiles say that we are executing less instructions with LTO and PGO for
Aarch64.
* PR 63173- Reproduced the issue and changed the test case to work with
trunk. Now Looks like someone else has a patch for it. (1/10). so will
work on other bugs.
* Misc [3/10]
Internal work, emails, AMD meetings and 1-1 with inline manger.
1-1 with Maxim, christophe and 1-1 with ryan
== Plan ==
* Coremark benchmark and profiling.
Investigate trunk degradation for O3+ PGO + LTO and report.
== leaves ==
Diwali holiday (22-24)
== Issues ==
* Still no network at home and will not be fixed before at least one week :(
== Progress ==
* GCC 4.9 2014.10 (8/10)
- Merged FSF 4.9 branch
- Released Linaro 4.9 2014.10
* Misc: (2/10)
- Various meetings.
== Plan ==
* Analyse some failures that occur only in --enable-release.
== Progress ==
Catch up with work after return from Eid ul Adha and Annual Holidays [7/10]
* Hong Kong visa application
* UPS repairs and office cleanup
* Catching up with work, gdb roadmap and open/running cards.
* Emails/Patch scrolling/Meetings etc
* Sick day off on Monday
GDB Tracepoints/Fast Tracepoints support on arm [TCWG-480] [3/10]
* Getting re-synced with code where I left.
== Plan ==
Further progress on GDB Tracepoints/Fast Tracepoints support on arm [TCWG-480]
Investigate possibility of AArch64 trace-point work without
availability of hardware.
Check for GDB status on ARM and AArch64 vs x86.
