== Progress ==
* GCC trunk/4.9 cross-validation (2/10)
- noticed a couple of newly introduced failing tests in some corner cases
- improved notification of selected commits to help fill the
backports speadsheet
* AArch64 libsanitizer
- answered Marcus/Andrew after their feedback
* Misc (conf calls, meetings, ....) 6/10
- usual 1/1 and team calls
- Connect preparation
- travelled on Friday
== Next ==
* Connect LCU14
== Progress ==
* More work on malloc app benchmark framework (1/10, TCWG-441)
- Postgres still has an issue with SELinux on Fedora...
* Email, meetings, etc. (1/10)
* Upstream work (3/10, CARD-341)
- Patch review
- Investigate glibc testsuite build failures on ARM
* Investigate malloc single-thread optimizations (4/10, TCWG-436)
- Atomics changes look like they will only help on AArch64
- Some improvements can be made to atomic code in general on ARM and AArch64
- Still need to look at locking
* Peparing and packing for Connect (1/10)
== Issues ==
* Electric/gas meter replacement and broken refrigerator consumed some time
== Plan ==
* Linaro Connect
--
Will Newton
Toolchain Working Group, Linaro
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2014.09
release of the Linaro GCC 4.9 source package.
Linaro GCC 4.9 2014.08 is the sixth Linaro GCC source package release.
It is based
on FSF GCC 4.9.2-pre+svn214896 and includes performance improvements
and bug fixes.
With the imminent release of ARMv8 hardware and the recent release of
the GCC 4.9
compiler the Linaro TCWG will be focusing on stabilization and
performance of the
compiler as the FSF GCC compiler. The Linaro TCWG provides stable[1] quarterly
releases and monthly enginering[2] releases.
Interesting changes in this GCC source package release include
* Updates to GCC 4.9.2-pre+svn214896
* Backport of [AArch32] TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook
* Backport of [AArch32] Enable arm target in ira-shrinkwrap-prep* testcases
* Backport of [AArch32] fix check_effective_target_arm_nothumb
* Backport of Do not convert cast + __builtin_round into __builtin_lround unless
-fno-math-errno is used
* Backport of [AArch64] Fix Thumb2 testsuite fallout
* Backport of [AArch64_be] Fix vec_select hi/lo mask confusions.
* Backport of [AArch64_be] Don't fold reduction intrinsics
* Backport of [AArch64] Fix offset glitch in load reg pair pattern
* Backport of [AArch64][2/2] Add constrain to address offset in
storewb_pair/loadwb_pair insns
* Backport of [AArch64] Improve TARGET_LEGITIMIZE_ADDRESS_P hook
* Backport of [AArch64] Removed unused get_lane and dup_lane builtins.
* Backport of [sched-deps] Generalise usage of macro fusion to work on
any two insns
* Backport of [doc] Document clrsb optab and fix some inconsistencies
* Backport of [AArch64] Some aarch64-builtins.c cleanup.
* Backport of Guard transformation to lrint by -fno-math-errno
* Backport of [AArch32] Adjust clz, rbit and rev patterns for -mrestrict-it
* Backport of [AArch32/AArch64] Add CRC32 scheduling information to
Cortex-A53 and
Cortex-A57
* Backport of [AArch64] Use REG_P and CONST_INT_P instead of GET_CODE
+ comparison
* Backport of [AArch64] Prefer dup to zip for vec_perm_const; enable
dup for bigendian;
* Backport of [AArch32] TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook
* Backport of [AArch64] Use MOVN to generate 64-bit negative
immediates where sensible
* Backport of [AArch64] Delete f_sels, f_seld types, use fcsel instead
* Backport of PR target/60606 target/61330 fix ICE
* Backport of [AArch64] PR target/63190
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in Launchpad against "Linaro GCC project":
http://bugs.launchpad.net/gcc-linaro/+filebug.
* Questions? "ask Linaro":
http://ask.linaro.org/.
* Interested in commercial support? inquire at "Linaro support":mailto:
support(a)linaro.org
[1] Stable source package releases are defined as releases where the full Linaro
Toolchain validation plan is executed.
[2] Engineering source package releases are defined as releases where the
compiler is only put through unit-testing and full validation is not
performed.
Hi,
I'm having some very odd problems building the 2014.08 toolchain respin --
in the cbuild1 i686-lucid env, building glibc fails with
[ERROR] ../sysdeps/unix/sysv/linux/bits/sched.h:127:14: error:
variably modified '__bits' at file scope
[ERROR] ../sysdeps/unix/sysv/linux/bits/sched.h:127:14: error:
variably modified '__bits' at file scope
[ERROR] ../sysdeps/unix/sysv/linux/bits/sigset.h:29:23: error:
variably modified '__val' at file scope
[ERROR] ../sysdeps/unix/sysv/linux/bits/sigset.h:29:23: error:
variably modified '__val' at file scope
[ERROR] ../misc/sys/select.h:69:15: error: variably modified
'fds_bits' at file scope
[ERROR] ../misc/sys/select.h:69:15: error: variably modified
'fds_bits' at file scope
[ERROR] /cbuild/slaves/oorts/crosstool-ng/builds/aarch64_be-linux-gnu-linux/install/aarch64_be-linux-gnu/libc/usr/include/linux/posix_types.h:25:16:
error: variably modified 'fds_bits' at file scope
[ERROR] /cbuild/slaves/oorts/crosstool-ng/builds/aarch64_be-linux-gnu-linux/install/aarch64_be-linux-gnu/libc/usr/include/asm/sigcontext.h:33:2:
error: requested alignment is not a positive power of 2
[ERROR] /cbuild/slaves/oorts/crosstool-ng/builds/aarch64_be-linux-gnu-linux/install/aarch64_be-linux-gnu/libc/usr/include/asm/sigcontext.h:53:2:
error: unknown type name '__uint128_t'
[ERROR] /cbuild/slaves/oorts/crosstool-ng/builds/aarch64_be-linux-gnu-linux/install/aarch64_be-linux-gnu/libc/usr/include/linux/posix_types.h:25:16:
error: variably modified 'fds_bits' at file scope
[ERROR] /cbuild/slaves/oorts/crosstool-ng/builds/aarch64_be-linux-gnu-linux/install/aarch64_be-linux-gnu/libc/usr/include/asm/sigcontext.h:33:2:
error: requested alignment is not a positive power of 2
[ERROR] /cbuild/slaves/oorts/crosstool-ng/builds/aarch64_be-linux-gnu-linux/install/aarch64_be-linux-gnu/libc/usr/include/asm/sigcontext.h:53:2:
error: unknown type name '__uint128_t'
[ERROR] ../ports/sysdeps/unix/sysv/linux/aarch64/sys/user.h:32:3:
error: unknown type name '__uint128_t'
[ERROR] ../ports/sysdeps/unix/sysv/linux/aarch64/sys/user.h:32:3:
error: unknown type name '__uint128_t'
(Yes, the fix is to get rid of cbuild1 and more importantly the requirement
for 32-bit builds in a prehistoric environment - it builds just fine on
64-bit present-day boxes... But I don't think we want to make that change
in a respin).
The "variably modified" errors remain even after hardcoding
typedef struct {
__cpu_mask __bits[16];
} cpu_set_t;
instead of relying on __CPU_SETSIZE and __NCPUBITS, and the line where it
complains about alignment not being a positive power of 2 actually
hardcodes an alignment of 16.
Have you run into those before?
ttyl
bero
== Progress ==
Debug KGDB with gdb for testing [4/10]
LCU14 slides preparation and study for presentation. [2/10]
Miscellaneous [4/10]
* Configure to use hackbox to test aarch64 gdb remote configs
* Retrieve gdb test results in different configurations.
* Emails/Patch scrolling/Meetings etc
== Plan ==
patch updates and re submission.
Figure ARM and AArch64 gdb missing features.
Prepare and travel LCU14
=Progress=
cbuild2 benchmarking - TCWG-360 [8/10]
* Got an end-to-end run in my test environment
* Patched tests to run more selectively (in review)
Meetings/mail/etc - [2/10]
=Plan=
cbuild2 benchmarking:
* Clean up some lose ends
* Sort out source/results storage
glibc:
* Finish comments in lowlevellock.h (if time)
4 days week.
== Issues ==
* Unfortunate cbuild schroot-branch merge, silently brake the validation, and we
had to revert a commit in our FSF repo.
* aarch64 bare valdiation was broken all week, now workaround but it
still have to
be fixed.
== Progress ==
* GCC 4.9 2014.09 (6/10)
- Completed new backports.
- Started FSF 4.9 branch merge for 2014.09
- Investigated validation breakages.
* Misc:
- Various meetings (2/10)
== Next ==
- 4.9 2014.09 release.
- Prepare LCU hacking session
- Travel to CA
== This week ==
* USA Holiday, Monday September 1st
* TCWG-534 - Neon intrinsic testing part 8 (2/10)
- Tested final eighteen neon intrinsics on ARM with no regressions
identified
- Unable to test on aarch64 due to test harness issues
* Linaro Bugzilla 331 - [4.9 Regression] ICE in final_scan_insn, at
final.c:2952 (aarch64-linux-gnu) (2/10)
- Bug fix investigation
* Launchpad 1312931- gcc 4.8 internal compiler error: in add_stores, at
var-tracking.c (2/10)
- validation test results review and code review submission
* Misc. (2/10)
- Linaro Connect presentation finalization and conference call
- 1:1 with Christophe
== Next week ==
- Complete Neon intrinsic testing on Aarch64
- Identify bug fix for Linaro Bugzilla 331
- Investigate failures identified in Neon intrinsic testing
== Progress ==
* TCWG-181 - Bench marking core mark with LTO (2/10)
Measured -O3 -flto vs -O3 on Aarch64 machine with Linaro GCC and
Trunk FSF GCC on Aarch64 and X86_64. Performance in both cases seems
to be same level. Planning to remeasure in trunk now.
* TCWG-531 Fix invalid use of vector register (3/10).
Completed fixing. patch tested on Aarch64 machine and up streamed the
patch to FSF trunk.
* TCWG-532 Fix abinit fails to build on AArch64 (2/10)
Bug does not appear in trunk. Case of missing back port.
Did git bisect experiments in trunk and found that r213078 solves the problem.
Case of code generation for loading labels at -O0 getting fixed after
changes to IRA register class.
* Cbuildv2 preparation for hack session in LCU14.(1/10)
* Others (2/10)
* Meetings Christophe, Ryan, Maxim and GCC status meeting
* Misc and internal meeting.
* Cbuildv2 preparation for hack session in LCU14.
== Plan ==
* Continue testing fix for TCWG-532
* Continue backport fix for TCWG-531.
* Continue Benchmark Core mark with LTO (TCWG-181).
* TCWG-533 Creating scripting to run git bisect with cbuild2.
* Cbuildv2 preparation for hack session in LCU14.
