== This Week ==
* TCWG-528 (2/10)
- Addressed comments from Richard and committed upstream (r236502, r236503)
* TCWG-72 (5/10)
- Updated patch and fixed regressions caused due to patch.
* TCWG-319 (1/10)
- Found why big endian vectorizer was not vectorizing the test-case with -O2.
* Holiday (2/10)
== Next Week ==
- TCWG-319: Post patch upstream and get it committed.
- TCWG-72: Post patch upstream and hopefully get it committed this week.
- TCWG-548: Start re-looking at section anchors.
=== Progress ===
TCWG-591 MOVW incorrectly allowed on ARM v5 committed upstream
TCWG-595 LLD port to ARM architecture
I am getting close to being able to run hello world built with lld.
I'm converging 1 bug at a time.
- The PLT handling code is working and the loader can execute the
image and starts the .init function.
- Currently failing in the weak call to __gmon_start__. At present lld
is removing undefined weak references from executables instead of
passing them on for the dynamic loader to resolve. This may not be
necessary on x86 but it is necessary on ARM.
-- Just finished a hack that should make this work, although it will
need some tidying up.
=== Plan ===
Get hello world working and then take stock of what I've learned and
come up with a plan in Jira for what needs to be done.
== Progress ==
* Add a diag handler for llc so it doesn't exit on the first error it
finds [TCWG-592] [1/10]
- Fixed and rebased the patch, it has been committed upstream
* Inline assembly constraints support for ARM [TCWG-560] [1/10]
- Rebased the patch, it has been committed upstream
* Remove exit-on-error flag from CodeGen tests [TCWG-604] [4/10]
- This is a follow-up of TCWG-592: when changing the diag handler,
some of the tests started to fail, so we had to add an exit-on-error
flag to preserve the old behaviour until we can fix the tests.
- Submitted a patch fixing the MIR tests (PR27770) - in upstream review
- Submitted a patch fixing an AMDGPU test (PR27762) - in upstream review
- Submitted a patch fixing a BPF test (PR27766) - in upstream review
- Investigated the ARM test (PR27765)
* Use git worktree in llvm helper scripts [TCWG-587] [3/10]
- Working on a prototype
* Misc [1/10]
- Meetings, buildbots, IRC issues
- Got LLVM commit access, yay!
== Plan ==
* Remove exit-on-error flag from CodeGen tests [TCWG-604]
- Fix the remaining ARM, BPF and AMDGPU tests (unfortunately the ARM
test seems a bit more involved, so I might pick out the others first
just to get them out of the way)
* Use git worktree in llvm helper scripts [TCWG-587]
- Continue prototyping, start a RFC on it next week
# Progress #
* TCWG-518, [6/10]
fix all bugs, and post them upstreams for review!
* PR 19998, write a patch to fix it. [2/10]
* Some discussions on unstable GDB test results in validation tests.
[1/10]
* Meetings [1/10]
# Plan #
* Respond comments to my patches,
* TCWG-333, think about the right fix.
--
Yao
This may be a better question for the linaro tools group. +cc their list
for the general question of conventions surrounding how shared library
objects identify and access thread-local storage that they need as part of
calling threads.
On Tue, May 17, 2016 at 11:06 AM, Nikhil Agarwal <nikhil.agarwal(a)linaro.org>
wrote:
> Hi All,
>
> I am trying to write a shared library object over ODP. Our ODP library has
> some per thread variables. When my application invokes an API of shared
> object which accesses per thread variable it gives segmentation fault.
>
> My concern is that when a shared object is loaded dynamically, how memory
> is assigned to thread specific variables defined inside shared objects.
> AFAIK we need to compile it with -ftls-model=global-dynamic, which is
> enabled by default when compiled with -fPIC flag, and library loader
> takes care for these issues.
>
> I am not an expert in this area, please help me in getting to some
> suitable reference pointers or some steps I might have missed.
>
> Thanks in advance
>
> Nikhil
>
=== This Week ===
Enable LLDB testsuite to show zero failures on Hikey 96 Board (AArch64
Linux) [TCWG-231] [4/10]
-- Ran multiple builds and testsuite runs to figure out latency issues.
-- Investigated remaining failures and submitted appropriate bugzilla bugs.
-- Committed xfails upstream.
Support for watchpoint un-alligned watchpoint addresses on LLDB
AArch64 [TCWG-367] [1/10]
-- Some investigation on possible solutions and frequently encountered
scenarios.
LLDB Chromebook Test Stability [TCWG-563] [3/10]
-- Investigation of noreturn unwinding test failure
-- Investigation of step over load library call failure
-- Investigation of other failures and commit xfails for reported issues.
Miscellaneous [2/10]
-- Meetings, emails, discussions etc.
-- Portugal visa information gathering
=== Next Week ===
Support for watchpoint un-alligned watchpoint addresses on LLDB
AArch64 [TCWG-367]
-- Add code changes required to manage a watchpoint with multiple
hardware watchpoint resources.
LLDB Chromebook Test Stability [TCWG-563]
-- Fix noreturn unwinding test failure and report relevent bug.
-- Fix step over load library call failure or report relevent bug.
Miscellaneous
-- Portugal visa application documents preparation.
== Progress ==
* Validation
- cleanup
- reviews
- looked a bit a using docker from Jenkins
- investigating how to select toolchain components versions
depending on the gcc version
* GCC
- Sent Neon intrinsics tests patches.
- trunk timeouts: caused by the libcilkrts merge, which has a bug on
arm. Disabled cilkplus to avoid too much noise in the results.
- reported a couple of regressions/bisects
* Misc (conf-calls, meetings, emails, ....)
- support for M-profile related queries ( multilib etc...)
== Next ==
* Validation
- cleanup
- reviews
- armv8l vs arm
- multiple gcc branches vs other components versions handling
* GCC
- trunk monitoring
- some dev if time permits
== Progress ==
o Linaro GCC (5/10)
* Linaro GCC 5.3 2016.05 snapshot
- FSF branch merge + release
* Linaro GCC 6.1 2016.05 snapshot
- Create new branch + release
o Extended validation (3/10)
* Fixed validation issues when binary tarballs are created.
o Misc (2/10)
* Various meetings and discussions.
== Plan ==
o Continue on validation/benchmarking
o Catch up with upstream work.
== Progress ==
* Add a diag handler for llc so it doesn't exit on the first error it
finds [TCWG-592] [5/10]
- Started a discussion about a new diagnostic handler for llc
- Patch accepted upstream, but broke a few things (Renato has
investigated/fixed some of them - thanks)
* Inline assembly constraints support for ARM [TCWG-560] [5/10]
- Patch in upstream review, but should be committed after the new
llc diagnostic is in place (otherwise it's difficult to test it
meaningfully)
== Plan ==
* Add a diag handler for llc so it doesn't exit on the first error it
finds [TCWG-592]
- Fix the remaining issues and get the patch committed again
* Inline assembly constraints support for ARM [TCWG-560]
- Rebase patch and try to get it reviewed
* Investigate exit-on-error on LLC [TCWG-594]
- Track the tests that need the exit-on-error flag with the new
diagnostic handler
== Progress ==
- ldr rt,= implementation transform to MOV committed upstream
[TCWG-468] [PR25722]]
-- Thanks to Renato for committing.
- Started looking at what would be needed to port lld to ARM
-- The ELF lld port looks to have a fairly small amount of
architecture specific hooks. Decided that I would learn fastest by
just trying to do an ARM only prototype port to see if I could get
hello world on linux working.
-- spent too much time trying to think about how to best implement the
group relocations for the PLT sequences then remembered that for a
quick prototype I could use larger sequences that didn't need the
relocations.
== Plan ==
- Continue working on an ARM LLD port. Will hopefully have a good idea
of what the scope of work needed is next week.
