linaro-toolchain

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6 participants
5605 discussions

[Activity] 12-16 September 2016

by Diana Picus

== Progress == * [AArch64] Support for label arithmetic in the assembler [TCWG-710] - 2 patches in upstream review * Handle special cases in AArch64InstrInfo::GetInstSizeInBytes [TCWG-757] - Committed a patch for stackmap / patchpoint sizes - Since this was a bit cumbersome to test otherwise, I had to add unit tests for it, which took a bit of CMake plumbing because these are the first target-specific unit tests in LLVM * Add worktree module to tcwg-release-tools [TCWG-783] - Started working on it * Misc - Helped test/setup the new TK1 buildbots == Plan == * Add worktree module to tcwg-release-tools [TCWG-783] * Help get the TK1 buildbots into a stable state * Ping upstream patches

8 years, 9 months

[Activity] 05th - 16th Sep.

by Yao Qi

* Off on Mon and Tue. [4/20] # Progress # * Range stepping in ARM. TCWG-518 [5/20] The thread starvation is fixed by randomly selecting pending events among threads. Being regression tested. * GDB 7.12 release. TCWG-685. [4/20] Due to the recent kernel change, single step in GDBserver stops working, because new kernel becomes sensitive on writing RES0 bits in CPSR. Fixed in GDB side. * GNU Cauldron. [7/20] Discussed with GDB people on the projects we are working on. Got some agreement on the general direction of some projects. Discussed with the possible GDB changes to handle variable length registers, such as SVE. Agreed to move ptrace-test from sourceware to kernel tree. Sync on 7.12 release. Discussed on AArch64 TLS var debug information, looks it is less complex than expected. # Plan # * Off on Mon and Tue. * TCWG-685, TCWG-518 * Prepare for the US travel. -- Yao Qi

8 years, 9 months

[Activity] 12 - 16 September

by Peter Smith

== Activity == Exceptions support in LLD; 3rd try at an implementation that will be accepted upstream. Now implementation complete and passing my existing tests but needs some more cases checked. Helped track down an intermittent build bot failure to an ld stub generation problem Some upstream patch review == Next Week == Add more test cases and send exceptions support upstream Use some of the Cauldron slides to replace existing LLD ones in the Connect presentation. == Planned Absences == Holiday 10th - 14th October

8 years, 9 months

[ANNOUNCE] Linaro Binary Toolchain Release-Candidate GCC 6.1-2016.08-rc2

by Ryan Arnold

The Linaro Binary Toolchain ============================ The Linaro GCC 6.1-2016.08-rc2 Release-Candidate is now available. The GCC 6 Release series has significant changes from the GCC 5 release series. For an explanation of the changes please see the following website: https://gcc.gnu.org/gcc-6/changes.html For help in porting to GCC 6 please see the following explanation: https://gcc.gnu.org/gcc-6/porting_to.html Download release-candidate packages from: http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.08-rc2/ http://snapshots.linaro.org/components/toolchain/binaries/6.1-2016.08-rc2/ Previous snapshots and release-candidates are at: http://snapshots.linaro.org/components/toolchain/binaries/ Previous releases are at: http://releases.linaro.org/components/toolchain/binaries/ Host Requirements ================== Linaro officially supports the current and previous Ubuntu LTS releases (as of the time of this release). This does not mean that the toolchain will not work on other/older Linux distributions. See the following for the life-time of Ubuntu LTS releases. https://wiki.ubuntu.com/Releases The host system upon which the cross-compiler will run requires a minimum of glibc 2.14, because of API changes to glibc's memcpy API. https://bugs.linaro.org/show_bug.cgi?id=1869 Package Versions ================= Linaro GCC 6.1-2016.08-rc2 http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.08-rc2/ FSF glibc 2.23 (linaro/2.23) https://www.sourceware.org/ml/libc-alpha/2016-08/msg00212.html Linaro newlib 2.4.0-2016.03 (linaro-2.4-branch) Linaro binutils 2.27 (linaro_binutils-2_27-branch) https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=bin… FSF GDB 7.11 (binutils-gdb.git~gdb-7.11-branch) https://lists.gnu.org/archive/html/info-gnu/2016-02/msg00010.html Linaro toolchain package git branches are hosted at: http://git.linaro.org/?a=project_list&s=toolchain%2F&btnS=Search NEWS for Linaro GCC 6.1-2016.08-rc2 ==================================== * Copy the libwinpthread DLL into the bin directories so it gets into the tmp directory before tar is run. https://review.linaro.org/#/c/13723/ * Include GNU Assembler fix for PR 20364 commit 5fe7ebe5ab43750abf8f490b785d99a1e598e7fd Author: Nick Clifton <nickc(a)redhat.com> Date: Fri Aug 5 10:37:57 2016 +0100 Fix the generation of alignment frags in code sections for AArch64. https://sourceware.org/bugzilla/show_bug.cgi?id=20364 * Performance related backports from Linaro GCC 6.1-2016.06, and Linaro GCC 6.1-2016.07 have been included. See the following Linaro GCC snapshots: http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.06/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.07/ Contact Linaro =============== File bugs at http://bugs.linaro.org For Linaro member support see http://support.linaro.org For Linaro community support email linaro-toolchain(a)lists.linaro.org -- Ryan S. Arnold | Linaro Toolchain Engineering Manager ryan.arnold(a)linaro.org | ryanarn on #linaro-tcwg @ freenode.irc.net

8 years, 10 months

Heads-up: big.LITTLE and cache flushing

by Riku Voipio

Hi, As painfully found out by mono team, if big/little cores have different cache line sizes, __clear_cache doesn't work as expected. This affects any home-grown cache flushing mechanism as well. http://www.mono-project.com/news/2016/09/12/arm64-icache/ protip, if you suspect your application issues might related to big.LITTLE, use taskset(1) or hwloc-bind(1) to tie the process to either big or little cluster (or just a single core).

8 years, 10 months

[Activity] 5 - 8 Sept 2016

by Peter Smith

== Progress == - Still trying to get support for .ARM.exidx into upstream LLD, looks like more changes are needed by the owners, but I think I should be able to get this by the next report. - LLVM Cauldron on Thursday. Trip report sent separately - Holiday on Friday == Next week == Planned: - ARM Exceptions support in lld - Further lld porting work

8 years, 10 months

[ACTIVITY] 5-9 Sept 2016

by kugan

== Progress == - Connect slides - Analyzed IPA-VRP performance for slides - Started working on return jump function - Reading C++ ABI and other documents referred in Honza's blog to understand the C++ related issues in IPA/LTO = Next == - Work on IPA/LTO improvements - Benchmarking - Follow up on pending patches

8 years, 10 months

[ANNOUNCE] Linaro GCC 6 2016.09 snapshot

by Yvan Roux

The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2016.09 snapshot of the Linaro GCC 6 source package. This monthly snapshot[1] is based on FSF GCC 6.2+svn239654 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the 2016.11 stable[2] quarterly release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.09/ Interesting changes in this GCC source package snapshot include: * Backport of [Bugfix] [AArch32] PR target/53440 Handle generic thunks better for TARGET_32BIT * Backport of [Bugfix] [AArch32] PR target/59833 ARM soft-float extendsfdf2 fails to quiet signaling NaN * Backport of [Bugfix] [AArch32] PR target/70473 Reduce size of Cortex-A8 automaton * Backport of [Bugfix] [AArch32] PR target/71061 length pop* pattern in epilogue correctly * Backport of [Bugfix] [AArch32] PR target/77281 Fix an invalid check for vectors of the same floating-point constants. * Backport of [Bugfix] [AArch64] PR 64971 Convert function pointer to Pmode when emit call. * Backport of [Bugfix] [AArch64] PR 70904 Relax the restriction on subreg reload for wide mode * Backport of [Bugfix] [AArch64] PR target/63596 Honor tree-stdarg analysis result to improve VAARG codegen * Backport of [Bugfix] [AArch64] PR target/63874 vtable address generation goes through memory * Backport of [Bugfix] PR 70751 Correct the cost for spilling non-pseudo into memory * Backport of [Bugfix] PR 77421 Redundant second assignment of bb_copy = NULL in free_original_copy_tables * Backport of [Bugfix] PR middle-end/37780 Conditional expression with __builtin_clz() should be optimized out * Backport of [Bugfix] PR middle-end/68217 Wrong constant folding * Backport of [Bugfix] PR middle-end/71700 zero-extend sub-word value when widening constructor element * Backport of [Bugfix] PR rtl-optimization/66940 Avoid signed overflow in noce_get_alt_condition * Backport of [Bugfix] PR rtl-optimization/71150 Guard in_class_p with REG_P check * Backport of [Bugfix] PR rtl-optimization/71295 * Backport of [Bugfix] PR rtl-optimization/71594 ICE in noce_emit_cmove due to mismatched source modes * Backport of [Bugfix] PR rtl-optimization/71878 * Backport of [Bugfix] PR tree-optimization/61839 More optimize opportunity for VRP * Backport of [Bugfix] PR tree-optimization/71818 ICE in as_a, at is-a.h:192 w/ -O2 -ftree-vectorize * Backport of [AArch32] Keep ctz expressions together until after reload * Backport of [AArch32] Add fcsel to Cortex-A57 scheduler * Backport of [AArch32] Add initial support for Cortex-A73 * Backport of [AArch32] Add support for overflow add, sub, and neg operations * Backport of [AArch32] Add support for some ARMv8-A cores to driver-arm.c * Backport of [AArch32] arm_neon.h: s/__FAST_MATH/__FAST_MATH__/g * Backport of [AArch32] Emit vmov.i64 to load 0.0 into FP reg when neon enabled. * Backport of [AArch32] Enable __fp16 as a function parameter and return type * Backport of [AArch32] Fix aprofile multilib mappings * Backport of [AArch32] Fix predicable_short_it attribute for arm_movqi_insn * Backport of [AArch32] genmultilib: improve error reporting for MULTILIB_REUSE * Backport of [AArch32] improve Cortex-A53 integer scheduler * Backport of [AArch32] Model CSEL instruction in Cortex-A57 scheduling model * Backport of [AArch32] no-data-is-text-relative & msingle-pic-base * Backport of [AArch32] Refactor MOVW/MOVT fusion logic to allow extension * Backport of [AArch32] Replace uses of int_log2 by exact_log2 * Backport of [AArch32] Update documentation for ARM architecture * Backport of [AArch32] Use a MULTILIB_REQUIRED approach for aprofile multilib * Backport of [AArch64] 1/2 Add support INS (element) instruction to copy lanes between vectors * Backport of [AArch64] 2/2 (Re)Implement vcopy<q>_lane<q> intrinsics * Backport of [AArch64] 1/2 Improve zero extend * Backport of [AArch64] 2/2 Improve zero extend * Backport of [AArch64] 1/3 Migrate aarch64_add_constant to new interface & kill aarch64_build_constant * Backport of [AArch64] 2/3 Optimize aarch64_add_constant to generate better addition sequences * Backport of [AArch64] 3/3 Migrate aarch64_expand_prologue/epilogue to aarch64_add_constant * Backport of [AArch64] 1/6 Reimplement scalar fixed-point intrinsics * Backport of [AArch64] 2/6 Reimplement vector fixed-point intrinsics * Backport of [AArch64] 3/6 Reimplement frsqrte intrinsics * Backport of [AArch64] 4/6 Reimplement frsqrts intrinsics * Backport of [AArch64] 5/6 Reimplement fabd intrinsics & merge rtl patterns * Backport of [AArch64] 6/6 Reimplement vpadd intrinsics & extend rtl patterns to all modes * Backport of [AArch64] Accept vulcan as a cpu name for the AArch64 port of GCC * Backport of [AArch64] Add ANDS pattern for CMP+ZERO_EXTEND * Backport of [AArch64] Add commit message * Backport of [AArch64] Add initial support for Cortex-A73 * Backport of [AArch64] Add legitimize_address_displacement hook * Backport of [AArch64] Add more choices for the reciprocal square root approximation * Backport of [AArch64] Add rtx_costs routine for vulcan * Backport of [AArch64] Add some more missing intrinsics * Backport of [AArch64] Add ThunderX vector cost model * Backport of [AArch64] Allow multiple-of-8 immediate offsets for TImode LDP/STP * Backport of [AArch64] Canonicalize Cortex core tunings * Backport of [AArch64] Cleanup -mpc-relative-loads * Backport of [AArch64] Define WORD_REGISTER_OPERATIONS to zero and comment why * Backport of [AArch64] Emit division using the Newton series * Backport of [AArch64] Emit square root using the Newton series * Backport of [AArch64] Enable tree-stdarg pass for AArch64 by defining counter fields * Backport of [AArch64] Fix typo in aarch64_legitimize_address * Backport of [AArch64] Fixup to fcvt patterns added in r237200 * Backport of [AArch64] Fix vld2/3/4 on big endian systems * Backport of [AArch64] Give some new costs for Cortex-A53 floating-point operations * Backport of [AArch64] Give some new costs for Cortex-A57 floating-point operations * Backport of [AArch64] Handle AND+ASHIFT form of UBFIZ correctly in costs * Backport of [AArch64] Handle iterator definitions with conditionals in geniterator.sh * Backport of [AArch64] Improve aarch64_modes_tieable_p * Backport of [AArch64] Increase code alignment * Backport of [AArch64] Keep CTZ components together until after reload * Backport of [AArch64] Optimize prolog/epilog * Backport of [AArch64] Remove aarch64_cannot_change_mode_class * Backport of [AArch64] Remove spurious attribute __unused__ from NEON intrinsic * Backport of [AArch64] Renaming ARMv8.1 to ARMv8.1-A in comments and documentations * Backport of [AArch64] Replace insn to zero up SIMD registers * Backport of [AArch64] update vulcan L1 cacheline size * Backport of [ARMv8.2] [AArch64] 10/10 ARMv8.2-A FP16 lane scalar intrinsics * Backport of [ARMv8.2] [AArch64] 1/10 ARMv8.2-A FP16 data processing intrinsics * Backport of [ARMv8.2] [AArch64] 2/10 ARMv8.2-A FP16 one operand vector intrinsics * Backport of [ARMv8.2] [AArch64] 3/10 ARMv8.2-A FP16 two operands vector intrinsics * Backport of [ARMv8.2] [AArch64] 4/10 ARMv8.2-A FP16 three operands vector intrinsics * Backport of [ARMv8.2] [AArch64] 5/10 ARMv8.2-A FP16 lane vector intrinsics * Backport of [ARMv8.2] [AArch64] 6/10 ARMv8.2-A FP16 reduction vector intrinsics * Backport of [ARMv8.2] [AArch64] 7/10 ARMv8.2-A FP16 one operand scalar intrinsics * Backport of [ARMv8.2] [AArch64] 8/10 ARMv8.2-A FP16 two operands scalar intrinsics * Backport of [ARMv8.2] [AArch64] 9/10 ARMv8.2-A FP16 three operands scalar intrinsics * Backport of [ARMv8.2] [AArch64] ARMv8.2 command line and feature macros support * Backport of [Misc] 1/2 Move choose_mult_variant declaration and dependent declarations to expmed.h * Backport of [Misc] 2/2 Hook up mult synthesis logic into vectorisation of mult-by-constant * Backport of [Misc] Append "evaluates to 0" for Wundef diagnostic * Backport of [Misc] Avoid unnecessary peeling for gaps with LD3 * Backport of [Misc] Check for POINTER_TYPE_P before accessing SSA_NAME_PTR_INFO in tree-inline * Backport of [Misc] Disable ifunc on *-musl by default * Backport of [Misc] Disable setting param of __builtin_constant_p to null * Backport of [Misc] Don't count spilling cost for it offmemok * Backport of [Misc] Don't use section anchors for declarations that don't fit in a single anchor range * Backport of [Misc] Fix ChangeLog entry * Backport of [Misc] Fix GROUP_GAP for single-element interleaving * Backport of [Misc] Fix unused variable warning in simplify_cond_clz_ctz on some targets * Backport of [Misc] Increase alignment of global structs in increase_alignment pass * Backport of [Misc] Latent alignment bug in tree-ssa-address.c * Backport of [Misc] Report supported function classes correctly on *-musl * Backport of [Testsuite] 29_atomics/atomic/65913.cc: require atomic-builtins rather than specific target * Backport of [testsuite] [AArch32] Add missing guards to fp16 AdvSIMD tests * Backport of [Testsuite] [AArch32] Fix, add tests for FP16 aapcs * Backport of [Testsuite] [AArch32] Fix dg-do and dg-skip order * Backport of [Testsuite] [AArch32] gcc.target/arm/pr37780_1.c: Use arm_arch_v6t2 effective target and options * Backport of [Testsuite] [AArch32] Make arm_neon_fp16 depend on arm_neon_ok * Backport of [Testsuite] [AArch32] Selectors and options directives for ARM VFP FP16 support * Backport of [Testsuite] [AArch64] Ensure vrnd* tests run on ARMv8 cores * Backport of [Testsuite] Add testcases * Backport of [testsuite] asan/clone-test-1.c: Handle clone() failure * Backport of [Testsuite] Fix testcases * Backport of [Testsuite] Use setrlimit for testing libstdc++ in cross toolchains * Backport of [Cleanup] [AArch32] 2/4 Replace casts of 1 to HOST_WIDE_INT by HOST_WIDE_INT_1 and HOST_WIDE_INT_1U * Backport of [Cleanup] [AArch32] 3/4 Cleanup casts from INTVAL to [unsigned] HOST_WIDE_INT * Backport of [Cleanup] [AArch32] 4/4 Simplify checks for CONST_INT_P and comparison against 1/0 * Backport of [cleanup] [AArch32] Delete thumb_reload_in_h * Backport of [Cleanup] [AArch32] Remove non-existent extern declarations in arm.h * Backport of [Cleanup] [AArch64] aarch64_elf_asm_named_section: Remove declaration. * Backport of [Cleanup] [AArch64] Clean up parentheses and use GET_MODE_UNIT_BITSIZE in a couple of patterns * Backport of [Cleanup] [AArch64] Remove static variable all_extensions from aarch64.c * Backport of [Cleanup] Cleanup frame push/pop code * Backport of [Cleanup] rtlanal.c: Convert conditional compilation on WORD_REGISTER_OPERATIONS * Backport of [Debug] ifcvt: Print name of noce trasform that succeeded in dump file Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list": http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in bugzilla against GCC product: http://bugs.linaro.org/enter_bug.cgi?product=GCC * Interested in commercial support? inquire at "Linaro support": mailto:support@linaro.org [1]. Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed. [2]. Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed.

8 years, 10 months

Question on "Using deprecated CP15 barrier instruction".

by stimits＠comcast.net

Hi, For reference, the following questions refer to a Linux 3.10 aarch64 kernel (ARMv8, ARMv8-A) compiled with Linaro 5.3-2016.02 (5.3-2016.02 arm64 CROSS_COMPILE and 5.3-2016.02 armhf CROSS32CC cross compiled from x86_64). This Linux kernel compile requires the full 64-bit tool chain plus the 32-bit gcc. There is a Linux kernel file "arch/arm64/kernel/deprecated.c". Within that file is a block of code which is apparently designed to detect some sort of older obsolete 32-bit code. Specifically, the warning message is "Using deprecated CP15 barrier instruction". I wouldn't think that this kernel, when compiled with such a recent compiler, would ever introduce CP15 barrier code (from what I see barrier code was deprecated in ARMv7 and used to deal with obsolete ARMv6 code). Is there any chance the 32-bit 5.3 gcc would still generate CP15 barrier code? Although this kernel and "most" modules are built with Linaro 5.3 I'd like to be able to narrow the cause down to existing binary modules not compiled with the 5.3 Linaro. If I can guarantee 5.3 32-bit gcc does not produce the CP15 barrier instruction then I'll know it is in pre-built binary modules. Can anyone tell me if C code compiled from Linaro version 5.3 32-bit gcc code would ever contain CP15 instructions? Thanks!

8 years, 10 months

RE: Question on "Using deprecated CP15 barrier instruction".

by stimits＠comcast.net

What I need to confirm is if the Linaro 5.3 would generate such code from a normal block of C without any kind of asm in it? Detecting the code is part of the kernel...I need to figure out where it was generated. Is Linaro 5.3 going to generate such code without explicitly writing it in? ----- Original Message -----From: Andrew Pinski <Andrew.Pinski(a)cavium.com>To: stimits(a)comcast.net, Linaro Toolchain Mailman List <linaro-toolchain(a)lists.linaro.org>Sent: Mon, 05 Sep 2016 17:21:24 -0000 (UTC)Subject: RE: Question on "Using deprecated CP15 barrier instruction". Simple answer is yes. There are a lot of assembly out there and someone (seen it in the past) could have used this barrier method in their code and not really thought it was going to change in the future. Thanks, Andrew From: linaro-toolchain [mailto:linaro-toolchain-bounces@lists.linaro.org]On Behalf Of stimits(a)comcast.netSent: Monday, September 5, 2016 8:10 AMTo: Linaro Toolchain Mailman List <linaro-toolchain(a)lists.linaro.org>Subject: Question on "Using deprecated CP15 barrier instruction". Hi, For reference, the following questions refer to a Linux 3.10 aarch64 kernel (ARMv8, ARMv8-A) compiled with Linaro5.3-2016.02 (5.3-2016.02 arm64 CROSS_COMPILE and 5.3-2016.02 armhf CROSS32CC cross compiled from x86_64). This Linux kernel compile requires the full 64-bit tool chain plus the 32-bit gcc. There is a Linux kernel file "arch/arm64/kernel/deprecated.c". Within that file is a block of code which is apparently designed to detect some sort of older obsolete 32-bit code. Specifically, the warning message is "Using deprecated CP15 barrier instruction". I wouldn't think that this kernel, when compiled with such a recent compiler, would ever introduce CP15 barrier code (from what I see barrier code was deprecated in ARMv7 and used to deal with obsolete ARMv6 code). Is there any chance the 32-bit 5.3 gcc would still generate CP15 barrier code? Although this kernel and "most" modules are built with Linaro 5.3 I'd like to be able to narrow the cause down to existing binary modules not compiled with the 5.3 Linaro. If I can guarantee 5.3 32-bit gcc does not produce the CP15 barrier instruction then I'll know it is in pre-built binary modules. Can anyone tell me if C code compiled from Linaro version 5.3 32-bit gcc code would ever contain CP15 instructions? Thanks!

8 years, 10 months

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