o 4 days week.
o LLVM
* 7.0.1-rc2:
- Built ARM and AArch64 binaries
- Investigating miscompare on AArch64
* Machine Outliner on ARM prototype:
- Investigating issues in PIC mode
- Testing IR Outliner
o Misc
* Various meetings and discussions.
[VIRT-241 # QEMU ARMv8.x support ]
The new ARM ARM was released (DDI0487 D_a) including ARMv8.4.
Add jira cards for all of the v8.4 features. Rearrange all of
the stories into a hierarchy so that it's easier to track which
cards belong to which architecture revision.
[VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ]
Working my way through this rather large extension:
* Cleanup (most) direct uses of hcr_el2.
* Add new hypervisor virtual timer.
* Add contextidr_el2 and use it in breakpoint matching.
* Add system register aliasing and redirection.
* Added a new mmu_idx for the NS EL2&0 regime;
working through all the places that should be handled.
[Upstream]
Posted kvm-vs-idregs patch set v3.
r~
== Progress ==
* FDPIC
- Cortex-M uClibc-ng patch still pending
- GCC: handling feedback on v3 patches.
Managed to build/check xtensa uclinux toolchain with my patches.
Largely better, but a few new failures.
- working on kernel + qemu-system env to run more tests. Got help from
Nicolas Pitre.
* GCC upstream validation:
- reported a few regressions
- dealing with some random results, again
* GCC:
- bug report on aarch64 about misaligned accesses. Waiting for more
details to reproduce the problem.
* misc (conf-calls, meetings, emails, ....)
- reviewing infra script patches
== Next ==
FDPIC:
- GCC: followup v3 patches
- uclibc-ng: look at how to test fdpic mode with openadk
- use qemu-system mode to run more tests
Progress:
* VIRT-65 [QEMU upstream maintainership]
- code review
+ more microbit device models
+ some raspi device model improvements
- sent patches for more Coverity issue fixes
- put together a list of source files still with legacy
non-QOM device models (about 60 files total)
- tagged QEMU 3.1.0 rc0
* VIRT-251 [aarch32 Hyp/running microvisors]
- tracked down a regression affecting L4Re guest: we had
misimplemented HCR.{VI,VF}. Sent patchset reverting the
broken version and implementing the correct semantics.
- finally tracked down why the 32-bit version of L4Re/Fiasco was
crashing -- we were incorrectly implementing Hyp mode as having
a banked r14, but it shares that register with User and System modes.
- These patches fix all the known issues with these guests.
thanks
-- PMM
=== Work done during the past week ===
* Resurrect code size optimization for fmul/dmul from Tony Wang:
+ clean up new testsuite directive andd testcases
* Fix -mslow-flash-data:
+ resurrect / rebase Arm internal patch to fix -mslow-flash-data
once and for all
+ many fixes to make it pass all testsuite with -mslow-flash-data without ICE
* Line management.
=== Plan for week 45 ===
* LLVM-432 (Support arithmetic on FileCheck regex variable):
+ extend testcase coverage (add tests for latest syntax change and
add more negative testing)
+ finish cleaning up the code
* Try to reproduce perf issue mentioned in week #30's weekly report on
latest perf
o Two days off.
o LLVM
* Machine Outliner on ARM prototype:
- catch-up after vacation
- re-based prototype branch on upstream
- Investigating issues in PIC mode
== This Week ==
* PR83750: CSE erf/erfc pair (6/10)
- Submitted patch upstream
* SVE ACLE (2/10)
- Started working on shift intrinsics
* GNU-235 (1/10)
- Cancelled card after I realized vrp does not support floating point ranges -:/
* Misc (1/10)
- Meetings
== Next Week ==
- PR83750: Address upstream comments
- GNU-405: Benchmark patch to provide more evidence to make it acceptable.
- SVE ACLE: Continue work on shift intrinsics.
[VIRT-241 # QEMU ARMv8.3 support ]
Finished filling out the sub-tasks for v8.3. Added some implementation
notes to some of those tasks as I reread the relevant documentation.
[VIRT-246 # ARMv8.1-LOR Limited Ordering Regions ]
Posted a trivial implementation.
[VIRT-247 # ARMv8.1-HPD and ARMv8.2-AA32HPD ]
Posted.
[Upstream]
Dirty tlb patches and decodetree changes squeeked in for softfreeze.
Another round of tlb flush reduction for aa64. This time exposing
asid's to the softmmu core and allowing it to flush when necessary.
Some more work toward moving x86 softmmu load sequences out of line.
The bulk of the code for 32-bit is now written, but it doesn't work yet.
Fix my thinko wrt divdeu and power7.
[GCC]
The cleanup part of my atomics patch set has been approved and committed.
Posted v3 of the out-of-line atomics part as well.
r~
