On Wed, Feb 25, 2026 at 01:42:19PM +0000, Bryan O'Donoghue wrote:

On 23/02/2026 19:08, Ekansh Gupta wrote:

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User-space staging branch

https://github.com/qualcomm/fastrpc/tree/accel/staging

What would be really nice to see would be mesa integration allowing convergence of the xDSP/xPU accelerator space around something like a standard.

I'd say, writing Mesa compiler to build Hexagon code for Teflon frontend would be a nice item. It would probably also allow us to use DSPs for OpenCL acceleration. But, I'd say, it's a separate topic.

See: https://blog.tomeuvizoso.net/2025/07/rockchip-npu-update-6-we-are-in-mainlin...

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bod