Add the node for Neutron NPU. Also add a reserved memory region for allocating Neutron buffers, which have a 1MB alignment constraint.
Signed-off-by: Jiwei Fu jiwei.fu@nxp.com Signed-off-by: Ioana Ciocoi-Radulescu ruxandra.radulescu@nxp.com --- v2: Match changes in dt bindings --- arch/arm64/boot/dts/freescale/imx95.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 55e2da094c88..1c6865a8d482 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -336,6 +336,19 @@ sram1: sram@204c0000 { #size-cells = <1>; };
+ reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + neutron_pool: neutron-pool { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + alignment = <0x0 0x100000>; + reusable; + }; + }; + firmware { scmi { compatible = "arm,scmi"; @@ -2181,5 +2194,20 @@ ddr-pmu@4e090dc0 { reg = <0x0 0x4e090dc0 0x0 0x200>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; }; + + neutron: npu@4ab00000 { + compatible = "nxp,imx95-neutron"; + reg = <0x0 0x4ab00000 0x0 0x00000400>, + <0x0 0x4ab10000 0x0 0x00010000>, + <0x0 0x4ab08000 0x0 0x00008000>; + reg-names = "regs", "itcm", "dtcm"; + memory-region = <&neutron_pool>; + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX95_CLK_NPU>, + <&scmi_clk IMX95_CLK_NPUAPB>; + clock-names = "core", "apb"; + power-domains = <&scmi_devpd IMX95_PD_NPU>; + iommus = <&smmu 0xd>; + }; }; };