Hi Aniket,
On Fri, Apr 10, 2026 at 03:49:49PM +0530, Aniket Randive wrote:
In GPI mode, the I2C GENI driver programs an extra TX DMA transfer descriptor (TRE) on the TX channel when handling a single read message. This results in an unintended write phase being issued on the I2C bus, even though a read transaction does not require any TX data.
For a single-byte read, the correct hardware sequence consists of the CONFIG and GO commands followed by a single RX DMA TRE. Programming an additional TX DMA TRE is redundant, causes unnecessary DMA buffer mapping on the TX channel, and may lead to incorrect bus behavior.
Update the transfer logic to avoid programming a TX DMA TRE for single read messages in GPI mode.
Co-developed-by: Maramaina Naresh naresh.maramaina@oss.qualcomm.com Signed-off-by: Maramaina Naresh naresh.maramaina@oss.qualcomm.com Signed-off-by: Aniket Randive aniket.randive@oss.qualcomm.com
merged to i2c/i2c-host.
Thank you and thanks Mukesh for the review.
Andi