CoreSight

coresight@lists.linaro.org

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2338 discussions

Re: [PATCH v4 3/4] arm64: dts: juno: add CoreSight support for Juno r1/r2 variants

by Suzuki K Poulose

On 17/01/17 12:15, Sudeep Holla wrote: > From: Mike Leach <mike.leach(a)linaro.org> > > The CoreSight support added for Juno is valid for only Juno r0. > The Juno r1 and r2 variants have additional components and alternative > connection routes between trace source and sinks. > > This patch builds on top of the existing r0 support and extends it to > Juno r1/r2 variants. > > Reviewed-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Signed-off-by: Mike Leach <mike.leach(a)linaro.org> > [sudeep.holla(a)arm.com: minor changelog update and major reorganisation of > the common coresight components back into juno-base.dtsi to avoid > duplication, also renamed funnel node names] > Signed-off-by: Sudeep Holla <sudeep.holla(a)arm.com> > --- > arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi | 100 ++++++++++++++++++++++++++++++ > arch/arm64/boot/dts/arm/juno-r1.dts | 9 +++ > arch/arm64/boot/dts/arm/juno-r2.dts | 9 +++ > 3 files changed, 118 insertions(+) > create mode 100644 arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi > > diff --git a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi > new file mode 100644 > index 000000000000..563463ed28c7 > --- /dev/null > +++ b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi > @@ -0,0 +1,100 @@ > +/ { > + funnel@20130000 { /* cssys2 */ Typo, that should be csys1. Rest looks good to me. Reviewed-by: Suzuki K Poulose <suzuki.poulose(a)arm.com>

8 years, 3 months

[PATCH] makefile: Support to cross compile for arm/arm64

by Chunyan Zhang

In order to support cross compile the OpenCSD for arm/arm64, this patch added two environment variables, 'CROSS_COMPILE' and 'ARCH' which can be set by users before compiling the code. Like documented in Kernel Makefile, CROSS_COMPILE specifies the prefix used for all executables used during compilation. CROSS_COMPILE can be set on the command line, as is ARCH. For example, if you want to build the libraryies for Aarch64, you can set "ARCH=arm64", the the compiled libs will be located at lib/linux-arm64/<rel\dbg>.` Signed-off-by: Chunyan Zhang <zhang.chunyan(a)linaro.org> --- decoder/build/linux/makefile | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/decoder/build/linux/makefile b/decoder/build/linux/makefile index 3b6a623..dc1f32b 100644 --- a/decoder/build/linux/makefile +++ b/decoder/build/linux/makefile @@ -47,7 +47,11 @@ export LIB_CAPI_NAME # determine base architecture, heavily borrowed from the Linux kernel v4.4's # tools/perf/config/Makefile.arch +# For example, to compile for arm64 on a X86 PC, you can issue the command: +# "export ARCH=arm64" +ifndef ARCH ARCH := $(shell uname -m 2>/dev/null || echo not) +endif # source root directories export OCSD_LIB_ROOT=$(OCSD_ROOT)/lib @@ -58,10 +62,10 @@ export OCSD_SOURCE=$(OCSD_ROOT)/source export OCSD_TESTS=$(OCSD_ROOT)/tests # tools -export MASTER_CC=gcc -export MASTER_CPP=g++ -export MASTER_LINKER=g++ -export MASTER_LIB=ar +export MASTER_CC=$(CROSS_COMPILE)gcc +export MASTER_CPP=$(CROSS_COMPILE)g++ +export MASTER_LINKER=$(CROSS_COMPILE)g++ +export MASTER_LIB=$(CROSS_COMPILE)ar # compile flags MASTER_CC_FLAGS := -c -Wall -DLINUX @@ -87,6 +91,10 @@ ifeq ($(ARCH),x86) else ifeq ($(ARCH),x86_64) MFLAG:="-m64" BIT_VARIANT=64 +else ifeq ($(ARCH),arm) + BIT_VARIANT=-arm +else ifeq ($(ARCH),arm64) + BIT_VARIANT=-arm64 endif MASTER_CC_FLAGS += $(MFLAG) -- 2.7.4

8 years, 3 months

[PATCH v2 0/2] arm64: dts: juno: Updates for juno r1/r2 boards

by Mike Leach

Juno r1/r2 boards have different CoreSight infrastructure outside the clusters. This patchset moves the none cluster CoreSight to separate .dtsi files to allow for these differences. v2 moves the Addition of the STM component into a separate patch. Mike Leach (2): arm64: dts: juno: Fix CoreSight support for Juno r1/r2 variants arm64: dts: juno: Adds missing CoreSight STM component. arch/arm64/boot/dts/arm/juno-base.dtsi | 135 --------------- arch/arm64/boot/dts/arm/juno-cs-r0.dtsi | 166 +++++++++++++++++++ arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi | 266 ++++++++++++++++++++++++++++++ arch/arm64/boot/dts/arm/juno-r1.dts | 1 + arch/arm64/boot/dts/arm/juno-r2.dts | 1 + arch/arm64/boot/dts/arm/juno.dts | 1 + 6 files changed, 435 insertions(+), 135 deletions(-) create mode 100644 arch/arm64/boot/dts/arm/juno-cs-r0.dtsi create mode 100644 arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi -- 2.7.4

8 years, 3 months

[PATCH] arm64: dts: juno: Fix CoreSight support for Juno r1/r2 variants

by Mike Leach

The CoreSight support added for Juno is valid for only Juno r0. The Juno r1 and r2 variants have additional components and alternative connection routes between trace source and sinks. The CoreSight infrastructure external to the Cortex-Axx clusters, has been split into separate .dtsi include files for r0 and r1/r2 to correctly represent these variations. Adds missing DT entry for the CoreSight STM component in the infrastructure .dtsi files. Signed-off-by: Mike Leach <mike.leach(a)linaro.org> --- arch/arm64/boot/dts/arm/juno-base.dtsi | 135 --------------- arch/arm64/boot/dts/arm/juno-cs-r0.dtsi | 166 +++++++++++++++++++ arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi | 266 ++++++++++++++++++++++++++++++ arch/arm64/boot/dts/arm/juno-r1.dts | 1 + arch/arm64/boot/dts/arm/juno-r2.dts | 1 + arch/arm64/boot/dts/arm/juno.dts | 1 + 6 files changed, 435 insertions(+), 135 deletions(-) create mode 100644 arch/arm64/boot/dts/arm/juno-cs-r0.dtsi create mode 100644 arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 7d83224..7c89000 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -83,104 +83,6 @@ * The actual size is just 4K though 64K is reserved. Access to the * unmapped reserved region results in a DECERR response. */ - etf@20010000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x20010000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* input port */ - port@0 { - reg = <0>; - etf_in_port: endpoint { - slave-mode; - remote-endpoint = <&main_funnel_out_port>; - }; - }; - - /* output port */ - port@1 { - reg = <0>; - etf_out_port: endpoint { - remote-endpoint = <&replicator_in_port0>; - }; - }; - }; - }; - - tpiu@20030000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0 0x20030000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - port { - tpiu_in_port: endpoint { - slave-mode; - remote-endpoint = <&replicator_out_port0>; - }; - }; - }; - - main-funnel@20040000 { - compatible = "arm,coresight-funnel", "arm,primecell"; - reg = <0 0x20040000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - main_funnel_out_port: endpoint { - remote-endpoint = <&etf_in_port>; - }; - }; - - port@1 { - reg = <0>; - main_funnel_in_port0: endpoint { - slave-mode; - remote-endpoint = <&cluster0_funnel_out_port>; - }; - }; - - port@2 { - reg = <1>; - main_funnel_in_port1: endpoint { - slave-mode; - remote-endpoint = <&cluster1_funnel_out_port>; - }; - }; - - }; - }; - - etr@20070000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x20070000 0 0x1000>; - iommus = <&smmu_etr 0>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - port { - etr_in_port: endpoint { - slave-mode; - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - etm0: etm@22040000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x22040000 0 0x1000>; @@ -351,43 +253,6 @@ }; }; - coresight-replicator { - /* - * Non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-replicator"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&etr_in_port>; - }; - }; - - /* replicator input port */ - port@2 { - reg = <0>; - replicator_in_port0: endpoint { - slave-mode; - remote-endpoint = <&etf_out_port>; - }; - }; - }; - }; - sram: sram@2e000000 { compatible = "arm,juno-sram-ns", "mmio-sram"; reg = <0x0 0x2e000000 0x0 0x8000>; diff --git a/arch/arm64/boot/dts/arm/juno-cs-r0.dtsi b/arch/arm64/boot/dts/arm/juno-cs-r0.dtsi new file mode 100644 index 0000000..4e01b0e --- /dev/null +++ b/arch/arm64/boot/dts/arm/juno-cs-r0.dtsi @@ -0,0 +1,166 @@ + /* + * Juno trace infrastructure. + * Trace links and sinks and interconnections + * from clusters. + * Connections for Juno r0. + */ + etf@20010000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x20010000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* input port */ + port@0 { + reg = <0>; + etf_in_port: endpoint { + slave-mode; + remote-endpoint = <&main_funnel_out_port>; + }; + }; + + /* output port */ + port@1 { + reg = <0>; + etf_out_port: endpoint { + remote-endpoint = <&replicator_in_port0>; + }; + }; + }; + }; + + tpiu@20030000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0 0x20030000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + port { + tpiu_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + + main-funnel@20040000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0x20040000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* output port */ + port@0 { + reg = <0>; + main_funnel_out_port: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + + /* input ports */ + port@1 { + reg = <0>; + main_funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&cluster0_funnel_out_port>; + }; + }; + + port@2 { + reg = <1>; + main_funnel_in_port1: endpoint { + slave-mode; + remote-endpoint = <&cluster1_funnel_out_port>; + }; + }; + + port@3 { + reg = <2>; + main_funnel_in_port2: endpoint { + slave-mode; + remote-endpoint = <&stm_out_port>; + }; + }; + + + }; + }; + + etr@20070000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x20070000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + port { + etr_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + + coresight-replicator { + /* + * Non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-replicator"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + + /* replicator input port */ + port@2 { + reg = <0>; + replicator_in_port0: endpoint { + slave-mode; + remote-endpoint = <&etf_out_port>; + }; + }; + }; + }; + + stm@20100000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x20100000 0 0x1000>, + <0 0x28000000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + port { + stm_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port2>; + }; + }; + }; diff --git a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi new file mode 100644 index 0000000..6fe8b62 --- /dev/null +++ b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi @@ -0,0 +1,266 @@ + /* + * Juno trace infrastructure. + * Trace links and sinks and interconnections + * from clusters. + * Connections for Juno r1 and r2. + */ + etf0@20010000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x20010000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* input port */ + port@0 { + reg = <0>; + etf0_in_port: endpoint { + slave-mode; + remote-endpoint = <&main_funnel_out_port>; + }; + }; + + /* output port */ + port@1 { + reg = <0>; + etf0_out_port: endpoint { + remote-endpoint = <&csys2_funnel_in_port0>; + }; + }; + }; + }; + + etf1@20140000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x20140000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* input port */ + port@0 { + reg = <0>; + etf1_in_port: endpoint { + slave-mode; + remote-endpoint = + <&csys1_funnel_out_port>; + }; + }; + + /* output port */ + port@1 { + reg = <0>; + etf1_out_port: endpoint { + remote-endpoint = + <&csys2_funnel_in_port1>; + }; + }; + }; + }; + + csys1_funnel@20130000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0x20130000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* input port */ + port@0 { + reg = <0>; + csys1_funnel_out_port: endpoint { + remote-endpoint = + <&etf1_in_port>; + }; + }; + + /* output port */ + port@1 { + reg = <0>; + csys1_funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = + <&stm_out_port>; + }; + }; + + }; + }; + + csys2_funnel@20150000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0x20150000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* output port */ + port@0 { + reg = <0>; + csys2_funnel_out_port: endpoint { + remote-endpoint = + <&replicator_in_port0>; + }; + }; + + /* input ports */ + port@1 { + reg = <0>; + csys2_funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&etf0_out_port>; + }; + }; + + port@2 { + reg = <1>; + csys2_funnel_in_port1: endpoint { + slave-mode; + remote-endpoint = <&etf1_out_port>; + }; + }; + + }; + }; + + tpiu@20030000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0 0x20030000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + port { + tpiu_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + + /* + * This is labelled cssys0 funnel in the Juno r1/r2 TRM + * Retain the name from r0 to maintain compatibility with common + * juno-base.dtsi + */ + main-funnel@20040000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0x20040000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* output port */ + port@0 { + reg = <0>; + main_funnel_out_port: endpoint { + remote-endpoint = <&etf0_in_port>; + }; + }; + + /* input ports */ + port@1 { + reg = <0>; + main_funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&cluster0_funnel_out_port>; + }; + }; + + port@2 { + reg = <1>; + main_funnel_in_port1: endpoint { + slave-mode; + remote-endpoint = <&cluster1_funnel_out_port>; + }; + }; + }; + }; + + etr@20070000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x20070000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + port { + etr_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + + coresight-replicator { + /* + * Non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-replicator"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + + /* replicator input port */ + port@2 { + reg = <0>; + replicator_in_port0: endpoint { + slave-mode; + remote-endpoint = <&csys2_funnel_out_port>; + }; + }; + }; + }; + + stm@20100000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x20100000 0 0x1000>, + <0 0x28000000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + port { + stm_out_port: endpoint { + remote-endpoint = <&csys1_funnel_in_port0>; + }; + }; + }; diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts index eec37fe..8813395 100644 --- a/arch/arm64/boot/dts/arm/juno-r1.dts +++ b/arch/arm64/boot/dts/arm/juno-r1.dts @@ -178,6 +178,7 @@ }; #include "juno-base.dtsi" + #include "juno-cs-r1r2.dtsi" }; &memtimer { diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts index 28f40ec..fca3a17 100644 --- a/arch/arm64/boot/dts/arm/juno-r2.dts +++ b/arch/arm64/boot/dts/arm/juno-r2.dts @@ -178,6 +178,7 @@ }; #include "juno-base.dtsi" + #include "juno-cs-r1r2.dtsi" }; &memtimer { diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts index ac5ceb7..c90c37b 100644 --- a/arch/arm64/boot/dts/arm/juno.dts +++ b/arch/arm64/boot/dts/arm/juno.dts @@ -178,6 +178,7 @@ }; #include "juno-base.dtsi" + #include "juno-cs-r0.dtsi" }; &etm0 { -- 2.7.4

8 years, 4 months

[PATCH] Add documentation on AutoFDO

by Sebastian Pop

The patch adds documentation to HOWTO.md on how to use CoreSight ETM to perform Feedback Directed Optimization. Sebastian Pop (1): HOWTO: add example of how to extract coverage files for autoFDO HOWTO.md | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) -- 2.6.3

8 years, 4 months

[PATCH v2] coresight: etm4x: Fix enabling of cycle accurate tracing in perf.

by Mike Leach

Using perf record 'cyclacc' option in cs_etm event was not setting up cycle accurate trace correctly. Corrects bit set in TRCCONFIGR to enable cycle accurate trace. Programs TRCCCCTLR with a valid threshold value as required by ETMv4 spec. Signed-off-by: Mike Leach <mike.leach(a)linaro.org> --- drivers/hwtracing/coresight/coresight-etm4x.c | 7 +++++-- drivers/hwtracing/coresight/coresight-etm4x.h | 1 + 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 4db8d6a..c5a65d1 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -216,8 +216,11 @@ static int etm4_parse_event_config(struct etmv4_drvdata *drvdata, goto out; /* Go from generic option to ETMv4 specifics */ - if (attr->config & BIT(ETM_OPT_CYCACC)) - config->cfg |= ETMv4_MODE_CYCACC; + if (attr->config & BIT(ETM_OPT_CYCACC)) { + config->cfg |= BIT(4); + /* TRM: Must program this for cycacc to work */ + config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT; + } if (attr->config & BIT(ETM_OPT_TS)) config->cfg |= ETMv4_MODE_TIMESTAMP; diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index ba8d3f8..b3b5ea7 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -146,6 +146,7 @@ #define ETM_ARCH_V4 0x40 #define ETMv4_SYNC_MASK 0x1F #define ETM_CYC_THRESHOLD_MASK 0xFFF +#define ETM_CYC_THRESHOLD_DEFAULT 0x100 #define ETMv4_EVENT_MASK 0xFF #define ETM_CNTR_MAX_VAL 0xFFFF #define ETM_TRACEID_MASK 0x3f -- 2.7.4

8 years, 4 months

Fwd: [PATCH] coresight: etm4x: Fix enabling of cycle accurate tracing in perf.

by Mike Leach

---------- Forwarded message ---------- From: Mike Leach <mike.leach(a)linaro.org> Date: 2 January 2017 at 22:55 Subject: [PATCH] coresight: etm4x: Fix enabling of cycle accurate tracing in perf. To: mathieu.poirier(a)linaro.org Cc: linux-arm-kernel(a)lists.infradead.org, coresignt(a)lists.linaro.org, Mike Leach <mike.leach(a)linaro.org> Using perf record 'cyclacc' option in cs_etm event was not setting up cycle accurate trace correctly. Corrects bit set in TRCCONFIGR to enable cycle accurate trace. Programs TRCCCCTLR with a valid threshold value as required by ETMv4 spec. Signed-off-by: Mike Leach <mike.leach(a)linaro.org> --- drivers/hwtracing/coresight/coresight-etm4x.c | 7 +++++-- drivers/hwtracing/coresight/coresight-etm4x.h | 1 + 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 4db8d6a..07be032 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -216,8 +216,11 @@ static int etm4_parse_event_config(struct etmv4_drvdata *drvdata, goto out; /* Go from generic option to ETMv4 specifics */ - if (attr->config & BIT(ETM_OPT_CYCACC)) - config->cfg |= ETMv4_MODE_CYCACC; + if (attr->config & BIT(ETM_OPT_CYCACC)) { + config->cfg |= BIT(4); + /* TRM: Must program this for cycacc to work */ + config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT; + } if (attr->config & BIT(ETM_OPT_TS)) config->cfg |= ETMv4_MODE_TIMESTAMP; diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index ba8d3f8..8a62c6c 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -146,6 +146,7 @@ #define ETM_ARCH_V4 0x40 #define ETMv4_SYNC_MASK 0x1F #define ETM_CYC_THRESHOLD_MASK 0xFFF +#define ETM_CYC_THRESHOLD_DEFAULT 256 #define ETMv4_EVENT_MASK 0xFF #define ETM_CNTR_MAX_VAL 0xFFFF #define ETM_TRACEID_MASK 0x3f -- 2.7.4 -- Mike Leach Principal Engineer, ARM Ltd. Blackburn Design Centre. UK

8 years, 4 months

Re: My Dragonboard not working

by Mathieu Poirier

On 8 December 2016 at 02:04, Chunyan Zhang <zhang.chunyan(a)linaro.org> wrote: > > Hi Nicolas, > > On 8 December 2016 at 16:07, Nicolas GUION <nicolas.guion(a)st.com> wrote: > >> Chunyan, >> >> No problem and it offers me the opportunity to inform you that this last >> months in ST I worked on ARM coresight trace. >> >> Several month ago I contacted Mathieu about ARM STM coresight feature. >> Actually this year we started a new SOC project Accorod5, around A7ss and >> of course with integration of ARM coresight components. Mathieu described >> me the status in january, the next steps and especially added me in the >> group for all patch dedicated to this topic. >> >> >> So I followed the progression of the patch set delivery in official linux >> stream, and in october I started the integration of this topic in our BSP >> (based form 4.1) >> >> -update the both components (stm_class/coresight) of hwtracing from >> recent kernel in our old kernel. >> -integrate the on-going ftrace patch (it was the version 6) >> >> > So happy to know you have been following the progress of this patch > series, Steven Rostedt has included these for next merge window, it's > supposed to be merged into 4.10. > git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace.git > <http://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace.gitfor-n…> > for-next > >> >> One difference with the Linaro usage that your team usually describes is >> the capture way, instead to use the target itself >> we configure the stm to tpiu directly (skip ETF path) and use an external >> probe to capture the trace (Lauterbach tool), >> (to cover a long trace session, get the trace for kernel >> crash/deadlock...) >> > > As an assignee from Spreadtrum, I believe that Spreadtrum also would need > this functionality. > Hello Nicolas, First and foremost congratulation on the very good integration work. I have been adamant on that point many times before and today won't be different - ST has really good tracing technology and knowledge. You guys have been working on this for a very long time and the results are there. Au plaisir, Mathieu > >> Here is a view of the T32 output with 2 masters (Cortex A7 and Cortex >> M3), and 2 STM client for A7 part (Kernel log and FTRACE) >> > That's amazing, but I haven't seen the snapshot you mentioned here :) > > >> this snaphot is not the last version, now the Timestamp are correctly >> handled and the differentiation between the both A7 CPUs has been deported >> on STMchannel due to a regression of our SOC >> (our SOC didn't implement correctly the AHB link between the both A7 >> master to STM, so I used the even channel for A7_0 and odd channel for >> A7_1, it was more or less the only modification from your patch) >> >> >> Thanks for sharing, > Chunyan > >> >> *Great Job for all this coresight trace development!* >> >> >> br >> >> Nicolas >> >> >> >> On 12/08/2016 08:30 AM, Chunyan Zhang wrote: >> >> >> >> On 8 December 2016 at 15:04, Nicolas GUION <nicolas.guion(a)st.com> wrote: >> >>> Hi Chunyan, >>> >>> Are you sure that you pointed the correct Nicolas, cause I'm really far >>> to know the Dragonboard 410c board? >>> >> >> Ah, my mistake, thanks for telling me :) >> >> Chunyan >> >> >>> I'm working in STMicroelectronics and not usual with other boards than >>> ST ones. >>> >>> br >>> Nicolas >>> >>> >>> On 12/08/2016 07:24 AM, Chunyan Zhang wrote: >>> >>> Hi Nicolas, >>> >>> I noticed on 96boards forum, some person reported a similar problem "*Dragonboard >>> not working after failed linux instalation*" [1] which has been >>> annoying me recently. >>> >>> I posted some details on that page the day before yesterday. Could you >>> give me some suggestion on how to retrieve my Dragon board? >>> >>> Many thanks, >>> Chunyan >>> >>> >>> [1] http://www.96boards.org/forums/topic/dragonboard-not-working >>> -after-failed-linux-instalation/#post-18901&gsc.tab=0 >>> >>> >>> >> >> >

8 years, 4 months

non deterministic records of ETM trace

by Sebastian Pop

Hi, could somebody help me understand why the total size of the recorded ETM trace differs from run to run? Is this something in my Juno machine setup, or do you also see this? The maximum length that has been recorded is about 6MB on my setup. When I am recording the trace of the same program on intel-pt: $ perf record -e intel_pt//u ./sort the amount of captured data is deterministic (around 296MB +/- a few KB.) Thanks, Sebastian sort.c is from https://gcc.gnu.org/wiki/AutoFDO/Tutorial + gcc sort.c -o sort -O3 ++ seq 1 10 + for i in '$(seq 1 10)' + /root/etm/OpenCSD/tools/perf/perf record -e cs_etm/(a)20070000.etr/u --per-thread ./sort Bubble sorting array of 30000 elements 7779 ms [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.610 MB perf.data ] + for i in '$(seq 1 10)' + /root/etm/OpenCSD/tools/perf/perf record -e cs_etm/(a)20070000.etr/u --per-thread ./sort Bubble sorting array of 30000 elements 7789 ms [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.545 MB perf.data ] + for i in '$(seq 1 10)' + /root/etm/OpenCSD/tools/perf/perf record -e cs_etm/(a)20070000.etr/u --per-thread ./sort Bubble sorting array of 30000 elements 7797 ms [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.353 MB perf.data ] + for i in '$(seq 1 10)' + /root/etm/OpenCSD/tools/perf/perf record -e cs_etm/(a)20070000.etr/u --per-thread ./sort Bubble sorting array of 30000 elements 5949 ms [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.353 MB perf.data ] + for i in '$(seq 1 10)' + /root/etm/OpenCSD/tools/perf/perf record -e cs_etm/(a)20070000.etr/u --per-thread ./sort Bubble sorting array of 30000 elements 7807 ms [ perf record: Woken up 2 times to write data ] [ perf record: Captured and wrote 3.287 MB perf.data ] + for i in '$(seq 1 10)' + /root/etm/OpenCSD/tools/perf/perf record -e cs_etm/(a)20070000.etr/u --per-thread ./sort Bubble sorting array of 30000 elements 7772 ms [ perf record: Woken up 3 times to write data ] Warning: AUX data lost 2 times out of 4! [ perf record: Captured and wrote 0.126 MB perf.data ] + for i in '$(seq 1 10)' + /root/etm/OpenCSD/tools/perf/perf record -e cs_etm/(a)20070000.etr/u --per-thread ./sort Bubble sorting array of 30000 elements 7811 ms [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.001 MB perf.data ] + for i in '$(seq 1 10)' + /root/etm/OpenCSD/tools/perf/perf record -e cs_etm/(a)20070000.etr/u --per-thread ./sort Bubble sorting array of 30000 elements 7784 ms [ perf record: Woken up 3 times to write data ] Warning: AUX data lost 2 times out of 4! [ perf record: Captured and wrote 0.619 MB perf.data ] + for i in '$(seq 1 10)' + /root/etm/OpenCSD/tools/perf/perf record -e cs_etm/(a)20070000.etr/u --per-thread ./sort Bubble sorting array of 30000 elements 7770 ms [ perf record: Woken up 2 times to write data ] Warning: AUX data lost 1 times out of 1! [ perf record: Captured and wrote 0.002 MB perf.data ] + for i in '$(seq 1 10)' + /root/etm/OpenCSD/tools/perf/perf record -e cs_etm/(a)20070000.etr/u --per-thread ./sort Bubble sorting array of 30000 elements 5934 ms [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 1.236 MB perf.data ]

8 years, 4 months

Using perf inject to transform ETM traces into branch events

by Sebastian Pop

Hi Mathieu, perf/Documentation/intel-pt.txt describes how to make autoFDO work with Intel-PT recorded traces: # perf record -e intel_pt//u ./sort # perf inject -i perf.data -o inj --itrace=i100usl --strip # create_gcov --binary=./sort --profile=inj --gcov=sort.gcov -gcov_version=1 # gcc -O3 -fauto-profile=sort.gcov sort.c -o sort_autofdo On the ARM side, I was able to get an ETM trace, and I started working with my colleague Brian Rzycki on the second step that translates the trace into branch events. Attached is the current state of the patch that adds functionality from intel-pt.c to cs-etm.c. We are still trying to get more than one branch recorded in the branch stack before emitting an event, and it looks like what we need is to decode more than a packet at a time in cs-etm-decoder.c like in cs_etm_decoder__buffer_packet() Comments on the early version of the patch are welcome. Thanks, Sebastian

8 years, 4 months

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