CoreSight

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2666 discussions

by Michael Petlan

Hello coresight-list! I have a question about the future of OpenCSD library API. How stable is it going to be? I see there's currently v1.0, so I understand it as that there's already some API version which is considered to be "mature". Could anyone please help estimating whether major API changes are planned/to be expected in upcoming years? Thank you! Michael

5 years, 2 months

opencsd in gdb: difference between etm parser report when hitting an exception between STM32MP1 and APQ 8016e

by Zied Guermazi

hi Mike I am compiling , running and debugging a program generated from the same source code on ARMv7 and ARMv8 processors. when a breakpoint is hit, I am using the traces to reconstruct the execution flow. I noticed that on stm32 the decoder emits the address of the breakpoint in an OCSD_GEN_TRC_ELEM_INSTR_RANGE twice (before and after the exception), whereas it emits it only once (after the exception). I need to have different handling according to the situation. what can I use to distinguish both cases and handle the traces properly: - the ETM version (v3.x vs v4.x) - the CPU architecture (Cortex A v7 vs cortex A v8) - the ISA of executed program (A64 vs (A32 or T32 )) - the exception number below are the logs on stm32MP1 (ARMv7, cortex A7) [btrace] ETM trace_element: index= 12, channel= 0x10, OCSD_GEN_TRC_ELEM_INSTR_RANGE(exec range=0x103f4:[0x103f6] num_i(1) last_sz(2) (ISA=T32) E --- ) [btrace] ETM trace_element: index= 13, channel= 0x10, OCSD_GEN_TRC_ELEM_EXCEPTION(excep num (0x09) ) [btrace] ETM trace_element: index= 54, channel= 0x10, OCSD_GEN_TRC_ELEM_TRACE_ON( [begin or filter]) [btrace] ETM trace_element: index= 54, channel= 0x10, OCSD_GEN_TRC_ELEM_PE_CONTEXT((ISA=T32) N; 32-bit; ) [btrace] ETM trace_element: index= 60, channel= 0x10, OCSD_GEN_TRC_ELEM_INSTR_RANGE(exec range=0x103f4:[0x103f6] num_i(1) last_sz(2) (ISA=T32) E --- ) on qcom APQ8016e(ARMv8, Cortex A53) [btrace] ETM trace_element: index= 38, channel= 0x12, OCSD_GEN_TRC_ELEM_INSTR_RANGE(exec range=0x4005b4:[0x4005b8] num_i(1) last_sz(4) (ISA=A64) E --- ) [btrace] ETM trace_element: index= 38, channel= 0x12, OCSD_GEN_TRC_ELEM_EXCEPTION(pref ret addr:0x4005b8; excep num (0x06) ) [btrace] ETM trace_element: index= 112, channel= 0x16, OCSD_GEN_TRC_ELEM_NO_SYNC( [init-decoder]) [btrace] ETM trace_element: index= 138, channel= 0x16, OCSD_GEN_TRC_ELEM_TRACE_ON( [begin or filter]) [btrace] ETM trace_element: index= 139, channel= 0x16, OCSD_GEN_TRC_ELEM_PE_CONTEXT((ISA=A64) EL0N; 64-bit; ) [btrace] ETM trace_element: index= 150, channel= 0x16, OCSD_GEN_TRC_ELEM_INSTR_RANGE(exec range=0x4005b8:[0x4005bc] num_i(1) last_sz(4) (ISA=A64) E BR ) Kind Regards Zied Guermazi -- *Zied Guermazi* founder Trande UG Leuschnerstraße 2 69469 Weinheim/Germany Mobile: +491722645127 mailto:zied.guermazi@trande.de *Trande UG* Leuschnerstraße 2, D-69469 Weinheim; Telefon: +491722645127 Sitz der Gesellschaft: Weinheim- Registergericht: AG Mannheim HRB 736209 - Geschäftsführung: Zied Guermazi *Confidentiality Note* This message is intended only for the use of the named recipient(s) and may contain confidential and/or privileged information. If you are not the intended recipient, please contact the sender and delete the message. Any unauthorized use of the information contained in this message is prohibited.

5 years, 2 months

Invitation to Introduction to GIS using ArcGIS training FEB 2021

by FDC Training

5 years, 2 months

[PATCH v1 0/7] coresight: etm-perf: Fix pid tracing with VHE

by Leo Yan

This patch series is a following up for the previous version which was delivered by Suzuki [1]. Below gives the background info for why we need this patch series, directly quotes the description in the cover letter of the previous version: "With the Virtualization Host Extensions, the kernel can run at EL2. In this case the pid is written to CONTEXTIDR_EL2 instead of the CONTEXTIDR_EL1. Thus the normal coresight tracing will be unable to detect the PID of the thread generating the trace by looking at the CONTEXTIDR_EL1. Thus, depending on the kernel EL, we must switch to tracing the correct CONTEXTIDR register. With VHE, we must set the TRCCONFIGR.VMID and TRCCONFIGR.VMID_OPT to include the CONTEXTIDR_EL2 as the VMID in the trace. This requires the perf tool to detect the changes in the TRCCONFIGR and use the VMID / CID field for the PID. The challenge here is for the perf tool to detect the kernel behavior. Instead of the previously proposed invasive approaches, this set implements a less intrusive mechanism, by playing with the perf_event.attribute.config bits." Same as the previous series, this series keeps the same implementation for two introduced format bits: - contextid_in_vmid -> Is only supported when the VMID tracing and CONTEXTIDR_EL2 both are supported. When requested the perf etm4x backend sets (TRCCONFIGR.VMID | TRCCONFIGR.VMID_OPT). As per ETMv4.4 TRM, when the core supports VHE, the CONTEXTIDR_EL2 tracing is mandatory. (See the field TRCID2.VMIDOPT) - pid -> Is an alias for the correct config to enable PID tracing on any kernel. i.e, in EL1 kernel -> pid == contextid EL2 kernel -> pid == contextid_in_vmid With this, the perf tool is also updated to request the "pid" tracing whenever available, falling back to "contextid" if it is unavailable. Comparing against the old version, this patch series uses the metadata to save PID format; after add new item into metadata, it introduces backward compatibility issue. To allow backward compatibility, this series calculates per CPU metadata array size and avoid to use the defined macro, so can always know the correct array size based on the info stored in perf data file. Finally, the PID format stored in metadata is passed to decoder and guide the decoder to set PID from CONTEXTIDR_EL1 or VMID. This patch series has been tested on Arm Juno-r2 board, with testing two perf data files: one data file is recorded by the latest perf tool after applied this patch series, and another data file is recorded by old perf tool without this patch series, so this can prove the tool is backward compatible. Changes from RFC: * Added comments to clarify cases requested (Leo); * Explain the change to generic flags for cs_etm_set_option() in the commit description; * Stored PID format in metadata and passed it to decoder (Leo); * Enhanced cs-etm for backward compatibility (Denis Nikitin). [1] https://archive.armlinux.org.uk/lurker/message/20201110.183310.24406f33.en.… Leo Yan (4): perf cs-etm: Calculate per CPU metadata array size perf cs-etm: Add PID format into metadata perf cs-etm: Fixup PID_FMT when it is zero perf cs-etm: Add helper cs_etm__get_pid_fmt() Suzuki K Poulose (3): coresight: etm-perf: Add support for PID tracing for kernel at EL2 perf cs_etm: Use pid tracing explicitly instead of contextid perf cs-etm: Detect pid in VMID for kernel running at EL2 .../hwtracing/coresight/coresight-etm-perf.c | 14 +++ .../coresight/coresight-etm4x-core.c | 9 ++ include/linux/coresight-pmu.h | 11 ++- tools/include/linux/coresight-pmu.h | 11 ++- tools/perf/arch/arm/util/cs-etm.c | 89 +++++++++++++++---- .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 32 ++++++- tools/perf/util/cs-etm.c | 61 ++++++++++++- tools/perf/util/cs-etm.h | 3 + 8 files changed, 198 insertions(+), 32 deletions(-) -- 2.25.1

5 years, 2 months

Copia de seguridad de mensajes de WhatsApp *913071605 Nº (826171)

by Incc WhatsApp.582527

5 years, 2 months

Fwd: factura pendiente - Nº (431764)

by Notificacion

5 years, 2 months

Consulta FOESCO

by FOESCO

Buenos días Os informamos desde FOESCO (Formación Estatal Continua) que nos encontramos organizando el Calendario de Cursos Bonificables 2021 para empleados en activo o en ERTE. Rogamos respondáis a este mismo correo electrónico eligiendo una de las opciones que a continuación indicamos: 1 - Precisamos información para la PRESENTE convocatoria ENERO 2021 2 - Precisamos información para el mes de .......... (Indicar mes) 3 - No precisamos ninguna información este año Quedamos a la espera de vuestra respuesta. Un cordial saludo. Alex Pons. Director FOESCO. FOESCO Formación Estatal Continua e-mail: cursos(a)foesco.net Tel.: 91 032 37 94 (Horario de 9h a 14h y de 16:30h a 21h de Lunes a Viernes) FOESCO ofrece formación a empresas y trabajadores en activo a través de cursos bonificables por la Fundación Estatal para la Formación en el Empleo (antiguo FORCEM) que gestiona las acciones formativas de FORMACIÓN CONTINUA para trabajadores y se rige por la ley 30/2015 de 9 de Septiembre. Antes de imprimir este e-mail piense bien si es necesario hacerlo. Before printing this e-mail please think twice if you really need it. FOESCO Tfno: 910 382 880 Email: cursos(a)foesco.com. La información transmitida en este mensaje está dirigida solamente a las personas o entidades que figuran en el encabezamiento y contiene información confidencial, por lo que, si usted lo recibiera por error, por favor destrúyalo sin copiarlo, usarlo ni distribuirlo, comunicándolo inmediatamente al emisor del mensaje. De conformidad con lo dispuesto en el Reglamento Europeo del 2016/679, del 27 de Abril de 2016, FOESCO le informa que los datos por usted suministrados serán tratados con las medidas de seguridad conformes a la normativa vigente que se requiere. Dichos datos serán empleados con fines de gestión. Para el ejercicio de sus derechos de transparencia, información, acceso, rectificación, supresión o derecho al olvido, limitación del tratamiento , portabilidad de datos y oposición de sus datos de carácter personal deberá dirigirse a la dirección del Responsable del tratamiento a C/ LAGUNA DEL MARQUESADO Nº10, 28021, MADRID, "PULSANDO AQUI" <mailto:bajas@foesco.com?Subject=BAJA%20CORREOS> y "ENVIAR" o a traves de la dirección de correo electrónico: bajas(a)foesco.com <mailto:bajas@foesco.com?Subject=BAJA%20CORREOS>

5 years, 2 months

[PATCH V2] coresight: etm4x: add AMBA id for Cortex-A55 and Cortex-A75

by Chunyan Zhang

From: Chunyan Zhang <chunyan.zhang(a)unisoc.com> Add AMBA UCI id to support Cortex-A55(Ananke) and Cortex-A75(Promethus). Signed-off-by: Bin Ji <bin.ji(a)unisoc.com> Signed-off-by: Chunyan Zhang <chunyan.zhang(a)unisoc.com> --- Changes since v1: * Addressed Mike's comments - changed to use CS_AMBA_UCI_ID(). --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index b20b6ff17cf6..8c4b0c46c8f3 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1713,6 +1713,8 @@ static const struct amba_id etm4_ids[] = { CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */ CS_AMBA_ID(0x000bb959), /* Cortex-A73 */ CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */ + CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */ + CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */ CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */ CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */ CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */ -- 2.25.1

5 years, 2 months

[PATCH] coresight: etm4x: add AMBA id for Cortex-A55 and Cortex-A75

by Chunyan Zhang

From: Bin Ji <bin.ji(a)unisoc.com> Add ETM amba id to support Cortex-A55(Ananke) and Cortex-A75(Promethus). Signed-off-by: Bin Ji <bin.ji(a)unisoc.com> Signed-off-by: Chunyan Zhang <chunyan.zhang(a)unisoc.com> --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index b20b6ff17cf6..66c6641c71ea 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1709,9 +1709,11 @@ static int etm4_remove(struct amba_device *adev) static const struct amba_id etm4_ids[] = { CS_AMBA_ID(0x000bb95d), /* Cortex-A53 */ + CS_AMBA_ID(0x000bbd05), /* Cortex-A55 */ CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */ CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */ CS_AMBA_ID(0x000bb959), /* Cortex-A73 */ + CS_AMBA_ID(0x000bbd0a), /* Cortex-A75 */ CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */ CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */ CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */ -- 2.25.1

5 years, 2 months

[PATCH] perf tools: Update OpenCSD to v1.0.0

by James Clark

Replace the OCSD_INSTR switch statement with an if to fix compilation error about unhandled values and avoid this issue again in the future. Add new OCSD_GEN_TRC_ELEM_SYNC_MARKER and OCSD_GEN_TRC_ELEM_MEMTRANS enum values to fix unhandled value compilation error. Currently they are ignored. Increase the minimum version number to v1.0.0 now that new enum values are used that are only present in this version. Signed-off-by: James Clark <james.clark(a)arm.com> Cc: John Garry <john.garry(a)huawei.com> Cc: Will Deacon <will(a)kernel.org> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Leo Yan <leo.yan(a)linaro.org> Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> Cc: Mike Leach <mike.leach(a)linaro.org> Cc: Al Grant <al.grant(a)arm.com> Cc: Peter Zijlstra <peterz(a)infradead.org> Cc: Ingo Molnar <mingo(a)redhat.com> Cc: Arnaldo Carvalho de Melo <acme(a)kernel.org> Cc: Mark Rutland <mark.rutland(a)arm.com> Cc: Alexander Shishkin <alexander.shishkin(a)linux.intel.com> Cc: Jiri Olsa <jolsa(a)redhat.com> Cc: Namhyung Kim <namhyung(a)kernel.org> --- tools/build/feature/test-libopencsd.c | 4 ++-- tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 15 ++++----------- 2 files changed, 6 insertions(+), 13 deletions(-) diff --git a/tools/build/feature/test-libopencsd.c b/tools/build/feature/test-libopencsd.c index 1547bc2c0950..52c790b0317b 100644 --- a/tools/build/feature/test-libopencsd.c +++ b/tools/build/feature/test-libopencsd.c @@ -4,9 +4,9 @@ /* * Check OpenCSD library version is sufficient to provide required features */ -#define OCSD_MIN_VER ((0 << 16) | (14 << 8) | (0)) +#define OCSD_MIN_VER ((1 << 16) | (0 << 8) | (0)) #if !defined(OCSD_VER_NUM) || (OCSD_VER_NUM < OCSD_MIN_VER) -#error "OpenCSD >= 0.14.0 is required" +#error "OpenCSD >= 1.0.0 is required" #endif int main(void) diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c index cd007cc9c283..3f4bc4050477 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c @@ -419,19 +419,10 @@ cs_etm_decoder__buffer_range(struct cs_etm_queue *etmq, packet->last_instr_subtype = elem->last_i_subtype; packet->last_instr_cond = elem->last_instr_cond; - switch (elem->last_i_type) { - case OCSD_INSTR_BR: - case OCSD_INSTR_BR_INDIRECT: + if (elem->last_i_type == OCSD_INSTR_BR || elem->last_i_type == OCSD_INSTR_BR_INDIRECT) packet->last_instr_taken_branch = elem->last_instr_exec; - break; - case OCSD_INSTR_ISB: - case OCSD_INSTR_DSB_DMB: - case OCSD_INSTR_WFI_WFE: - case OCSD_INSTR_OTHER: - default: + else packet->last_instr_taken_branch = false; - break; - } packet->last_instr_size = elem->last_instr_sz; @@ -572,6 +563,8 @@ static ocsd_datapath_resp_t cs_etm_decoder__gen_trace_elem_printer( case OCSD_GEN_TRC_ELEM_EVENT: case OCSD_GEN_TRC_ELEM_SWTRACE: case OCSD_GEN_TRC_ELEM_CUSTOM: + case OCSD_GEN_TRC_ELEM_SYNC_MARKER: + case OCSD_GEN_TRC_ELEM_MEMTRANS: default: break; } -- 2.28.0

5 years, 2 months

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