CoreSight

coresight@lists.linaro.org

4 participants
2387 discussions

[PATCH V3] coresight: Make sysFS functional on topologies with per core sink

by Linu Cherian

Coresight driver assumes sink is common across all the ETMs, and tries to build a path between ETM and the first enabled sink found using bus based search. This breaks sysFS usage on implementations that has multiple per core sinks in enabled state. For this, - coresight_find_sink API is updated with an additional flag so that it is able to return an enabled sink - coresight_get_enabled_sink API is updated to do a connection based search, when a source reference is given. Signed-off-by: Linu Cherian <lcherian(a)marvell.com> --- Applies on https://git.linaro.org/kernel/coresight.git/log/?h=next Changes in V3: Fixed checkpatch issue. .../hwtracing/coresight/coresight-etm-perf.c | 2 +- drivers/hwtracing/coresight/coresight-priv.h | 5 +- drivers/hwtracing/coresight/coresight.c | 51 +++++++++++++++++-- 3 files changed, 51 insertions(+), 7 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 1a3169e69bb1..25041d2654e3 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -223,7 +223,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, id = (u32)event->attr.config2; sink = coresight_get_sink_by_id(id); } else { - sink = coresight_get_enabled_sink(true); + sink = coresight_get_enabled_sink(NULL, true); } mask = &event_data->mask; diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index f2dc625ea585..010ed26db340 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -148,10 +148,13 @@ static inline void coresight_write_reg_pair(void __iomem *addr, u64 val, void coresight_disable_path(struct list_head *path); int coresight_enable_path(struct list_head *path, u32 mode, void *sink_data); struct coresight_device *coresight_get_sink(struct list_head *path); -struct coresight_device *coresight_get_enabled_sink(bool reset); +struct coresight_device * +coresight_get_enabled_sink(struct coresight_device *source, bool reset); struct coresight_device *coresight_get_sink_by_id(u32 id); struct coresight_device * coresight_find_default_sink(struct coresight_device *csdev); +struct coresight_device * +coresight_find_enabled_sink(struct coresight_device *csdev); struct list_head *coresight_build_path(struct coresight_device *csdev, struct coresight_device *sink); void coresight_release_path(struct list_head *path); diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c index e9c90f2de34a..ae69169c58d3 100644 --- a/drivers/hwtracing/coresight/coresight.c +++ b/drivers/hwtracing/coresight/coresight.c @@ -566,6 +566,10 @@ static int coresight_enabled_sink(struct device *dev, const void *data) /** * coresight_get_enabled_sink - returns the first enabled sink found on the bus + * When a source reference is given, enabled sink is found using connection based + * search. + * + * @source: Coresight source device reference * @deactivate: Whether the 'enable_sink' flag should be reset * * When operated from perf the deactivate parameter should be set to 'true'. @@ -576,10 +580,21 @@ static int coresight_enabled_sink(struct device *dev, const void *data) * parameter should be set to 'false', hence mandating users to explicitly * clear the flag. */ -struct coresight_device *coresight_get_enabled_sink(bool deactivate) +struct coresight_device * +coresight_get_enabled_sink(struct coresight_device *source, bool deactivate) { struct device *dev = NULL; + struct coresight_device *sink; + + if (!source) + goto bus_search; + sink = coresight_find_enabled_sink(source); + if (sink && deactivate) + sink->activated = false; + + return sink; +bus_search: dev = bus_find_device(&coresight_bustype, NULL, &deactivate, coresight_enabled_sink); @@ -828,6 +843,7 @@ coresight_select_best_sink(struct coresight_device *sink, int *depth, * * @csdev: source / current device to check. * @depth: [in] search depth of calling dev, [out] depth of found sink. + * @enabled: flag to search only enabled sinks * * This will walk the connection path from a source (ETM) till a suitable * sink is encountered and return that sink to the original caller. @@ -839,7 +855,7 @@ coresight_select_best_sink(struct coresight_device *sink, int *depth, * return best sink found, or NULL if not found at this node or child nodes. */ static struct coresight_device * -coresight_find_sink(struct coresight_device *csdev, int *depth) +coresight_find_sink(struct coresight_device *csdev, int *depth, bool enabled) { int i, curr_depth = *depth + 1, found_depth = 0; struct coresight_device *found_sink = NULL; @@ -862,7 +878,8 @@ coresight_find_sink(struct coresight_device *csdev, int *depth) child_dev = csdev->pdata->conns[i].child_dev; if (child_dev) - sink = coresight_find_sink(child_dev, &child_depth); + sink = coresight_find_sink(child_dev, &child_depth, + enabled); if (sink) found_sink = coresight_select_best_sink(found_sink, @@ -872,6 +889,10 @@ coresight_find_sink(struct coresight_device *csdev, int *depth) } return_def_sink: + /* Check if we need to return an enabled sink */ + if (enabled && found_sink) + if (!found_sink->activated) + found_sink = NULL; /* return found sink and depth */ if (found_sink) *depth = found_depth; @@ -901,10 +922,30 @@ coresight_find_default_sink(struct coresight_device *csdev) /* look for a default sink if we have not found for this device */ if (!csdev->def_sink) - csdev->def_sink = coresight_find_sink(csdev, &depth); + csdev->def_sink = coresight_find_sink(csdev, &depth, false); return csdev->def_sink; } +/** + * coresight_find_enabled_sink: Find the suitable enabled sink + * + * @csdev: starting source to find a connected sink. + * + * Walks connections graph looking for a suitable sink to enable for the + * supplied source. Uses CoreSight device subtypes and distance from source + * to select the best sink. + * + * Used in cases where the CoreSight user (sysfs) has selected a sink. + */ +struct coresight_device * +coresight_find_enabled_sink(struct coresight_device *csdev) +{ + int depth = 0; + + /* look for the enabled sink */ + return coresight_find_sink(csdev, &depth, true); +} + static int coresight_remove_sink_ref(struct device *dev, void *data) { struct coresight_device *sink = data; @@ -992,7 +1033,7 @@ int coresight_enable(struct coresight_device *csdev) * Search for a valid sink for this session but don't reset the * "enable_sink" flag in sysFS. Users get to do that explicitly. */ - sink = coresight_get_enabled_sink(false); + sink = coresight_get_enabled_sink(csdev, false); if (!sink) { ret = -EINVAL; goto out; -- 2.25.1

4 years, 10 months

linaro kernel for dragonboard410c

by Robert Henry

Greetings: I am relatively new to the dragon board 410c. I am running the branch debian-qcom-dragonboard410c-20.07 from http://git.linaro.org/landing-teams/working/qualcomm/kernel.git which boots kernel 5.7.0-qcomlt-arm64 This 5.7.0 kernel and associated files does not compile cs-etm-decoder.c as symbol OCSD_GEN_TRC_ELEM_I_RANGE_NOPATH is undefined. Mathieu Portier, a developer of the coresight package for aarch64 processors, says that this symbol has been defined in linux kernels >= 5.8 Is there a more recent branch of the kernel for the dragonboard 410c that is based on linux kernel 5.8 (or even 5.9-rc1)? Thanks in advance, Robert Henry

4 years, 10 months

[PATCH v8 00/24] coresight: allow to build coresight as modules

by Tingwei Zhang

Allow to build coresight as modules. This gives developers the feasibility to test their code without reboot. This series is based on below two series. - "coresight: allow to build components as modules" https://lkml.org/lkml/2018/6/5/989 - "coresight: make drivers modular" https://lkml.org/lkml/2020/1/17/468 Change from v7: Depends on below change for ETM hotplug (Sai) https://lore.kernel.org/linux-arm-kernel/20200729051310.18436-1-saiprakash.… Add mutex lock to protect etmdrvdata[] (Suzuki) Add helper function coresight_get_ref() (Suzuki) Reorg replicator and funnel change. Use two patches to support these two drivers. (Suzuki) Add fix tag to "coresight: etm: perf: Fix warning caused by etm_setup_aux failure" (Suzuki) Update author of "coresight: cti: Fix bug clearing sysfs links on callback" Change from v6: Correct module description for CATU (Mike) Check ect_ret equals 0 and set ect_enabled flag (Mike) Add Tested-by and Reviewed-by from Mike Change from v5: Add below CTI clean up change from Mike into series -https://lists.linaro.org/pipermail/coresight/2020-July/004349.html Increase module reference count when enabling CTI device (Mike) Change from v4: Fix error handling in coresight_grab_devicei() (Greg) Add coresight: cti: Fix remove sysfs link error from Mike -https://lists.linaro.org/pipermail/coresight/2020-July/004275.html Move cti_remove_conn_xrefs() into cti_remove() (Mike) Align patch subject to coresight: <component>: <description> (Mike) Change from v3: Rebase to coresight-next (Mike and Mathieu) Reorder try_get_module() (Suzuki) Clean up etmdrvdata[] in device remote path (Mike) Move cti_remove_conn_xrefs to cti_remove (Mike) Change from v2: Rebase to 5.8-rc5. Export coresight_add_sysfs_link and coresight_remove_sysfs_link Fix one cut and paste error on MODULE_DESCRIPTION of CTI Change from v1: Use try_module_get() to avoid module to be unloaded when device is used in active trace session. (Mathieu P) Change from above two series. This series adds the support to dynamically remove module when the device in that module is enabled and used by some trace path. It disables all trace paths with that device and release the trace path. Kim Phillips (8): coresight: use IS_ENABLED for CONFIGs that may be modules coresight: etm3x: allow etm3x to be built as a module coresight: etm4x: allow etm4x to be built as a module coresight: etb: allow etb to be built as a module coresight: tpiu: allow tpiu to be built as a module coresight: tmc: allow tmc to be built as a module coresight: allow funnel driver to be built as module coresight: allow replicator driver to be built as module Mian Yousaf Kaukab (2): coresight: export global symbols coresight: tmc-etr: add function to register catu ops Mike Leach (2): coresight: cti: Fix remove sysfs link error coresight: cti: Fix bug clearing sysfs links on callback Tingwei Zhang (12): coresight: cpu_debug: add module name in Kconfig coresight: cpu_debug: define MODULE_DEVICE_TABLE coresight: add coresight prefix to barrier_pkt coresight: add try_get_module() in coresight_grab_device() coresight: stm: allow to build coresight-stm as a module coresight: etm: perf: Fix warning caused by etm_setup_aux failure coresight: cti: add function to register cti associate ops coresight: cti: don't disable ect device if it's not enabled coresight: cti: increase reference count when enabling cti coresight: cti: allow cti to be built as a module coresight: catu: allow catu drivers to be built as modules coresight: allow the coresight core driver to be built as a module drivers/hwtracing/coresight/Kconfig | 54 ++++-- drivers/hwtracing/coresight/Makefile | 22 +-- drivers/hwtracing/coresight/coresight-catu.c | 37 ++++- drivers/hwtracing/coresight/coresight-catu.h | 2 - .../{coresight.c => coresight-core.c} | 156 +++++++++++++++--- .../hwtracing/coresight/coresight-cpu-debug.c | 2 + .../{coresight-cti.c => coresight-cti-core.c} | 62 ++++++- drivers/hwtracing/coresight/coresight-etb10.c | 27 ++- .../hwtracing/coresight/coresight-etm-perf.c | 13 +- .../hwtracing/coresight/coresight-etm-perf.h | 5 +- ...resight-etm3x.c => coresight-etm3x-core.c} | 27 ++- ...resight-etm4x.c => coresight-etm4x-core.c} | 118 +++++++++---- .../hwtracing/coresight/coresight-funnel.c | 62 ++++++- .../hwtracing/coresight/coresight-platform.c | 1 + drivers/hwtracing/coresight/coresight-priv.h | 24 ++- .../coresight/coresight-replicator.c | 63 ++++++- drivers/hwtracing/coresight/coresight-stm.c | 20 ++- drivers/hwtracing/coresight/coresight-sysfs.c | 2 + .../{coresight-tmc.c => coresight-tmc-core.c} | 24 ++- .../hwtracing/coresight/coresight-tmc-etf.c | 2 +- .../hwtracing/coresight/coresight-tmc-etr.c | 21 ++- drivers/hwtracing/coresight/coresight-tmc.h | 3 + drivers/hwtracing/coresight/coresight-tpiu.c | 19 ++- include/linux/coresight.h | 3 +- 24 files changed, 650 insertions(+), 119 deletions(-) rename drivers/hwtracing/coresight/{coresight.c => coresight-core.c} (92%) rename drivers/hwtracing/coresight/{coresight-cti.c => coresight-cti-core.c} (94%) rename drivers/hwtracing/coresight/{coresight-etm3x.c => coresight-etm3x-core.c} (97%) rename drivers/hwtracing/coresight/{coresight-etm4x.c => coresight-etm4x-core.c} (95%) rename drivers/hwtracing/coresight/{coresight-tmc.c => coresight-tmc-core.c} (95%) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

4 years, 10 months

[PATCH] coresight: etm4x: Ensure default perf settings filter user/kernel

by Mike Leach

Moving from using an address filter to trace the default "all addresses" range to no filtering to acheive the same result, has caused the perf filtering of kernel/user address spaces from not working unless an explicit address filter was used. This due to the global TRCVICTLR exception level filtering not being set correctly. This patch fixes this. Reported-by: Leo Yan <leo.yan(a)linaro.org> Signed-off-by: Mike Leach <mike.leach(a)linaro.org> --- drivers/hwtracing/coresight/coresight-etm4x.c | 11 +++++++++++ drivers/hwtracing/coresight/coresight-etm4x.h | 3 +++ 2 files changed, 14 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 8b0634ebef77..d0f800753590 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -52,6 +52,7 @@ static struct etmv4_drvdata *etmdrvdata[NR_CPUS]; static void etm4_set_default_config(struct etmv4_config *config); static int etm4_set_event_filters(struct etmv4_drvdata *drvdata, struct perf_event *event); +static u64 etm4_get_access_type(struct etmv4_config *config); static enum cpuhp_state hp_online; @@ -785,6 +786,8 @@ static void etm4_init_arch_data(void *info) static void etm4_set_default_config(struct etmv4_config *config) { + u64 access_type; + /* disable all events tracing */ config->eventctrl0 = 0x0; config->eventctrl1 = 0x0; @@ -800,6 +803,14 @@ static void etm4_set_default_config(struct etmv4_config *config) /* TRCVICTLR::EVENT = 0x01, select the always on logic */ config->vinst_ctrl = BIT(0); + + /* + * TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering + * bits in vinst, same bit pattern as address comparator acc values + * but offset in this register + */ + access_type = etm4_get_access_type(config) << ETM_EXLEVEL_VINST_OFFSET; + config->vinst_ctrl |= (u32)access_type; } static u64 etm4_get_ns_access_type(struct etmv4_config *config) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index b8283e1d6d88..369abc25c597 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -192,6 +192,9 @@ #define ETM_EXLEVEL_NS_HYP BIT(14) #define ETM_EXLEVEL_NS_NA BIT(15) +/* access level control in VINST - same bits as TRCACATRn but offset */ +#define ETM_EXLEVEL_VINST_OFFSET 8 + /* secure / non secure masks - TRCVICTLR, IDR3 */ #define ETM_EXLEVEL_S_VICTLR_MASK GENMASK(19, 16) /* NS MON (EL3) mode never implemented */ -- 2.17.1

4 years, 10 months

perf report: Error when collecting kernel traces on CPU-wide scenario

by Raphael GALLAIS-POU

Hi all, I am trying to enable Coresight framework on STM32MP1 (ARMv7). More specifically on CPU-wide kernel trace collection with perf. I recently came across a decoding error from OpenCSD, which prevent the proper trace decoding : > perf report --stdio DCD_ETMV3_0018 : 0x0013 (OCSD_ERR_BAD_PACKET_SEQ) [Bad packet sequence]; TrcIdx=6969; CS ID=12; Bad Packet sequence. 0x27438 [0x8]: failed to process type: 68 [Invalid argument] > perf report --dump [...] Idx:6961; ID:12; P_HDR : Atom P-header.; Idx:6962; ID:12; BRANCH_ADDRESS : Branch address.; Addr=0x6C67BD40 ~[0x6C67BD40]; Exception=Jazelle; Idx:6967; ID:12; P_HDR : Atom P-header.; EE Idx:6968; ID:12; P_HDR : Atom P-header.; PKTP_ETMV3_0018 : 0x0013 (OCSD_ERR_BAD_PACKET_SEQ) [Bad packet sequence]; TrcIdx=6969; CS ID=12; A-Sync ? : Unexpected byte in sequence Idx:6969; ID:12; BAD_SEQUENCE : Invalid sequence for packet type.[A_SYNC] Idx:6970; ID:12; P_HDR : Atom P-header.; EEEEEEEEEEEEEEE What could explain this behavior ? Thanks, Raphaël

4 years, 10 months

Quarantine Summary: 15 message(s) quarantined

by lists.linaro.org

4 years, 10 months

CTI issue on CPU hotplug

by Tingwei Zhang

Hi Mike, I was doing CPU hot plug test today and encoutner some CTI issues. I'd like to know whether they are known issues so someone is already on it. If no one is working on this, I can provide some patch later. 1. Deadlock [ 988.335937] CPU: 6 PID: 10258 Comm: sh Tainted: G W L 5.8.0-rc6-mainline-16783-gc38daa79b26b-dirty #1 [ 988.346364] Hardware name: Thundercomm Dragonboard 845c (DT) [ 988.352073] pstate: 20400005 (nzCv daif +PAN -UAO BTYPE=--) [ 988.357689] pc : smp_call_function_single+0x158/0x1b8 [ 988.362782] lr : smp_call_function_single+0x124/0x1b8 ... [ 988.451638] Call trace: [ 988.454119] smp_call_function_single+0x158/0x1b8 [ 988.458866] cti_enable+0xb4/0xf8 [coresight_cti] [ 988.463618] coresight_control_assoc_ectdev+0x6c/0x128 [coresight] [ 988.469855] coresight_enable+0x1f0/0x364 [coresight] [ 988.474957] enable_source_store+0x5c/0x9c [coresight] [ 988.480140] dev_attr_store+0x14/0x28 [ 988.483839] sysfs_kf_write+0x38/0x4c [ 988.487532] kernfs_fop_write+0x1c0/0x2b0 [ 988.491585] vfs_write+0xfc/0x300 [ 988.494931] ksys_write+0x78/0xe0 [ 988.498283] __arm64_sys_write+0x18/0x20 [ 988.502240] el0_svc_common+0x98/0x160 [ 988.506024] do_el0_svc+0x78/0x80 [ 988.509377] el0_sync_handler+0xd4/0x270 [ 988.513337] el0_sync+0x164/0x180 Root cause: CPU6: Grab drvdata->spinlock in cti_enable() Call smp_call_function_single(drvdata->ctidev.cpu, cti_enable_hw_smp_call, drvdata, 1); and wait for CPU2 to write CTI HW. CPU2: In cti_cpu_pm_notify() with interrupt disabled and spin on drvdata->spinlock. 2. Warning [ 121.436987] WARNING: CPU: 1 PID: 15 at drivers/hwtracing/coresight/coresight-core.c:227 coresight_disclaim_device+0x30/0x44 [coresight] [ 121.438144] Hardware name: Thundercomm Dragonboard 845c (DT) [ 121.438156] pstate: 80c00085 (Nzcv daIf +PAN +UAO BTYPE=--) [ 121.438167] pc : coresight_disclaim_device+0x30/0x44 [coresight] [ 121.438203] lr : cti_dying_cpu+0x34/0x4c [coresight_cti] Root cause: coresight_disclaim() is called in dying unconditionally while coresight_claim() is called only when it's enabled. 3. When checking the code, I think there's some issue on pm_runtime_get_sync() as well. It's called in cti_starting_cpu but put() is not called in dying. We could have unbalanced pm count here. Test script: adb wait-for-device root adb wait-for-device :loop adb shell "echo 1 > /sys/bus/coresight/devices/tmc_etr0/enable_sink" adb shell "echo 1 > /sys/bus/coresight/devices/etm2/enable_source" adb shell "echo 0 > /sys/devices/system/cpu/cpu2/online" adb shell "echo 1 > /sys/devices/system/cpu/cpu2/online" adb shell "echo 0 > /sys/devices/system/cpu/cpu2/online" adb shell "echo 1 > /sys/devices/system/cpu/cpu2/online" adb shell "echo 0 > /sys/bus/coresight/devices/etm2/enable_source" goto loop Thanks, Tingwei

4 years, 10 months

[PATCH v3 0/6] tracing: export event trace and trace_marker

by Tingwei Zhang

Ftrace has ability to export trace packets to other destination. Currently, only function trace can be exported. This series extends the support to event trace and trace_maker. STM is one possible destination to export ftrace. Use separate channel for each CPU to avoid mixing up packets from different CPUs together. Change from v2: Change flag definition to BIT(). (Steven) Add comment in stm_ftrace_write() to clarify it's safe to use smp_processor_id() here since preempt is disabled. (Steven) Change from v1: All changes are suggested by Steven Rostedt. User separate flag to control function trace, event trace and trace mark. Allocate channels according to num_possible_cpu() dynamically. Move ftrace_exports routines up so all ftrace can use them. Tingwei Zhang (6): stm class: ftrace: change dependency to TRACING tracing: add flag to control different traces tracing: add trace_export support for event trace tracing: add trace_export support for trace_marker stm class: ftrace: enable supported trace export flag stm class: ftrace: use different channel accroding to CPU drivers/hwtracing/stm/Kconfig | 2 +- drivers/hwtracing/stm/ftrace.c | 7 +- include/linux/trace.h | 7 + kernel/trace/trace.c | 270 ++++++++++++++++++--------------- 4 files changed, 159 insertions(+), 127 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

4 years, 10 months

[RFC] Making trace reads independent to task scheduling

by Andrea Brunato

Good morning, I noticed the trace data is read from the buffer only when the target task is scheduled in/out, leading to high variability of the trace data size. This can be an issue because trace data gets very different as in size (and thus as in its coverage) under different system load. Is getting trace reads independent w.r.t. task scheduling an idea which has already been considered? One possibility I’m considering is using an independent timer which triggers periodically trace reads from the sink buffer to achieve less variability. A couple of buffers (struct etr_buf) could also be used: one for gathering the trace data coming from the sink and another whose content to be copied over to the perf aux buffer. When the timer triggers, the buffers are switched such that it's always possible to copy the trace data to the perf aux buffer (in one buffer) while gathering the trace data coming from all the ETMs (in the other one). I have been thinking about this solution with a N:1 source:sink topology in mind, but I'm not sure how this would fit in a N:N topology, where every sink has its own buffer. What do you think about it? Are you aware of any limitations that should be taken into account? If we think this could work, the next step would probably be to prototype something that works on my N:1 topology board Thanks, Andrea

4 years, 10 months

Questions on OpenCSD tool

by Smitha Gautham

Hello, I am a PhD student from Virginia Commonwealth University. I wanted to use the OpenCSD tool to decode ETM and PTM traces. I have downloaded the OpenCSD tool and have decoded the test examples that come with it. I have some questions about the tool: 1) OpenCSD Interface to read trace a) As a first step towards learning about OpenCSD, I have installed it on my PC. I have Cortex M4 and Cortex A9 boards that have ETM/PTM modules. What are the interfaces supported by OpenCSD to read the trace from these boards ? b) Are there any specific boards, software and interfaces that OpenCSD has been tested against ? c) Can OpenCSD decoder interface with debuggers such as Segger JTrace or Keil Ulink Pro and decode instruction traces read from them ? d) Can OpenCSD be installed on a ARM Cortex processor and decode the traces for an application running on the same processor or a co-processor? 2) Can we decode traces of exceptions, changes in processor instruction set state, changes in processor security state, global system timestamps with OpenCSD ? 3) Is there a way to get raw decoded traces which have only Atom information(branch taken or not) and addresses from OpenCSD ? Thank you for your time and help with these questions. regards, Smitha

4 years, 10 months

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