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Re: [PATCH v2 01/15] coresight: Make ETM4x TRCIDR0 register accesses consistent with sysreg.h

by Mathieu Poirier

On Mon, Feb 07, 2022 at 11:14:50AM +0530, Anshuman Khandual wrote: > Hi James, > > These are all ETM4X specific changes. Something like this might be cleaner > and also more compact. Also would suggest to follow the same for subsequent > patches as well. > > coresight: etm4x: Cleanup TRCIDR0 register accesses > > Consistency with sysreg.h could be mentioned in the commit message itself. > I agree with the above two comments. > On 2/3/22 5:35 PM, James Clark wrote: > > This is a no-op change for style and consistency and has no effect on the > > binary produced by gcc-11. > > This patch adds register definitions, helper macros as well. Please expand > the commit message to add more details. This is too short, for the change > it creates. BTW why is it necessary to mention GCC version number here. > Here too - I'm not sure adding gcc's version number helps in any way. > > > > Signed-off-by: James Clark <james.clark(a)arm.com> > > --- > > .../coresight/coresight-etm4x-core.c | 36 +++++-------------- > > drivers/hwtracing/coresight/coresight-etm4x.h | 17 +++++++++ > > drivers/hwtracing/coresight/coresight-priv.h | 5 +++ > > 3 files changed, 30 insertions(+), 28 deletions(-) > > > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > > index e2eebd865241..107e81948f76 100644 > > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > > @@ -1091,41 +1091,21 @@ static void etm4_init_arch_data(void *info) > > etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0); > > > > /* INSTP0, bits[2:1] P0 tracing support field */ > > - if (BMVAL(etmidr0, 1, 2) == 0b11) > > - drvdata->instrp0 = true; > > - else > > - drvdata->instrp0 = false; > > - > > + drvdata->instrp0 = !!(REG_VAL(etmidr0, TRCIDR0_INSTP0) == 0b11); > > /* TRCBB, bit[5] Branch broadcast tracing support bit */ > > - if (BMVAL(etmidr0, 5, 5)) > > - drvdata->trcbb = true; > > - else > > - drvdata->trcbb = false; > > - > > + drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB); > > /* TRCCOND, bit[6] Conditional instruction tracing support bit */ > > - if (BMVAL(etmidr0, 6, 6)) > > - drvdata->trccond = true; > > - else > > - drvdata->trccond = false; > > - > > + drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND); > > /* TRCCCI, bit[7] Cycle counting instruction bit */ > > - if (BMVAL(etmidr0, 7, 7)) > > - drvdata->trccci = true; > > - else > > - drvdata->trccci = false; > > - > > + drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI); > > /* RETSTACK, bit[9] Return stack bit */ > > - if (BMVAL(etmidr0, 9, 9)) > > - drvdata->retstack = true; > > - else > > - drvdata->retstack = false; > > - > > + drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK); > > /* NUMEVENT, bits[11:10] Number of events field */ > > - drvdata->nr_event = BMVAL(etmidr0, 10, 11); > > + drvdata->nr_event = REG_VAL(etmidr0, TRCIDR0_NUMEVENT); > > /* QSUPP, bits[16:15] Q element support field */ > > - drvdata->q_support = BMVAL(etmidr0, 15, 16); > > + drvdata->q_support = REG_VAL(etmidr0, TRCIDR0_QSUPP); > > /* TSSIZE, bits[28:24] Global timestamp size field */ > > - drvdata->ts_size = BMVAL(etmidr0, 24, 28); > > + drvdata->ts_size = REG_VAL(etmidr0, TRCIDR0_TSSIZE); > > > > /* maximum size of resources */ > > etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2); > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > > index 3c4d69b096ca..2bd8ad953b8e 100644 > > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > > @@ -130,6 +130,23 @@ > > > > #define TRCRSR_TA BIT(12) > > > > +/* > > + * Bit positions of registers that are defined above, in the sysreg.h style > > + * of _MASK, _SHIFT and BIT(). > > + */ > > ^^^ not really necessary. Instead the format requirement for below mentioned > CORESIGHT_REG_VAL() macro might be relevant and should be mentioned. I'm not sure if you're asking to move the comment further below or remove it altogether. In any case more comments is always better than less. > > > +#define TRCIDR0_INSTP0_SHIFT 1 > > +#define TRCIDR0_INSTP0_MASK GENMASK(1, 0) > > +#define TRCIDR0_TRCBB BIT(5) > > +#define TRCIDR0_TRCCOND BIT(6) > > +#define TRCIDR0_TRCCCI BIT(7) > > +#define TRCIDR0_RETSTACK BIT(9) > > +#define TRCIDR0_NUMEVENT_SHIFT 10 > > +#define TRCIDR0_NUMEVENT_MASK GENMASK(1, 0) > > +#define TRCIDR0_QSUPP_SHIFT 15 > > +#define TRCIDR0_QSUPP_MASK GENMASK(1, 0) > > +#define TRCIDR0_TSSIZE_SHIFT 24 > > +#define TRCIDR0_TSSIZE_MASK GENMASK(4, 0) > > + > > /* > > * System instructions to access ETM registers. > > * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions > > diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h > > index ff1dd2092ac5..1452c6038421 100644 > > --- a/drivers/hwtracing/coresight/coresight-priv.h > > +++ b/drivers/hwtracing/coresight/coresight-priv.h > > @@ -36,6 +36,11 @@ > > > > #define TIMEOUT_US 100 > > #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) > > +/* > > + * Extract a field from a register where field is #defined in the form > > + * <register_name>_<field_name>_MASK and <register_name>_<field_name>_SHIFT > > + */ > > Looking at the usage, <register_name> is already embedded in <filed_name>. So > it requires <field_name>_SHIFT and <field_name>_MASK instead. Unless register > name should be passed as separate argument (which actually might be better). > > REG_VAL(etmidr0, TRCIDR0_TSSIZE) ----> REG_VAL(etmidr0, TRCIDR0, TSSIZE) I don't have strong preference, I'm good either way. > > with some restructuring in the comment .. > > /* > * Extract a field from a coresight register > * > * Required fields are defined as macros like the following > * > * <register_name>_<field_name>_MASK and <register_name>_<field_name>_SHIFT > */ > > > +#define REG_VAL(val, field) ((val & (field##_MASK << field##_SHIFT)) >> field##_SHIFT) > > This is too generic to be in a coresight header or it should just be > named CORESIGHT_REG_VAL() instead, making it more specific for here. > > The build should fail in case any required macro definition is absent. > I guess no more fortification is required in case macros are missing. > > However CORESIGHT_REG_VAL() is better placed in <coresight-etm4x.h> > just before all the dependent SHIFT/MASK register field definition > starts. > Not sure about this... Someone might want to do the same for etmv3 and in that case we'll end up moving the macro again. Thanks, Mathieu > > > > #define ETM_MODE_EXCL_KERN BIT(30) > > #define ETM_MODE_EXCL_USER BIT(31) > > > > - Anshuman

3 years, 10 months

Re: [PATCH v2 00/15] Make ETM register accesses consistent with sysreg.h

by James Clark

On 07/02/2022 05:51, Anshuman Khandual wrote: > Hi James, > > On 2/3/22 5:35 PM, James Clark wrote: >> James Clark (15): >> coresight: Make ETM4x TRCIDR0 register accesses consistent with >> sysreg.h >> coresight: Make ETM4x TRCIDR2 register accesses consistent with >> sysreg.h >> coresight: Make ETM4x TRCIDR3 register accesses consistent with >> sysreg.h >> coresight: Make ETM4x TRCIDR4 register accesses consistent with >> sysreg.h >> coresight: Make ETM4x TRCIDR5 register accesses consistent with >> sysreg.h >> coresight: Make ETM4x TRCCONFIGR register accesses consistent with >> sysreg.h >> coresight: Make ETM4x TRCEVENTCTL1R register accesses consistent with >> sysreg.h >> coresight: Make ETM4x TRCSTALLCTLR register accesses consistent with >> sysreg.h >> coresight: Make ETM4x TRCVICTLR register accesses consistent with >> sysreg.h >> coresight: Make ETM3x ETMTECR1 register accesses consistent with >> sysreg.h >> coresight: Make ETM4x TRCACATRn register accesses consistent with >> sysreg.h >> coresight: Make ETM4x TRCSSCCRn and TRCSSCSRn register accesses >> consistent with sysreg.h >> coresight: Make ETM4x TRCSSPCICRn register accesses consistent with >> sysreg.h >> coresight: Make ETM4x TRCBBCTLR register accesses consistent with >> sysreg.h >> coresight: Make ETM4x TRCRSCTLRn register accesses consistent with >> sysreg.h > > The changes here are very similar to each other. But they are split > into different patches according to register names just for better > review process ? OR is there any other rationale ? Yes just for the review process. I didn't see a way of reviewing them all in one change because it's so big, and the only logical way to split it was by register so I did it that way. > > - Anshuman

3 years, 10 months

[PATCH v4 0/5] pid: Use helper task_is_in_root_ns()

by Leo Yan

The helper task_is_in_root_ns() has been merged into the mainline kernel (thanks Jakub Kicinski for merging the patches [1]). On the other hand, there have 5 patches were left out in the patch series v2 [2], this patch series is to resend these 5 patches so that sub-module maintainers could pick patches without concerning dependency issue. This patch series can be cleanly applied on the mainline kernel with latest commit dcb85f85fa6f ("gcc-plugins/stackleak: Use noinstr in favor of notrace"). [1] https://lore.kernel.org/lkml/20220126050427.605628-1-leo.yan@linaro.org/ [2] https://lore.kernel.org/lkml/20211208083320.472503-1-leo.yan@linaro.org/ Changes from v2: * Added review and ack tags. * Dropped two merged patches and resend the left 5 patches. Changes from v1: * Renamed helper function from task_is_in_root_ns() to task_is_in_init_pid_ns(). (Leon Romanovsky) * Improved patches' commit logs for more neat. Leo Yan (5): coresight: etm3x: Use task_is_in_init_pid_ns() coresight: etm4x: Use task_is_in_init_pid_ns() coda: Use task_is_in_init_pid_ns() audit: Use task_is_in_init_pid_ns() taskstats: Use task_is_in_init_pid_ns() drivers/hwtracing/coresight/coresight-etm3x-sysfs.c | 8 ++++---- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 8 ++++---- fs/coda/inode.c | 2 +- fs/coda/psdev.c | 2 +- kernel/audit.c | 2 +- kernel/taskstats.c | 2 +- 6 files changed, 12 insertions(+), 12 deletions(-) -- 2.25.1

3 years, 10 months

Re: [PATCH v2] coresight: trbe: Move check for kernel page table isolation from EL0 to probe

by Suzuki K Poulose

On 03/02/2022 19:01, Sudeep Holla wrote: > Currently with the check present in the module initialisation, it shouts > on all the systems irrespective of presence of coresight trace buffer > extensions. > > Similar to Arm SPE perf driver, move the check for kernel page table > isolation from EL0 to the device probe stage instead of the module > initialisation so that it complains only on the systems that support TRBE. > > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> > Cc: Mike Leach <mike.leach(a)linaro.org> > Cc: Leo Yan <leo.yan(a)linaro.org> > Cc: Anshuman Khandual <anshuman.khandual(a)arm.com> > Cc: coresight(a)lists.linaro.org > Signed-off-by: Sudeep Holla <sudeep.holla(a)arm.com> Thanks, I have now queued this. https://git.kernel.org/coresight/c/ebbce265bba164c4f0d5271c277a540bd3b2fd3c Kind regards Suzuki

3 years, 10 months

[PATCH 00/15] Make ETM register accesses consistent with sysreg.h

by James Clark

While working on the branch broadcast change I found it difficult to search for usages of registers and fields because of the magic numbers. I also found it difficult to decide which style to make new code in because of the varying ones used. There was also a code review comment from Suzuki about replacing a magic number so I'm proposing to refactor as many as possible into the style used in sysreg.h which seems to be the new and most consistently used method. For example it was used in the SPE and TRBE drivers. This isn't an exhaustive refactor, but it does get all the basic accesses. There are a couple of odd other cases remaining, mainly in the ETM3x code. These can be found by searching for BMVAL. There is one compromise to ensure this is a complete no-op and has binary equivalence with the old version. I needed to keep two register accesses here, where something like etmidr0 & TRCIDR0_INSTP0_LOAD_STORE would be better: - if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2)) - drvdata->instrp0 = true; - else - drvdata->instrp0 = false; - + drvdata->instrp0 = !!((REG_VAL(etmidr0, TRCIDR0_INSTP0) & 0b01) && + (REG_VAL(etmidr0, TRCIDR0_INSTP0) & 0b10)); I think this change fixes quite a few issues like: * Some registers aren't referred to by name but a different variable name. For example eventctrl1 in mode_store() where TRCEVENTCTL1R isn't mentioned in that function. * Some bits aren't referred to by the name in the manual, even in the comments. For example TRCCONFIGR.RS only occurs as /* bit[12], Return stack enable bit */. * Some bits in the same register are referred to either as magic numbers or the publicly exported config macros, neiher of which are consistent with any other register accesses. For example config->cfg |= BIT(11); config->cfg |= BIT(ETM4_CFG_BIT_CTXTID); * Some fields are already partially referred to in the sysfs.h style way: TRCVICTLR_EXLEVEL_... etc. But other fields in the same register are not * Some fields are magic numbers that are repeated many times in different functions. For example vinst_ctrl |= BIT(9) * Some fields were referred to by magic numbers, even when there were already existing #defines. For example ETMTECR1_INC_EXC * Another benefit is that the #defines could be automatically checked against the reference manual because the style is uniform. Testing ======= To test this I used gcc-11 which doesn't have a quirk about changing register widths in some cases (as in w -> x). I also used elf_diff which showed me exactly where I'd made a mistake when I did (https://github.com/noseglasses/elf_diff). But now that there is no difference, objdump and diff also work for validation. make CC=gcc-11 modules diff <(objdump -d drivers/hwtracing/coresight/coresight-etm4x.ko) <(objdump -d ../linux2/drivers/hwtracing/coresight/coresight-etm4x.ko) diff <(objdump -d drivers/hwtracing/coresight/coresight.ko) <(objdump -d ../linux2/drivers/hwtracing/coresight/coresight.ko) And for ETM3x (doesn't need gcc 11): make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- modules diff <(objdump -d drivers/hwtracing/coresight/coresight-etm3x.ko) <(objdump -d ../linux2/drivers/hwtracing/coresight/coresight-etm3x.ko) When there are no differences, the diff output looks like this with only the filename listed: < drivers/hwtracing/coresight/coresight-etm4x.ko: file format elf64-littleaarch64 --- > ../linux2/drivers/hwtracing/coresight/coresight-etm4x.ko: file format elf64-littleaarch64 Applies to coresight/next 30d1f1c71b James Clark (15): coresight: Make ETM4x TRCIDR0 register accesses consistent with sysreg.h coresight: Make ETM4x TRCIDR2 register accesses consistent with sysreg.h coresight: Make ETM4x TRCIDR3 register accesses consistent with sysreg.h coresight: Make ETM4x TRCIDR4 register accesses consistent with sysreg.h coresight: Make ETM4x TRCIDR5 register accesses consistent with sysreg.h coresight: Make ETM4x TRCCONFIGR register accesses consistent with sysreg.h coresight: Make ETM4x TRCEVENTCTL1R register accesses consistent with sysreg.h coresight: Make ETM4x TRCSTALLCTLR register accesses consistent with sysreg.h coresight: Make ETM4x TRCVICTLR register accesses consistent with sysreg.h coresight: Make ETM3x ETMTECR1 register accesses consistent with sysreg.h coresight: Make ETM4x TRCACATRn register accesses consistent with sysreg.h coresight: Make ETM4x TRCSSCCRn and TRCSSCSRn register accesses consistent with sysreg.h coresight: Make ETM4x TRCSSPCICRn register accesses consistent with sysreg.h coresight: Make ETM4x TRCBBCTLR register accesses consistent with sysreg.h coresight: Make ETM4x TRCRSCTLRn register accesses consistent with sysreg.h .../coresight/coresight-etm3x-core.c | 2 +- .../coresight/coresight-etm3x-sysfs.c | 2 +- .../coresight/coresight-etm4x-core.c | 135 +++++-------- .../coresight/coresight-etm4x-sysfs.c | 178 +++++++++--------- drivers/hwtracing/coresight/coresight-etm4x.h | 159 ++++++++++++++-- drivers/hwtracing/coresight/coresight-priv.h | 1 + 6 files changed, 283 insertions(+), 194 deletions(-) -- 2.28.0

3 years, 10 months

Re: [PATCH] coresight: trbe: Move check for kernelspace unmapped at EL0 to probe

by Suzuki K Poulose

On 03/02/2022 12:04, Sudeep Holla wrote: > On Thu, Feb 03, 2022 at 11:55:58AM +0530, Anshuman Khandual wrote: >> >> >> On 2/1/22 5:52 PM, Sudeep Holla wrote: >>> Currently with the check present in the module initialisation, it shouts >>> on all the systems irrespective of presence of coresight trace buffer >>> extensions. >> >> IIUC a system with CONFIG_CORESIGHT_TRBE enabled but without a TRBE DT >> i.e "arm,trace-buffer-extension" complains about kernel space unmapping >> at EL0 (even though it does not even really have TRBE HW to initialize). > > > Correct. Basically, this error will be seen on all systems(DT and ACPI) when > the module is compiled. It really doesn't matter if the system supports TRBE. > >>> >>> Similar to Arm SPE perf driver, move the check for kernelspace unmapping >>> when running at EL0 to the device probe instead of module initialisation. >> >> Makes sense. >> > > Thanks. > >>> >>> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> >>> Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> >>> Cc: Mike Leach <mike.leach(a)linaro.org> >>> Cc: Leo Yan <leo.yan(a)linaro.org> >>> Cc: Anshuman Khandual <anshuman.khandual(a)arm.com> >>> Cc: coresight(a)lists.linaro.org >>> Signed-off-by: Sudeep Holla <sudeep.holla(a)arm.com> >>> --- >>> drivers/hwtracing/coresight/coresight-trbe.c | 10 +++++----- >>> 1 file changed, 5 insertions(+), 5 deletions(-) >>> >>> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c >>> index 276862c07e32..3fe2ce1ba5bf 100644 >>> --- a/drivers/hwtracing/coresight/coresight-trbe.c >>> +++ b/drivers/hwtracing/coresight/coresight-trbe.c >>> @@ -1423,6 +1423,11 @@ static int arm_trbe_device_probe(struct platform_device *pdev) >>> struct device *dev = &pdev->dev; >>> int ret; >>> >> >> Could you please add a similar comment like SPE driver regarding how >> the TRBE buffer will be inaccessible, if kernel gets unmapped at EL0 >> and trace capture will terminate. >> > > Sure I can add that. But if the device probe fails, will you be able to even > start the trace capture, sorry I didn't get what you mean by "trace capture > will terminate". I assume it must be "trace capture is not possible or not > allowed" IIUC. > "Trace capture is not possible with kernel page table isolation" is good enough. Thanks for making these changes Cheers Suzuki

3 years, 10 months

[PATCH 0/1] coresight: no-op refactor to make INSTP0 check more idiomatic

by James Clark

In preparation for the bigger register refactor, simplify one of the accesses otherwise it looked even more obfuscated after the refactor. This can't be included in the main set because it causes a small change in the binary, although functionally this refactor is also a no-op. Applies to coresight/next 30d1f1c71b James Clark (1): coresight: no-op refactor to make INSTP0 check more idiomatic drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.28.0

3 years, 10 months

[PATCH v2 0/6] coresight: syscfg: Extend configfs for config load

by Mike Leach

This set extends the configfs support to allow loading and unloading of configurations as binary files via configfs. Additional attributes - load, unload and last_load_status are provided to implement the load functionality. Routines to generate binary configuration files are supplied in ./samples/coresight. Example generator and reader applications are provided. Additional Makefile.host supplied to build the generator and reader applications on the host system separate from a cross compiled kernel. Documentation is updated to describe feature usage. Applies and tested on latest coresight/next that includes the previous coresight configuration dynamic load patchset. Changes since v1: 1) Rebased to coresight/next - 5.16-rc1 with previous coresight config set applied. 2) Makefile.host fixed to default to all target. Mike Leach (6): coresight: configfs: Add in functionality for load via configfs coresight: configfs: Add in binary attributes to load files coresight: configfs: Modify config files to allow userspace use coresight: samples: Add an example config writer for configfs load coresight: samples: Add coresight file reader sample program Documentation: coresight: docs for config load via configfs .../trace/coresight/coresight-config.rst | 151 +++++- drivers/hwtracing/coresight/Makefile | 2 +- .../coresight/coresight-config-file.c | 472 ++++++++++++++++++ .../coresight/coresight-config-file.h | 158 ++++++ .../hwtracing/coresight/coresight-config.h | 38 ++ .../coresight/coresight-syscfg-configfs.c | 148 +++++- .../coresight/coresight-syscfg-configfs.h | 8 + .../hwtracing/coresight/coresight-syscfg.c | 36 ++ .../hwtracing/coresight/coresight-syscfg.h | 2 + samples/coresight/Makefile | 23 + samples/coresight/Makefile.host | 47 ++ samples/coresight/coresight-cfg-bufw.c | 302 +++++++++++ samples/coresight/coresight-cfg-bufw.h | 24 + samples/coresight/coresight-cfg-file-read.c | 191 +++++++ samples/coresight/coresight-cfg-filegen.c | 89 ++++ 15 files changed, 1677 insertions(+), 14 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-config-file.c create mode 100644 drivers/hwtracing/coresight/coresight-config-file.h create mode 100644 samples/coresight/Makefile.host create mode 100644 samples/coresight/coresight-cfg-bufw.c create mode 100644 samples/coresight/coresight-cfg-bufw.h create mode 100644 samples/coresight/coresight-cfg-file-read.c create mode 100644 samples/coresight/coresight-cfg-filegen.c -- 2.17.1

3 years, 10 months

Re: [PATCH v2] coresight: syscfg: Fix memleak on registration failure in cscfg_create_device

by Mathieu Poirier

On Mon, Jan 24, 2022 at 12:41:21PM +0000, Miaoqian Lin wrote: > device_register() calls device_initialize(), > according to doc of device_initialize: > > Use put_device() to give up your reference instead of freeing > * @dev directly once you have called this function. > > To prevent potential memleak, use put_device() for error handling. > > Signed-off-by: Miaoqian Lin <linmq006(a)gmail.com> > --- > Changes in v2: > - simply call put_device() instead of cscfg_dev_release() in the error > path of cscfg_create_device. > --- > drivers/hwtracing/coresight/coresight-syscfg.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c b/drivers/hwtracing/coresight/coresight-syscfg.c > index 43054568430f..c30989e0675f 100644 > --- a/drivers/hwtracing/coresight/coresight-syscfg.c > +++ b/drivers/hwtracing/coresight/coresight-syscfg.c > @@ -791,7 +791,7 @@ static int cscfg_create_device(void) > > err = device_register(dev); > if (err) > - cscfg_dev_release(dev); > + put_device(dev); Applied. Thanks, Mathieu > > create_dev_exit_unlock: > mutex_unlock(&cscfg_mutex); > -- > 2.17.1 >

3 years, 10 months

[PATCH v2 0/1] coresight: Fix TRCCONFIGR.QE sysfs interface

by James Clark

Changes since v1: * Add Mike's reviewed by tag * Also make it impossible to write the reserved value of 0b10, regardless of what is supplied by the user. James Clark (1): coresight: Fix TRCCONFIGR.QE sysfs interface drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- 2.28.0

3 years, 10 months

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