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Re: [PATCH V2 3/7] arm64: errata: Add detection for TRBE invalid prohibited states

by Suzuki K Poulose

On 07/01/2022 01:10, Anshuman Khandual wrote: > TRBE implementations affected by Arm erratum #2038923 might get TRBE into > an inconsistent view on whether trace is prohibited within the CPU. As a > result, the trace buffer or trace buffer state might be corrupted. This > happens after TRBE buffer has been enabled by setting TRBLIMITR_EL1.E, > followed by just a single context synchronization event before execution > changes from a context, in which trace is prohibited to one where it isn't, > or vice versa. In these mentioned conditions, the view of whether trace is > prohibited is inconsistent between parts of the CPU, and the trace buffer > or the trace buffer state might be corrupted. This adds a new errata > ARM64_ERRATUM_2038923 in arm64 errata framework. > > Cc: Catalin Marinas <catalin.marinas(a)arm.com> > Cc: Will Deacon <will(a)kernel.org> > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Cc: Suzuki Poulose <suzuki.poulose(a)arm.com> > Cc: coresight(a)lists.linaro.org > Cc: linux-doc(a)vger.kernel.org > Cc: linux-arm-kernel(a)lists.infradead.org > Cc: linux-kernel(a)vger.kernel.org > Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> > --- Reviewed-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > Documentation/arm64/silicon-errata.rst | 2 ++ > arch/arm64/Kconfig | 23 +++++++++++++++++++++++ > arch/arm64/kernel/cpu_errata.c | 9 +++++++++ > arch/arm64/tools/cpucaps | 1 + > 4 files changed, 35 insertions(+) > > diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst > index c9b30e6c2b6c..e0ef3e9a4b8b 100644 > --- a/Documentation/arm64/silicon-errata.rst > +++ b/Documentation/arm64/silicon-errata.rst > @@ -54,6 +54,8 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A510 | #2064142 | ARM64_ERRATUM_2064142 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Cortex-A510 | #2038923 | ARM64_ERRATUM_2038923 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index e27ccfe9fa9c..188eae6ef28d 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -796,6 +796,29 @@ config ARM64_ERRATUM_2064142 > > If unsure, say Y. > > +config ARM64_ERRATUM_2038923 > + bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" > + depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in > + default y > + help > + This option adds the workaround for ARM Cortex-A510 erratum 2038923. > + > + Affected Cortex-A510 core might cause an inconsistent view on whether trace is > + prohibited within the CPU. As a result, the trace buffer or trace buffer state > + might be corrupted. This happens after TRBE buffer has been enabled by setting > + TRBLIMITR_EL1.E, followed by just a single context synchronization event before > + execution changes from a context, in which trace is prohibited to one where it > + isn't, or vice versa. In these mentioned conditions, the view of whether trace > + is prohibited is inconsistent between parts of the CPU, and the trace buffer or > + the trace buffer state might be corrupted. > + > + Work around this in the driver by preventing an inconsistent view of whether the > + trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a > + change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or > + two ISB instructions if no ERET is to take place. > + > + If unsure, say Y. > + > config CAVIUM_ERRATUM_22375 > bool "Cavium erratum 22375, 24313" > default y > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index cbb7d5a9aee7..60b0c1f1d912 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -607,6 +607,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { > ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) > }, > #endif > +#ifdef CONFIG_ARM64_ERRATUM_2038923 > + { > + .desc = "ARM erratum 2038923", > + .capability = ARM64_WORKAROUND_2038923, > + > + /* Cortex-A510 r0p0 - r0p2 */ > + ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) > + }, > +#endif > { > } > }; > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index fca3cb329e1d..45a06d36d080 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -56,6 +56,7 @@ WORKAROUND_1463225 > WORKAROUND_1508412 > WORKAROUND_1542419 > WORKAROUND_2064142 > +WORKAROUND_2038923 > WORKAROUND_TRBE_OVERWRITE_FILL_MODE > WORKAROUND_TSB_FLUSH_FAILURE > WORKAROUND_TRBE_WRITE_OUT_OF_RANGE

3 years, 4 months

Re: [PATCH V2 2/7] arm64: errata: Add detection for TRBE ignored system register writes

by Suzuki K Poulose

On 07/01/2022 01:10, Anshuman Khandual wrote: > TRBE implementations affected by Arm erratum #2064142 might fail to write > into certain system registers after the TRBE has been disabled. Under some > conditions after TRBE has been disabled, writes into certain TRBE registers > TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1 and TRBTRG_EL1 will be > ignored and not be effected. This adds a new errata ARM64_ERRATUM_2064142 > in arm64 errata framework. > > Cc: Catalin Marinas <catalin.marinas(a)arm.com> > Cc: Will Deacon <will(a)kernel.org> > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Cc: Suzuki Poulose <suzuki.poulose(a)arm.com> > Cc: coresight(a)lists.linaro.org > Cc: linux-doc(a)vger.kernel.org > Cc: linux-arm-kernel(a)lists.infradead.org > Cc: linux-kernel(a)vger.kernel.org > Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> > --- > Documentation/arm64/silicon-errata.rst | 2 ++ > arch/arm64/Kconfig | 18 ++++++++++++++++++ > arch/arm64/kernel/cpu_errata.c | 9 +++++++++ > arch/arm64/tools/cpucaps | 1 + > 4 files changed, 30 insertions(+) > Reviewed-by: Suzuki K Poulose <suzuki.poulose(a)arm.com>

3 years, 4 months

Re: [PATCH 3/4] coresight: trbe: Work around the invalid prohibited states

by Suzuki K Poulose

On 06/01/2022 09:10, Anshuman Khandual wrote: > > > On 1/5/22 7:24 PM, Suzuki K Poulose wrote: >> On 05/01/2022 11:16, Anshuman Khandual wrote: >>> >>> >>> On 1/5/22 3:43 PM, Suzuki K Poulose wrote: >>>> Hi Anshuman >>>> >>>> On 05/01/2022 05:05, Anshuman Khandual wrote: >>>>> TRBE implementations affected by Arm erratum #2038923 might get TRBE into >>>>> an inconsistent view on whether trace is prohibited within the CPU. As a >>>>> result, the trace buffer or trace buffer state might be corrupted. This >>>>> happens after TRBE buffer has been enabled by setting TRBLIMITR_EL1.E, >>>>> followed by just a single context synchronization event before execution >>>>> changes from a context, in which trace is prohibited to one where it isn't, >>>>> or vice versa. In these mentioned conditions, the view of whether trace is >>>>> prohibited is inconsistent between parts of the CPU, and the trace buffer >>>>> or the trace buffer state might be corrupted. >>>>> >>>>> Work around this problem in the TRBE driver by preventing an inconsistent >>>>> view of whether the trace is prohibited or not based on TRBLIMITR_EL1.E by >>>>> immediately following a change to TRBLIMITR_EL1.E with at least one ISB >>>>> instruction before an ERET, or two ISB instructions if no ERET is to take >>>>> place. This adds a new cpu errata in arm64 errata framework and also >>>>> updates TRBE driver as required. >>>>> >>>>> Cc: Catalin Marinas <catalin.marinas(a)arm.com> >>>>> Cc: Will Deacon <will(a)kernel.org> >>>>> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> >>>>> Cc: Suzuki Poulose <suzuki.poulose(a)arm.com> >>>>> Cc: coresight(a)lists.linaro.org >>>>> Cc: linux-doc(a)vger.kernel.org >>>>> Cc: linux-arm-kernel(a)lists.infradead.org >>>>> Cc: linux-kernel(a)vger.kernel.org >>>>> Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> >>>>> --- >>>>> Documentation/arm64/silicon-errata.rst | 2 + >>>>> arch/arm64/Kconfig | 23 ++++++++++ >>>>> arch/arm64/kernel/cpu_errata.c | 9 ++++ >>>>> arch/arm64/tools/cpucaps | 1 + >>>>> drivers/hwtracing/coresight/coresight-trbe.c | 47 +++++++++++++++----- >>>>> 5 files changed, 72 insertions(+), 10 deletions(-) >>>> >>>> As with the previous patch, it may be a good idea to split the >>>> patch to arm64 and trbe parts. >>> >>> Sure, will do. >>> >>>> >>>>> >>>>> diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst >>>>> index c9b30e6c2b6c..e0ef3e9a4b8b 100644 >>>>> --- a/Documentation/arm64/silicon-errata.rst >>>>> +++ b/Documentation/arm64/silicon-errata.rst >>>>> @@ -54,6 +54,8 @@ stable kernels. >>>>> +----------------+-----------------+-----------------+-----------------------------+ >>>>> | ARM | Cortex-A510 | #2064142 | ARM64_ERRATUM_2064142 | >>>>> +----------------+-----------------+-----------------+-----------------------------+ >>>>> +| ARM | Cortex-A510 | #2038923 | ARM64_ERRATUM_2038923 | >>>>> ++----------------+-----------------+-----------------+-----------------------------+ >>>>> | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | >>>>> +----------------+-----------------+-----------------+-----------------------------+ >>>>> | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | >>>>> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >>>>> index 2105b68d88db..026e34fb6fad 100644 >>>>> --- a/arch/arm64/Kconfig >>>>> +++ b/arch/arm64/Kconfig >>>>> @@ -796,6 +796,29 @@ config ARM64_ERRATUM_2064142 >>>>> If unsure, say Y. >>>>> +config ARM64_ERRATUM_2038923 >>>>> + bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" >>>>> + depends on CORESIGHT_TRBE >>>>> + default y >>>>> + help >>>>> + This option adds the workaround for ARM Cortex-A510 erratum 2038923. >>>>> + >>>>> + Affected Cortex-A510 core might cause an inconsistent view on whether trace is >>>>> + prohibited within the CPU. As a result, the trace buffer or trace buffer state >>>>> + might be corrupted. This happens after TRBE buffer has been enabled by setting >>>>> + TRBLIMITR_EL1.E, followed by just a single context synchronization event before >>>>> + execution changes from a context, in which trace is prohibited to one where it >>>>> + isn't, or vice versa. In these mentioned conditions, the view of whether trace >>>>> + is prohibited is inconsistent between parts of the CPU, and the trace buffer or >>>>> + the trace buffer state might be corrupted. >>>>> + >>>>> + Work around this in the driver by preventing an inconsistent view of whether the >>>>> + trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a >>>>> + change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or >>>>> + two ISB instructions if no ERET is to take place. >>>>> + >>>>> + If unsure, say Y. >>>>> + >>>>> config CAVIUM_ERRATUM_22375 >>>>> bool "Cavium erratum 22375, 24313" >>>>> default y >>>>> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c >>>>> index cbb7d5a9aee7..60b0c1f1d912 100644 >>>>> --- a/arch/arm64/kernel/cpu_errata.c >>>>> +++ b/arch/arm64/kernel/cpu_errata.c >>>>> @@ -607,6 +607,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { >>>>> ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) >>>>> }, >>>>> #endif >>>>> +#ifdef CONFIG_ARM64_ERRATUM_2038923 >>>>> + { >>>>> + .desc = "ARM erratum 2038923", >>>>> + .capability = ARM64_WORKAROUND_2038923, >>>>> + >>>>> + /* Cortex-A510 r0p0 - r0p2 */ >>>>> + ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) >>>>> + }, >>>>> +#endif >>>>> { >>>>> } >>>>> }; >>>>> diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps >>>>> index fca3cb329e1d..45a06d36d080 100644 >>>>> --- a/arch/arm64/tools/cpucaps >>>>> +++ b/arch/arm64/tools/cpucaps >>>>> @@ -56,6 +56,7 @@ WORKAROUND_1463225 >>>>> WORKAROUND_1508412 >>>>> WORKAROUND_1542419 >>>>> WORKAROUND_2064142 >>>>> +WORKAROUND_2038923 >>>>> WORKAROUND_TRBE_OVERWRITE_FILL_MODE >>>>> WORKAROUND_TSB_FLUSH_FAILURE >>>>> WORKAROUND_TRBE_WRITE_OUT_OF_RANGE >>>>> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c >>>>> index ec24b62b2cec..0689c6dab96d 100644 >>>>> --- a/drivers/hwtracing/coresight/coresight-trbe.c >>>>> +++ b/drivers/hwtracing/coresight/coresight-trbe.c >>>>> @@ -92,11 +92,13 @@ struct trbe_buf { >>>>> #define TRBE_WORKAROUND_OVERWRITE_FILL_MODE 0 >>>>> #define TRBE_WORKAROUND_WRITE_OUT_OF_RANGE 1 >>>>> #define TRBE_WORKAROUND_SYSREG_WRITE_FAILURE 2 >>>>> +#define TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE 3 >>>>> static int trbe_errata_cpucaps[] = { >>>>> [TRBE_WORKAROUND_OVERWRITE_FILL_MODE] = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, >>>>> [TRBE_WORKAROUND_WRITE_OUT_OF_RANGE] = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, >>>>> [TRBE_WORKAROUND_SYSREG_WRITE_FAILURE] = ARM64_WORKAROUND_2064142, >>>>> + [TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE] = ARM64_WORKAROUND_2038923, >>>>> -1, /* Sentinel, must be the last entry */ >>>>> }; >>>>> @@ -174,6 +176,11 @@ static inline bool trbe_may_fail_sysreg_write(struct trbe_cpudata *cpudata) >>>>> return trbe_has_erratum(cpudata, TRBE_WORKAROUND_SYSREG_WRITE_FAILURE); >>>>> } >>>>> +static inline bool trbe_may_corrupt_with_enable(struct trbe_cpudata *cpudata) >>>>> +{ >>>> >>>> minor nit: trbe_needs_{ctxt_sync, isb}_after_enable() ? >>> >>> trbe_needs_ctxt_sync_after_enable() sounds better. Also will have to change >>> the index above as well .. TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE. >>> >>>> >>>>> + return trbe_has_erratum(cpudata, TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE); >>>>> +} >>>>> + >>>>> static int trbe_alloc_node(struct perf_event *event) >>>>> { >>>>> if (event->cpu == -1) >>>>> @@ -187,6 +194,30 @@ static inline void trbe_drain_buffer(void) >>>>> dsb(nsh); >>>>> } >>>>> +static inline void set_trbe_enabled(struct trbe_cpudata *cpudata) >>>>> +{ >>>>> + u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1); >>>> >>>> minor nit: This implies we do the TRBE programming in the following >>>> manner in the common case (i.e, TRBE enabled in the beginning of a >>>> session). >>>> -> set TRBE LIMIT >>>> -> read TRBE LIMIT >>>> -> set TRBE ENABLED >>>> >>>> Could we please optimize this ? I believe the buf->trbe_limit >>>> must hold the LIMITR value at any point in time. And thus this >>> >>> But is not bit risky though ! We have got the following places where >>> given trbe_limit instance changes its value. >>> >>> drivers/../coresight-trbe.c: buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE; >>> drivers/../coresight-trbe.c: buf->trbe_limit = compute_trbe_buffer_limit(handle); >>> drivers/../coresight-trbe.c: buf->trbe_limit -= PAGE_SIZE; >> >> Those are the places where we compute the trbe_limit, *before* >> we enable the TRBE. And we don't change recompute the limit >> *without disabling* the TRBE. To make it more clear, the >> only place where we set TRBE enabled without "computing" >> the trbe_limit is when we hit a spurious interrupt. >> But the value in the TRBLIMITR should already match the >> buf->trbe_limit and we are only going to re-enable the >> TRBE with the same limit. The other option is to >> pass down the "limit" to the set_trbe_enabled(). > > Since there are just two instances where set_trbe_enabled() gets > called, passing down an additional parameter 'trblimitr' should > still be okay. Some additional code change (like the following) > will achieve this. Does this look okay ? > > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -201,10 +201,8 @@ static inline void trbe_drain_buffer(void) > dsb(nsh); > } > > -static inline void set_trbe_enabled(struct trbe_cpudata *cpudata) > +static inline void set_trbe_enabled(struct trbe_cpudata *cpudata, u64 trblimitr) > { > - u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1); > - > /* > * Enable the TRBE without clearing LIMITPTR which > * might be required for fetching the buffer limits. > @@ -626,7 +624,7 @@ static void set_trbe_limit_pointer_enabled(struct trbe_buf *buf) > trblimitr |= (addr & PAGE_MASK); > > write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1); You could skip this ^ write. Otherwise looks good to me. Suzuki > - set_trbe_enabled(buf->cpudata); > + set_trbe_enabled(buf->cpudata, trblimitr); > } > > static void trbe_enable_hw(struct trbe_buf *buf) > @@ -1050,13 +1048,14 @@ static int arm_trbe_disable(struct coresight_device *csdev) > static void trbe_handle_spurious(struct perf_output_handle *handle) > { > struct trbe_buf *buf = etm_perf_sink_config(handle); > + u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1); > > /* > * If the IRQ was spurious, simply re-enable the TRBE > * back without modifying the buffer parameters to > * retain the trace collected so far. > */ > - set_trbe_enabled(buf->cpudata); > + set_trbe_enabled(buf->cpudata, trblimitr); > } > > static int trbe_handle_overflow(struct perf_output_handle *handle) > > >> >>> >>>> function could simply be : >>>> >>>> set_trbe_enabled(trbe_buf) >>>> { >>>> limitr = trbe_buf->limit | LIMITR_ENABLE >>>> write(limitr, TRBLIMITR_EL1); >>>> ... >>>> } >>> >>> Is the potential for performance improvement here, out weigh possible >>> risks of using buf->trbe_limit directly while enabling the TRBE ? >> >> I somehow don't like the fact that we have additional write and read >> for the most common case of the TRBE usage (i.e, for arm_trbe_enable()). >> If we could avoid that, that may be better. >> >> Cheers >> Suzuki

3 years, 4 months

Re: [PATCH 3/4] coresight: trbe: Work around the invalid prohibited states

by Suzuki K Poulose

On 05/01/2022 11:16, Anshuman Khandual wrote: > > > On 1/5/22 3:43 PM, Suzuki K Poulose wrote: >> Hi Anshuman >> >> On 05/01/2022 05:05, Anshuman Khandual wrote: >>> TRBE implementations affected by Arm erratum #2038923 might get TRBE into >>> an inconsistent view on whether trace is prohibited within the CPU. As a >>> result, the trace buffer or trace buffer state might be corrupted. This >>> happens after TRBE buffer has been enabled by setting TRBLIMITR_EL1.E, >>> followed by just a single context synchronization event before execution >>> changes from a context, in which trace is prohibited to one where it isn't, >>> or vice versa. In these mentioned conditions, the view of whether trace is >>> prohibited is inconsistent between parts of the CPU, and the trace buffer >>> or the trace buffer state might be corrupted. >>> >>> Work around this problem in the TRBE driver by preventing an inconsistent >>> view of whether the trace is prohibited or not based on TRBLIMITR_EL1.E by >>> immediately following a change to TRBLIMITR_EL1.E with at least one ISB >>> instruction before an ERET, or two ISB instructions if no ERET is to take >>> place. This adds a new cpu errata in arm64 errata framework and also >>> updates TRBE driver as required. >>> >>> Cc: Catalin Marinas <catalin.marinas(a)arm.com> >>> Cc: Will Deacon <will(a)kernel.org> >>> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> >>> Cc: Suzuki Poulose <suzuki.poulose(a)arm.com> >>> Cc: coresight(a)lists.linaro.org >>> Cc: linux-doc(a)vger.kernel.org >>> Cc: linux-arm-kernel(a)lists.infradead.org >>> Cc: linux-kernel(a)vger.kernel.org >>> Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> >>> --- >>> Documentation/arm64/silicon-errata.rst | 2 + >>> arch/arm64/Kconfig | 23 ++++++++++ >>> arch/arm64/kernel/cpu_errata.c | 9 ++++ >>> arch/arm64/tools/cpucaps | 1 + >>> drivers/hwtracing/coresight/coresight-trbe.c | 47 +++++++++++++++----- >>> 5 files changed, 72 insertions(+), 10 deletions(-) >> >> As with the previous patch, it may be a good idea to split the >> patch to arm64 and trbe parts. > > Sure, will do. > >> >>> >>> diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst >>> index c9b30e6c2b6c..e0ef3e9a4b8b 100644 >>> --- a/Documentation/arm64/silicon-errata.rst >>> +++ b/Documentation/arm64/silicon-errata.rst >>> @@ -54,6 +54,8 @@ stable kernels. >>> +----------------+-----------------+-----------------+-----------------------------+ >>> | ARM | Cortex-A510 | #2064142 | ARM64_ERRATUM_2064142 | >>> +----------------+-----------------+-----------------+-----------------------------+ >>> +| ARM | Cortex-A510 | #2038923 | ARM64_ERRATUM_2038923 | >>> ++----------------+-----------------+-----------------+-----------------------------+ >>> | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | >>> +----------------+-----------------+-----------------+-----------------------------+ >>> | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | >>> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >>> index 2105b68d88db..026e34fb6fad 100644 >>> --- a/arch/arm64/Kconfig >>> +++ b/arch/arm64/Kconfig >>> @@ -796,6 +796,29 @@ config ARM64_ERRATUM_2064142 >>> If unsure, say Y. >>> +config ARM64_ERRATUM_2038923 >>> + bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" >>> + depends on CORESIGHT_TRBE >>> + default y >>> + help >>> + This option adds the workaround for ARM Cortex-A510 erratum 2038923. >>> + >>> + Affected Cortex-A510 core might cause an inconsistent view on whether trace is >>> + prohibited within the CPU. As a result, the trace buffer or trace buffer state >>> + might be corrupted. This happens after TRBE buffer has been enabled by setting >>> + TRBLIMITR_EL1.E, followed by just a single context synchronization event before >>> + execution changes from a context, in which trace is prohibited to one where it >>> + isn't, or vice versa. In these mentioned conditions, the view of whether trace >>> + is prohibited is inconsistent between parts of the CPU, and the trace buffer or >>> + the trace buffer state might be corrupted. >>> + >>> + Work around this in the driver by preventing an inconsistent view of whether the >>> + trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a >>> + change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or >>> + two ISB instructions if no ERET is to take place. >>> + >>> + If unsure, say Y. >>> + >>> config CAVIUM_ERRATUM_22375 >>> bool "Cavium erratum 22375, 24313" >>> default y >>> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c >>> index cbb7d5a9aee7..60b0c1f1d912 100644 >>> --- a/arch/arm64/kernel/cpu_errata.c >>> +++ b/arch/arm64/kernel/cpu_errata.c >>> @@ -607,6 +607,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { >>> ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) >>> }, >>> #endif >>> +#ifdef CONFIG_ARM64_ERRATUM_2038923 >>> + { >>> + .desc = "ARM erratum 2038923", >>> + .capability = ARM64_WORKAROUND_2038923, >>> + >>> + /* Cortex-A510 r0p0 - r0p2 */ >>> + ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) >>> + }, >>> +#endif >>> { >>> } >>> }; >>> diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps >>> index fca3cb329e1d..45a06d36d080 100644 >>> --- a/arch/arm64/tools/cpucaps >>> +++ b/arch/arm64/tools/cpucaps >>> @@ -56,6 +56,7 @@ WORKAROUND_1463225 >>> WORKAROUND_1508412 >>> WORKAROUND_1542419 >>> WORKAROUND_2064142 >>> +WORKAROUND_2038923 >>> WORKAROUND_TRBE_OVERWRITE_FILL_MODE >>> WORKAROUND_TSB_FLUSH_FAILURE >>> WORKAROUND_TRBE_WRITE_OUT_OF_RANGE >>> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c >>> index ec24b62b2cec..0689c6dab96d 100644 >>> --- a/drivers/hwtracing/coresight/coresight-trbe.c >>> +++ b/drivers/hwtracing/coresight/coresight-trbe.c >>> @@ -92,11 +92,13 @@ struct trbe_buf { >>> #define TRBE_WORKAROUND_OVERWRITE_FILL_MODE 0 >>> #define TRBE_WORKAROUND_WRITE_OUT_OF_RANGE 1 >>> #define TRBE_WORKAROUND_SYSREG_WRITE_FAILURE 2 >>> +#define TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE 3 >>> static int trbe_errata_cpucaps[] = { >>> [TRBE_WORKAROUND_OVERWRITE_FILL_MODE] = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, >>> [TRBE_WORKAROUND_WRITE_OUT_OF_RANGE] = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, >>> [TRBE_WORKAROUND_SYSREG_WRITE_FAILURE] = ARM64_WORKAROUND_2064142, >>> + [TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE] = ARM64_WORKAROUND_2038923, >>> -1, /* Sentinel, must be the last entry */ >>> }; >>> @@ -174,6 +176,11 @@ static inline bool trbe_may_fail_sysreg_write(struct trbe_cpudata *cpudata) >>> return trbe_has_erratum(cpudata, TRBE_WORKAROUND_SYSREG_WRITE_FAILURE); >>> } >>> +static inline bool trbe_may_corrupt_with_enable(struct trbe_cpudata *cpudata) >>> +{ >> >> minor nit: trbe_needs_{ctxt_sync, isb}_after_enable() ? > > trbe_needs_ctxt_sync_after_enable() sounds better. Also will have to change > the index above as well .. TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE. > >> >>> + return trbe_has_erratum(cpudata, TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE); >>> +} >>> + >>> static int trbe_alloc_node(struct perf_event *event) >>> { >>> if (event->cpu == -1) >>> @@ -187,6 +194,30 @@ static inline void trbe_drain_buffer(void) >>> dsb(nsh); >>> } >>> +static inline void set_trbe_enabled(struct trbe_cpudata *cpudata) >>> +{ >>> + u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1); >> >> minor nit: This implies we do the TRBE programming in the following >> manner in the common case (i.e, TRBE enabled in the beginning of a >> session). >> -> set TRBE LIMIT >> -> read TRBE LIMIT >> -> set TRBE ENABLED >> >> Could we please optimize this ? I believe the buf->trbe_limit >> must hold the LIMITR value at any point in time. And thus this > > But is not bit risky though ! We have got the following places where > given trbe_limit instance changes its value. > > drivers/../coresight-trbe.c: buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE; > drivers/../coresight-trbe.c: buf->trbe_limit = compute_trbe_buffer_limit(handle); > drivers/../coresight-trbe.c: buf->trbe_limit -= PAGE_SIZE; Those are the places where we compute the trbe_limit, *before* we enable the TRBE. And we don't change recompute the limit *without disabling* the TRBE. To make it more clear, the only place where we set TRBE enabled without "computing" the trbe_limit is when we hit a spurious interrupt. But the value in the TRBLIMITR should already match the buf->trbe_limit and we are only going to re-enable the TRBE with the same limit. The other option is to pass down the "limit" to the set_trbe_enabled(). > >> function could simply be : >> >> set_trbe_enabled(trbe_buf) >> { >> limitr = trbe_buf->limit | LIMITR_ENABLE >> write(limitr, TRBLIMITR_EL1); >> ... >> } > > Is the potential for performance improvement here, out weigh possible > risks of using buf->trbe_limit directly while enabling the TRBE ? I somehow don't like the fact that we have additional write and read for the most common case of the TRBE usage (i.e, for arm_trbe_enable()). If we could avoid that, that may be better. Cheers Suzuki

3 years, 4 months

Re: [PATCH 4/4] coresight: trbe: Workaround TRBE trace data corruption

by Suzuki K Poulose

On 05/01/2022 05:05, Anshuman Khandual wrote: > TRBE implementations affected by Arm erratum #1902691 might corrupt trace > data or deadlock, when it's being written into the memory. Workaround this > problem in the driver, by preventing TRBE initialization on affected cpus. > This adds a new cpu errata in arm64 errata framework and also updates TRBE > driver as required. > > Cc: Catalin Marinas <catalin.marinas(a)arm.com> > Cc: Will Deacon <will(a)kernel.org> > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Cc: Suzuki Poulose <suzuki.poulose(a)arm.com> > Cc: coresight(a)lists.linaro.org > Cc: linux-doc(a)vger.kernel.org > Cc: linux-arm-kernel(a)lists.infradead.org > Cc: linux-kernel(a)vger.kernel.org > Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> > --- > Documentation/arm64/silicon-errata.rst | 2 ++ > arch/arm64/Kconfig | 16 ++++++++++++++++ > arch/arm64/kernel/cpu_errata.c | 9 +++++++++ > arch/arm64/tools/cpucaps | 1 + > drivers/hwtracing/coresight/coresight-trbe.c | 12 ++++++++++++ > 5 files changed, 40 insertions(+) > > diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst > index e0ef3e9a4b8b..50018f60c4d4 100644 > --- a/Documentation/arm64/silicon-errata.rst > +++ b/Documentation/arm64/silicon-errata.rst > @@ -56,6 +56,8 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A510 | #2038923 | ARM64_ERRATUM_2038923 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Cortex-A510 | #1902691 | ARM64_ERRATUM_1902691 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 026e34fb6fad..1ea5c3b4aac0 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -819,6 +819,22 @@ config ARM64_ERRATUM_2038923 > > If unsure, say Y. > > +config ARM64_ERRATUM_1902691 > + bool "Cortex-A510: 1902691: workaround TRBE trace corruption" > + depends on CORESIGHT_TRBE > + default y > + help > + This option adds the workaround for ARM Cortex-A510 erratum 1902691. > + > + Affected Cortex-A510 core might cause trace data corruption, when being written > + into the memory. Effectively TRBE is broken and hence cannot be used to capture > + trace data. > + > + Work around this problem in the driver by just preventing TRBE initialization on > + affected cpus. > + > + If unsure, say Y. > + It might be better to add : "The firmware must have disabled the access to TRBE for the kernel on such implementations. This will cover the kernel for any firmware that doesn't do this already" > config CAVIUM_ERRATUM_22375 > bool "Cavium erratum 22375, 24313" > default y > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index 60b0c1f1d912..a3336dfb5a8a 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -615,6 +615,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { > /* Cortex-A510 r0p0 - r0p2 */ > ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) > }, > +#endif > +#ifdef CONFIG_ARM64_ERRATUM_1902691 > + { > + .desc = "ARM erratum 1902691", > + .capability = ARM64_WORKAROUND_1902691, > + > + /* Cortex-A510 r0p0 - r0p1 */ > + ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1) > + }, > #endif > { > } > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index 45a06d36d080..e7719e8f18de 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -57,6 +57,7 @@ WORKAROUND_1508412 > WORKAROUND_1542419 > WORKAROUND_2064142 > WORKAROUND_2038923 > +WORKAROUND_1902691 > WORKAROUND_TRBE_OVERWRITE_FILL_MODE > WORKAROUND_TSB_FLUSH_FAILURE > WORKAROUND_TRBE_WRITE_OUT_OF_RANGE > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > index 0689c6dab96d..b9b4e34fac15 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -93,12 +93,14 @@ struct trbe_buf { > #define TRBE_WORKAROUND_WRITE_OUT_OF_RANGE 1 > #define TRBE_WORKAROUND_SYSREG_WRITE_FAILURE 2 > #define TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE 3 > +#define TRBE_IS_BROKEN 4 > > static int trbe_errata_cpucaps[] = { > [TRBE_WORKAROUND_OVERWRITE_FILL_MODE] = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, > [TRBE_WORKAROUND_WRITE_OUT_OF_RANGE] = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, > [TRBE_WORKAROUND_SYSREG_WRITE_FAILURE] = ARM64_WORKAROUND_2064142, > [TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE] = ARM64_WORKAROUND_2038923, > + [TRBE_IS_BROKEN] = ARM64_WORKAROUND_1902691, > -1, /* Sentinel, must be the last entry */ > }; > > @@ -181,6 +183,11 @@ static inline bool trbe_may_corrupt_with_enable(struct trbe_cpudata *cpudata) > return trbe_has_erratum(cpudata, TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE); > } > > +static inline bool trbe_is_broken(struct trbe_cpudata *cpudata) > +{ > + return trbe_has_erratum(cpudata, TRBE_IS_BROKEN); > +} > + > static int trbe_alloc_node(struct perf_event *event) > { > if (event->cpu == -1) > @@ -1291,6 +1298,11 @@ static void arm_trbe_probe_cpu(void *info) > */ > trbe_check_errata(cpudata); > > + if (trbe_is_broken(cpudata)) { > + pr_err("TRBE might corrupt the trace on cpu %d\n", cpu); It may be better to say: "Disabling TRBE on CPU%d due to erratum" Otherwise looks good to me. Suzuki

3 years, 4 months

Re: [PATCH 3/4] coresight: trbe: Work around the invalid prohibited states

by Suzuki K Poulose

Hi Anshuman On 05/01/2022 05:05, Anshuman Khandual wrote: > TRBE implementations affected by Arm erratum #2038923 might get TRBE into > an inconsistent view on whether trace is prohibited within the CPU. As a > result, the trace buffer or trace buffer state might be corrupted. This > happens after TRBE buffer has been enabled by setting TRBLIMITR_EL1.E, > followed by just a single context synchronization event before execution > changes from a context, in which trace is prohibited to one where it isn't, > or vice versa. In these mentioned conditions, the view of whether trace is > prohibited is inconsistent between parts of the CPU, and the trace buffer > or the trace buffer state might be corrupted. > > Work around this problem in the TRBE driver by preventing an inconsistent > view of whether the trace is prohibited or not based on TRBLIMITR_EL1.E by > immediately following a change to TRBLIMITR_EL1.E with at least one ISB > instruction before an ERET, or two ISB instructions if no ERET is to take > place. This adds a new cpu errata in arm64 errata framework and also > updates TRBE driver as required. > > Cc: Catalin Marinas <catalin.marinas(a)arm.com> > Cc: Will Deacon <will(a)kernel.org> > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Cc: Suzuki Poulose <suzuki.poulose(a)arm.com> > Cc: coresight(a)lists.linaro.org > Cc: linux-doc(a)vger.kernel.org > Cc: linux-arm-kernel(a)lists.infradead.org > Cc: linux-kernel(a)vger.kernel.org > Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> > --- > Documentation/arm64/silicon-errata.rst | 2 + > arch/arm64/Kconfig | 23 ++++++++++ > arch/arm64/kernel/cpu_errata.c | 9 ++++ > arch/arm64/tools/cpucaps | 1 + > drivers/hwtracing/coresight/coresight-trbe.c | 47 +++++++++++++++----- > 5 files changed, 72 insertions(+), 10 deletions(-) As with the previous patch, it may be a good idea to split the patch to arm64 and trbe parts. > > diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst > index c9b30e6c2b6c..e0ef3e9a4b8b 100644 > --- a/Documentation/arm64/silicon-errata.rst > +++ b/Documentation/arm64/silicon-errata.rst > @@ -54,6 +54,8 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A510 | #2064142 | ARM64_ERRATUM_2064142 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Cortex-A510 | #2038923 | ARM64_ERRATUM_2038923 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 2105b68d88db..026e34fb6fad 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -796,6 +796,29 @@ config ARM64_ERRATUM_2064142 > > If unsure, say Y. > > +config ARM64_ERRATUM_2038923 > + bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" > + depends on CORESIGHT_TRBE > + default y > + help > + This option adds the workaround for ARM Cortex-A510 erratum 2038923. > + > + Affected Cortex-A510 core might cause an inconsistent view on whether trace is > + prohibited within the CPU. As a result, the trace buffer or trace buffer state > + might be corrupted. This happens after TRBE buffer has been enabled by setting > + TRBLIMITR_EL1.E, followed by just a single context synchronization event before > + execution changes from a context, in which trace is prohibited to one where it > + isn't, or vice versa. In these mentioned conditions, the view of whether trace > + is prohibited is inconsistent between parts of the CPU, and the trace buffer or > + the trace buffer state might be corrupted. > + > + Work around this in the driver by preventing an inconsistent view of whether the > + trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a > + change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or > + two ISB instructions if no ERET is to take place. > + > + If unsure, say Y. > + > config CAVIUM_ERRATUM_22375 > bool "Cavium erratum 22375, 24313" > default y > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index cbb7d5a9aee7..60b0c1f1d912 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -607,6 +607,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { > ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) > }, > #endif > +#ifdef CONFIG_ARM64_ERRATUM_2038923 > + { > + .desc = "ARM erratum 2038923", > + .capability = ARM64_WORKAROUND_2038923, > + > + /* Cortex-A510 r0p0 - r0p2 */ > + ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) > + }, > +#endif > { > } > }; > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index fca3cb329e1d..45a06d36d080 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -56,6 +56,7 @@ WORKAROUND_1463225 > WORKAROUND_1508412 > WORKAROUND_1542419 > WORKAROUND_2064142 > +WORKAROUND_2038923 > WORKAROUND_TRBE_OVERWRITE_FILL_MODE > WORKAROUND_TSB_FLUSH_FAILURE > WORKAROUND_TRBE_WRITE_OUT_OF_RANGE > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > index ec24b62b2cec..0689c6dab96d 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -92,11 +92,13 @@ struct trbe_buf { > #define TRBE_WORKAROUND_OVERWRITE_FILL_MODE 0 > #define TRBE_WORKAROUND_WRITE_OUT_OF_RANGE 1 > #define TRBE_WORKAROUND_SYSREG_WRITE_FAILURE 2 > +#define TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE 3 > > static int trbe_errata_cpucaps[] = { > [TRBE_WORKAROUND_OVERWRITE_FILL_MODE] = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, > [TRBE_WORKAROUND_WRITE_OUT_OF_RANGE] = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, > [TRBE_WORKAROUND_SYSREG_WRITE_FAILURE] = ARM64_WORKAROUND_2064142, > + [TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE] = ARM64_WORKAROUND_2038923, > -1, /* Sentinel, must be the last entry */ > }; > > @@ -174,6 +176,11 @@ static inline bool trbe_may_fail_sysreg_write(struct trbe_cpudata *cpudata) > return trbe_has_erratum(cpudata, TRBE_WORKAROUND_SYSREG_WRITE_FAILURE); > } > > +static inline bool trbe_may_corrupt_with_enable(struct trbe_cpudata *cpudata) > +{ minor nit: trbe_needs_{ctxt_sync, isb}_after_enable() ? > + return trbe_has_erratum(cpudata, TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE); > +} > + > static int trbe_alloc_node(struct perf_event *event) > { > if (event->cpu == -1) > @@ -187,6 +194,30 @@ static inline void trbe_drain_buffer(void) > dsb(nsh); > } > > +static inline void set_trbe_enabled(struct trbe_cpudata *cpudata) > +{ > + u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1); minor nit: This implies we do the TRBE programming in the following manner in the common case (i.e, TRBE enabled in the beginning of a session). -> set TRBE LIMIT -> read TRBE LIMIT -> set TRBE ENABLED Could we please optimize this ? I believe the buf->trbe_limit must hold the LIMITR value at any point in time. And thus this function could simply be : set_trbe_enabled(trbe_buf) { limitr = trbe_buf->limit | LIMITR_ENABLE write(limitr, TRBLIMITR_EL1); ... } Otherwise looks good to me Suzuki

3 years, 4 months

Re: [PATCH 1/4] arm64: Add Cortex-A510 CPU part definition

by Suzuki K Poulose

On 05/01/2022 05:05, Anshuman Khandual wrote: > Add the CPU Partnumbers for the new Arm designs. > > Cc: Catalin Marinas <catalin.marinas(a)arm.com> > Cc: Will Deacon <will(a)kernel.org> > Cc: Suzuki Poulose <suzuki.poulose(a)arm.com> > Cc: linux-arm-kernel(a)lists.infradead.org > Cc: linux-kernel(a)vger.kernel.org > Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> > --- > arch/arm64/include/asm/cputype.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h > index 19b8441aa8f2..e8fdc10395b6 100644 > --- a/arch/arm64/include/asm/cputype.h > +++ b/arch/arm64/include/asm/cputype.h > @@ -73,6 +73,7 @@ > #define ARM_CPU_PART_CORTEX_A76 0xD0B > #define ARM_CPU_PART_NEOVERSE_N1 0xD0C > #define ARM_CPU_PART_CORTEX_A77 0xD0D > +#define ARM_CPU_PART_CORTEX_A510 0xD46 > #define ARM_CPU_PART_CORTEX_A710 0xD47 > #define ARM_CPU_PART_NEOVERSE_N2 0xD49 Reviewed-by: Suzuki K Poulose <suzuki.poulose(a)arm.com>

3 years, 4 months

Re: [PATCH 2/4] coresight: trbe: Work around the ignored system register writes

by Suzuki K Poulose

Hi Anshuman On 05/01/2022 05:05, Anshuman Khandual wrote: > TRBE implementations affected by Arm erratum #2064142 might fail to write > into certain system registers after the TRBE has been disabled. Under some > conditions after TRBE has been disabled, writes into certain TRBE registers > TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1 and TRBTRG_EL1 will be > ignored and not be effected. > > Work around this problem in the TRBE driver by executing TSB CSYNC and DSB > just after the trace collection has stopped and before performing a system > register write to one of the affected registers. This adds a new cpu errata > in arm64 errata framework and also updates TRBE driver as required. > > Cc: Catalin Marinas <catalin.marinas(a)arm.com> > Cc: Will Deacon <will(a)kernel.org> > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Cc: Suzuki Poulose <suzuki.poulose(a)arm.com> > Cc: coresight(a)lists.linaro.org > Cc: linux-doc(a)vger.kernel.org > Cc: linux-arm-kernel(a)lists.infradead.org > Cc: linux-kernel(a)vger.kernel.org > Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> > --- > Documentation/arm64/silicon-errata.rst | 2 + > arch/arm64/Kconfig | 18 +++++++ > arch/arm64/kernel/cpu_errata.c | 9 ++++ > arch/arm64/tools/cpucaps | 1 + > drivers/hwtracing/coresight/coresight-trbe.c | 54 ++++++++++++++------ > drivers/hwtracing/coresight/coresight-trbe.h | 8 --- > 6 files changed, 68 insertions(+), 24 deletions(-) I think it may be a good idea to split the patch into two parts : - arm64 kernel part. (cpucap defintions and detection) - trbe driver part So that it is easier to merge these series upstream to avoid conflicts. > > diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst > index 5342e895fb60..c9b30e6c2b6c 100644 > --- a/Documentation/arm64/silicon-errata.rst > +++ b/Documentation/arm64/silicon-errata.rst > @@ -52,6 +52,8 @@ stable kernels. > | Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 | > +----------------+-----------------+-----------------+-----------------------------+ > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Cortex-A510 | #2064142 | ARM64_ERRATUM_2064142 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index c4207cf9bb17..2105b68d88db 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -778,6 +778,24 @@ config ARM64_ERRATUM_2224489 > > If unsure, say Y. > > +config ARM64_ERRATUM_2064142 > + bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" > + depends on CORESIGHT_TRBE > + default y > + help > + This option adds the workaround for ARM Cortex-A510 erratum 2064142. > + > + Affected Cortex-A510 core might fail to write into system registers after the > + TRBE has been disabled. Under some conditions after the TRBE has been disabled > + writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, > + and TRBTRG_EL1 will be ignored and will not be effected. > + > + Work around this in the driver by executing TSB CSYNC and DSB after collection > + is stopped and before performing a system register write to one of the affected > + registers. > + > + If unsure, say Y. > + > config CAVIUM_ERRATUM_22375 > bool "Cavium erratum 22375, 24313" > default y > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index 9e1c1aef9ebd..cbb7d5a9aee7 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -597,6 +597,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { > .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, > CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus), > }, > +#endif > +#ifdef CONFIG_ARM64_ERRATUM_2064142 > + { > + .desc = "ARM erratum 2064142", > + .capability = ARM64_WORKAROUND_2064142, > + > + /* Cortex-A510 r0p0 - r0p2 */ > + ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) > + }, > #endif > { > } > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index 870c39537dd0..fca3cb329e1d 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -55,6 +55,7 @@ WORKAROUND_1418040 > WORKAROUND_1463225 > WORKAROUND_1508412 > WORKAROUND_1542419 > +WORKAROUND_2064142 > WORKAROUND_TRBE_OVERWRITE_FILL_MODE > WORKAROUND_TSB_FLUSH_FAILURE > WORKAROUND_TRBE_WRITE_OUT_OF_RANGE > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > index 276862c07e32..ec24b62b2cec 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -91,10 +91,12 @@ struct trbe_buf { > */ > #define TRBE_WORKAROUND_OVERWRITE_FILL_MODE 0 > #define TRBE_WORKAROUND_WRITE_OUT_OF_RANGE 1 > +#define TRBE_WORKAROUND_SYSREG_WRITE_FAILURE 2 > > static int trbe_errata_cpucaps[] = { > [TRBE_WORKAROUND_OVERWRITE_FILL_MODE] = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, > [TRBE_WORKAROUND_WRITE_OUT_OF_RANGE] = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, > + [TRBE_WORKAROUND_SYSREG_WRITE_FAILURE] = ARM64_WORKAROUND_2064142, super minor nit: TRBE_NEEDS_DRAIN_AFTER_DISABLE ? > -1, /* Sentinel, must be the last entry */ > }; > > @@ -167,6 +169,11 @@ static inline bool trbe_may_write_out_of_range(struct trbe_cpudata *cpudata) > return trbe_has_erratum(cpudata, TRBE_WORKAROUND_WRITE_OUT_OF_RANGE); > } > > +static inline bool trbe_may_fail_sysreg_write(struct trbe_cpudata *cpudata) > +{ minor nit: trbe_needs_drain_after_disable() ? Either ways, the patch looks good to me. Suzuki

3 years, 4 months

Re: [RFC V3 PATCH] coresight: change tmc from misc device to cdev device

by Mathieu Poirier

Good day Jay, For your next iteration, please remove the "RFC" from the patch title, we are well pass that now. On Tue, Dec 21, 2021 at 08:04:37PM +0800, Jay Chen wrote: > Currently, there are 130 etr and etf on our machine, > but the current coresight tmc driver uses misc_register > to register the device, which leads to the error that > the device number is not enough. > > coresight-tmc: probe of xxxxx failed with error -16 > > This patch changes the device registration method > to cdev's dynamic registration method to solve the > problem of insufficient device numbers. This is much better. > > Signed-off-by: Jay Chen <jkchen(a)linux.alibaba.com> > --- > .../hwtracing/coresight/coresight-tmc-core.c | 91 +++++++++++++++---- > drivers/hwtracing/coresight/coresight-tmc.h | 10 +- > 2 files changed, 83 insertions(+), 18 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c > index d0276af82494..0d51071e9f88 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-core.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c > @@ -31,6 +31,12 @@ DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb"); > DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf"); > DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr"); > > +static DEFINE_IDA(tmc_ida); > +static dev_t tmc_major; > +static struct class *tmc_class; > + > +#define TMC_DEV_MAX (MINORMASK + 1) > + > void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) > { > struct coresight_device *csdev = drvdata->csdev; > @@ -147,7 +153,7 @@ static int tmc_open(struct inode *inode, struct file *file) > { > int ret; > struct tmc_drvdata *drvdata = container_of(file->private_data, > - struct tmc_drvdata, miscdev); > + struct tmc_drvdata, cdev); > > ret = tmc_read_prepare(drvdata); > if (ret) > @@ -179,7 +185,7 @@ static ssize_t tmc_read(struct file *file, char __user *data, size_t len, > char *bufp; > ssize_t actual; > struct tmc_drvdata *drvdata = container_of(file->private_data, > - struct tmc_drvdata, miscdev); > + struct tmc_drvdata, cdev); > actual = tmc_get_sysfs_trace(drvdata, *ppos, len, &bufp); > if (actual <= 0) > return 0; > @@ -200,7 +206,7 @@ static int tmc_release(struct inode *inode, struct file *file) > { > int ret; > struct tmc_drvdata *drvdata = container_of(file->private_data, > - struct tmc_drvdata, miscdev); > + struct tmc_drvdata, cdev); > > ret = tmc_read_unprepare(drvdata); > if (ret) > @@ -451,6 +457,7 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) > { > int ret = 0; > u32 devid; > + dev_t devt; > void __iomem *base; > struct device *dev = &adev->dev; > struct coresight_platform_data *pdata = NULL; > @@ -546,14 +553,32 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) > goto out; > } > > - drvdata->miscdev.name = desc.name; > - drvdata->miscdev.minor = MISC_DYNAMIC_MINOR; > - drvdata->miscdev.fops = &tmc_fops; > - ret = misc_register(&drvdata->miscdev); > + ret = ida_simple_get(&tmc_ida, 0, TMC_DEV_MAX, GFP_KERNEL); > + if (ret < 0) > + goto err_coresight_unregister; > + > + cdev_init(&drvdata->cdev.cdev, &tmc_fops); > + drvdata->cdev.cdev.owner = THIS_MODULE; > + devt = MKDEV(MAJOR(tmc_major), ret); > + ret = cdev_add(&drvdata->cdev.cdev, devt, 1); > if (ret) > - coresight_unregister(drvdata->csdev); > - else > + goto err_free_tmc_ida; > + > + drvdata->cdev.dev = device_create(tmc_class, NULL, devt, &drvdata->cdev, desc.name); > + if (IS_ERR(drvdata->cdev.dev)) { > + ret = PTR_ERR(drvdata->cdev.dev); > + goto err_delete_cdev; > + } else > pm_runtime_put(&adev->dev); > + > + return 0; > + > +err_delete_cdev: > + cdev_del(&drvdata->cdev.cdev); > +err_free_tmc_ida: > + ida_simple_remove(&tmc_ida, MINOR(devt)); > +err_coresight_unregister: > + coresight_unregister(drvdata->csdev); > out: > return ret; > } > @@ -583,13 +608,11 @@ static void tmc_shutdown(struct amba_device *adev) > static void tmc_remove(struct amba_device *adev) > { > struct tmc_drvdata *drvdata = dev_get_drvdata(&adev->dev); > + struct device *dev = drvdata->cdev.dev; > > - /* > - * Since misc_open() holds a refcount on the f_ops, which is > - * etb fops in this case, device is there until last file > - * handler to this device is closed. > - */ > - misc_deregister(&drvdata->miscdev); > + ida_simple_remove(&tmc_ida, dev->devt); ida_simple_remove(&tmc_ida, MINOR(dev->devt)); > + device_destroy(tmc_class, dev->devt); > + cdev_del(&drvdata->cdev.cdev); > coresight_unregister(drvdata->csdev); > } > > @@ -618,7 +641,43 @@ static struct amba_driver tmc_driver = { > .id_table = tmc_ids, > }; > > -module_amba_driver(tmc_driver); > +static int __init tmc_init(void) > +{ > + int ret; > + > + ret = alloc_chrdev_region(&tmc_major, 0, TMC_DEV_MAX, "tmc"); > + if (ret < 0) { > + pr_err("tmc: failed to allocate char dev region\n"); > + return ret; > + } > + > + tmc_class = class_create(THIS_MODULE, "tmc"); > + if (IS_ERR(tmc_class)) { > + pr_err("tmc: failed to create class\n"); > + ret = PTR_ERR(tmc_class); > + unregister_chrdev_region(tmc_major, TMC_DEV_MAX); > + return ret; You can simply return PTR_ERR(tmc_class)... > + } > + > + ret = amba_driver_register(&tmc_driver); > + if (ret) { > + pr_err("tmc: error registering amba driver\n"); > + class_destroy(tmc_class); > + unregister_chrdev_region(tmc_major, TMC_DEV_MAX); > + } > + > + return ret; > +} > + > +static void __exit tmc_exit(void) > +{ > + amba_driver_unregister(&tmc_driver); > + class_destroy(tmc_class); > + unregister_chrdev_region(tmc_major, TMC_DEV_MAX); > +} > + > +module_init(tmc_init); > +module_exit(tmc_exit); > > MODULE_AUTHOR("Pratik Patel <pratikp(a)codeaurora.org>"); > MODULE_DESCRIPTION("Arm CoreSight Trace Memory Controller driver"); > diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h > index 6bec20a392b3..b65ac363f9e4 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc.h > +++ b/drivers/hwtracing/coresight/coresight-tmc.h > @@ -7,6 +7,7 @@ > #ifndef _CORESIGHT_TMC_H > #define _CORESIGHT_TMC_H > > +#include <linux/cdev.h> > #include <linux/dma-mapping.h> > #include <linux/idr.h> > #include <linux/miscdevice.h> miscdevice.h can likely be removed in both .c and .h files. Thanks, Mathieu > @@ -163,11 +164,16 @@ struct etr_buf { > void *private; > }; > > +struct tmc_cdev { > + struct cdev cdev; > + struct device *dev; > +}; > + > /** > * struct tmc_drvdata - specifics associated to an TMC component > * @base: memory mapped base address for this component. > * @csdev: component vitals needed by the framework. > - * @miscdev: specifics to handle "/dev/xyz.tmc" entry. > + * @tmc_cdev: specifics to handle "/dev/xyz.tmc" entry. > * @spinlock: only one at a time pls. > * @pid: Process ID of the process being monitored by the session > * that is using this component. > @@ -191,7 +197,7 @@ struct etr_buf { > struct tmc_drvdata { > void __iomem *base; > struct coresight_device *csdev; > - struct miscdevice miscdev; > + struct tmc_cdev cdev; > spinlock_t spinlock; > pid_t pid; > bool reading; > -- > 2.27.0 >

3 years, 4 months

[GIT PULL] Coresight changes for v5.17

by Mathieu Poirier

The following changes since commit fa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf: Linux 5.16-rc1 (2021-11-14 13:56:52 -0800) are available in the Git repository at: git@gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v5.17 for you to fetch changes up to efa56eddf5d5c03a90abe708431f16c12c291837: coresight: core: Fix typo in a comment (2021-12-13 11:54:07 -0700) ---------------------------------------------------------------- Coresight changes for v5.17 Hi Greg, I'm sending this a little early due to the holiday schedule. There might be another pull request for rc8 in January - let's see when we get there. This pull request includes: - A patch that uses devm_bitmap_zalloc() instead of the open-coded equivalent. - Work to make coresight complex configuration loadable via modules. - Some coresight documentation updates. Signed-off-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> ---------------------------------------------------------------- Christophe JAILLET (1): coresight: Use devm_bitmap_zalloc when applicable Jason Wang (1): coresight: core: Fix typo in a comment Mike Leach (7): Documentation: coresight: Fix documentation issue coresight: configuration: Update API to introduce load owner concept coresight: configuration: Update API to permit dynamic load/unload coresight: syscfg: Update load API for config loadable modules coresight: syscfg: Example CoreSight configuration loadable module coresight: configfs: Allow configfs to activate configuration Documentation: coresight: Update coresight configuration docs Documentation/trace/coresight/coresight-config.rst | 78 ++++- MAINTAINERS | 1 + .../hwtracing/coresight/coresight-cfg-preload.c | 9 +- drivers/hwtracing/coresight/coresight-config.h | 9 +- drivers/hwtracing/coresight/coresight-core.c | 2 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 11 +- drivers/hwtracing/coresight/coresight-stm.c | 10 +- .../coresight/coresight-syscfg-configfs.c | 87 ++++++ .../coresight/coresight-syscfg-configfs.h | 4 + drivers/hwtracing/coresight/coresight-syscfg.c | 315 +++++++++++++++++++-- drivers/hwtracing/coresight/coresight-syscfg.h | 39 ++- samples/Kconfig | 9 + samples/Makefile | 1 + samples/coresight/Makefile | 4 + samples/coresight/coresight-cfg-sample.c | 73 +++++ 15 files changed, 595 insertions(+), 57 deletions(-) create mode 100644 samples/coresight/Makefile create mode 100644 samples/coresight/coresight-cfg-sample.c

3 years, 4 months

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