CoreSight

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2387 discussions

[PATCH v2 RESEND 0/4] coresight: etm: Correct PID tracing for non-root namespace

by Leo Yan

If a profiling program runs in a non-root PID namespace and CoreSight driver enables PID tracing (with contextID), it can lead to mismatching issue between the context ID traced in hardware (from the root namespace) and the PIDs gathered by profiling tool (e.g. perf) in its non-root namespace. CoreSight driver has tried to address this issue for the contextID related interfaces under sysfs, but it misses to prevent user to set VMID (virtual contextID) for kernel runs in EL2 with VHE; furthermore, it misses to handle the case when the profiling tool runs in the non-root PID namespace. For this reason, this patch series is to correct contextID tracing for non-root namespace. After applied this patchset, patch 02 doesn't permit users to access virtual contextID via sysfs nodes in the non-root PID namespace, patch 03 and 04 stop to trace PID packet for non-root PID namespace. This patch series has been rebased on the mainline kernel and applied cleanly on latest commit dcb85f85fa6f ("gcc-plugins/stackleak: Use noinstr in favor of notrace"). Leo Yan (4): coresight: etm4x: Add lock for reading virtual context ID comparator coresight: etm4x: Don't use virtual contextID for non-root PID namespace coresight: etm4x: Don't trace PID for non-root PID namespace coresight: etm3x: Don't trace PID for non-root PID namespace .../coresight/coresight-etm3x-core.c | 4 +++ .../coresight/coresight-etm4x-core.c | 10 +++++-- .../coresight/coresight-etm4x-sysfs.c | 30 +++++++++++++++++++ 3 files changed, 42 insertions(+), 2 deletions(-) -- 2.25.1

3 years, 4 months

Re: [PATCH v2 01/15] coresight: Make ETM4x TRCIDR0 register accesses consistent with sysreg.h

by Suzuki K Poulose

On 07/02/2022 05:44, Anshuman Khandual wrote: > Hi James, > > These are all ETM4X specific changes. Something like this might be cleaner > and also more compact. Also would suggest to follow the same for subsequent > patches as well. > > coresight: etm4x: Cleanup TRCIDR0 register accesses > > Consistency with sysreg.h could be mentioned in the commit message itself. > > On 2/3/22 5:35 PM, James Clark wrote: >> This is a no-op change for style and consistency and has no effect on the >> binary produced by gcc-11. > > This patch adds register definitions, helper macros as well. Please expand > the commit message to add more details. This is too short, for the change > it creates. BTW why is it necessary to mention GCC version number here. > >> >> Signed-off-by: James Clark <james.clark(a)arm.com> >> --- >> .../coresight/coresight-etm4x-core.c | 36 +++++-------------- >> drivers/hwtracing/coresight/coresight-etm4x.h | 17 +++++++++ >> drivers/hwtracing/coresight/coresight-priv.h | 5 +++ >> 3 files changed, 30 insertions(+), 28 deletions(-) >> >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> index e2eebd865241..107e81948f76 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> @@ -1091,41 +1091,21 @@ static void etm4_init_arch_data(void *info) >> etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0); >> >> /* INSTP0, bits[2:1] P0 tracing support field */ >> - if (BMVAL(etmidr0, 1, 2) == 0b11) >> - drvdata->instrp0 = true; >> - else >> - drvdata->instrp0 = false; >> - >> + drvdata->instrp0 = !!(REG_VAL(etmidr0, TRCIDR0_INSTP0) == 0b11); >> /* TRCBB, bit[5] Branch broadcast tracing support bit */ >> - if (BMVAL(etmidr0, 5, 5)) >> - drvdata->trcbb = true; >> - else >> - drvdata->trcbb = false; >> - >> + drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB); >> /* TRCCOND, bit[6] Conditional instruction tracing support bit */ >> - if (BMVAL(etmidr0, 6, 6)) >> - drvdata->trccond = true; >> - else >> - drvdata->trccond = false; >> - >> + drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND); >> /* TRCCCI, bit[7] Cycle counting instruction bit */ >> - if (BMVAL(etmidr0, 7, 7)) >> - drvdata->trccci = true; >> - else >> - drvdata->trccci = false; >> - >> + drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI); >> /* RETSTACK, bit[9] Return stack bit */ >> - if (BMVAL(etmidr0, 9, 9)) >> - drvdata->retstack = true; >> - else >> - drvdata->retstack = false; >> - >> + drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK); >> /* NUMEVENT, bits[11:10] Number of events field */ >> - drvdata->nr_event = BMVAL(etmidr0, 10, 11); >> + drvdata->nr_event = REG_VAL(etmidr0, TRCIDR0_NUMEVENT); >> /* QSUPP, bits[16:15] Q element support field */ >> - drvdata->q_support = BMVAL(etmidr0, 15, 16); >> + drvdata->q_support = REG_VAL(etmidr0, TRCIDR0_QSUPP); >> /* TSSIZE, bits[28:24] Global timestamp size field */ >> - drvdata->ts_size = BMVAL(etmidr0, 24, 28); >> + drvdata->ts_size = REG_VAL(etmidr0, TRCIDR0_TSSIZE); >> >> /* maximum size of resources */ >> etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2); >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h >> index 3c4d69b096ca..2bd8ad953b8e 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x.h >> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h >> @@ -130,6 +130,23 @@ >> >> #define TRCRSR_TA BIT(12) >> >> +/* >> + * Bit positions of registers that are defined above, in the sysreg.h style >> + * of _MASK, _SHIFT and BIT(). >> + */ > > ^^^ not really necessary. Instead the format requirement for below mentioned > CORESIGHT_REG_VAL() macro might be relevant and should be mentioned. > >> +#define TRCIDR0_INSTP0_SHIFT 1 >> +#define TRCIDR0_INSTP0_MASK GENMASK(1, 0) >> +#define TRCIDR0_TRCBB BIT(5) >> +#define TRCIDR0_TRCCOND BIT(6) >> +#define TRCIDR0_TRCCCI BIT(7) >> +#define TRCIDR0_RETSTACK BIT(9) >> +#define TRCIDR0_NUMEVENT_SHIFT 10 >> +#define TRCIDR0_NUMEVENT_MASK GENMASK(1, 0) >> +#define TRCIDR0_QSUPP_SHIFT 15 >> +#define TRCIDR0_QSUPP_MASK GENMASK(1, 0) >> +#define TRCIDR0_TSSIZE_SHIFT 24 >> +#define TRCIDR0_TSSIZE_MASK GENMASK(4, 0) >> + >> /* >> * System instructions to access ETM registers. >> * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions >> diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h >> index ff1dd2092ac5..1452c6038421 100644 >> --- a/drivers/hwtracing/coresight/coresight-priv.h >> +++ b/drivers/hwtracing/coresight/coresight-priv.h >> @@ -36,6 +36,11 @@ >> >> #define TIMEOUT_US 100 >> #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) >> +/* >> + * Extract a field from a register where field is #defined in the form >> + * <register_name>_<field_name>_MASK and <register_name>_<field_name>_SHIFT >> + */ > > Looking at the usage, <register_name> is already embedded in <filed_name>. So > it requires <field_name>_SHIFT and <field_name>_MASK instead. Unless register > name should be passed as separate argument (which actually might be better). > > REG_VAL(etmidr0, TRCIDR0_TSSIZE) ----> REG_VAL(etmidr0, TRCIDR0, TSSIZE) I don't see much difference here. So I am fine either way. > > with some restructuring in the comment .. > > /* > * Extract a field from a coresight register > * > * Required fields are defined as macros like the following > * > * <register_name>_<field_name>_MASK and <register_name>_<field_name>_SHIFT > */ > >> +#define REG_VAL(val, field) ((val & (field##_MASK << field##_SHIFT)) >> field##_SHIFT) > > This is too generic to be in a coresight header or it should just be > named CORESIGHT_REG_VAL() instead, making it more specific for here. > > The build should fail in case any required macro definition is absent. > I guess no more fortification is required in case macros are missing. > > However CORESIGHT_REG_VAL() is better placed in <coresight-etm4x.h> > just before all the dependent SHIFT/MASK register field definition > starts. Not necessarily. CORESIGHT_REG_VAL() is a generic function and doesn't have anything specific to do with etm4x. We could reuse that for cleaning up other drivers in CoreSight. Cheers Suzuki

3 years, 4 months

[PATCH 0/1] perf: Set build-id using build-id header on new mmap records

by James Clark

Hi, We are seeing an issue with doing Coresight decode off target where initially the correct dso from ~/.debug is used, but after a new thread in the perf.data file is passed with its mmap record, the local version of the dso is picked up instead. This happens if the binary exists in the same path on both devices, for example /bin/ls. Initially when parsing the build-ids in the header, the dso for /bin/ls will be created, and the file will correctly point to ~/.debug/bin/ls/2f15ad836be3339dec0e2e6a3c637e08e48aacbd/elf, but for any new threads or mmaps that are also for /bin/ls, they will not have a build-id set so they point to /bin/ls on the local machine rather than the debug folder. To fix this I made it possible to look up which existing dsos have build id's set that originate from the header and then copy that build-id onto the new dso if the name matches. Another way to do it would be to stop comparing the mmap id so it matches on filename only, but I think we do want to differentiate between different mmaps, even if they have the same name, which is how it works in this version. Applies to perf/core 859f7e4554 Thanks James James Clark (1): perf: Set build-id using build-id header on new mmap records tools/perf/util/dso.h | 1 + tools/perf/util/header.c | 1 + tools/perf/util/map.c | 16 ++++++++++++++-- 3 files changed, 16 insertions(+), 2 deletions(-) -- 2.28.0

3 years, 4 months

[PATCH 1/2] perf: cs-etm: No-op refactor of synth opt usage

by James Clark

sample_branches and sample_instructions are already saved in the synth_opts struct. Other usages like synth_opts.last_branch don't save a value, so make this more consistent by always going through synth_opts and not saving duplicate values. Signed-off-by: James Clark <james.clark(a)arm.com> --- tools/perf/util/cs-etm.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 4f672f7d008c..796a065a500e 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -50,8 +50,6 @@ struct cs_etm_auxtrace { u8 timeless_decoding; u8 snapshot_mode; u8 data_queued; - u8 sample_branches; - u8 sample_instructions; int num_cpu; u64 latest_kernel_timestamp; @@ -410,8 +408,8 @@ static void cs_etm__packet_swap(struct cs_etm_auxtrace *etm, { struct cs_etm_packet *tmp; - if (etm->sample_branches || etm->synth_opts.last_branch || - etm->sample_instructions) { + if (etm->synth_opts.branches || etm->synth_opts.last_branch || + etm->synth_opts.instructions) { /* * Swap PACKET with PREV_PACKET: PACKET becomes PREV_PACKET for * the next incoming packet. @@ -1365,7 +1363,6 @@ static int cs_etm__synth_events(struct cs_etm_auxtrace *etm, err = cs_etm__synth_event(session, &attr, id); if (err) return err; - etm->sample_branches = true; etm->branches_sample_type = attr.sample_type; etm->branches_id = id; id += 1; @@ -1389,7 +1386,6 @@ static int cs_etm__synth_events(struct cs_etm_auxtrace *etm, err = cs_etm__synth_event(session, &attr, id); if (err) return err; - etm->sample_instructions = true; etm->instructions_sample_type = attr.sample_type; etm->instructions_id = id; id += 1; @@ -1420,7 +1416,7 @@ static int cs_etm__sample(struct cs_etm_queue *etmq, tidq->prev_packet->last_instr_taken_branch) cs_etm__update_last_branch_rb(etmq, tidq); - if (etm->sample_instructions && + if (etm->synth_opts.instructions && tidq->period_instructions >= etm->instructions_sample_period) { /* * Emit instruction sample periodically @@ -1503,7 +1499,7 @@ static int cs_etm__sample(struct cs_etm_queue *etmq, } } - if (etm->sample_branches) { + if (etm->synth_opts.branches) { bool generate_sample = false; /* Generate sample for tracing on packet */ @@ -1582,7 +1578,7 @@ static int cs_etm__flush(struct cs_etm_queue *etmq, } - if (etm->sample_branches && + if (etm->synth_opts.branches && tidq->prev_packet->sample_type == CS_ETM_RANGE) { err = cs_etm__synth_branch_sample(etmq, tidq); if (err) -- 2.28.0

3 years, 4 months

Re: [PATCH v3 10/10] ARM: dts: msm: Add coresight components for SM8250

by Mike Leach

Hi, It would appear here that normal coresight funnels appear between tpdm and tpda devices. This is contrary to my understanding of your hardware and the descriptions and conversations we had in patch 00/10 in this set. trace path appears to be tpdm_mm => funnel@6c0b000 => funnel@6c2d000 => tpda@6004000 => funnel@6005000 => rest of ATB The documentation states that the TPDA is responsible for for funneling and packetising - so why do we have extra funnels? I have no way of knowing if that topology is right or wrong. Are the funnels between tpdm and tpda actual coresight funnels, a component that is register compatible with CS funnels but designed for the TPDM / TPDA transport, or the funnels are being used, but without driving ATID from the sources. It is difficult to review this set without better information on the hardware represented. Regards Mike On Wed, 9 Feb 2022 at 10:58, Mao Jinlong <quic_jinlmao(a)quicinc.com> wrote: > > Add coresight device tree for sm8250. STM/ETM/TPDM are added. > > Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> > Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> > --- > .../arm64/boot/dts/qcom/sm8250-coresight.dtsi | 690 ++++++++++++++++++ > arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 + > 2 files changed, 692 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi > > diff --git a/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi > new file mode 100644 > index 000000000000..732dab7f8674 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi > @@ -0,0 +1,690 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +&soc { > + > + stm@6002000 { > + compatible = "arm,coresight-stm", "arm,primecell"; > + reg = <0 0x06002000 0 0x1000>, > + <0 0x16280000 0 0x180000>; > + reg-names = "stm-base", "stm-stimulus-base"; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + stm_out: endpoint { > + remote-endpoint = > + <&funnel0_in7>; > + }; > + }; > + }; > + }; > + > + funnel@6041000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0 0x06041000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + funnel0_out: endpoint { > + remote-endpoint = > + <&merge_funnel_in0>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@6 { > + reg = <6>; > + funnel_in0_in_funnel_qatb: endpoint { > + remote-endpoint = > + <&funnel_qatb_out_funnel_in0>; > + }; > + }; > + > + port@7 { > + reg = <7>; > + funnel0_in7: endpoint { > + remote-endpoint = <&stm_out>; > + }; > + }; > + }; > + }; > + > + funnel@6042000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0 0x06042000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + funnel2_out: endpoint { > + remote-endpoint = > + <&merge_funnel_in2>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@2 { > + reg = <4>; > + funnel2_in5: endpoint { > + remote-endpoint = > + <&apss_merge_funnel_out>; > + }; > + }; > + }; > + }; > + > + funnel@6b04000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + arm,primecell-periphid = <0x000bb908>; > + > + reg = <0 0x6b04000 0 0x1000>; > + reg-names = "funnel-base"; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + merge_funnel_out: endpoint { > + remote-endpoint = > + <&etf_in>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@7 { > + reg = <7>; > + funnel_swao_in_funnel_merg: endpoint { > + remote-endpoint= > + <&funnel_merg_out_funnel_swao>; > + }; > + }; > + }; > + > + }; > + > + funnel@6045000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0 0x06045000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + funnel_merg_out_funnel_swao: endpoint { > + remote-endpoint = <&funnel_swao_in_funnel_merg>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@1 { > + reg = <0>; > + merge_funnel_in0: endpoint { > + remote-endpoint = > + <&funnel0_out>; > + }; > + }; > + > + port@2 { > + reg = <1>; > + merge_funnel_in2: endpoint { > + remote-endpoint = > + <&funnel2_out>; > + }; > + }; > + }; > + }; > + > + replicator@6046000 { > + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; > + reg = <0 0x06046000 0 0x1000>; > + > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + replicator_out: endpoint { > + remote-endpoint = <&etr_in>; > + }; > + }; > + }; > + > + in-ports { > + port { > + replicator_cx_in_swao_out: endpoint { > + remote-endpoint = <&replicator_swao_out_cx_in>; > + }; > + }; > + }; > + }; > + > + replicator@6b06000 { > + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; > + reg = <0 0x06b06000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + replicator_swao_out_cx_in: endpoint { > + remote-endpoint = <&replicator_cx_in_swao_out>; > + }; > + }; > + }; > + > + in-ports { > + port { > + replicator_in: endpoint { > + remote-endpoint = <&etf_out>; > + }; > + }; > + }; > + }; > + > + etf@6b05000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0 0x6b05000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + etf_out: endpoint { > + remote-endpoint = > + <&replicator_in>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@1 { > + reg = <0>; > + etf_in: endpoint { > + remote-endpoint = > + <&merge_funnel_out>; > + }; > + }; > + }; > + }; > + > + etr@6048000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0 0x06048000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,scatter-gather; > + > + in-ports { > + port { > + etr_in: endpoint { > + remote-endpoint = > + <&replicator_out>; > + }; > + }; > + }; > + }; > + > + etm@7040000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07040000 0 0x1000>; > + > + cpu = <&CPU0>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm0_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in0>; > + }; > + }; > + }; > + }; > + > + etm@7140000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07140000 0 0x1000>; > + > + cpu = <&CPU1>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm1_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in1>; > + }; > + }; > + }; > + }; > + > + etm@7240000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07240000 0 0x1000>; > + > + cpu = <&CPU2>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm2_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in2>; > + }; > + }; > + }; > + }; > + > + etm@7340000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07340000 0 0x1000>; > + > + cpu = <&CPU3>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm3_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in3>; > + }; > + }; > + }; > + }; > + > + etm@7440000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07440000 0 0x1000>; > + > + cpu = <&CPU4>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm4_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in4>; > + }; > + }; > + }; > + }; > + > + etm@7540000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07540000 0 0x1000>; > + > + cpu = <&CPU5>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm5_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in5>; > + }; > + }; > + }; > + }; > + > + etm@7640000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07640000 0 0x1000>; > + > + cpu = <&CPU6>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm6_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in6>; > + }; > + }; > + }; > + }; > + > + etm@7740000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07740000 0 0x1000>; > + > + cpu = <&CPU7>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm7_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in7>; > + }; > + }; > + }; > + }; > + > + funnel@7800000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0 0x07800000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + apss_funnel_out: endpoint { > + remote-endpoint = > + <&apss_merge_funnel_in>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + apss_funnel_in0: endpoint { > + remote-endpoint = > + <&etm0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + apss_funnel_in1: endpoint { > + remote-endpoint = > + <&etm1_out>; > + }; > + }; > + > + port@2 { > + reg = <2>; > + apss_funnel_in2: endpoint { > + remote-endpoint = > + <&etm2_out>; > + }; > + }; > + > + port@3 { > + reg = <3>; > + apss_funnel_in3: endpoint { > + remote-endpoint = > + <&etm3_out>; > + }; > + }; > + > + port@4 { > + reg = <4>; > + apss_funnel_in4: endpoint { > + remote-endpoint = > + <&etm4_out>; > + }; > + }; > + > + port@5 { > + reg = <5>; > + apss_funnel_in5: endpoint { > + remote-endpoint = > + <&etm5_out>; > + }; > + }; > + > + port@6 { > + reg = <6>; > + apss_funnel_in6: endpoint { > + remote-endpoint = > + <&etm6_out>; > + }; > + }; > + > + port@7 { > + reg = <7>; > + apss_funnel_in7: endpoint { > + remote-endpoint = > + <&etm7_out>; > + }; > + }; > + }; > + }; > + > + funnel@7810000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0 0x07810000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + apss_merge_funnel_out: endpoint { > + remote-endpoint = > + <&funnel2_in5>; > + }; > + }; > + }; > + > + in-ports { > + port@1 { > + reg = <0>; > + apss_merge_funnel_in: endpoint { > + remote-endpoint = > + <&apss_funnel_out>; > + }; > + }; > + }; > + }; > + > + tpdm_mm: mm.tpdm@6c08000 { > + compatible = "arm,primecell"; > + reg = <0 0x6c08000 0 0x1000>; > + reg-names = "tpdm-base"; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + qcom,msr-fix-req; > + > + out-ports { > + port { > + tpdm_mm_out_funnel_dl_mm: endpoint { > + remote-endpoint = > + <&funnel_dl_mm_in_tpdm_mm>; > + }; > + }; > + }; > + }; > + > + funnel@6c0b000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + > + reg = <0 0x6c0b000 0 0x1000>; > + reg-names = "funnel-base"; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + funnel_dl_mm_out_funnel_dl_center: endpoint { > + remote-endpoint = > + <&funnel_dl_center_in_funnel_dl_mm>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@3 { > + reg = <3>; > + funnel_dl_mm_in_tpdm_mm: endpoint { > + remote-endpoint = > + <&tpdm_mm_out_funnel_dl_mm>; > + }; > + }; > + }; > + }; > + > + funnel@6c2d000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + > + reg = <0 0x6c2d000 0 0x1000>; > + reg-names = "funnel-base"; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + port { > + tpdm_mm_out_tpda9: endpoint { > + remote-endpoint = > + <&tpda_9_in_tpdm_mm>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@2 { > + reg = <2>; > + funnel_dl_center_in_funnel_dl_mm: endpoint { > + remote-endpoint = > + <&funnel_dl_mm_out_funnel_dl_center>; > + }; > + }; > + }; > + }; > + > + tpda@6004000 { > + compatible = "arm,primecell"; > + reg = <0 0x6004000 0 0x1000>; > + reg-names = "tpda-base"; > + > + qcom,tpda-atid = <65>; > + > + qcom,dsb-elem-size = <9 32>, > + <10 32>, > + <14 32>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + reg = <0>; > + tpda_out_funnel_qatb: endpoint { > + remote-endpoint = > + <&funnel_qatb_in_tpda>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@9 { > + reg = <9>; > + tpda_9_in_tpdm_mm: endpoint { > + remote-endpoint = > + <&tpdm_mm_out_tpda9>; > + }; > + }; > + }; > + }; > + > + funnel@6005000 { > + compatible = "arm,primecell"; > + > + reg = <0 0x6005000 0 0x1000>; > + reg-names = "funnel-base"; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + funnel_qatb_out_funnel_in0: endpoint { > + remote-endpoint = > + <&funnel_in0_in_funnel_qatb>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + funnel_qatb_in_tpda: endpoint { > + remote-endpoint = > + <&tpda_out_funnel_qatb>; > + }; > + }; > + }; > + }; > +}; > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi > index 5617a46e5ccd..d1837e3df30a 100644 > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi > @@ -5323,3 +5323,5 @@ > }; > }; > }; > + > +#include "sm8250-coresight.dtsi" > -- > 2.17.1 > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

3 years, 4 months

Re: [PATCH v3 05/10] coresight-tpdm: Add DSB dataset support

by Mike Leach

Hi This patch does not apply cleanly:- ======================================= git apply -v ../patch.in/qcom/qcom-05.patch Checking patch drivers/hwtracing/coresight/coresight-tpdm.c... error: while searching for: DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm"); /** TPDM enable operations **/ static int tpdm_enable(struct coresight_device *csdev, struct perf_event *event, u32 mode) { error: patch failed: drivers/hwtracing/coresight/coresight-tpdm.c:20 error: drivers/hwtracing/coresight/coresight-tpdm.c: patch does not apply Checking patch drivers/hwtracing/coresight/coresight-tpdm.h... ======================================= In patch 3 - the first time coresight-tpdm.c. is added the comment line is /* TPDM enable operations */ Note the single * in the comment. This would seem to indicate missing intermediate patches, or patches from different trees / times. A coherent patch set is needed for review Regards Mike On Wed, 9 Feb 2022 at 10:57, Mao Jinlong <quic_jinlmao(a)quicinc.com> wrote: > > TPDM serves as data collection component for various dataset types. > DSB(Discrete Single Bit) is one of the dataset types. DSB subunit > can be enabled for data collection by writing 1 to the first bit of > DSB_CR register. This change is to add enable/disable function for > DSB dataset by writing DSB_CR register. > > Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> > Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> > --- > drivers/hwtracing/coresight/coresight-tpdm.c | 57 ++++++++++++++++++++ > drivers/hwtracing/coresight/coresight-tpdm.h | 21 ++++++++ > 2 files changed, 78 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c > index 51b8b17e6a80..c6480b7389b0 100644 > --- a/drivers/hwtracing/coresight/coresight-tpdm.c > +++ b/drivers/hwtracing/coresight/coresight-tpdm.c > @@ -20,7 +20,28 @@ > > DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm"); > > +static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) > +{ > + u32 val; > + > + /* Set the enable bit of DSB control register to 1 */ > + val = readl_relaxed(drvdata->base + TPDM_DSB_CR); > + val = val | BIT(0); > + writel_relaxed(val, drvdata->base + TPDM_DSB_CR); > +} > + > /** TPDM enable operations **/ > +static void _tpdm_enable(struct tpdm_drvdata *drvdata) > +{ > + CS_UNLOCK(drvdata->base); > + > + /* Check if DSB datasets is present for TPDM. */ > + if (test_bit(TPDM_DS_DSB, drvdata->datasets)) > + tpdm_enable_dsb(drvdata); > + > + CS_LOCK(drvdata->base); > +} > + > static int tpdm_enable(struct coresight_device *csdev, > struct perf_event *event, u32 mode) > { > @@ -32,6 +53,7 @@ static int tpdm_enable(struct coresight_device *csdev, > return -EBUSY; > } > > + _tpdm_enable(drvdata); > drvdata->enable = true; > mutex_unlock(&drvdata->lock); > > @@ -39,7 +61,29 @@ static int tpdm_enable(struct coresight_device *csdev, > return 0; > } > > +static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata) > +{ > + u32 val; > + > + /* Set the enable bit of DSB control register to 0 */ > + val = readl_relaxed(drvdata->base + TPDM_DSB_CR); > + val = val & ~BIT(0); > + writel_relaxed(val, drvdata->base + TPDM_DSB_CR); > +} > + > /** TPDM disable operations **/ > +static void _tpdm_disable(struct tpdm_drvdata *drvdata) > +{ > + CS_UNLOCK(drvdata->base); > + > + /* Check if DSB datasets is present for TPDM. */ > + if (test_bit(TPDM_DS_DSB, drvdata->datasets)) > + tpdm_disable_dsb(drvdata); > + > + CS_LOCK(drvdata->base); > + > +} > + > static void tpdm_disable(struct coresight_device *csdev, > struct perf_event *event) > { > @@ -51,6 +95,7 @@ static void tpdm_disable(struct coresight_device *csdev, > return; > } > > + _tpdm_disable(drvdata); > drvdata->enable = false; > mutex_unlock(&drvdata->lock); > > @@ -76,7 +121,19 @@ static const struct coresight_ops tpdm_cs_ops = { > > static void tpdm_init_default_data(struct tpdm_drvdata *drvdata) > { > + int i; > + u32 pidr; > + > drvdata->traceid = coresight_get_system_trace_id(); > + > + CS_UNLOCK(drvdata->base); > + /* Get the datasets present on the TPDM. */ > + pidr = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR0); > + for (i = 0; i < TPDM_DATASETS; i++) { > + if (pidr & BIT(i)) > + __set_bit(i, drvdata->datasets); > + } > + CS_LOCK(drvdata->base); > } > > static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h > index 2effbabf349b..cb3ddc6c89ae 100644 > --- a/drivers/hwtracing/coresight/coresight-tpdm.h > +++ b/drivers/hwtracing/coresight/coresight-tpdm.h > @@ -6,6 +6,25 @@ > #ifndef _CORESIGHT_CORESIGHT_TPDM_H > #define _CORESIGHT_CORESIGHT_TPDM_H > > +/* The max number of the datasets that TPDM supports */ > +#define TPDM_DATASETS 7 > + > +/* DSB Subunit Registers */ > +#define TPDM_DSB_CR (0x780) > + > +/** > + * This enum is for PERIPHIDR0 register of TPDM. > + * The fields [6:0] of PERIPHIDR0 are used to determine what > + * interfaces and subunits are present on a given TPDM. > + * > + * PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0 > + * PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0 > + */ > +enum tpdm_dataset { > + TPDM_DS_IMPLDEF, > + TPDM_DS_DSB, > +}; > + > /** > * struct tpdm_drvdata - specifics associated to an TPDM component > * @base: memory mapped base address for this component. > @@ -13,6 +32,7 @@ > * @csdev: component vitals needed by the framework. > * @lock: lock for the enable value. > * @enable: enable status of the component. > + * @datasets: The datasets types present of the TPDM. > * @traceid: value of the current ID for this component. > */ > > @@ -22,6 +42,7 @@ struct tpdm_drvdata { > struct coresight_device *csdev; > struct mutex lock; > bool enable; > + DECLARE_BITMAP(datasets, TPDM_DATASETS); > int traceid; > }; > > -- > 2.17.1 > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

3 years, 4 months

Re: [PATCH v3 03/10] Coresight: Add coresight TPDM source driver

by Mike Leach

HI, On Wed, 9 Feb 2022 at 10:57, Mao Jinlong <quic_jinlmao(a)quicinc.com> wrote: > > Add driver to support Coresight device TPDM (Trace, Profiling and > Diagnostics Monitor). TPDM is a monitor to collect data from > different datasets. This change is to add probe/enable/disable > functions for tpdm source. > > Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> > Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> > --- > drivers/hwtracing/coresight/Kconfig | 13 ++ > drivers/hwtracing/coresight/Makefile | 1 + > drivers/hwtracing/coresight/coresight-core.c | 3 +- > drivers/hwtracing/coresight/coresight-tpdm.c | 159 +++++++++++++++++++ > drivers/hwtracing/coresight/coresight-tpdm.h | 28 ++++ > include/linux/coresight.h | 1 + > 6 files changed, 204 insertions(+), 1 deletion(-) > create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.c > create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.h > > diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig > index 514a9b8086e3..5c506a1cd08f 100644 > --- a/drivers/hwtracing/coresight/Kconfig > +++ b/drivers/hwtracing/coresight/Kconfig > @@ -201,4 +201,17 @@ config CORESIGHT_TRBE > > To compile this driver as a module, choose M here: the module will be > called coresight-trbe. > + > +config CORESIGHT_TPDM > + tristate "CoreSight Trace, Profiling & Diagnostics Monitor driver" > + select CORESIGHT_LINKS_AND_SINKS > + help > + This driver provides support for configuring monitor. Monitors are > + primarily responsible for data set collection and support the > + ability to collect any permutation of data set types. Monitors are > + also responsible for interaction with system cross triggering. > + > + To compile this driver as a module, choose M here: the module will be > + called coresight-tpdm. > + > endif > diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile > index b6c4a48140ec..e7392a0dddeb 100644 > --- a/drivers/hwtracing/coresight/Makefile > +++ b/drivers/hwtracing/coresight/Makefile > @@ -25,5 +25,6 @@ obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o > obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o > obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o > obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o > +obj-$(CONFIG_CORESIGHT_TPDM) += coresight-tpdm.o > coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ > coresight-cti-sysfs.o > diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c > index 6cb55c3f41d5..b56826d9a2b3 100644 > --- a/drivers/hwtracing/coresight/coresight-core.c > +++ b/drivers/hwtracing/coresight/coresight-core.c > @@ -1117,7 +1117,8 @@ static int coresight_validate_source(struct coresight_device *csdev, > } > > if (subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_PROC && > - subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE) { > + subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE && > + subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SYS) { > dev_err(&csdev->dev, "wrong device subtype in %s\n", function); > return -EINVAL; > } > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c > new file mode 100644 > index 000000000000..51b8b17e6a80 > --- /dev/null > +++ b/drivers/hwtracing/coresight/coresight-tpdm.c > @@ -0,0 +1,159 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include <linux/amba/bus.h> > +#include <linux/bitmap.h> > +#include <linux/coresight.h> > +#include <linux/coresight-pmu.h> > +#include <linux/device.h> > +#include <linux/err.h> > +#include <linux/fs.h> > +#include <linux/io.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of.h> > + > +#include "coresight-priv.h" > +#include "coresight-tpdm.h" > + > +DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm"); > + > +/* TPDM enable operations */ > +static int tpdm_enable(struct coresight_device *csdev, > + struct perf_event *event, u32 mode) > +{ > + struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > + > + mutex_lock(&drvdata->lock); > + if (drvdata->enable) { > + mutex_unlock(&drvdata->lock); > + return -EBUSY; > + } > + > + drvdata->enable = true; > + mutex_unlock(&drvdata->lock); > + > + dev_info(drvdata->dev, "TPDM tracing enabled\n"); > + return 0; > +} > + > +/* TPDM disable operations */ > +static void tpdm_disable(struct coresight_device *csdev, > + struct perf_event *event) > +{ > + struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > + > + mutex_lock(&drvdata->lock); > + if (!drvdata->enable) { > + mutex_unlock(&drvdata->lock); > + return; > + } > + > + drvdata->enable = false; > + mutex_unlock(&drvdata->lock); > + > + dev_info(drvdata->dev, "TPDM tracing disabled\n"); > +} > + > +static int tpdm_trace_id(struct coresight_device *csdev) > +{ > + struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > + > + return drvdata->traceid; > +} > + > +static const struct coresight_ops_source tpdm_source_ops = { > + .trace_id = tpdm_trace_id, > + .enable = tpdm_enable, > + .disable = tpdm_disable, > +}; > + > +static const struct coresight_ops tpdm_cs_ops = { > + .source_ops = &tpdm_source_ops, > +}; > + > +static void tpdm_init_default_data(struct tpdm_drvdata *drvdata) > +{ > + drvdata->traceid = coresight_get_system_trace_id(); > +} > + > +static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) > +{ > + struct device *dev = &adev->dev; > + struct coresight_platform_data *pdata; > + struct tpdm_drvdata *drvdata; > + struct coresight_desc desc = { 0 }; > + > + pdata = coresight_get_platform_data(dev); > + if (IS_ERR(pdata)) > + return PTR_ERR(pdata); > + adev->dev.platform_data = pdata; > + > + /* driver data*/ > + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > + if (!drvdata) > + return -ENOMEM; > + drvdata->dev = &adev->dev; > + dev_set_drvdata(dev, drvdata); > + > + drvdata->base = devm_ioremap_resource(dev, &adev->res); > + if (!drvdata->base) > + return -ENOMEM; > + > + mutex_init(&drvdata->lock); > + tpdm_init_default_data(drvdata); > + > + /* Set up coresight component description */ > + desc.name = coresight_alloc_device_name(&tpdm_devs, dev); > + if (!desc.name) > + return -ENOMEM; > + desc.type = CORESIGHT_DEV_TYPE_SOURCE; > + desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_SYS; > + desc.ops = &tpdm_cs_ops; > + desc.pdata = adev->dev.platform_data; > + desc.dev = &adev->dev; > + drvdata->csdev = coresight_register(&desc); > + if (IS_ERR(drvdata->csdev)) > + return PTR_ERR(drvdata->csdev); > + > + /* Decrease pm refcount when probe is done.*/ > + pm_runtime_put(&adev->dev); > + > + return 0; > +} > + > +static void __exit tpdm_remove(struct amba_device *adev) > +{ > + struct tpdm_drvdata *drvdata = dev_get_drvdata(&adev->dev); > + > + coresight_unregister(drvdata->csdev); > +} > + > +/* > + * Different TPDM has different periph id. > + * The difference is 0-7 bits' value. So ignore 0-7 bits. > + */ > +static struct amba_id tpdm_ids[] = { > + { > + .id = 0x000f0e00, > + .mask = 0x000fff00, > + }, > + { 0, 0}, > +}; > + > +static struct amba_driver tpdm_driver = { > + .drv = { > + .name = "coresight-tpdm", > + .owner = THIS_MODULE, > + .suppress_bind_attrs = true, > + }, > + .probe = tpdm_probe, > + .id_table = tpdm_ids, > +}; > + > +module_amba_driver(tpdm_driver); > + > +MODULE_LICENSE("GPL v2"); > +MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Monitor driver"); > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h > new file mode 100644 > index 000000000000..2effbabf349b > --- /dev/null > +++ b/drivers/hwtracing/coresight/coresight-tpdm.h > @@ -0,0 +1,28 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#ifndef _CORESIGHT_CORESIGHT_TPDM_H > +#define _CORESIGHT_CORESIGHT_TPDM_H > + > +/** > + * struct tpdm_drvdata - specifics associated to an TPDM component > + * @base: memory mapped base address for this component. > + * @dev: The device entity associated to this component. > + * @csdev: component vitals needed by the framework. > + * @lock: lock for the enable value. > + * @enable: enable status of the component. > + * @traceid: value of the current ID for this component. > + */ > + > +struct tpdm_drvdata { > + void __iomem *base; > + struct device *dev; > + struct coresight_device *csdev; > + struct mutex lock; > + bool enable; > + int traceid; TraceID appears to have no purpose in the hardware and does not apparently drive onto the ATB - ATID signals from this device. This should be dropped and the core code fixed to allow for sources that have no trace id. Regards Mike > +}; > + > +#endif /* _CORESIGHT_CORESIGHT_TPDM_H */ > diff --git a/include/linux/coresight.h b/include/linux/coresight.h > index 93a2922b7653..e48d463be63b 100644 > --- a/include/linux/coresight.h > +++ b/include/linux/coresight.h > @@ -65,6 +65,7 @@ enum coresight_dev_subtype_source { > CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, > CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, > CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, > + CORESIGHT_DEV_SUBTYPE_SOURCE_SYS, > }; > > enum coresight_dev_subtype_helper { > -- > 2.17.1 > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

3 years, 4 months

Re: [PATCH v3 04/10] dt-bindings: arm: Adds CoreSight TPDM hardware definitions

by Mike Leach

Hi, On Wed, 9 Feb 2022 at 10:57, Mao Jinlong <quic_jinlmao(a)quicinc.com> wrote: > > Adds new coresight-tpdm.yaml file describing the bindings required > to define tpdm in the device trees. > > Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> > Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> > --- > .../bindings/arm/coresight-tpdm.yaml | 81 +++++++++++++++++++ > .../devicetree/bindings/arm/coresight.txt | 7 ++ > MAINTAINERS | 1 + > 3 files changed, 89 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpdm.yaml > > diff --git a/Documentation/devicetree/bindings/arm/coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/coresight-tpdm.yaml > new file mode 100644 > index 000000000000..7ebc1bf7abc2 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/coresight-tpdm.yaml > @@ -0,0 +1,81 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +# Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/coresight-tpdm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Trace, Profiling and Diagnostics Monitor - TPDM > + > +description: | > + The TPDM or Monitor serves as data collection component for various dataset > + types specified in the QPMDA spec. It covers Implementation defined ((ImplDef), > + Basic Counts (BC), Tenure Counts (TC), Continuous Multi-Bit (CMB), and Discrete > + Single Bit (DSB). It performs data collection in the data producing clock > + domain and transfers it to the data collection time domain, generally ATB > + clock domain. > + > + The primary use case of the TPDM is to collect data from different data > + sources and send it to a TPDA for packetization, timestamping, and funneling. > + > +maintainers: > + - Suzuki K Poulose <suzuki.poulose(a)arm.com> > + - Mathieu Poirier <mathieu.poirier(a)linaro.org> > + > +properties: > + $nodename: > + pattern: "^tpdm(@[0-9a-f]+)$" > + compatible: > + items: > + - const: qcom,coresight-tpdm > + - const: arm,primecell > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + items: > + - const: apb_pclk > + > + out-ports: > + description: | > + Output connections from the TPDM to legacy CoreSight trace bus. > + $ref: /schemas/graph.yaml#/properties/ports > + properties: > + port: > + description: Output connection from the TPDM to legacy CoreSight > + Trace bus. > + $ref: /schemas/graph.yaml#/properties/port > + As we discussed in patch 0/10 of this set - the TDPM actually sends data to TDPA - not to coresight. These descriptions should match that. > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + # minimum TPDM definition. > + - | > + tpdm@6980000 { > + compatible = "qcom,coresight-tpdm", "arm,primecell"; > + reg = <0x6980000 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + tpdm_turing_out_funnel_turing: endpoint { > + remote-endpoint = > + <&funnel_turing_in_tpdm_turing>; > + }; > + }; > + }; > + }; > + example looks OK, but I would like to see something of a _tdpa in the nameing as that is the funnel / link the tdpm sends data to. Regards Mike > +... > diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt > index c68d93a35b6c..f7ce8af48574 100644 > --- a/Documentation/devicetree/bindings/arm/coresight.txt > +++ b/Documentation/devicetree/bindings/arm/coresight.txt > @@ -52,6 +52,10 @@ its hardware characteristcs. > "arm,coresight-cti", "arm,primecell"; > See coresight-cti.yaml for full CTI definitions. > > + - Trace, Profiling and Diagnostics Monitor (TPDM): > + "qcom,coresight-tpdm", "arm,primecell"; > + See coresight-tpdm.yaml for full TPDM definitions. > + > * reg: physical base address and length of the register > set(s) of the component. > > @@ -82,6 +86,9 @@ its hardware characteristcs. > * Required properties for Coresight Cross Trigger Interface (CTI) > See coresight-cti.yaml for full CTI definitions. > > +* Required properties for Trace, Profiling and Diagnostics Monitor (TPDM) > + See coresight-tpdm.yaml for full TPDM definitions. > + > * Required properties for devices that don't show up on the AMBA bus, such as > non-configurable replicators and non-configurable funnels: > > diff --git a/MAINTAINERS b/MAINTAINERS > index ea3e6c914384..434bbe98d22b 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1906,6 +1906,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git > F: Documentation/ABI/testing/sysfs-bus-coresight-devices-* > F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt > F: Documentation/devicetree/bindings/arm/coresight-cti.yaml > +F: Documentation/devicetree/bindings/arm/coresight-tpdm.yaml > F: Documentation/devicetree/bindings/arm/coresight.txt > F: Documentation/devicetree/bindings/arm/ete.yaml > F: Documentation/devicetree/bindings/arm/trbe.yaml > -- > 2.17.1 > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

3 years, 4 months

Re: [PATCH v3 02/10] coresight: Use bitmap to assign trace id to the sources

by Mike Leach

Hi, On Wed, 9 Feb 2022 at 10:57, Mao Jinlong <quic_jinlmao(a)quicinc.com> wrote: > > Except from STM and ETM/ETE, there could be other sources. Each > source needs a unique trace id. Define a bitmap for the trace ids. > The position of each bit represents trace id of the source. > > Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> > --- > drivers/hwtracing/coresight/coresight-core.c | 48 ++++++++++++++++++++ > include/linux/coresight-pmu.h | 11 +++++ > 2 files changed, 59 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c > index a90097f88425..6cb55c3f41d5 100644 > --- a/drivers/hwtracing/coresight/coresight-core.c > +++ b/drivers/hwtracing/coresight/coresight-core.c > @@ -16,6 +16,7 @@ > #include <linux/mutex.h> > #include <linux/clk.h> > #include <linux/coresight.h> > +#include <linux/coresight-pmu.h> see my comment below about using coresigh-priv.h > #include <linux/of_platform.h> > #include <linux/delay.h> > #include <linux/pm_runtime.h> > @@ -25,8 +26,11 @@ > #include "coresight-syscfg.h" > > static DEFINE_MUTEX(coresight_mutex); > +static DEFINE_MUTEX(coresight_id_mutex); > static DEFINE_PER_CPU(struct coresight_device *, csdev_sink); > > +static DECLARE_BITMAP(coresight_trace_id, CORESIGHT_TRACE_ID_NUM); > + > /* > * Use IDR to map the hash length of the source's device name > * to the pointer of path for the source > @@ -51,6 +55,48 @@ struct coresight_node { > const u32 coresight_barrier_pkt[4] = {0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff}; > EXPORT_SYMBOL_GPL(coresight_barrier_pkt); > > +/* Init the coresight_trace_id bit map. */ > +static void coresight_init_trace_id(void) > +{ > + int i; > + > + /* Trace id 0 is invalid. */ > + set_bit(CORESIGHT_TRACE_ID_0, coresight_trace_id); > + /* Trace id 1 is fixed for STM. */ > + set_bit(CORESIGHT_TRACE_ID_1, coresight_trace_id); > + /* Trace id from 112 to 127 are reserved. */ > + for (i = CORESIGHT_TRACE_ID_112; i <= CORESIGHT_TRACE_ID_127; i++) > + set_bit(i, coresight_trace_id); > + /* Skip the trace ids of ETM/ETE. */ > + for (i = 0; i <= cpumask_last(cpu_possible_mask); i++) > + set_bit(coresight_get_trace_id(i), coresight_trace_id); > + > +} > + > +/* > + * Return the first zero bit position of bitmap coresight_trace_id > + * as source's trace id. > + * > + */ > +int coresight_get_system_trace_id(void) > +{ > + int id; > + > + mutex_lock(&coresight_id_mutex); > + id = find_first_zero_bit(coresight_trace_id, CORESIGHT_TRACE_ID_NUM); > + /* If no zero bit is found, return error value. */ > + if (id == CORESIGHT_TRACE_ID_NUM) { > + mutex_unlock(&coresight_id_mutex); > + return -EINVAL; > + } > + > + set_bit(id, coresight_trace_id); > + mutex_unlock(&coresight_id_mutex); > + > + return id; > +} > +EXPORT_SYMBOL(coresight_get_system_trace_id); > + > static const struct cti_assoc_op *cti_assoc_ops; > > void coresight_set_cti_ops(const struct cti_assoc_op *cti_op) > @@ -1750,6 +1796,8 @@ static int __init coresight_init(void) > return 0; > > etm_perf_exit(); > + > + coresight_init_trace_id(); > exit_bus_unregister: > bus_unregister(&coresight_bustype); > return ret; > diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h > index 4ac5c081af93..1e2c5ca4c6e6 100644 > --- a/include/linux/coresight-pmu.h > +++ b/include/linux/coresight-pmu.h > @@ -32,6 +32,14 @@ > #define ETM4_CFG_BIT_RETSTK 12 > #define ETM4_CFG_BIT_VMID_OPT 15 > The following additional defines and function should appear in coresight-priv.h The coresight-pmu.h file contains data for the interface between the drivers and perf. > +/* Coresight component supports 7 bits trace id. */ additional comment here to explain that 0, 0x70- 0x7F IDs are reserved by the architecture, 1 is default for STM > +#define CORESIGHT_TRACE_ID_NUM 128 > + > +#define CORESIGHT_TRACE_ID_0 0 > +#define CORESIGHT_TRACE_ID_1 1 > +#define CORESIGHT_TRACE_ID_112 112 > +#define CORESIGHT_TRACE_ID_127 127 > + can we have these names a little more descriptive - e.g. CORESIGHT_TRACE_ID_0_RES 0 CORESIGHT_TRACE_ID_STM 1 CORESIGHT_TRACE_ID_RANGE_LO_RES 0x70 CORESIGHT_TRACE_ID_RANGE_HI_RES 0x7F Additionally - now we are declaring a #define for the STM ID - it would be better to use that in coresight-stm.c stm_init_default_data() to set the trace id for the STM. Regards Mike > static inline int coresight_get_trace_id(int cpu) > { > /* > @@ -43,4 +51,7 @@ static inline int coresight_get_trace_id(int cpu) > return (CORESIGHT_ETM_PMU_SEED + (cpu * 2)); > } > > +/* Get the trace id for the sources except from STM, ETM/ETE. */ > +extern int coresight_get_system_trace_id(void); > + > #endif > -- > 2.17.1 > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

3 years, 4 months

Re: [PATCH v3 00/10] Coresight: Add support for TPDM and TPDA

by Mike Leach

Hi, On Fri, 11 Feb 2022 at 04:17, Jinlong Mao <quic_jinlmao(a)quicinc.com> wrote: > > > On 2/10/2022 6:30 PM, Mike Leach wrote: > > Hello Mao, > > > > I have looked through this set and have a few general questions. > > > > My understanding based on the information in the code is that the TPDM > > devices will always send data to the TPDA device, the TPDM is not > > capable of directly driving the ATB itself? > > The TPDA device will then packetize the inputs and output these to > > the ATB over the normal CoreSight architecture to a standard ETR / ETF > > for collection. > > > > Looking at the TPDM driver - it is assigned a trace ID but never > > actually uses it in the hardware. My assumption here is that this is > > used purely to satisfy the requirement that the CoreSight core has > > that all sources have a unique trace id? > > > > For the TPDA driver you assign an ATID as an attribute in device tree, > > and then program this into the devices control register. > > > > The trace IDs in ETM / ETE / STM, are programmed into the hardware and > > these values drive the ATID value on the trace bus. So assigning an > > ATID value to the TPDA driver through device tree will lead to clashes > > with the assignment of trace IDs in the other driver software. > > > > The topology here appears to me that you have multiple "data source" > > devices TPDM, supplying a TPDA - which is the real CoreSight "trace > > source" from the viewpoint of the trace bus and CoreSight > > infrastructure. > > To get this to work in the current CoreSight driver stack, you have > > assigned the TPDM as a source type, and the TPDA as a link to ensure > > that when a TPDM is started, all the components on the path to the > > sink are activated. > > This is fine. > > > > If my assumptions above are all accurate I suggest the following improvements > > > > For TPDA drop the device tree assignment of ATID and instead use the > > coresight_get_system_trace_id() function you introduce in the 2nd > > patch in this set. > > > > For TPDM you have assigned a unique source sub-type > > CORESIGHT_DEV_SUBTYPE_SOURCE_SYS.- this could become > > CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY. If the trace ID assigned to > > this device is only to satisfy the unique ID requirement and is not > > used elsewhere, then the sub type could become > > CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY. We can agree that this sub > > type does not need a unique ID and acts as none ATB a source for > > another component, The core code can be altered to drop the > > requirement for this sub-type and trace ID can be dropped for this > > component. > > > > You should be aware that we are in the process of re-designed how > > trace IDs are allocated. The current mechanism does not scale for > > large multi-core systems (currently broken for any system > 46 cores), > > and as you have discovered there is a need for additional allocation > > of IDs. Also the ETE / TRBE combination does not need a trace ID. A > > dynamic allocation system is being proposed. > > > > Regards > > > > Mike > > > Hi Mike, > > Your assumptions above are all correct. > TPDMs connect to the same TPDA will share the atid of the TPDA. > We have a PC tool to parse the TPDM trace data. It needs the fixed atid > for each TPDA to identify the data. > So we configure the atid for TPDA in device tree with fixed ids. > I will discuss with internal tool team to see if TPDA's id can become > dynamic when parse the data. > I understand that it is essential to know the ID when extracting the trace from a sink with a coresight frame fomatter. However, tools such as perf, achieve this by saving the metadata for the session. If you are programming the trace ID, then it should be possible to read back the same register to get the required information for your trace session. If this is genuinely not possible for your system, then treat as a fixed ID as I describe below. > Apart from the TPDA's atid, we also have some other sources with fixed > id in HW on our internal device. > Do you have any suggestion to how to allocate the IDs for the source > with fixed id in HW ? > > Fixed IDs in hardware - assuming that these devices do write directly onto the trace bus using the ATID, should be accommodated by reserving the fixed ID in any scheme used to allocate IDs, In your case this would be to set a bit at the correct area in the bitfield. As mentioned we are working on an updated system to dynamically allocate IDs for CoreSight sources - a reservation scheme for fixed ID devices will be provided . Regards Mike >< Thanks > Jinlong Mao > > > > > > > > On Wed, 9 Feb 2022 at 10:57, Mao Jinlong <quic_jinlmao(a)quicinc.com> wrote: > >> This series adds support for the trace performance monitoring and > >> diagnostics hardware (TPDM and TPDA). It is composed of two major > >> elements. > >> a) Changes for original coresight framework to support for TPDM and TPDA. > >> b) Add driver code for TPDM and TPDA. > >> > >> Introduction of changes for original coresight framework > >> Support TPDM as new coresight source. > >> Since only STM and ETM are supported as coresight source originally. > >> TPDM is a newly added coresight source. We need to change > >> the original way of saving coresight path to support more types source > >> for coresight driver. > >> The following patch is to add support more coresight sources. > >> Use IDR to maintain all the enabled sources' paths. > >> coresight: Use bitmap to assign trace id to the sources > >> > >> Introduction of TPDM and TPDA > >> TPDM - The trace performance monitoring and diagnostics monitor or TPDM in > >> short serves as data collection component for various dataset types > >> specified in the QPMDA(Qualcomm performance monitoring and diagnostics > >> architecture) spec. The primary use case of the TPDM is to collect data > >> from different data sources and send it to a TPDA for packetization, > >> timestamping and funneling. > >> Coresight: Add coresight TPDM source driver > >> dt-bindings: arm: Adds CoreSight TPDM hardware definitions > >> coresight-tpdm: Add DSB dataset support > >> coresight-tpdm: Add integration test support > >> docs: sysfs: coresight: Add sysfs ABI documentation for TPDM > >> > >> TPDA - The trace performance monitoring and diagnostics aggregator or > >> TPDA in short serves as an arbitration and packetization engine for the > >> performance monitoring and diagnostics network as specified in the QPMDA > >> (Qualcomm performance monitoring and diagnostics architecture) > >> specification. The primary use case of the TPDA is to provide > >> packetization, funneling and timestamping of Monitor data as specified > >> in the QPMDA specification. > >> The following patch is to add driver for TPDA. > >> Coresight: Add TPDA link driver > >> dt-bindings: arm: Adds CoreSight TPDA hardware definitions > >> > >> The last patch of this series is a device tree modification, which add > >> the TPDM and TPDA configuration to device tree for validating. > >> ARM: dts: msm: Add coresight components for SM8250 > >> > >> Once this series patches are applied properly, the tpdm and tpda nodes > >> should be observed at the coresight path /sys/bus/coresight/devices > >> e.g. > >> /sys/bus/coresight/devices # ls -l | grep tpd > >> tpda0 -> ../../../devices/platform/soc(a)0/6004000.tpda/tpda0 > >> tpdm0 -> ../../../devices/platform/soc(a)0/6c08000.mm.tpdm/tpdm0 > >> > >> We can use the commands are similar to the below to validate TPDMs. > >> Enable coresight sink first. > >> > >> echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink > >> echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source > >> echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test > >> echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test > >> The test data will be collected in the coresight sink which is enabled. > >> If rwp register of the sink is keeping updating when do > >> integration_test (by cat tmc_etf0/mgmt/rwp), it means there is data > >> generated from TPDM to sink. > >> > >> Changes from V2: > >> 1. Use bitmap to assign the trace id. (Mathieu Poirier) > >> > >> Mao Jinlong (10): > >> Use IDR to maintain all the enabled sources' paths. > >> coresight: Use bitmap to assign trace id to the sources > >> Coresight: Add coresight TPDM source driver > >> dt-bindings: arm: Adds CoreSight TPDM hardware definitions > >> coresight-tpdm: Add DSB dataset support > >> coresight-tpdm: Add integration test support > >> docs: sysfs: coresight: Add sysfs ABI documentation for TPDM > >> Coresight: Add TPDA link driver > >> dt-bindings: arm: Adds CoreSight TPDA hardware definitions > >> ARM: dts: msm: Add coresight components for SM8250 > >> > >> .../testing/sysfs-bus-coresight-devices-tpdm | 6 + > >> .../bindings/arm/coresight-tpda.yaml | 129 ++++ > >> .../bindings/arm/coresight-tpdm.yaml | 81 ++ > >> .../devicetree/bindings/arm/coresight.txt | 7 + > >> MAINTAINERS | 1 + > >> .../arm64/boot/dts/qcom/sm8250-coresight.dtsi | 690 ++++++++++++++++++ > >> arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 + > >> drivers/hwtracing/coresight/Kconfig | 33 + > >> drivers/hwtracing/coresight/Makefile | 2 + > >> drivers/hwtracing/coresight/coresight-core.c | 127 ++-- > >> drivers/hwtracing/coresight/coresight-tpda.c | 193 +++++ > >> drivers/hwtracing/coresight/coresight-tpda.h | 32 + > >> drivers/hwtracing/coresight/coresight-tpdm.c | 270 +++++++ > >> drivers/hwtracing/coresight/coresight-tpdm.h | 57 ++ > >> include/linux/coresight-pmu.h | 11 + > >> include/linux/coresight.h | 1 + > >> 16 files changed, 1592 insertions(+), 50 deletions(-) > >> create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > >> create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpda.yaml > >> create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpdm.yaml > >> create mode 100644 arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi > >> create mode 100644 drivers/hwtracing/coresight/coresight-tpda.c > >> create mode 100644 drivers/hwtracing/coresight/coresight-tpda.h > >> create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.c > >> create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.h > >> > >> -- > >> 2.17.1 > >> > > > > -- > > Mike Leach > > Principal Engineer, ARM Ltd. > > Manchester Design Centre. UK -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

3 years, 4 months

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