CoreSight September 2026

coresight@lists.linaro.org

5 participants
23 discussions

[PATCH v11 0/9] fix several inconsistencies with sysfs configuration in etmX

by Yeoreum Yun

The current ETMx configuration via sysfs can lead to the following inconsistencies: - If a configuration is modified via sysfs while a perf session is active, the running configuration may differ between before a sched-out and after a subsequent sched-in. - If a perf session and sysfs session tries to enable concurrently, configuration from configfs could be corrupted (etm4). - There is chance to corrupt drvdata->config if perf session tries to enabled among handling cscfg_csdev_disable_active_config() in etm4_disable_sysfs() (etm4). To resolve these inconsistencies, the configuration should be separated into: - active_config, which is applied configuration for the current session - config, which stores the settings configured via sysfs. and apply configuration from configfs after taking a mode. Patch History ============= from v10 to 11: - replace direct register read from etm3 sysfs with IPI. - fix issue cntr_val and others field which required to be shown after sysfs session disable. - prohibit the write for some etm3 sysfs while sysfs session is enabled. - drop locktype change in etm3 - Link to v10: https://lore.kernel.org/r/20260911-separate_etm_cfg_v2-v10-0-1b715d95927a@a… from v9 to v10: - rebase to coresight/next - https://lore.kernel.org/all/20260725113645.57519-1-yeoreum.yun@arm.com/ from v8 to v9: - add feat_csdev_lock guard interface. - set feat_csdev->drv_spinlock as NULL for etmv4_drvdata. - https://lore.kernel.org/all/20260629090007.1718746-1-yeoreum.yun@arm.com/ from v7 to v8: - accept @Leo Yan' suggestion to handle error. - small minor fixes following @Suzuki' suggestion. - https://lore.kernel.org/all/20260519154812.254884-1-yeoreum.yun@arm.com/ from v6 to v7: - rebase on coresight/next - add ETM_MAX_SEQ_TRANSITIONS define - remove redundant patch relavent cpu-hotplug as coresight-pm patch merged. - https://lore.kernel.org/all/20260422132203.977549-1-yeoreum.yun@arm.com/ from v5 to v6: - fix missing of calling cscfg_csdev_disable_active_config() - add rb & fixes tags. - add ss_status field in etm4x_drvdata to expose STATUS and PENDING bits. - https://lore.kernel.org/all/20260415165528.3369607-1-yeoreum.yun@arm.com/ from v4 to v5: - add rb-tag. - fix underflow issue for nrseqstate. - fix wrong check in etm4_sspcicrn_present(). - remove redundant fields on etmv4_save_state. - rename caps->ss_status to ss_cmp. - fix wrong location of etm4_release_trace_id. - https://lore.kernel.org/all/20260413142003.3549310-1-yeoreum.yun@arm.com/ from v3 to v4: - change etm_drvdata->spinlock type to raw_spin_lock_t - remove redundant call etmX_enable_hw() with starting_cpu() callsback. - fix missing trace id release. - add missing docs. - https://lore.kernel.org/all/20260412175506.412301-1-yeoreum.yun@arm.com/ from v2 to v3: - fix build error for etm3x. - fix checkpatch warning. - https://lore.kernel.org/all/20260410074310.2693385-1-yeoreum.yun@arm.com/ from v1 to v2 - rebased to v7.0-rc7. - introduce etmX_caps structure to save etmX's capabilities. - remove ss_status from etmv4_config. - modify active_config after taking a mode (perf/sysfs). - https://lore.kernel.org/all/20260317181705.2456271-1-yeoreum.yun@arm.com/ --- Yeoreum Yun (9): coresight: etm4x: prohibit modifying ss_status and cntr_val while session is enabled coresight: etm3x: prohibit modifying cntr_val and reset while session is enabled coresight: etm4x: fix inconsistencies with sysfs configuration coresight: etm3x: fix inconsistencies with sysfs configuration coresight: etm3x: remove redundant cpu online check on etm_enable_sysfs() coresight: etm4x: introduce struct etm4_caps coresight: etm4x: exclude ss_status from drvdata->config coresight: etm4x: remove s_ex_level from config coresight: etm3x: introduce struct etm_caps drivers/hwtracing/coresight/coresight-config.c | 18 +- drivers/hwtracing/coresight/coresight-config.h | 22 ++ drivers/hwtracing/coresight/coresight-etm.h | 46 ++- drivers/hwtracing/coresight/coresight-etm3x-core.c | 126 +++--- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 104 +++-- drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 14 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 426 +++++++++++---------- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 210 ++++++---- drivers/hwtracing/coresight/coresight-etm4x.h | 196 +++++----- 9 files changed, 676 insertions(+), 486 deletions(-) --- base-commit: 9e3604d7369cfc0110100eb1a0acab1865ee2d18 change-id: 20260911-separate_etm_cfg_v2-3518a168cbff Best regards, -- Sincerely, Yeoreum Yun

2 days, 10 hours

[PATCH v10 0/8] fix several inconsistencies with sysfs configuration in etmX

by Yeoreum Yun

The current ETMx configuration via sysfs can lead to the following inconsistencies: - If a configuration is modified via sysfs while a perf session is active, the running configuration may differ between before a sched-out and after a subsequent sched-in. - If a perf session and sysfs session tries to enable concurrently, configuration from configfs could be corrupted (etm4). - There is chance to corrupt drvdata->config if perf session tries to enabled among handling cscfg_csdev_disable_active_config() in etm4_disable_sysfs() (etm4). To resolve these inconsistencies, the configuration should be separated into: - active_config, which is applied configuration for the current session - config, which stores the settings configured via sysfs. and apply configuration from configfs after taking a mode. Patch History ============= from v9 to v10: - rebase to coresight/next - https://lore.kernel.org/all/20260725113645.57519-1-yeoreum.yun@arm.com/ from v8 to v9: - add feat_csdev_lock guard interface. - set feat_csdev->drv_spinlock as NULL for etmv4_drvdata. - https://lore.kernel.org/all/20260629090007.1718746-1-yeoreum.yun@arm.com/ from v7 to v8: - accept @Leo Yan' suggestion to handle error. - small minor fixes following @Suzuki' suggestion. - https://lore.kernel.org/all/20260519154812.254884-1-yeoreum.yun@arm.com/ from v6 to v7: - rebase on coresight/next - add ETM_MAX_SEQ_TRANSITIONS define - remove redundant patch relavent cpu-hotplug as coresight-pm patch merged. - https://lore.kernel.org/all/20260422132203.977549-1-yeoreum.yun@arm.com/ from v5 to v6: - fix missing of calling cscfg_csdev_disable_active_config() - add rb & fixes tags. - add ss_status field in etm4x_drvdata to expose STATUS and PENDING bits. - https://lore.kernel.org/all/20260415165528.3369607-1-yeoreum.yun@arm.com/ from v4 to v5: - add rb-tag. - fix underflow issue for nrseqstate. - fix wrong check in etm4_sspcicrn_present(). - remove redundant fields on etmv4_save_state. - rename caps->ss_status to ss_cmp. - fix wrong location of etm4_release_trace_id. - https://lore.kernel.org/all/20260413142003.3549310-1-yeoreum.yun@arm.com/ from v3 to v4: - change etm_drvdata->spinlock type to raw_spin_lock_t - remove redundant call etmX_enable_hw() with starting_cpu() callsback. - fix missing trace id release. - add missing docs. - https://lore.kernel.org/all/20260412175506.412301-1-yeoreum.yun@arm.com/ from v2 to v3: - fix build error for etm3x. - fix checkpatch warning. - https://lore.kernel.org/all/20260410074310.2693385-1-yeoreum.yun@arm.com/ from v1 to v2 - rebased to v7.0-rc7. - introduce etmX_caps structure to save etmX's capabilities. - remove ss_status from etmv4_config. - modify active_config after taking a mode (perf/sysfs). - https://lore.kernel.org/all/20260317181705.2456271-1-yeoreum.yun@arm.com/ --- Yeoreum Yun (8): coresight: etm4x: fix inconsistencies with sysfs configuration coresight: etm3x: fix inconsistencies with sysfs configuration coresight: etm3x: change drvdata->spinlock type to raw_spin_lock_t coresight: etm3x: remove redundant cpu online check on etm_enable_sysfs() coresight: etm4x: introduce struct etm4_caps coresight: etm4x: exclude ss_status from drvdata->config coresight: etm4x: remove s_ex_level from config coresight: etm3x: introduce struct etm_caps drivers/hwtracing/coresight/coresight-config.c | 18 +- drivers/hwtracing/coresight/coresight-config.h | 22 ++ drivers/hwtracing/coresight/coresight-etm.h | 48 ++- drivers/hwtracing/coresight/coresight-etm3x-core.c | 96 ++--- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 155 ++++---- drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 14 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 413 +++++++++++---------- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 204 +++++----- drivers/hwtracing/coresight/coresight-etm4x.h | 196 +++++----- 9 files changed, 645 insertions(+), 521 deletions(-) --- base-commit: 9e3604d7369cfc0110100eb1a0acab1865ee2d18 change-id: 20260911-separate_etm_cfg_v2-3518a168cbff Best regards, -- Sincerely, Yeoreum Yun

2 days, 17 hours

Re: [PATCH 1/1] coresight: tmc-etr: Sync the trace buffer for the device

by Leo Yan

On Wed, Sep 16, 2026 at 11:04:20AM +0800, Jie Gan wrote: [...] > > From: Min Chen <min.chen(a)siengine.com> > > > > The flat ETR buffer comes from dma_alloc_noncoherent(), which zeroes it > > with CPU stores. The DMA API requires the caller to sync the buffer for > > the device before the device writes into it, but the TMC driver only > > ever syncs for the CPU afterwards. On a non-coherent sink the zero fill > > is therefore still dirty in cache when the ETR starts writing, and its > > write-back lands on top of the trace data. Good catch! I'm curious how you observed the dirty cache lines overwriting trace data in DDR and causing corruption. > Agree, without the sync, the dirty data may overwrites the trace data. > > Add a sync_for_device() buffer operation and call it from > > __tmc_etr_enable_hw() just before the TMC is enabled. I don't think __tmc_etr_enable_hw() is the best place for the sync, as it can be called frequently when an event is enabled, e.g. when a task is scheduled in or migrated between CPUs. We should be able to sync once after dma_alloc_noncoherent() instead. The issue is not limited to buffer init. The driver also injects barrier packets into the bounce buffer, which can race with the sink. Even worse, the barrier packet write may collide with trace data when they share a cache line. I think we should consider writing barrier packets directly into the AUX buffer. This would avoid stale cache data from barrier packet writes and simplify the flow without additional sync operations. Would you mind if I pick up this patch (keeping you as the author) and add a second patch to address the barrier packet issue? That part may need some several rounds refactoring so can have better shape, I think it would be easier to consolidate the fixes on my side. Thanks, Leo P.s. Please CC me on future CoreSight patches. If you're using the mainline ./scripts/get_maintainer.pl, it should add me automatically. I didn't receive this patch directly, which is why I'm replying to Jie's email (also thanks Jie's review).

4 days, 13 hours

[PATCH] coresight: handle runtime PM resume failures

by Yuanfang Zhang

When a CoreSight component's parent power domain, such as a CPU cluster genpd, fails to power on, runtime resume returns a negative error. Several call sites ignored that error and continued to access registers on an unpowered device, risking an external abort. Replace the remaining pm_runtime_get_sync() calls with pm_runtime_resume_and_get(), which restores the runtime PM usage count when resume fails. Abort before accessing hardware and propagate the error to the caller. In coresight_get_ref(), unwind the module and device references. In debug_enable_func(), roll back the CPUs that resumed successfully before the failure. Finally, release the mode acquired by stm_enable() if its runtime resume fails. Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> --- This patch converts the remaining CoreSight pm_runtime_get_sync() users to pm_runtime_resume_and_get(), propagates resume failures before hardware access, and completes the related module, device, CPU and mode unwind paths. --- drivers/hwtracing/coresight/coresight-core.c | 13 ++++++++++--- drivers/hwtracing/coresight/coresight-cpu-debug.c | 10 +++++----- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 10 ++++++++-- drivers/hwtracing/coresight/coresight-etm3x-sysfs.c | 10 ++++++++-- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 5 ++++- drivers/hwtracing/coresight/coresight-funnel.c | 5 ++++- drivers/hwtracing/coresight/coresight-stm.c | 7 ++++++- drivers/hwtracing/coresight/coresight-sysfs.c | 11 +++++++++-- 8 files changed, 54 insertions(+), 17 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 928488a216d4eafa3cdb5f882ae5f44ddaff0448..ff93a017dbe22b01236ac2e5021da9b82890e72c 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -822,14 +822,16 @@ struct coresight_device *coresight_get_sink_by_id(u32 id) * * @csdev: The coresight device to get a reference on. * - * Return true in successful case and power up the device. - * Return false when failed to get reference of module. + * Return true on success and power up the device. + * Return false if a reference cannot be obtained or the device cannot be + * powered up. */ static bool coresight_get_ref(struct coresight_device *csdev) { struct device *dev = &csdev->dev; struct device *parent = csdev->dev.parent; struct device_driver *drv; + int ret; /* Make sure csdev can't go away */ get_device(dev); @@ -843,9 +845,14 @@ static bool coresight_get_ref(struct coresight_device *csdev) goto err_module; /* Make sure the device is powered on */ - pm_runtime_get_sync(parent); + ret = pm_runtime_resume_and_get(parent); + if (ret < 0) + goto err_pm; + return true; +err_pm: + module_put(drv->owner); err_module: put_device(parent); put_device(dev); diff --git a/drivers/hwtracing/coresight/coresight-cpu-debug.c b/drivers/hwtracing/coresight/coresight-cpu-debug.c index 3a806c1d50eafb4249ab516ef846e437831b9681..39602d610e5b22ec4f165dbb126a7c06aea08eb0 100644 --- a/drivers/hwtracing/coresight/coresight-cpu-debug.c +++ b/drivers/hwtracing/coresight/coresight-cpu-debug.c @@ -429,19 +429,19 @@ static int debug_enable_func(void) if (!drvdata) continue; - ret = pm_runtime_get_sync(drvdata->dev); + ret = pm_runtime_resume_and_get(drvdata->dev); if (ret < 0) goto err; - else - cpumask_set_cpu(cpu, &mask); + + cpumask_set_cpu(cpu, &mask); } return 0; err: /* - * If pm_runtime_get_sync() has failed, need rollback on - * all the other CPUs that have been enabled before that. + * If runtime resume has failed, roll back all the other CPUs + * that have been enabled before that. */ for_each_cpu(cpu, &mask) { drvdata = per_cpu(debug_drvdata, cpu); diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index 3fe2c916d228808233ef19e9213a0cc0ce3cf297..6886b8713368058b9cf33ab7fafb5f87e23c1ec9 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -167,8 +167,11 @@ static ssize_t coresight_cti_reg_show(struct device *dev, struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); struct cs_off_attribute *cti_attr = container_of(attr, struct cs_off_attribute, attr); u32 val = 0; + int ret; - pm_runtime_get_sync(dev->parent); + ret = pm_runtime_resume_and_get(dev->parent); + if (ret < 0) + return ret; scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) val = cti_read_single_reg(drvdata, cti_attr->off); @@ -185,11 +188,14 @@ static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); struct cs_off_attribute *cti_attr = container_of(attr, struct cs_off_attribute, attr); unsigned long val = 0; + int ret; if (kstrtoul(buf, 0, &val)) return -EINVAL; - pm_runtime_get_sync(dev->parent); + ret = pm_runtime_resume_and_get(dev->parent); + if (ret < 0) + return ret; scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) cti_write_single_reg(drvdata, cti_attr->off, val); diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c index b3c67e96a82a4995515457d1ac0a5b183b162f0f..b34e282ec4a5f37f7de1d2ff118042b47368acd7 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c @@ -47,8 +47,11 @@ static ssize_t etmsr_show(struct device *dev, { unsigned long flags, val; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); + int ret; - pm_runtime_get_sync(dev->parent); + ret = pm_runtime_resume_and_get(dev->parent); + if (ret < 0) + return ret; spin_lock_irqsave(&drvdata->spinlock, flags); CS_UNLOCK(drvdata->csa.base); @@ -933,13 +936,16 @@ static ssize_t seq_curr_state_show(struct device *dev, unsigned long val, flags; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etm_config *config = &drvdata->config; + int ret; if (!coresight_get_mode(drvdata->csdev)) { val = config->seq_curr_state; goto out; } - pm_runtime_get_sync(dev->parent); + ret = pm_runtime_resume_and_get(dev->parent); + if (ret < 0) + return ret; spin_lock_irqsave(&drvdata->spinlock, flags); CS_UNLOCK(drvdata->csa.base); diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index cc6cdd3ae29d502a2e67f07400de957b6dc71af6..55e05c20b302d4bf55c4df30c9ee6d6a1b5f1031 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -2457,10 +2457,13 @@ static ssize_t coresight_etm4x_reg_show(struct device *dev, { u32 val, offset; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + int ret; offset = coresight_etm4x_attr_to_offset(d_attr); - pm_runtime_get_sync(dev->parent); + ret = pm_runtime_resume_and_get(dev->parent); + if (ret < 0) + return ret; val = etmv4_cross_read(drvdata, offset); pm_runtime_put_sync(dev->parent); diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c index 0abc11f0690c5272ebd55df9e98544e3b401cfe6..5824a1e4d046a3caf5b32ed1d8526b8bd7e9ca76 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -190,9 +190,12 @@ static ssize_t funnel_ctrl_show(struct device *dev, struct device_attribute *attr, char *buf) { u32 val; + int ret; struct funnel_drvdata *drvdata = dev_get_drvdata(dev->parent); - pm_runtime_get_sync(dev->parent); + ret = pm_runtime_resume_and_get(dev->parent); + if (ret < 0) + return ret; val = get_funnel_ctrl_hw(drvdata); diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index 4e860519a73f6fff640090cf58298b89a31e6359..b9f15990ed994ea827c8e237d764e74d8d231ddd 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -196,6 +196,7 @@ static int stm_enable(struct coresight_device *csdev, struct perf_event *event, __maybe_unused struct coresight_path *path) { struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + int ret; if (mode != CS_MODE_SYSFS) return -EINVAL; @@ -205,7 +206,11 @@ static int stm_enable(struct coresight_device *csdev, struct perf_event *event, return -EBUSY; } - pm_runtime_get_sync(csdev->dev.parent); + ret = pm_runtime_resume_and_get(csdev->dev.parent); + if (ret < 0) { + coresight_set_mode(csdev, CS_MODE_DISABLED); + return ret; + } spin_lock(&drvdata->spinlock); stm_enable_hw(drvdata); diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/hwtracing/coresight/coresight-sysfs.c index 4b010f8bc4c08da31b3d295be6c37b6d941629d2..5849dfbd9d0bd3ad10734919f78bc39cc968539c 100644 --- a/drivers/hwtracing/coresight/coresight-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-sysfs.c @@ -17,8 +17,12 @@ ssize_t coresight_simple_show_pair(struct device *_dev, struct coresight_device *csdev = container_of(_dev, struct coresight_device, dev); struct cs_pair_attribute *cs_attr = container_of(attr, struct cs_pair_attribute, attr); u64 val; + int ret; + + ret = pm_runtime_resume_and_get(_dev->parent); + if (ret < 0) + return ret; - pm_runtime_get_sync(_dev->parent); val = csdev_access_relaxed_read_pair(&csdev->access, cs_attr->lo_off, cs_attr->hi_off); pm_runtime_put_sync(_dev->parent); return sysfs_emit(buf, "0x%llx\n", val); @@ -31,8 +35,11 @@ ssize_t coresight_simple_show32(struct device *_dev, struct coresight_device *csdev = container_of(_dev, struct coresight_device, dev); struct cs_off_attribute *cs_attr = container_of(attr, struct cs_off_attribute, attr); u64 val; + int ret; - pm_runtime_get_sync(_dev->parent); + ret = pm_runtime_resume_and_get(_dev->parent); + if (ret < 0) + return ret; val = csdev_access_relaxed_read32(&csdev->access, cs_attr->off); pm_runtime_put_sync(_dev->parent); return sysfs_emit(buf, "0x%llx\n", val); --- base-commit: 08df884136f1c1197bab2a27814404fd329d9aac change-id: 20260911-b4-coresight-runtime-pm-failures-70f250927aeb Best regards, -- Yuanfang Zhang <yuanfang(a)qti.qualcomm.com>

4 days, 17 hours

[PATCH 00/25] CoreSight / perf: Support AUX sampling

by Leo Yan

This series adds AUX sampling support to Arm CoreSight. A PMU sample can carry a window of recent AUX trace, which perf generates callchain and branch stack for the sampled thread. This provides execution history for context-based profiling. The series can be divided into four parts: 1. Patches 01 ~ 03 for event core: The perf event core changes warn on non-positive AUX snapshot returns before checking alignment padding. Space for a non-zero AUX payload has already been reserved, so a zero return leaves that payload unwritten. CoreSight fills unavailable trace with zeros and returns the requested size. It also prevents AUX sampling and pause/resume from nesting through an NMI. A driver guard alone can leave perf's pause state (aux_paused) inconsistent with the hardware state. The event core ensures only one AUX callback is exclusively invoked. Export the output copy helpers so CoreSight can fill sample payloads when the driver is built as a module. 2. Patches 04 ~ 09 for ETM perf: The ETM perf changes separate the lifetime of the published CoreSight context from that of the AUX output handle. Centralize buffer updates, and end AUX output when throttling stops an event without PERF_EF_UPDATE so a later restart can acquire a fresh handle. Make hardware-state transitions reflect completed operations. 3. Patches 10 ~ 13 for TRBE driver: TRBE snapshot buffers need padding to meet the CPU's alignment and wrap constraints. Use circular buffer mode for overwrite snapshots, retaining Fill mode on CPUs that require the write out-of-range workaround. TRBE faults can still raise interrupts in circular mode. Track when the sink is handling an interrupt so an AUX sampling NMI can skip a snapshot while the interrupted handler is updating the buffer. Make repeated sink disable safe for deferred cleanup after a snapshot failure. 4. Patches 14 ~ 25 for AUX sampling and decoding: Shared atomic STOP and AUX action bits prevent an NMI stop from tearing down the context while pause, resume or snapshot accesses it. The AUX operation finishes and then completes the deferred stop, publishing the stopped state only after hardware teardown. Add snapshot_aux() to the CoreSight driver to pause the source, update the sink buffer, disable the path, copy the recent trace into the PMU sample, and then re-enable the path and resume the source. Patch 17 fixes history collection for zero-IP PMU samples. Perf clears the IP when a user-only sampling interrupt skids into the kernel, but the timestamp and TID remain valid for matching the trace history. In perf, decode each embedded payload as an independent trace window, selecting the decoder with the sampled CPU and using the sample's PID/TID and traced context IDs to attribute history to the sampled thread. Refactor common timeless decoding and history collection, and drain pending OpenCSD output so buffered history is not lost. Attach reconstructed callchains and branch stacks to the original PMU samples, preserving histories already present in the samples. Add a test, and document the recording and decoding workflow and its limitations. The initial support targets unformatted trace from per-CPU sinks such as TRBE. Shared formatted sinks such as ETR can mix trace from multiple CPUs, consuming the limited sample window with execution unrelated to the sampled thread. This series is based on Amir's series "perf: Add CoreSight branch history to existing samples" [1] for perf tool's branch / callchain generating. [1] https://lore.kernel.org/linux-perf-users/cover.1787005265.git.aaupov@fb.com/ Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (25): perf/core: Reject non-positive AUX snapshot sizes perf/core: Prevent AUX sampling from racing with pause/resume perf/core: Export output copy helpers for CoreSight coresight: perf: End AUX output when an event is throttled coresight: perf: Extract AUX buffer update helper coresight: perf: Simplify flow for CPUs without a path coresight: perf: Validate the live context through its path coresight: perf: Validate context before resuming trace coresight: perf: Improve hardware state transitions coresight: trbe: Pad snapshot buffers coresight: trbe: Use circular buffer mode for snapshots coresight: trbe: Track per-CPU sink interrupt handling coresight: trbe: Handle an already disabled sink coresight: perf: Look up the trace path in etm_event_pause() coresight: perf: Serialize AUX pause and resume with event stops coresight: perf: Support AUX sampling with per-CPU sinks perf cs-etm: Allow history collection for samples with zero IP perf cs-etm: Unify timeless buffer decoding perf cs-etm: Propagate errors from trace queue flushing perf cs-etm: Drain pending packets before finishing trace blocks perf cs-etm: Complete packet draining with end of trace perf cs-etm: Centralize sample history collection perf cs-etm: Decode AUX samples into callchains and branch stacks perf test: Add CoreSight AUX sample decoding test Documentation: coresight: Document AUX sample decoding Documentation/trace/coresight/coresight-perf.rst | 39 ++ drivers/hwtracing/coresight/coresight-etm-perf.c | 396 +++++++++++++----- drivers/hwtracing/coresight/coresight-etm-perf.h | 2 + drivers/hwtracing/coresight/coresight-trbe.c | 122 ++++-- include/linux/coresight.h | 2 + kernel/events/core.c | 26 +- kernel/events/ring_buffer.c | 2 + tools/perf/arch/arm/util/cs-etm.c | 6 + tools/perf/tests/shell/coresight/aux_sample.sh | 189 +++++++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 39 ++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 7 + tools/perf/util/cs-etm.c | 491 ++++++++++++++++------- 12 files changed, 1040 insertions(+), 281 deletions(-) --- base-commit: 134e1295eedfc9a3c6e4e63d8ef45dc63749449b change-id: 20260826-arm_cs_support_aux_sample-275664545588 Best regards, -- Leo Yan <leo.yan(a)arm.com>

5 days, 12 hours

[PATCH 00/14] perf cs-etm: Per-thread mode fixes and snapshot wrap support

by James Clark

Fix a few issues with per-thread mode: - With TRBE, thread migrations hit a queue without a decoder assert - On nVHE, everything looks like guest trace instead of host - Tracing multiple threads didn't really work After adding a tests for those, it turns out there were some snapshot bugs not picked up by the other snapshot tests. That showed that the different snapshot searches for Intel BTS and Arm SPE were inconsistent and I think all tracers can benefit from using the same pointer fixup logic, so that gets refactored into the common auxtrace.c. Then SPE can just share the Intel BTS search as it was obviously copied from it originally. IntelPT keeps the more advanced duplicate data search, but in the future that could probably be made the common one and all tracers would benefit from using it (except maybe BTS if it always has a very small buffer, but I doubt the overhead of the duplicate search would be an issue). For now this is more of a refactor rather than behavioral change so don't do that yet. Signed-off-by: James Clark <james.clark(a)linaro.org> --- James Clark (14): perf cs-etm: Fix nVHE per-thread decoding perf cs-etm: Warn for invalid timestamp option perf cs-etm: Turn on context packet timestamps in per-thread mode perf cs-etm: Use per-CPU queues for per-thread mode perf cs-etm: Increase default timestamp generation period perf auxtrace: Turn Intel BTS snapshot search into a generic one perf arm-spe: Use generic snapshot search perf auxtrace: intel-pt: Use new snapshot_has_wrapped callback perf cs-etm: Queue partial AUX records perf cs-etm: Don't print missing buffers in snapshot mode perf auxtrace: cs-etm: Capture wrapped snapshots perf test: Allow infinite named_thread loops perf test: Add test for per-thread mode perf cs-etm: Test multiple per-thread threads Documentation/userspace-api/perf_ring_buffer.rst | 6 +- tools/perf/Documentation/perf-test.txt | 2 +- tools/perf/arch/arm/util/cs-etm.c | 30 ++++- tools/perf/arch/arm64/util/arm-spe.c | 147 +-------------------- tools/perf/arch/x86/util/intel-bts.c | 115 +--------------- tools/perf/arch/x86/util/intel-pt.c | 58 +++----- .../perf/tests/shell/coresight/per-thread-multi.sh | 78 +++++++++++ tools/perf/tests/shell/coresight/per-thread.sh | 48 +++++++ .../perf/tests/shell/coresight/raw_dump_stress.sh | 5 - tools/perf/tests/workloads/named_threads.c | 7 +- tools/perf/util/auxtrace.c | 136 +++++++++++++++++-- tools/perf/util/auxtrace.h | 20 ++- tools/perf/util/cs-etm.c | 98 ++++++++++---- 13 files changed, 382 insertions(+), 368 deletions(-) --- base-commit: bf10e6ee2ac3034c9068e03eed418fd16961984e change-id: 20260605-james-cs-unformatted-per-thread-fix-50e723aa7f0e Best regards, -- James Clark <james.clark(a)linaro.org>

6 days, 3 hours

Re: [PATCH v10 3/5] coresight: cti: add Qualcomm extended CTI identification and quirks

by Mike Leach

On 6/15/26 13:32, Yingchao Deng wrote: > Qualcomm implements an extended variant of the ARM CoreSight CTI with a > different register layout and vendor-specific behavior. While the > programming model remains largely compatible, the register offsets differ > from the standard ARM CTI and require explicit handling. > > Detect Qualcomm CTIs via the DEVARCH register and record this in the CTI > driver data. Introduce a small mapping layer to translate standard CTI > register offsets to Qualcomm-specific offsets, allowing the rest of the > driver to use a common register access path. > > Additionally, handle a Qualcomm-specific quirk where the hardware does > not implement the CoreSight Claim tag protocol. Instead of clearing the > CLAIMSET register at probe time, bypass the claim/disclaim operations > entirely for Qualcomm CTIs by wrapping coresight_claim_device(), > coresight_disclaim_device_unlocked() and coresight_clear_self_claim_tag() > in thin helpers that early-return when is_qcom_cti is set. > > No functional change is intended for standard ARM CTI devices. > > Co-developed-by: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com> > Signed-off-by: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com> > Signed-off-by: Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-cti-core.c | 47 +++++++++++++++-- > drivers/hwtracing/coresight/coresight-cti.h | 64 +++++++++++++++++++++++- > 2 files changed, 105 insertions(+), 6 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c > index fa758c535ccb..5b83dd4e603b 100644 > --- a/drivers/hwtracing/coresight/coresight-cti-core.c > +++ b/drivers/hwtracing/coresight/coresight-cti-core.c > @@ -73,6 +73,35 @@ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) > CS_LOCK(drvdata->base); > } > > +/* > + * Qualcomm CTIs do not implement the CoreSight Claim tag protocol, so > + * bypass coresight_clear_self_claim_tag() for them. > + */ > +static void cti_clear_self_claim_tag(struct cti_drvdata *drvdata, > + struct csdev_access *csa) > +{ > + if (drvdata->is_qcom_cti) > + return; > + > + coresight_clear_self_claim_tag(csa); > +} > + > +static int cti_claim_device(struct cti_drvdata *drvdata) > +{ > + if (drvdata->is_qcom_cti) > + return 0; > + > + return coresight_claim_device(drvdata->csdev); > +} > + > +static void cti_unclaim_device_unlocked(struct cti_drvdata *drvdata) > +{ > + if (drvdata->is_qcom_cti) > + return; > + > + coresight_disclaim_device_unlocked(drvdata->csdev); > +} > + > /* write regs to hardware and enable */ > static int cti_enable_hw(struct cti_drvdata *drvdata) > { > @@ -86,7 +115,7 @@ static int cti_enable_hw(struct cti_drvdata *drvdata) > goto cti_state_unchanged; > > /* claim the device */ > - rc = coresight_claim_device(drvdata->csdev); > + rc = cti_claim_device(drvdata); > if (rc) > return rc; > > @@ -101,7 +130,6 @@ static int cti_enable_hw(struct cti_drvdata *drvdata) > static int cti_disable_hw(struct cti_drvdata *drvdata) > { > struct cti_config *config = &drvdata->config; > - struct coresight_device *csdev = drvdata->csdev; > > guard(raw_spinlock_irqsave)(&drvdata->spinlock); > > @@ -118,7 +146,7 @@ static int cti_disable_hw(struct cti_drvdata *drvdata) > /* disable CTI */ > writel_relaxed(0, drvdata->base + CTICONTROL); > > - coresight_disclaim_device_unlocked(csdev); > + cti_unclaim_device_unlocked(drvdata); > CS_LOCK(drvdata->base); > return 0; > } > @@ -144,6 +172,9 @@ void cti_write_intack(struct device *dev, u32 ackval) > /* DEVID[19:16] - number of CTM channels */ > #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 19)) > > +/* DEVARCH[31:21] - ARCHITECT */ > +#define CTI_DEVARCH_ARCHITECT(devarch_val) ((int)BMVAL(devarch_val, 21, 31)) > + > static int cti_set_default_config(struct device *dev, > struct cti_drvdata *drvdata) > { > @@ -684,6 +715,7 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) > struct coresight_desc cti_desc = { 0 }; > struct coresight_platform_data *pdata = NULL; > struct resource *res = &adev->res; > + u32 devarch; > > /* driver data*/ > drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > @@ -708,6 +740,10 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) > > raw_spin_lock_init(&drvdata->spinlock); > > + devarch = readl_relaxed(drvdata->base + CORESIGHT_DEVARCH); > + if (CTI_DEVARCH_ARCHITECT(devarch) == QCOM_ARCHITECT) > + drvdata->is_qcom_cti = true; > + > /* initialise CTI driver config values */ > ret = cti_set_default_config(dev, drvdata); > if (ret) > @@ -753,7 +789,7 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) > cti_desc.groups = drvdata->ctidev.con_groups; > cti_desc.dev = dev; > > - coresight_clear_self_claim_tag(&cti_desc.access); > + cti_clear_self_claim_tag(drvdata, &cti_desc.access); > drvdata->csdev = coresight_register(&cti_desc); > if (IS_ERR(drvdata->csdev)) > return PTR_ERR(drvdata->csdev); > @@ -767,7 +803,8 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) > > /* all done - dec pm refcount */ > pm_runtime_put(&adev->dev); > - dev_info(&drvdata->csdev->dev, "CTI initialized\n"); > + dev_info(&drvdata->csdev->dev, > + "%sCTI initialized\n", drvdata->is_qcom_cti ? "QCOM " : ""); > return 0; > } > > diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h > index 634bdce5cdfd..4b6fd6b55114 100644 > --- a/drivers/hwtracing/coresight/coresight-cti.h > +++ b/drivers/hwtracing/coresight/coresight-cti.h > @@ -54,10 +54,36 @@ struct fwnode_handle; > /* > * CTI CSSoc 600 has a max of 32 trigger signals per direction. > * CTI CSSoc 400 has 8 IO triggers - other CTIs can be impl def. > + * QCOM CTI support up to 128 trigger signals per direction. > * Max of in and out defined in the DEVID register. > * - pick up actual number used from .dts parameters if present. I haven't seen anything in these patches that actually does check for max CTIINOUT values in .dts. Would it not be better to have a QCOM_CTIINOUTENMAX and set the max value in config based on the is_qcom_cti flag? Otherwise it appears that the standard arm CTIs are going to create a whole lot of unneeded/unused registers Regards Mike > */ > -#define CTIINOUTEN_MAX 32 > +#define CTIINOUTEN_MAX 128 > + > +/* QCOM CTI extension */ > +#define QCOM_ARCHITECT 0x477 > + > +#define QCOM_CTIINTACK 0x020 > +#define QCOM_CTIAPPSET 0x004 > +#define QCOM_CTIAPPCLEAR 0x008 > +#define QCOM_CTIAPPPULSE 0x00C > +#define QCOM_CTIINEN 0x400 > +#define QCOM_CTIOUTEN 0x800 > +#define QCOM_CTITRIGINSTATUS 0x040 > +#define QCOM_CTITRIGOUTSTATUS 0x060 > +#define QCOM_CTICHINSTATUS 0x080 > +#define QCOM_CTICHOUTSTATUS 0x084 > +#define QCOM_CTIGATE 0x088 > +#define QCOM_ASICCTL 0x08C > +/* Integration test registers */ > +#define QCOM_ITCHINACK 0xE70 > +#define QCOM_ITTRIGINACK 0xE80 > +#define QCOM_ITCHOUT 0xE74 > +#define QCOM_ITTRIGOUT 0xEA0 > +#define QCOM_ITCHOUTACK 0xE78 > +#define QCOM_ITTRIGOUTACK 0xEC0 > +#define QCOM_ITCHIN 0xE7C > +#define QCOM_ITTRIGIN 0xEE0 > > /** > * Group of related trigger signals > @@ -168,6 +194,9 @@ struct cti_config { > * @spinlock: Control data access to one at a time. > * @config: Configuration data for this CTI device. > * @node: List entry of this device in the list of CTI devices. > + * @is_qcom_cti: True if this CTI is a Qualcomm vendor-specific > + * variant that requires register offset translation > + * via cti_qcom_reg_off(). > */ > struct cti_drvdata { > void __iomem *base; > @@ -176,6 +205,7 @@ struct cti_drvdata { > raw_spinlock_t spinlock; > struct cti_config config; > struct list_head node; > + bool is_qcom_cti; > }; > > /* > @@ -229,9 +259,41 @@ struct coresight_platform_data * > coresight_cti_get_platform_data(struct device *dev); > const char *cti_plat_get_node_name(struct fwnode_handle *fwnode); > > +static inline u32 cti_qcom_reg_off(u32 offset) > +{ > + switch (offset) { > + case CTIINTACK: return QCOM_CTIINTACK; > + case CTIAPPSET: return QCOM_CTIAPPSET; > + case CTIAPPCLEAR: return QCOM_CTIAPPCLEAR; > + case CTIAPPPULSE: return QCOM_CTIAPPPULSE; > + case CTIINEN: return QCOM_CTIINEN; > + case CTIOUTEN: return QCOM_CTIOUTEN; > + case CTITRIGINSTATUS: return QCOM_CTITRIGINSTATUS; > + case CTITRIGOUTSTATUS: return QCOM_CTITRIGOUTSTATUS; > + case CTICHINSTATUS: return QCOM_CTICHINSTATUS; > + case CTICHOUTSTATUS: return QCOM_CTICHOUTSTATUS; > + case CTIGATE: return QCOM_CTIGATE; > + case ASICCTL: return QCOM_ASICCTL; > + case ITCHINACK: return QCOM_ITCHINACK; > + case ITTRIGINACK: return QCOM_ITTRIGINACK; > + case ITCHOUT: return QCOM_ITCHOUT; > + case ITTRIGOUT: return QCOM_ITTRIGOUT; > + case ITCHOUTACK: return QCOM_ITCHOUTACK; > + case ITTRIGOUTACK: return QCOM_ITTRIGOUTACK; > + case ITCHIN: return QCOM_ITCHIN; > + case ITTRIGIN: return QCOM_ITTRIGIN; > + > + default: > + return offset; > + } > +} > + > static inline void __iomem *__reg_addr(struct cti_drvdata *drvdata, > u32 off, u32 index) > { > + if (unlikely(drvdata->is_qcom_cti)) > + off = cti_qcom_reg_off(off); > + > return drvdata->base + off + index * sizeof(u32); > } > >

1 week, 2 days

Re: [PATCH v10 1/5] coresight: cti: Convert trigger usage fields to dynamic

by Mike Leach

Reviewed-by: Mike Leach <mike.leach(a)arm.com> On 6/15/26 13:32, Yingchao Deng wrote: > Replace the fixed-size u32 fields in the cti_config and cti_trig_grp > structure with dynamically allocated bitmaps and arrays. This allows > memory to be allocated based on the actual number of triggers during probe > time, reducing memory footprint and improving scalability for platforms > with varying trigger counts. > > Also add a bounds check in cti_allocate_trig_con() to ensure the caller > does not pass in/out signal counts larger than nr_trig_max. > > Reviewed-by: Leo Yan <leo.yan(a)arm.com> > Signed-off-by: Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-cti-core.c | 70 +++++++++++++++++----- > .../hwtracing/coresight/coresight-cti-platform.c | 26 +++++--- > drivers/hwtracing/coresight/coresight-cti-sysfs.c | 14 ++--- > drivers/hwtracing/coresight/coresight-cti.h | 12 ++-- > 4 files changed, 87 insertions(+), 35 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c > index b2c9a4db13b4..572798ab504c 100644 > --- a/drivers/hwtracing/coresight/coresight-cti-core.c > +++ b/drivers/hwtracing/coresight/coresight-cti-core.c > @@ -161,8 +161,8 @@ void cti_write_intack(struct device *dev, u32 ackval) > /* DEVID[19:16] - number of CTM channels */ > #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 19)) > > -static void cti_set_default_config(struct device *dev, > - struct cti_drvdata *drvdata) > +static int cti_set_default_config(struct device *dev, > + struct cti_drvdata *drvdata) > { > struct cti_config *config = &drvdata->config; > u32 devid; > @@ -181,6 +181,31 @@ static void cti_set_default_config(struct device *dev, > config->nr_trig_max = CTIINOUTEN_MAX; > } > > + config->trig_in_use = devm_bitmap_zalloc(dev, config->nr_trig_max, > + GFP_KERNEL); > + if (!config->trig_in_use) > + return -ENOMEM; > + > + config->trig_out_use = devm_bitmap_zalloc(dev, config->nr_trig_max, > + GFP_KERNEL); > + if (!config->trig_out_use) > + return -ENOMEM; > + > + config->trig_out_filter = devm_bitmap_zalloc(dev, config->nr_trig_max, > + GFP_KERNEL); > + if (!config->trig_out_filter) > + return -ENOMEM; > + > + config->ctiinen = devm_kcalloc(dev, config->nr_trig_max, sizeof(u32), > + GFP_KERNEL); > + if (!config->ctiinen) > + return -ENOMEM; > + > + config->ctiouten = devm_kcalloc(dev, config->nr_trig_max, sizeof(u32), > + GFP_KERNEL); > + if (!config->ctiouten) > + return -ENOMEM; > + > config->nr_ctm_channels = CTI_DEVID_CTMCHANNELS(devid); > > /* Most regs default to 0 as zalloc'ed except...*/ > @@ -189,6 +214,7 @@ static void cti_set_default_config(struct device *dev, > config->enable_req_count = 0; > > config->asicctl_impl = !!FIELD_GET(GENMASK(4, 0), devid); > + return 0; > } > > /* > @@ -219,8 +245,10 @@ int cti_add_connection_entry(struct device *dev, struct cti_drvdata *drvdata, > cti_dev->nr_trig_con++; > > /* add connection usage bit info to overall info */ > - drvdata->config.trig_in_use |= tc->con_in->used_mask; > - drvdata->config.trig_out_use |= tc->con_out->used_mask; > + bitmap_or(drvdata->config.trig_in_use, drvdata->config.trig_in_use, > + tc->con_in->used_mask, drvdata->config.nr_trig_max); > + bitmap_or(drvdata->config.trig_out_use, drvdata->config.trig_out_use, > + tc->con_out->used_mask, drvdata->config.nr_trig_max); > > return 0; > } > @@ -231,6 +259,14 @@ struct cti_trig_con *cti_allocate_trig_con(struct device *dev, int in_sigs, > { > struct cti_trig_con *tc = NULL; > struct cti_trig_grp *in = NULL, *out = NULL; > + struct cti_drvdata *drvdata = dev_get_drvdata(dev); > + int n_trigs = drvdata->config.nr_trig_max; > + > + if (in_sigs > n_trigs || out_sigs > n_trigs) { > + dev_err(dev, "trigger signal is out of range: in=%d out=%d nr_max=%d\n", > + in_sigs, out_sigs, n_trigs); > + return NULL; > + } > > tc = devm_kzalloc(dev, sizeof(struct cti_trig_con), GFP_KERNEL); > if (!tc) > @@ -242,12 +278,20 @@ struct cti_trig_con *cti_allocate_trig_con(struct device *dev, int in_sigs, > if (!in) > return NULL; > > + in->used_mask = devm_bitmap_zalloc(dev, n_trigs, GFP_KERNEL); > + if (!in->used_mask) > + return NULL; > + > out = devm_kzalloc(dev, > offsetof(struct cti_trig_grp, sig_types[out_sigs]), > GFP_KERNEL); > if (!out) > return NULL; > > + out->used_mask = devm_bitmap_zalloc(dev, n_trigs, GFP_KERNEL); > + if (!out->used_mask) > + return NULL; > + > tc->con_in = in; > tc->con_out = out; > tc->con_in->nr_sigs = in_sigs; > @@ -263,7 +307,6 @@ int cti_add_default_connection(struct device *dev, struct cti_drvdata *drvdata) > { > int ret = 0; > int n_trigs = drvdata->config.nr_trig_max; > - u32 n_trig_mask = GENMASK(n_trigs - 1, 0); > struct cti_trig_con *tc = NULL; > > /* > @@ -274,8 +317,8 @@ int cti_add_default_connection(struct device *dev, struct cti_drvdata *drvdata) > if (!tc) > return -ENOMEM; > > - tc->con_in->used_mask = n_trig_mask; > - tc->con_out->used_mask = n_trig_mask; > + bitmap_fill(tc->con_in->used_mask, n_trigs); > + bitmap_fill(tc->con_out->used_mask, n_trigs); > ret = cti_add_connection_entry(dev, drvdata, tc, NULL, "default"); > return ret; > } > @@ -288,7 +331,6 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, > { > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct cti_config *config = &drvdata->config; > - u32 trig_bitmask; > u32 chan_bitmask; > u32 reg_value; > int reg_offset; > @@ -298,18 +340,16 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, > (trigger_idx >= config->nr_trig_max)) > return -EINVAL; > > - trig_bitmask = BIT(trigger_idx); > - > /* ensure registered triggers and not out filtered */ > if (direction == CTI_TRIG_IN) { > - if (!(trig_bitmask & config->trig_in_use)) > + if (!(test_bit(trigger_idx, config->trig_in_use))) > return -EINVAL; > } else { > - if (!(trig_bitmask & config->trig_out_use)) > + if (!(test_bit(trigger_idx, config->trig_out_use))) > return -EINVAL; > > if ((config->trig_filter_enable) && > - (config->trig_out_filter & trig_bitmask)) > + test_bit(trigger_idx, config->trig_out_filter)) > return -EINVAL; > } > > @@ -687,7 +727,9 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) > raw_spin_lock_init(&drvdata->spinlock); > > /* initialise CTI driver config values */ > - cti_set_default_config(dev, drvdata); > + ret = cti_set_default_config(dev, drvdata); > + if (ret) > + return ret; > > pdata = coresight_cti_get_platform_data(dev); > if (IS_ERR(pdata)) { > diff --git a/drivers/hwtracing/coresight/coresight-cti-platform.c b/drivers/hwtracing/coresight/coresight-cti-platform.c > index d6d5388705c3..ba5a7e4b6bff 100644 > --- a/drivers/hwtracing/coresight/coresight-cti-platform.c > +++ b/drivers/hwtracing/coresight/coresight-cti-platform.c > @@ -136,8 +136,8 @@ static int cti_plat_create_v8_etm_connection(struct device *dev, > goto create_v8_etm_out; > > /* build connection data */ > - tc->con_in->used_mask = 0xF0; /* sigs <4,5,6,7> */ > - tc->con_out->used_mask = 0xF0; /* sigs <4,5,6,7> */ > + bitmap_set(tc->con_in->used_mask, 4, 4); /* sigs <4,5,6,7> */ > + bitmap_set(tc->con_out->used_mask, 4, 4); /* sigs <4,5,6,7> */ > > /* > * The EXTOUT type signals from the ETM are connected to a set of input > @@ -194,10 +194,10 @@ static int cti_plat_create_v8_connections(struct device *dev, > goto of_create_v8_out; > > /* Set the v8 PE CTI connection data */ > - tc->con_in->used_mask = 0x3; /* sigs <0 1> */ > + bitmap_set(tc->con_in->used_mask, 0, 2); /* sigs <0 1> */ > tc->con_in->sig_types[0] = PE_DBGTRIGGER; > tc->con_in->sig_types[1] = PE_PMUIRQ; > - tc->con_out->used_mask = 0x7; /* sigs <0 1 2 > */ > + bitmap_set(tc->con_out->used_mask, 0, 3); /* sigs <0 1 2 > */ > tc->con_out->sig_types[0] = PE_EDBGREQ; > tc->con_out->sig_types[1] = PE_DBGRESTART; > tc->con_out->sig_types[2] = PE_CTIIRQ; > @@ -213,7 +213,7 @@ static int cti_plat_create_v8_connections(struct device *dev, > goto of_create_v8_out; > > /* filter pe_edbgreq - PE trigout sig <0> */ > - drvdata->config.trig_out_filter |= 0x1; > + set_bit(0, drvdata->config.trig_out_filter); > > of_create_v8_out: > return ret; > @@ -257,7 +257,7 @@ static int cti_plat_read_trig_group(struct cti_trig_grp *tgrp, > if (!err) { > /* set the signal usage mask */ > for (idx = 0; idx < tgrp->nr_sigs; idx++) > - tgrp->used_mask |= BIT(values[idx]); > + set_bit(values[idx], tgrp->used_mask); > } > > kfree(values); > @@ -316,24 +316,34 @@ static int cti_plat_process_filter_sigs(struct cti_drvdata *drvdata, > { > struct cti_trig_grp *tg = NULL; > int err = 0, nr_filter_sigs; > + int nr_trigs = drvdata->config.nr_trig_max; > > nr_filter_sigs = cti_plat_count_sig_elements(fwnode, > CTI_DT_FILTER_OUT_SIGS); > if (nr_filter_sigs == 0) > return 0; > > - if (nr_filter_sigs > drvdata->config.nr_trig_max) > + if (nr_filter_sigs > nr_trigs) > return -EINVAL; > > tg = kzalloc_obj(*tg); > if (!tg) > return -ENOMEM; > > + tg->used_mask = bitmap_zalloc(nr_trigs, GFP_KERNEL); > + if (!tg->used_mask) { > + kfree(tg); > + return -ENOMEM; > + } > + > tg->nr_sigs = nr_filter_sigs; > err = cti_plat_read_trig_group(tg, fwnode, CTI_DT_FILTER_OUT_SIGS); > if (!err) > - drvdata->config.trig_out_filter |= tg->used_mask; > + bitmap_or(drvdata->config.trig_out_filter, > + drvdata->config.trig_out_filter, > + tg->used_mask, nr_trigs); > > + bitmap_free(tg->used_mask); > kfree(tg); > return err; > } > diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c > index 3fe2c916d228..2bbfa405cb6b 100644 > --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c > @@ -719,12 +719,12 @@ static ssize_t trigout_filtered_show(struct device *dev, > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct cti_config *cfg = &drvdata->config; > int nr_trig_max = cfg->nr_trig_max; > - unsigned long mask = cfg->trig_out_filter; > + unsigned long *mask = cfg->trig_out_filter; > > - if (mask == 0) > + if (bitmap_empty(mask, nr_trig_max)) > return 0; > > - return sysfs_emit(buf, "%*pbl\n", nr_trig_max, &mask); > + return sysfs_emit(buf, "%*pbl\n", nr_trig_max, mask); > } > static DEVICE_ATTR_RO(trigout_filtered); > > @@ -931,9 +931,9 @@ static ssize_t trigin_sig_show(struct device *dev, > struct cti_trig_con *con = (struct cti_trig_con *)ext_attr->var; > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct cti_config *cfg = &drvdata->config; > - unsigned long mask = con->con_in->used_mask; > + unsigned long *mask = con->con_in->used_mask; > > - return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, &mask); > + return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, mask); > } > > static ssize_t trigout_sig_show(struct device *dev, > @@ -945,9 +945,9 @@ static ssize_t trigout_sig_show(struct device *dev, > struct cti_trig_con *con = (struct cti_trig_con *)ext_attr->var; > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct cti_config *cfg = &drvdata->config; > - unsigned long mask = con->con_out->used_mask; > + unsigned long *mask = con->con_out->used_mask; > > - return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, &mask); > + return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, mask); > } > > /* convert a sig type id to a name */ > diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h > index c5f9e79fabc6..ef079fc18b72 100644 > --- a/drivers/hwtracing/coresight/coresight-cti.h > +++ b/drivers/hwtracing/coresight/coresight-cti.h > @@ -68,7 +68,7 @@ struct fwnode_handle; > */ > struct cti_trig_grp { > int nr_sigs; > - u32 used_mask; > + unsigned long *used_mask; > int sig_types[]; > }; > > @@ -145,17 +145,17 @@ struct cti_config { > int enable_req_count; > > /* registered triggers and filtering */ > - u32 trig_in_use; > - u32 trig_out_use; > - u32 trig_out_filter; > + unsigned long *trig_in_use; > + unsigned long *trig_out_use; > + unsigned long *trig_out_filter; > bool trig_filter_enable; > u8 xtrig_rchan_sel; > > /* cti cross trig programmable regs */ > u32 ctiappset; > u8 ctiinout_sel; > - u32 ctiinen[CTIINOUTEN_MAX]; > - u32 ctiouten[CTIINOUTEN_MAX]; > + u32 *ctiinen; > + u32 *ctiouten; > u32 ctigate; > u32 asicctl; > }; >

1 week, 2 days

Re: [PATCH v10 5/5] coresight: cti: document banked and missing base CTI sysfs registers

by Mike Leach

Reviewed-by: Mike Leach <mike.leach(a)arm.com> On 6/15/26 13:32, Yingchao Deng wrote: > Document the new sysfs entries triginstatus[1-3], trigoutstatus[1-3], > ittrigin[1-3], ittrigout[1-3], ittrigoutack[1-3] and ittriginack[1-3] > in the coresight-cti ABI documentation. > > Also document the previously undocumented base integration test > registers itctrl, itchin, itchinack, ittrigin, ittriginack, itchout, > itchoutack, ittrigout and ittrigoutack, which were introduced in > kernel version 5.7. > > Signed-off-by: Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> > --- > .../ABI/testing/sysfs-bus-coresight-devices-cti | 90 ++++++++++++++++++++++ > 1 file changed, 90 insertions(+) > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti b/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti > index a2aef7f5a6d7..9d7831ac455b 100644 > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti > @@ -128,12 +128,102 @@ KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) read current status of input trigger signals > > +What: /sys/bus/coresight/devices/<cti-name>/regs/triginstatus[1-3] > +Date: June 2026 > +KernelVersion: 7.3 > +Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com> > +Description: (Read) read current status of QCOM extended input trigger signals. > + > What: /sys/bus/coresight/devices/<cti-name>/regs/trigoutstatus > Date: March 2020 > KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) read current status of output trigger signals. > > +What: /sys/bus/coresight/devices/<cti-name>/regs/trigoutstatus[1-3] > +Date: June 2026 > +KernelVersion: 7.3 > +Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com> > +Description: (Read) read current status of QCOM extended output trigger signals. > + > +What: /sys/bus/coresight/devices/<cti-name>/regs/itctrl > +Date: March 2020 > +KernelVersion: 5.7 > +Contact: coresight(a)lists.linaro.org > +Description: (RW) Control integration mode. > + > +What: /sys/bus/coresight/devices/<cti-name>/regs/itchin > +Date: March 2020 > +KernelVersion: 5.7 > +Contact: coresight(a)lists.linaro.org > +Description: (Read) Read the values of the CTCHIN inputs. > + > +What: /sys/bus/coresight/devices/<cti-name>/regs/itchinack > +Date: March 2020 > +KernelVersion: 5.7 > +Contact: coresight(a)lists.linaro.org > +Description: (Write) Write the value of the CTCHINACK input. > + > +What: /sys/bus/coresight/devices/<cti-name>/regs/ittrigin > +Date: March 2020 > +KernelVersion: 5.7 > +Contact: coresight(a)lists.linaro.org > +Description: (Read) Read the values of the CTTRIGIN inputs. > + > +What: /sys/bus/coresight/devices/<cti-name>/regs/ittrigin[1-3] > +Date: June 2026 > +KernelVersion: 7.3 > +Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com> > +Description: (Read) Read the values of the QCOM extended CTTRIGIN inputs. > + > +What: /sys/bus/coresight/devices/<cti-name>/regs/ittriginack > +Date: March 2020 > +KernelVersion: 5.7 > +Contact: coresight(a)lists.linaro.org > +Description: (Write) Write the value of the CTTRIGINACK input. > + > +What: /sys/bus/coresight/devices/<cti-name>/regs/ittriginack[1-3] > +Date: June 2026 > +KernelVersion: 7.3 > +Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com> > +Description: (Write) Write the value of the QCOM extended CTTRIGINACK input. > + > +What: /sys/bus/coresight/devices/<cti-name>/regs/itchout > +Date: March 2020 > +KernelVersion: 5.7 > +Contact: coresight(a)lists.linaro.org > +Description: (RW) Read or write the value of the CTCHOUT outputs. > + > +What: /sys/bus/coresight/devices/<cti-name>/regs/itchoutack > +Date: March 2020 > +KernelVersion: 5.7 > +Contact: coresight(a)lists.linaro.org > +Description: (Read) Read the value of the CTCHOUTACK input. > + > +What: /sys/bus/coresight/devices/<cti-name>/regs/ittrigout > +Date: March 2020 > +KernelVersion: 5.7 > +Contact: coresight(a)lists.linaro.org > +Description: (RW) Read or write the value of the CTTRIGOUT outputs. > + > +What: /sys/bus/coresight/devices/<cti-name>/regs/ittrigout[1-3] > +Date: June 2026 > +KernelVersion: 7.3 > +Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com> > +Description: (RW) Read or write the value of the QCOM extended CTTRIGOUT outputs. > + > +What: /sys/bus/coresight/devices/<cti-name>/regs/ittrigoutack > +Date: March 2020 > +KernelVersion: 5.7 > +Contact: coresight(a)lists.linaro.org > +Description: (Read) Read the value of the CTTRIGOUTACK input. > + > +What: /sys/bus/coresight/devices/<cti-name>/regs/ittrigoutack[1-3] > +Date: June 2026 > +KernelVersion: 7.3 > +Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com> > +Description: (Read) Read the value of the QCOM extended CTTRIGOUTACK input. > + > What: /sys/bus/coresight/devices/<cti-name>/channels/trigin_attach > Date: March 2020 > KernelVersion: 5.7 >

1 week, 2 days

[PATCH v4 0/1] coresight: fix issue with insufficient claim tags

by Mike Leach

All CoreSight compliant components have an implementation defined number of 0 to 8 claim tag bits in the claim tag registers. These are used to claim the CoreSight resources by system agents. ARM recommends implementions have 4 claim tag bits, though a valid implementation can have 0 claim tags bits. The CoreSight drivers implement a 2 claim tag bit protocol to allow self hosted and external debug agents to manage access to the hardware. However, if there are less than 2 claim tags available the protocol incorrectly returns an error on device claim, as no checks are made. If insufficient claim tags are present in a component then the protocol must return success on claim / disclaim to allow components to be used normally. Add initialisation to read the CLAIMSET bits to establish the number of available claim tag bits, and adjust the claim returns accordingly. Cache the claimtag protocol availablity in the coresight_device to reduce reads for the main claim/disclaim api. changes since v3: 1) removed unneeded bool casts (Leo) 2) rebased to kernel 7.2 on coresight/next changes since v2: 1) consolidated API to remove the API calls using just cs_access, which were used purely to clear down stale self claim tags, replace with a normal coresight_device API for initialisation, to match the claim/disclaim API. This does both the check on availability and the stale tag clearance. Updated all drivers to use the new init functionality 2) Added option for drivers to skip claim tag checking completely for devices with no-compliant hardware, that do not implement registers at the claim tag location, or do not operate correctly to indicate the correct number of claim tags for the device. changes since v1: 1) Added claim tag availability cache into coresight_device when using the main coresight_claim_device() / coresight_disclaim_device() API. Applies to coresight/next Mike Leach (1): coresight: fix issue where coresight component has no claimtags drivers/hwtracing/coresight/coresight-catu.c | 6 +- drivers/hwtracing/coresight/coresight-core.c | 139 ++++++++++++++++-- .../hwtracing/coresight/coresight-cti-core.c | 7 +- drivers/hwtracing/coresight/coresight-etb10.c | 9 +- .../coresight/coresight-etm3x-core.c | 8 +- .../coresight/coresight-etm4x-core.c | 8 +- .../hwtracing/coresight/coresight-funnel.c | 7 +- drivers/hwtracing/coresight/coresight-priv.h | 7 + .../coresight/coresight-replicator.c | 9 +- .../hwtracing/coresight/coresight-tmc-core.c | 7 +- include/linux/coresight.h | 23 ++- 11 files changed, 205 insertions(+), 25 deletions(-) -- 2.43.0

1 week, 2 days

2026

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

CoreSight September 2026