CoreSight February 2025

coresight@lists.linaro.org

8 participants
47 discussions

Re: [PATCH RESEND] coresight: etm4x: don't include '<linux/pm_wakeup.h>' directly

by Suzuki K Poulose

On Mon, 10 Feb 2025 12:36:36 +0100, Wolfram Sang wrote: > The header clearly states that it does not want to be included directly, > only via '<linux/(platform_)?device.h>'. Which is already present, so > delete the superfluous include. > > Applied, thanks! [1/1] coresight: etm4x: don't include '<linux/pm_wakeup.h>' directly commit: b2d67616fcf9f0a21940b2ba8d80af2fb0c81bc1 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

2 months

Re: [PATCH v4 0/9] coresight: change some driver' spinlock type to raw_spinlock_t

by Suzuki K Poulose

Hi Levi, On 20/12/2024 10:45, Yeoreum Yun wrote: > In some coresight drivers, drvdata->spinlock can be held during __schedule() > by perf_event_task_sched_out()/in(). > > Since drvdata->spinlock type is spinlock_t and > perf_event_task_sched_out()/in() is called after acquiring rq_lock, > which is raw_spinlock_t (an unsleepable lock), > this poses an issue in PREEMPT_RT kernel where spinlock_t is sleepable. > > To address this,change type drvdata->spinlock in some coresight drivers, > which can be called by perf_event_task_sched_out()/in(), > from spinlock_t to raw_spinlock_t. > > Reviewed-by: James Clark <james.clark(a)linaro.org> This doesn't apply cleanly on coresight next branch. Please could you rebase on coresight /next ? Cheers Suzuki > > Yeoreum Yun (9): > coresight: change coresight_device lock type to raw_spinlock_t > coresight-etm4x: change etmv4_drvdata spinlock type to raw_spinlock_t > coresight: change coresight_trace_id_map's lock type to > raw_spinlock_t > coresight-cti: change cti_drvdata spinlock's type to raw_spinlock_t > coresight-etb10: change etb_drvdata spinlock's type to raw_spinlock_t > coresight-funnel: change funnel_drvdata spinlock's type to > raw_spinlock_t > coresight-replicator: change replicator_drvdata spinlock's type to > raw_spinlock_t > coresight-tmc: change tmc_drvdata spinlock's type to raw_spinlock_t > coresight/ultrasoc: change smb_drv_data spinlock's type to > raw_spinlock_t > > .../hwtracing/coresight/coresight-config.c | 8 +- > .../hwtracing/coresight/coresight-config.h | 2 +- > drivers/hwtracing/coresight/coresight-core.c | 2 +- > .../hwtracing/coresight/coresight-cti-core.c | 44 +-- > .../hwtracing/coresight/coresight-cti-sysfs.c | 76 +++--- > drivers/hwtracing/coresight/coresight-cti.h | 2 +- > drivers/hwtracing/coresight/coresight-etb10.c | 26 +- > .../coresight/coresight-etm4x-core.c | 18 +- > .../coresight/coresight-etm4x-sysfs.c | 250 +++++++++--------- > drivers/hwtracing/coresight/coresight-etm4x.h | 2 +- > .../hwtracing/coresight/coresight-funnel.c | 12 +- > .../coresight/coresight-replicator.c | 12 +- > .../hwtracing/coresight/coresight-syscfg.c | 26 +- > .../hwtracing/coresight/coresight-tmc-core.c | 6 +- > .../hwtracing/coresight/coresight-tmc-etf.c | 48 ++-- > .../hwtracing/coresight/coresight-tmc-etr.c | 40 +-- > drivers/hwtracing/coresight/coresight-tmc.h | 2 +- > .../hwtracing/coresight/coresight-trace-id.c | 22 +- > drivers/hwtracing/coresight/ultrasoc-smb.c | 12 +- > drivers/hwtracing/coresight/ultrasoc-smb.h | 2 +- > include/linux/coresight.h | 4 +- > 21 files changed, 308 insertions(+), 308 deletions(-) > > -- > LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}

2 months

[PATCH v1 0/8] Arm CoreSight: Support AUX pause and resume

by Leo Yan

This series is to enable AUX pause and resume on Arm CoreSight. The first patch extracts the trace unit controlling operations to two functions. These two functions will be used by AUX pause and resume. Patches 02 and 03 change the ETMv4 driver to prepare callback functions for AUX pause and resume. Patch 04 changes the ETM perf layer to support AUX pause and resume in a perf session. The patches 05 and 06 offers an extra feature for updating buffer on AUX pause occasion, which can mitigate the trace data lose issue. Patch 07 documents the AUX pause usages with Arm CoreSight. The last patch syncs headers between user space and the kernel. This patch set has been verified on the Hikey960 board and TC platform. The previous one uses ETR and the later uses TRBE as sink. It is suggested to disable CPUIdle (add `nohlt` option in Linux command line) when verifying this series. ETM and funnel drivers are found issues during CPU suspend and resume which will be addressed separately. Leo Yan (8): coresight: etm4x: Extract the trace unit controlling coresight: Introduce pause and resume APIs for source coresight: etm4x: Hook pause and resume callbacks coresight: perf: Support AUX trace pause and resume coresight: etm: Add an attribute for updating buffer coresight: perf: Update buffer on AUX pause Documentation: coresight: Document AUX pause and resume perf cs-etm: Sync kernel coresight-pmu.h header .../trace/coresight/coresight-perf.rst | 50 ++++++ drivers/hwtracing/coresight/coresight-core.c | 12 ++ .../hwtracing/coresight/coresight-etm-perf.c | 94 +++++++++- .../hwtracing/coresight/coresight-etm-perf.h | 2 + .../coresight/coresight-etm4x-core.c | 166 ++++++++++++------ drivers/hwtracing/coresight/coresight-etm4x.h | 2 + drivers/hwtracing/coresight/coresight-priv.h | 2 + include/linux/coresight-pmu.h | 1 + include/linux/coresight.h | 4 + tools/include/linux/coresight-pmu.h | 1 + 10 files changed, 281 insertions(+), 53 deletions(-) -- 2.34.1

2 months

Re: [PATCH v12 6/7] Coresight: Add Coresight TMC Control Unit driver

by Suzuki K Poulose

On 24/02/2025 03:32, Jie Gan wrote: > > > On 2/21/2025 7:39 PM, Suzuki K Poulose wrote: >> On 17/02/2025 09:30, Jie Gan wrote: >>> The Coresight TMC Control Unit hosts miscellaneous configuration >>> registers >>> which control various features related to TMC ETR sink. >>> >>> Based on the trace ID, which is programmed in the related CTCU ATID >>> register of a specific ETR, trace data with that trace ID gets into >>> the ETR buffer, while other trace data gets dropped. >>> >>> Enabling source device sets one bit of the ATID register based on >>> source device's trace ID. >>> Disabling source device resets the bit according to the source >>> device's trace ID. >>> >>> Reviewed-by: James Clark <james.clark(a)linaro.org> >>> Signed-off-by: Jie Gan <quic_jiegan(a)quicinc.com> >>> --- >>> drivers/hwtracing/coresight/Kconfig | 12 + >>> drivers/hwtracing/coresight/Makefile | 1 + >>> drivers/hwtracing/coresight/coresight-ctcu.c | 268 +++++++++++++++++++ >>> drivers/hwtracing/coresight/coresight-ctcu.h | 24 ++ >>> include/linux/coresight.h | 3 +- >>> 5 files changed, 307 insertions(+), 1 deletion(-) >>> create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.c >>> create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.h >>> >>> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/ >>> coresight/Kconfig >>> index 06f0a7594169..ecd7086a5b83 100644 >>> --- a/drivers/hwtracing/coresight/Kconfig >>> +++ b/drivers/hwtracing/coresight/Kconfig >>> @@ -133,6 +133,18 @@ config CORESIGHT_STM >>> To compile this driver as a module, choose M here: the >>> module will be called coresight-stm. >>> +config CORESIGHT_CTCU >>> + tristate "CoreSight TMC Control Unit driver" >>> + depends on CORESIGHT_LINK_AND_SINK_TMC >>> + help >>> + This driver provides support for CoreSight TMC Control Unit >>> + that hosts miscellaneous configuration registers. This is >>> + primarily used for controlling the behaviors of the TMC >>> + ETR device. >>> + >>> + To compile this driver as a module, choose M here: the >>> + module will be called coresight-ctcu. >>> + >>> config CORESIGHT_CPU_DEBUG >>> tristate "CoreSight CPU Debug driver" >>> depends on ARM || ARM64 >>> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/ >>> hwtracing/ coresight/Makefile >>> index 4ba478211b31..1b7869910a12 100644 >>> --- a/drivers/hwtracing/coresight/Makefile >>> +++ b/drivers/hwtracing/coresight/Makefile >>> @@ -51,3 +51,4 @@ coresight-cti-y := coresight-cti-core.o coresight- >>> cti-platform.o \ >>> coresight-cti-sysfs.o >>> obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o >>> obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o >>> +obj-$(CONFIG_CORESIGHT_CTCU) += coresight-ctcu.o >>> diff --git a/drivers/hwtracing/coresight/coresight-ctcu.c b/drivers/ >>> hwtracing/coresight/coresight-ctcu.c >>> new file mode 100644 >>> index 000000000000..e1460a627c4d >>> --- /dev/null >>> +++ b/drivers/hwtracing/coresight/coresight-ctcu.c >>> @@ -0,0 +1,268 @@ >>> +// SPDX-License-Identifier: GPL-2.0-only >>> +/* >>> + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All >>> rights reserved. >>> + */ >>> + >>> +#include <linux/clk.h> >>> +#include <linux/coresight.h> >>> +#include <linux/device.h> >>> +#include <linux/err.h> >>> +#include <linux/kernel.h> >>> +#include <linux/init.h> >>> +#include <linux/io.h> >>> +#include <linux/module.h> >>> +#include <linux/mutex.h> >>> +#include <linux/of.h> >>> +#include <linux/platform_device.h> >>> +#include <linux/slab.h> >>> + >>> +#include "coresight-ctcu.h" >>> +#include "coresight-priv.h" >>> + >>> +DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu"); >>> + >>> +#define ctcu_writel(drvdata, val, offset) __raw_writel((val), >>> drvdata->base + offset) >>> +#define ctcu_readl(drvdata, offset) __raw_readl(drvdata->base >>> + offset) >>> + >>> +/* >>> + * The TMC Coresight Control Unit uses four ATID registers to >>> control the data >>> + * filter function based on the trace ID for each TMC ETR sink. The >>> length of >>> + * each ATID register is 32 bits. Therefore, the ETR has a related >>> field in >>> + * CTCU that is 128 bits long. Each trace ID is represented by one >>> bit in that >>> + * filed. >>> + * e.g. ETR0ATID0 layout, set bit 5 for traceid 5 >>> + * bit5 >>> + * ------------------------------------------------------ >>> + * | |28| |24| |20| |16| |12| |8| 1|4| |0| >>> + * ------------------------------------------------------ >>> + * >>> + * e.g. ETR0: >>> + * 127 0 from ATID_offset for ETR0ATID0 >>> + * ------------------------- >>> + * |ATID3|ATID2|ATID1|ATID0| >>> + */ >>> +#define CTCU_ATID_REG_OFFSET(traceid, atid_offset) \ >>> + ((traceid / 32) * 4 + atid_offset) >>> + >>> +#define CTCU_ATID_REG_BIT(traceid) (traceid % 32) >>> +#define CTCU_ATID_REG_SIZE 0x10 >>> + >>> +struct ctcu_atid_config { >>> + const u32 atid_offset; >>> + const u32 port_num; >>> +}; >>> + >>> +struct ctcu_config { >>> + const struct ctcu_atid_config *atid_config; >>> + int num_atid_config; >>> +}; >>> + >>> +static const struct ctcu_atid_config sa8775p_atid_cfgs[] = { >>> + {0xf8, 0}, >>> + {0x108, 1}, >>> +}; >>> + >>> +static const struct ctcu_config sa8775p_cfgs = { >>> + .atid_config = sa8775p_atid_cfgs, >>> + .num_atid_config = ARRAY_SIZE(sa8775p_atid_cfgs), >>> +}; >>> + >>> +static void ctcu_program_atid_register(struct ctcu_drvdata *drvdata, >>> u32 reg_offset, >>> + u8 bit, bool enable) >>> +{ >>> + u32 val; >>> + >>> + CS_UNLOCK(drvdata->base); >>> + val = ctcu_readl(drvdata, reg_offset); >>> + val = enable? (val | BIT(bit)) : (val & ~BIT(bit)); >> >> minor nit: If possible do not use the ternary operator like this. It >> is much better readable as: >> >> if (enable) >> val |= BIT(bit); >> else >> val &= ~BIT(bit); >> > > Will do this way. > >>> + ctcu_writel(drvdata, val, reg_offset); >>> + CS_LOCK(drvdata->base); >>> +} >>> + >>> +/* >>> + * __ctcu_set_etr_traceid: Set bit in the ATID register based on >>> trace ID when enable is true. >>> + * Reset the bit of the ATID register based on trace ID when enable >>> is false. >>> + * >>> + * @csdev: coresight_device struct related to the device >>> + * @traceid: trace ID of the source tracer. >>> + * @port_num: port number from TMC ETR sink. >>> + * @enable: True for set bit and false for reset bit. >>> + * >>> + * Returns 0 indicates success. Non-zero result means failure. >>> + */ >>> +static int __ctcu_set_etr_traceid(struct coresight_device *csdev, u8 >>> traceid, int port_num, >>> + bool enable) >>> +{ >>> + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); >>> + u32 atid_offset, reg_offset; >>> + u8 refcnt, bit; >>> + >>> + atid_offset = drvdata->atid_offset[port_num]; >>> + if (atid_offset == 0) >>> + return -EINVAL; >>> + >>> + bit = CTCU_ATID_REG_BIT(traceid); >>> + reg_offset = CTCU_ATID_REG_OFFSET(traceid, atid_offset); >>> + if (reg_offset - atid_offset > CTCU_ATID_REG_SIZE) >>> + return -EINVAL; >>> + >>> + guard(raw_spinlock_irqsave)(&drvdata->spin_lock); >>> + refcnt = drvdata->traceid_refcnt[port_num][traceid]; >>> + /* Only program the atid register when the refcnt value is 0 or >>> 1 */ >> >> A normal trace source won't be enabled more than once (e.g., ETM). The >> only odd one out is the STM, which may be driven by multiple agents. >> So this refcounting looks necessary. >> > > Besides, for the TPDMs which shared the trace_id of the TPDA also need > the refcnt. Consider we have TPDM1 and TPDM2 connected to the same TPDA > device. Once we disable one of the TPDM without checking the refcnt, the > filter function will be disabled for another TPDM. > >>> + if (enable && (++refcnt == 1)) >>> + ctcu_program_atid_register(drvdata, reg_offset, bit, enable); >>> + else if (!enable && (--refcnt == 0)) >>> + ctcu_program_atid_register(drvdata, reg_offset, bit, enable); >> >> minor nit: >> >> if ((enable && !refcount++) || >> (!enable && --refcount)) >> ctcu_program_atid_register(drvdata, reg_offset, bit, enable); >> >> > > I did (enable && (++refcnt == 1)) just because I think we only need > program the register when refcnt is equal to 1. We dont need reprogram > the register with same value when refcnt greater than 1. So I think it's > better for the performance? The code above is similar to yours. It would "set" only for the first time, when enable == 0, refcount == 0 now, but will be incremented to 1. Suzuki

2 months

Re: [PATCH v12 6/7] Coresight: Add Coresight TMC Control Unit driver

by James Clark

On 24/02/2025 3:32 am, Jie Gan wrote: > > > On 2/21/2025 7:39 PM, Suzuki K Poulose wrote: >> On 17/02/2025 09:30, Jie Gan wrote: >>> The Coresight TMC Control Unit hosts miscellaneous configuration >>> registers >>> which control various features related to TMC ETR sink. >>> >>> Based on the trace ID, which is programmed in the related CTCU ATID >>> register of a specific ETR, trace data with that trace ID gets into >>> the ETR buffer, while other trace data gets dropped. >>> >>> Enabling source device sets one bit of the ATID register based on >>> source device's trace ID. >>> Disabling source device resets the bit according to the source >>> device's trace ID. >>> >>> Reviewed-by: James Clark <james.clark(a)linaro.org> >>> Signed-off-by: Jie Gan <quic_jiegan(a)quicinc.com> >>> --- >>> drivers/hwtracing/coresight/Kconfig | 12 + >>> drivers/hwtracing/coresight/Makefile | 1 + >>> drivers/hwtracing/coresight/coresight-ctcu.c | 268 +++++++++++++++++++ >>> drivers/hwtracing/coresight/coresight-ctcu.h | 24 ++ >>> include/linux/coresight.h | 3 +- >>> 5 files changed, 307 insertions(+), 1 deletion(-) >>> create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.c >>> create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.h >>> >>> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/ >>> coresight/Kconfig >>> index 06f0a7594169..ecd7086a5b83 100644 >>> --- a/drivers/hwtracing/coresight/Kconfig >>> +++ b/drivers/hwtracing/coresight/Kconfig >>> @@ -133,6 +133,18 @@ config CORESIGHT_STM >>> To compile this driver as a module, choose M here: the >>> module will be called coresight-stm. >>> +config CORESIGHT_CTCU >>> + tristate "CoreSight TMC Control Unit driver" >>> + depends on CORESIGHT_LINK_AND_SINK_TMC >>> + help >>> + This driver provides support for CoreSight TMC Control Unit >>> + that hosts miscellaneous configuration registers. This is >>> + primarily used for controlling the behaviors of the TMC >>> + ETR device. >>> + >>> + To compile this driver as a module, choose M here: the >>> + module will be called coresight-ctcu. >>> + >>> config CORESIGHT_CPU_DEBUG >>> tristate "CoreSight CPU Debug driver" >>> depends on ARM || ARM64 >>> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/ >>> hwtracing/ coresight/Makefile >>> index 4ba478211b31..1b7869910a12 100644 >>> --- a/drivers/hwtracing/coresight/Makefile >>> +++ b/drivers/hwtracing/coresight/Makefile >>> @@ -51,3 +51,4 @@ coresight-cti-y := coresight-cti-core.o coresight- >>> cti-platform.o \ >>> coresight-cti-sysfs.o >>> obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o >>> obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o >>> +obj-$(CONFIG_CORESIGHT_CTCU) += coresight-ctcu.o >>> diff --git a/drivers/hwtracing/coresight/coresight-ctcu.c b/drivers/ >>> hwtracing/coresight/coresight-ctcu.c >>> new file mode 100644 >>> index 000000000000..e1460a627c4d >>> --- /dev/null >>> +++ b/drivers/hwtracing/coresight/coresight-ctcu.c >>> @@ -0,0 +1,268 @@ >>> +// SPDX-License-Identifier: GPL-2.0-only >>> +/* >>> + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All >>> rights reserved. >>> + */ >>> + >>> +#include <linux/clk.h> >>> +#include <linux/coresight.h> >>> +#include <linux/device.h> >>> +#include <linux/err.h> >>> +#include <linux/kernel.h> >>> +#include <linux/init.h> >>> +#include <linux/io.h> >>> +#include <linux/module.h> >>> +#include <linux/mutex.h> >>> +#include <linux/of.h> >>> +#include <linux/platform_device.h> >>> +#include <linux/slab.h> >>> + >>> +#include "coresight-ctcu.h" >>> +#include "coresight-priv.h" >>> + >>> +DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu"); >>> + >>> +#define ctcu_writel(drvdata, val, offset) __raw_writel((val), >>> drvdata->base + offset) >>> +#define ctcu_readl(drvdata, offset) __raw_readl(drvdata->base >>> + offset) >>> + >>> +/* >>> + * The TMC Coresight Control Unit uses four ATID registers to >>> control the data >>> + * filter function based on the trace ID for each TMC ETR sink. The >>> length of >>> + * each ATID register is 32 bits. Therefore, the ETR has a related >>> field in >>> + * CTCU that is 128 bits long. Each trace ID is represented by one >>> bit in that >>> + * filed. >>> + * e.g. ETR0ATID0 layout, set bit 5 for traceid 5 >>> + * bit5 >>> + * ------------------------------------------------------ >>> + * | |28| |24| |20| |16| |12| |8| 1|4| |0| >>> + * ------------------------------------------------------ >>> + * >>> + * e.g. ETR0: >>> + * 127 0 from ATID_offset for ETR0ATID0 >>> + * ------------------------- >>> + * |ATID3|ATID2|ATID1|ATID0| >>> + */ >>> +#define CTCU_ATID_REG_OFFSET(traceid, atid_offset) \ >>> + ((traceid / 32) * 4 + atid_offset) >>> + >>> +#define CTCU_ATID_REG_BIT(traceid) (traceid % 32) >>> +#define CTCU_ATID_REG_SIZE 0x10 >>> + >>> +struct ctcu_atid_config { >>> + const u32 atid_offset; >>> + const u32 port_num; >>> +}; >>> + >>> +struct ctcu_config { >>> + const struct ctcu_atid_config *atid_config; >>> + int num_atid_config; >>> +}; >>> + >>> +static const struct ctcu_atid_config sa8775p_atid_cfgs[] = { >>> + {0xf8, 0}, >>> + {0x108, 1}, >>> +}; >>> + >>> +static const struct ctcu_config sa8775p_cfgs = { >>> + .atid_config = sa8775p_atid_cfgs, >>> + .num_atid_config = ARRAY_SIZE(sa8775p_atid_cfgs), >>> +}; >>> + >>> +static void ctcu_program_atid_register(struct ctcu_drvdata *drvdata, >>> u32 reg_offset, >>> + u8 bit, bool enable) >>> +{ >>> + u32 val; >>> + >>> + CS_UNLOCK(drvdata->base); >>> + val = ctcu_readl(drvdata, reg_offset); >>> + val = enable? (val | BIT(bit)) : (val & ~BIT(bit)); >> >> minor nit: If possible do not use the ternary operator like this. It >> is much better readable as: >> >> if (enable) >> val |= BIT(bit); >> else >> val &= ~BIT(bit); >> > > Will do this way. > >>> + ctcu_writel(drvdata, val, reg_offset); >>> + CS_LOCK(drvdata->base); >>> +} >>> + >>> +/* >>> + * __ctcu_set_etr_traceid: Set bit in the ATID register based on >>> trace ID when enable is true. >>> + * Reset the bit of the ATID register based on trace ID when enable >>> is false. >>> + * >>> + * @csdev: coresight_device struct related to the device >>> + * @traceid: trace ID of the source tracer. >>> + * @port_num: port number from TMC ETR sink. >>> + * @enable: True for set bit and false for reset bit. >>> + * >>> + * Returns 0 indicates success. Non-zero result means failure. >>> + */ >>> +static int __ctcu_set_etr_traceid(struct coresight_device *csdev, u8 >>> traceid, int port_num, >>> + bool enable) >>> +{ >>> + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); >>> + u32 atid_offset, reg_offset; >>> + u8 refcnt, bit; >>> + >>> + atid_offset = drvdata->atid_offset[port_num]; >>> + if (atid_offset == 0) >>> + return -EINVAL; >>> + >>> + bit = CTCU_ATID_REG_BIT(traceid); >>> + reg_offset = CTCU_ATID_REG_OFFSET(traceid, atid_offset); >>> + if (reg_offset - atid_offset > CTCU_ATID_REG_SIZE) >>> + return -EINVAL; >>> + >>> + guard(raw_spinlock_irqsave)(&drvdata->spin_lock); >>> + refcnt = drvdata->traceid_refcnt[port_num][traceid]; >>> + /* Only program the atid register when the refcnt value is 0 or >>> 1 */ >> >> A normal trace source won't be enabled more than once (e.g., ETM). The >> only odd one out is the STM, which may be driven by multiple agents. >> So this refcounting looks necessary. >> > > Besides, for the TPDMs which shared the trace_id of the TPDA also need > the refcnt. Consider we have TPDM1 and TPDM2 connected to the same TPDA > device. Once we disable one of the TPDM without checking the refcnt, the > filter function will be disabled for another TPDM. > >>> + if (enable && (++refcnt == 1)) >>> + ctcu_program_atid_register(drvdata, reg_offset, bit, enable); >>> + else if (!enable && (--refcnt == 0)) >>> + ctcu_program_atid_register(drvdata, reg_offset, bit, enable); >> >> minor nit: >> >> if ((enable && !refcount++) || >> (!enable && --refcount)) >> ctcu_program_atid_register(drvdata, reg_offset, bit, enable); >> >> > > I did (enable && (++refcnt == 1)) just because I think we only need > program the register when refcnt is equal to 1. We dont need reprogram > the register with same value when refcnt greater than 1. So I think it's > better for the performance? > >> Also, see my comment the bottom for "refcount" being u8 . > > Sure, will check. > >> >> >>> + >>> + drvdata->traceid_refcnt[port_num][traceid] = refcnt; >>> + >>> + return 0; >>> +} >>> + >>> +static int ctcu_get_active_port(struct coresight_device *sink, >>> struct coresight_device *helper) >>> +{ >>> + int i; >>> + >>> + for (i = 0; i < sink->pdata->nr_outconns; ++i) { >>> + if (sink->pdata->out_conns[i]->dest_dev) >>> + return sink->pdata->out_conns[i]->dest_port; >> >> Don't we need to make sure it matches the helper ? What if there are >> multiple helpers ? e.g, a CATU connected to the ETR and CTCU ? >> Or even try the opposite ? i.e. search the helper and find the port >> matching the sink ? Good catch, looks like this should be done the opposite way around. >> >> struct coresight_platform_data *pdata = helper->pdata; >> >> for (i = 0; i < pdata->nr_inconns; ++i) >> if (pdata->in_conns[i]->dest_dev == sink) >> return pdata->in_conns[i]->src_port; >> >> Not sure if that works with the helper device connection, James ? Yeah connections are always made in both directions. > Can we check the subtype of the helper device? We should only have one > CTCU helper device for each ETR. > > enum coresight_dev_subtype_helper subtype; > > for (i = 0; i < sink->pdata->nr_outconns; ++i) { > subtype = sink->pdata->out_conns[i]->dest_dev->subtype.helper_subtype; > if (subtype == CORESIGHT_DEV_SUBTYPE_HELPER_CTCU) > return sink->pdata->out_conns[i]->dest_port; > I don't think we need to check the type, just search all the CTCU's in_conns until you find the sink. As Suzuki says, by looking at the out_conns of the sink you might find a different helper device. Checking that it really is connected to the sink is probably more robust that relying on the type anyway.

2 months, 1 week

Re: [PATCH 0/3] hwtracing: coresight: Minor const fixes

by Suzuki K Poulose

On Sat, 22 Feb 2025 12:38:56 +0100, Krzysztof Kozlowski wrote: > Just few improvements. > > Best regards, > Krzysztof > Applied, thanks! [1/3] coresight: catu: Constify amba_id table https://git.kernel.org/coresight/c/2ecdbebe [2/3] coresight: tpda: Constify amba_id table https://git.kernel.org/coresight/c/7b6d52e8 [3/3] coresight: tpdm: Constify amba_id table https://git.kernel.org/coresight/c/2197cbc2 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

2 months, 1 week

[PATCH v14 0/8] Coresight for Kernel panic and watchdog reset

by Linu Cherian

This patch series is rebased on coresight-next-v6.13.rc2 * Patches 1 & 2 adds support for allocation of trace buffer pages from reserved RAM * Patches 3 & 4 adds support for saving metadata at the time of kernel panic * Patch 5 adds support for reading trace data captured at the time of panic * Patches 6 & 7 adds support for disabling coresight blocks at the time of panic * Patch 8: Gives the full description about this feature as part of documentation v13 is posted here, https://lore.kernel.org/linux-arm-kernel/20241216053014.3427909-1-lcherian@… Changelog from v13: * Changed the log levels of crc error check failure prints from dev_dbg to dev_err as suggested by Suzuki * Add metadata valid flag checks for successfully opening crashdata files, as suggested by Suzuki * Report to the user during probe if valid crash tracedata is found, as suggested by Suzuki * Added CRC recalculation upon barrier packet insertion for overflow cases, this fixes crc check failures upon subsequent boots * Few other trivial cleanups suggested by Suzuki Changelog from v12: * Fixed wrong buffer pointer passed to coresigh_insert_barrier_packet * tmc_read_prepare/unprepare_crashdata need to be called only once and hence removed from read path and added to tmc_probe * tmc_read_prepare_crashdata renamed to tmc_prepare_crashdata and avoid taking locks as its moved to probe function. * Introduced read status flag, "reading" specific to reserved buffer to keep the reserved buffer reading independent of the regular buffer. * open/release ops for reserved buffer has to take care only about the set/unset the "reading" status flag as the reserved buffer is prepared during the probe time itself. * Few other trivial changes Changelog from v11: Convert all commands to literal code blocks, that was missed out in v11. No other code changes. Changelog from v10: * Converted all csdev_access_* to readl functions in tmc_panic_sync_* * Added "tmc" prefix for register snapshots in struct tmc_crash_metadata * Converted dev_info to dev_dbg in panic handlers * Converted dsb to dmb in panic handlers * Fixed marking metadata as invalid when a user is trying to use the reserved buffer. Earlier this was wrongly set at the time of reading reserved trace buffer. * Moved common validation checks to is_tmc_crashdata_valid and minor code rearrangements for efficiency * Got rid of sink specific prepare/unprepare invocations * Got rid of full from struct tmc_resrv_buf * While reading crashdata, size is now calculated from metadata instead of relying on reserved buffer size populated by dtb * Minor documenation fixes Changelog from v9: * Add common helper function of_tmc_get_reserved_resource_by_name for better code reuse * Reserved buffer validity and crashdata validity has been separated to avoid interdependence * New fields added to crash metadata: version, ffcr, ffsr, mode * Version checks added for metadata validation * Special file /dev/crash_tmc_xxx would be available only when crash metadata is valid * Removed READ_CRASHDATA mode meant for special casing crashdata reads. Instead, dedicated read function added for crashdata reads from reserved buffer which is common for both ETR and ETF sinks as well. * Documentation added to Documentation/tracing/coresight/panic.rst Changelog from v8: * Added missing exit path on error in __tmc_probe. * Few whitespace fixes, checkpatch fixes. * With perf sessions honouring stop_on_flush sysfs attribute, removed redundant variable stop_on_flush_en. Changelog from v7: * Fixed breakage on perf test -vvvv "arm coresight". No issues seen with and without "resrv" buffer mode * Moved the crashdev registration into a separate function. * Removed redundant variable in tmc_etr_setup_crashdata_buf * Avoided a redundant memcpy in tmc_panic_sync_etf. * Tested kernel panic with trace session started uisng perf. Please see the title "Perf based testing" below for details. For this, stop_on_flush sysfs attribute is taken into consideration while starting perf sessions as well. Changelog from v6: * Added special device files for reading crashdata, so that read_prevboot mode flag is removed. * Added new sysfs TMC device attribute, stop_on_flush. Stop on flush trigger event is disabled by default. User need to explicitly enable this from sysfs for panic stop to work. * Address parameter for panicstop ETM configuration is chosen as kernel "panic" address by default. * Added missing tmc_wait_for_tmcready during panic handling * Few other misc code rearrangements. Changelog from v5: * Fixed issues reported by CONFIG_DEBUG_ATOMIC_SLEEP * Fixed a memory leak while reading data from /dev/tmc_etrx in READ_PREVBOOT mode * Tested reading trace data from crashdump kernel Changelog from v4: * Device tree binding - Description is made more explicit on the usage of reserved memory region - Mismatch in memory region names in dts binding and driver fixed - Removed "mem" suffix from the memory region names * Rename "struct tmc_register_snapshot" -> "struct tmc_crash_metadata", since it contains more than register snapshot. Related variables are named accordingly. * Rename struct tmc_drvdata members resrv_buf -> crash_tbuf metadata -> crash_mdata * Size field in metadata refers to RSZ register and hence indicates the size in 32 bit words. ETR metadata follows this convention, the same has been extended to ETF metadata as well. * Added crc32 for more robust metadata and tracedata validation. * Added/modified dev_dbg messages during metadata validation * Fixed a typo in patch 5 commit description Changelog from v3: * Converted the Coresight ETM driver change to a named configuration. RFC tag has been removed with this change. * Fixed yaml issues reported by "make dt_binding_check" * Added names for reserved memory regions 0 and 1 * Added prevalidation checks for metadata processing * Fixed a regression introduced in RFC v3 - TMC Status register was getting saved wrongly * Reverted memremap attribute changes from _WB to _WC to match with the dma map attributes * Introduced reserved buffer mode specific .sync op. This fixes a possible crash when reserved buffer mode was used in normal trace capture, due to unwanted dma maintenance operations. Linu Cherian (8): dt-bindings: arm: coresight-tmc: Add "memory-region" property coresight: tmc-etr: Add support to use reserved trace memory coresight: core: Add provision for panic callbacks coresight: tmc: Enable panic sync handling coresight: tmc: Add support for reading crash data coresight: tmc: Stop trace capture on FlIn coresight: config: Add preloaded configuration Documentation: coresight: Panic support .../bindings/arm/arm,coresight-tmc.yaml | 26 ++ Documentation/trace/coresight/panic.rst | 362 ++++++++++++++++++ drivers/hwtracing/coresight/Makefile | 2 +- .../coresight/coresight-cfg-preload.c | 2 + .../coresight/coresight-cfg-preload.h | 2 + .../hwtracing/coresight/coresight-cfg-pstop.c | 83 ++++ drivers/hwtracing/coresight/coresight-core.c | 42 ++ .../hwtracing/coresight/coresight-tmc-core.c | 321 +++++++++++++++- .../hwtracing/coresight/coresight-tmc-etf.c | 92 ++++- .../hwtracing/coresight/coresight-tmc-etr.c | 184 ++++++++- drivers/hwtracing/coresight/coresight-tmc.h | 105 +++++ include/linux/coresight.h | 12 + 12 files changed, 1221 insertions(+), 12 deletions(-) create mode 100644 Documentation/trace/coresight/panic.rst create mode 100644 drivers/hwtracing/coresight/coresight-cfg-pstop.c -- 2.34.1

2 months, 1 week

Re: [PATCH] coresight: catu: Fix number of pages while using 64k pages

by Suzuki K Poulose

On Thu, 9 Jan 2025 21:53:48 +0000, Ilkka Koskinen wrote: > Trying to record a trace on kernel with 64k pages resulted in -ENOMEM. > This happens due to a bug in calculating the number of table pages, which > returns zero. Fix the issue by rounding up. > > $ perf record --kcore -e cs_etm/@tmc_etr55,cycacc,branch_broadcast/k --per-thread taskset --cpu-list 1 dd if=/dev/zero of=/dev/null > failed to mmap with 12 (Cannot allocate memory) > > [...] Applied, thanks! [1/1] coresight: catu: Fix number of pages while using 64k pages https://git.kernel.org/coresight/c/0e14e062f5ff Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

2 months, 1 week

Re: [PATCH v12 6/7] Coresight: Add Coresight TMC Control Unit driver

by Suzuki K Poulose

On 17/02/2025 09:30, Jie Gan wrote: > The Coresight TMC Control Unit hosts miscellaneous configuration registers > which control various features related to TMC ETR sink. > > Based on the trace ID, which is programmed in the related CTCU ATID > register of a specific ETR, trace data with that trace ID gets into > the ETR buffer, while other trace data gets dropped. > > Enabling source device sets one bit of the ATID register based on > source device's trace ID. > Disabling source device resets the bit according to the source > device's trace ID. > > Reviewed-by: James Clark <james.clark(a)linaro.org> > Signed-off-by: Jie Gan <quic_jiegan(a)quicinc.com> > --- > drivers/hwtracing/coresight/Kconfig | 12 + > drivers/hwtracing/coresight/Makefile | 1 + > drivers/hwtracing/coresight/coresight-ctcu.c | 268 +++++++++++++++++++ > drivers/hwtracing/coresight/coresight-ctcu.h | 24 ++ > include/linux/coresight.h | 3 +- > 5 files changed, 307 insertions(+), 1 deletion(-) > create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.c > create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.h > > diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig > index 06f0a7594169..ecd7086a5b83 100644 > --- a/drivers/hwtracing/coresight/Kconfig > +++ b/drivers/hwtracing/coresight/Kconfig > @@ -133,6 +133,18 @@ config CORESIGHT_STM > To compile this driver as a module, choose M here: the > module will be called coresight-stm. > > +config CORESIGHT_CTCU > + tristate "CoreSight TMC Control Unit driver" > + depends on CORESIGHT_LINK_AND_SINK_TMC > + help > + This driver provides support for CoreSight TMC Control Unit > + that hosts miscellaneous configuration registers. This is > + primarily used for controlling the behaviors of the TMC > + ETR device. > + > + To compile this driver as a module, choose M here: the > + module will be called coresight-ctcu. > + > config CORESIGHT_CPU_DEBUG > tristate "CoreSight CPU Debug driver" > depends on ARM || ARM64 > diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile > index 4ba478211b31..1b7869910a12 100644 > --- a/drivers/hwtracing/coresight/Makefile > +++ b/drivers/hwtracing/coresight/Makefile > @@ -51,3 +51,4 @@ coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ > coresight-cti-sysfs.o > obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o > obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o > +obj-$(CONFIG_CORESIGHT_CTCU) += coresight-ctcu.o > diff --git a/drivers/hwtracing/coresight/coresight-ctcu.c b/drivers/hwtracing/coresight/coresight-ctcu.c > new file mode 100644 > index 000000000000..e1460a627c4d > --- /dev/null > +++ b/drivers/hwtracing/coresight/coresight-ctcu.c > @@ -0,0 +1,268 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include <linux/clk.h> > +#include <linux/coresight.h> > +#include <linux/device.h> > +#include <linux/err.h> > +#include <linux/kernel.h> > +#include <linux/init.h> > +#include <linux/io.h> > +#include <linux/module.h> > +#include <linux/mutex.h> > +#include <linux/of.h> > +#include <linux/platform_device.h> > +#include <linux/slab.h> > + > +#include "coresight-ctcu.h" > +#include "coresight-priv.h" > + > +DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu"); > + > +#define ctcu_writel(drvdata, val, offset) __raw_writel((val), drvdata->base + offset) > +#define ctcu_readl(drvdata, offset) __raw_readl(drvdata->base + offset) > + > +/* > + * The TMC Coresight Control Unit uses four ATID registers to control the data > + * filter function based on the trace ID for each TMC ETR sink. The length of > + * each ATID register is 32 bits. Therefore, the ETR has a related field in > + * CTCU that is 128 bits long. Each trace ID is represented by one bit in that > + * filed. > + * e.g. ETR0ATID0 layout, set bit 5 for traceid 5 > + * bit5 > + * ------------------------------------------------------ > + * | |28| |24| |20| |16| |12| |8| 1|4| |0| > + * ------------------------------------------------------ > + * > + * e.g. ETR0: > + * 127 0 from ATID_offset for ETR0ATID0 > + * ------------------------- > + * |ATID3|ATID2|ATID1|ATID0| > + */ > +#define CTCU_ATID_REG_OFFSET(traceid, atid_offset) \ > + ((traceid / 32) * 4 + atid_offset) > + > +#define CTCU_ATID_REG_BIT(traceid) (traceid % 32) > +#define CTCU_ATID_REG_SIZE 0x10 > + > +struct ctcu_atid_config { > + const u32 atid_offset; > + const u32 port_num; > +}; > + > +struct ctcu_config { > + const struct ctcu_atid_config *atid_config; > + int num_atid_config; > +}; > + > +static const struct ctcu_atid_config sa8775p_atid_cfgs[] = { > + {0xf8, 0}, > + {0x108, 1}, > +}; > + > +static const struct ctcu_config sa8775p_cfgs = { > + .atid_config = sa8775p_atid_cfgs, > + .num_atid_config = ARRAY_SIZE(sa8775p_atid_cfgs), > +}; > + > +static void ctcu_program_atid_register(struct ctcu_drvdata *drvdata, u32 reg_offset, > + u8 bit, bool enable) > +{ > + u32 val; > + > + CS_UNLOCK(drvdata->base); > + val = ctcu_readl(drvdata, reg_offset); > + val = enable? (val | BIT(bit)) : (val & ~BIT(bit)); minor nit: If possible do not use the ternary operator like this. It is much better readable as: if (enable) val |= BIT(bit); else val &= ~BIT(bit); > + ctcu_writel(drvdata, val, reg_offset); > + CS_LOCK(drvdata->base); > +} > + > +/* > + * __ctcu_set_etr_traceid: Set bit in the ATID register based on trace ID when enable is true. > + * Reset the bit of the ATID register based on trace ID when enable is false. > + * > + * @csdev: coresight_device struct related to the device > + * @traceid: trace ID of the source tracer. > + * @port_num: port number from TMC ETR sink. > + * @enable: True for set bit and false for reset bit. > + * > + * Returns 0 indicates success. Non-zero result means failure. > + */ > +static int __ctcu_set_etr_traceid(struct coresight_device *csdev, u8 traceid, int port_num, > + bool enable) > +{ > + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > + u32 atid_offset, reg_offset; > + u8 refcnt, bit; > + > + atid_offset = drvdata->atid_offset[port_num]; > + if (atid_offset == 0) > + return -EINVAL; > + > + bit = CTCU_ATID_REG_BIT(traceid); > + reg_offset = CTCU_ATID_REG_OFFSET(traceid, atid_offset); > + if (reg_offset - atid_offset > CTCU_ATID_REG_SIZE) > + return -EINVAL; > + > + guard(raw_spinlock_irqsave)(&drvdata->spin_lock); > + refcnt = drvdata->traceid_refcnt[port_num][traceid]; > + /* Only program the atid register when the refcnt value is 0 or 1 */ A normal trace source won't be enabled more than once (e.g., ETM). The only odd one out is the STM, which may be driven by multiple agents. So this refcounting looks necessary. > + if (enable && (++refcnt == 1)) > + ctcu_program_atid_register(drvdata, reg_offset, bit, enable); > + else if (!enable && (--refcnt == 0)) > + ctcu_program_atid_register(drvdata, reg_offset, bit, enable); minor nit: if ((enable && !refcount++) || (!enable && --refcount)) ctcu_program_atid_register(drvdata, reg_offset, bit, enable); Also, see my comment the bottom for "refcount" being u8 . > + > + drvdata->traceid_refcnt[port_num][traceid] = refcnt; > + > + return 0; > +} > + > +static int ctcu_get_active_port(struct coresight_device *sink, struct coresight_device *helper) > +{ > + int i; > + > + for (i = 0; i < sink->pdata->nr_outconns; ++i) { > + if (sink->pdata->out_conns[i]->dest_dev) > + return sink->pdata->out_conns[i]->dest_port; Don't we need to make sure it matches the helper ? What if there are multiple helpers ? e.g, a CATU connected to the ETR and CTCU ? Or even try the opposite ? i.e. search the helper and find the port matching the sink ? struct coresight_platform_data *pdata = helper->pdata; for (i = 0; i < pdata->nr_inconns; ++i) if (pdata->in_conns[i]->dest_dev == sink) return pdata->in_conns[i]->src_port; Not sure if that works with the helper device connection, James ? > + } > + > + return -EINVAL; > +} > + > +static int ctcu_set_etr_traceid(struct coresight_device *csdev, struct coresight_path *path, > + bool enable) > +{ > + struct coresight_device *sink = coresight_get_sink(path); > + u8 traceid = path->trace_id; > + int port_num; > + > + if ((sink == NULL) || !IS_VALID_CS_TRACE_ID(traceid)) { > + dev_err(&csdev->dev, "Invalid parameters\n"); > + return -EINVAL; > + } > + > + port_num = ctcu_get_active_port(sink, csdev); > + if (port_num < 0) > + return -EINVAL; > + > + dev_dbg(&csdev->dev, "traceid is %d\n", traceid); > + > + return __ctcu_set_etr_traceid(csdev, traceid, port_num, enable); > +} > + > +static int ctcu_enable(struct coresight_device *csdev, enum cs_mode mode, > + void *data) > +{ > + struct coresight_path *path = (struct coresight_path *)data; > + > + return ctcu_set_etr_traceid(csdev, path, true); > +} > + > +static int ctcu_disable(struct coresight_device *csdev, void *data) > +{ > + struct coresight_path *path = (struct coresight_path *)data; > + > + return ctcu_set_etr_traceid(csdev, path, false); > +} > + > +static const struct coresight_ops_helper ctcu_helper_ops = { > + .enable = ctcu_enable, > + .disable = ctcu_disable, > +}; > + > +static const struct coresight_ops ctcu_ops = { > + .helper_ops = &ctcu_helper_ops, > +}; > + > +static int ctcu_probe(struct platform_device *pdev) > +{ > + int i; > + void __iomem *base; > + struct device *dev = &pdev->dev; > + struct coresight_platform_data *pdata; > + struct ctcu_drvdata *drvdata; > + struct coresight_desc desc = { 0 }; > + const struct ctcu_config *cfgs; > + const struct ctcu_atid_config *atid_cfg; > + > + desc.name = coresight_alloc_device_name(&ctcu_devs, dev); > + if (!desc.name) > + return -ENOMEM; > + > + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > + if (!drvdata) > + return -ENOMEM; > + > + pdata = coresight_get_platform_data(dev); > + if (IS_ERR(pdata)) > + return PTR_ERR(pdata); > + dev->platform_data = pdata; > + > + base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); > + if (!base) > + return -ENOMEM; > + > + drvdata->apb_clk = coresight_get_enable_apb_pclk(dev); > + if (IS_ERR(drvdata->apb_clk)) > + return -ENODEV; > + > + cfgs = of_device_get_match_data(dev); > + if (cfgs) { > + if (cfgs->num_atid_config <= ATID_MAX_NUM) { > + for (i = 0; i < cfgs->num_atid_config; i++) { > + atid_cfg = &cfgs->atid_config[i]; > + drvdata->atid_offset[i] = atid_cfg->atid_offset; > + } > + } > + } > + > + drvdata->base = base; > + drvdata->dev = dev; > + platform_set_drvdata(pdev, drvdata); > + > + desc.type = CORESIGHT_DEV_TYPE_HELPER; > + desc.subtype.helper_subtype = CORESIGHT_DEV_SUBTYPE_HELPER_CTCU; > + desc.pdata = pdata; > + desc.dev = dev; > + desc.ops = &ctcu_ops; Please set the desc.access desc.access = CSDEV_ACCESS_IOMEM(drvdata->base); > + > + drvdata->csdev = coresight_register(&desc); > + if (IS_ERR(drvdata->csdev)) { > + if (!IS_ERR_OR_NULL(drvdata->apb_clk)) > + clk_put(drvdata->apb_clk); > + > + return PTR_ERR(drvdata->csdev); > + } > + > + return 0; > +} > + > +static void ctcu_remove(struct platform_device *pdev) > +{ > + struct ctcu_drvdata *drvdata = platform_get_drvdata(pdev); > + > + coresight_unregister(drvdata->csdev); > + if (!IS_ERR_OR_NULL(drvdata->apb_clk)) > + clk_put(drvdata->apb_clk); Why isn't the clock get/put at runtime via pm_runtime calls ? See coresight-replicator driver for e.g. > +} > + > +static const struct of_device_id ctcu_match[] = { > + {.compatible = "qcom,sa8775p-ctcu", .data = &sa8775p_cfgs}, > + {} > +}; > + > +static struct platform_driver ctcu_driver = { > + .probe = ctcu_probe, > + .remove = ctcu_remove, > + .driver = { > + .name = "coresight-ctcu", > + .of_match_table = ctcu_match, > + .suppress_bind_attrs = true, > + }, > +}; > +module_platform_driver(ctcu_driver); > + > +MODULE_LICENSE("GPL"); > +MODULE_DESCRIPTION("CoreSight TMC Control Unit driver"); > diff --git a/drivers/hwtracing/coresight/coresight-ctcu.h b/drivers/hwtracing/coresight/coresight-ctcu.h > new file mode 100644 > index 000000000000..9890c3da5ec8 > --- /dev/null > +++ b/drivers/hwtracing/coresight/coresight-ctcu.h > @@ -0,0 +1,24 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#ifndef _CORESIGHT_CTCU_H > +#define _CORESIGHT_CTCU_H > +#include "coresight-trace-id.h" > + > +/* Maximum number of supported sink devices for a single CTCU in current projects. */ > +#define ATID_MAX_NUM 2 > + > +struct ctcu_drvdata { > + void __iomem *base; > + struct clk *apb_clk; > + phys_addr_t pbase; Where is this used ? > + struct device *dev; > + struct coresight_device *csdev; > + raw_spinlock_t spin_lock; > + u32 atid_offset[ATID_MAX_NUM]; > + /* refcnt for each traceid of each sink */ > + u8 traceid_refcnt[ATID_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP]; Hopefully u8 is sufficient, but is it ? Why don't we check this in "enable" path to see if we are going to overflow ? > +}; > +#endif > diff --git a/include/linux/coresight.h b/include/linux/coresight.h > index 03d833a15726..55bb825d509e 100644 > --- a/include/linux/coresight.h > +++ b/include/linux/coresight.h > @@ -71,7 +71,8 @@ enum coresight_dev_subtype_source { > > enum coresight_dev_subtype_helper { > CORESIGHT_DEV_SUBTYPE_HELPER_CATU, > - CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI > + CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI, > + CORESIGHT_DEV_SUBTYPE_HELPER_CTCU, > }; > > /**

2 months, 1 week

Re: [PATCH v12 4/7] Coresight: Introduce a new struct coresight_path

by Suzuki K Poulose

On 17/02/2025 09:30, Jie Gan wrote: > Add 'struct coresight_path' to store the data that is needed by > coresight_enable_path/coresight_disable_path. The structure will be > transmitted to any required devices to enable related funcationalities. > > The trace_id will be allocated after the path is built. Consequently, > The ETM3x and ETM4x devices will directly read the trace_id from path > which result in etm_read_alloc_trace_id and etm4_read_alloc_trace_id > being deleted. > > Co-developed-by: James Clark <james.clark(a)linaro.org> > Signed-off-by: James Clark <james.clark(a)linaro.org> > Reviewed-by: James Clark <james.clark(a)linaro.org> > Signed-off-by: Jie Gan <quic_jiegan(a)quicinc.com> > --- Personally, I find this patch doing 3 things in one shot, which is complicated TBH for the patch review. 1. Introduce coresight_path 2. Move trace-id to coresight_path and allocate it after building the path. 3. Change enable/disable to accept the "coresight_path" Please do not repeat this in the future, split them accordingly. At the least we could split this patch into 1 and 2+3 > drivers/hwtracing/coresight/coresight-core.c | 106 +++++++++++++----- > drivers/hwtracing/coresight/coresight-dummy.c | 5 +- > .../hwtracing/coresight/coresight-etm-perf.c | 24 ++-- > .../hwtracing/coresight/coresight-etm-perf.h | 2 +- > drivers/hwtracing/coresight/coresight-etm.h | 1 - > .../coresight/coresight-etm3x-core.c | 54 ++------- > .../coresight/coresight-etm4x-core.c | 54 ++------- > drivers/hwtracing/coresight/coresight-etm4x.h | 1 - > drivers/hwtracing/coresight/coresight-priv.h | 12 +- > drivers/hwtracing/coresight/coresight-stm.c | 3 +- > drivers/hwtracing/coresight/coresight-sysfs.c | 17 ++- > drivers/hwtracing/coresight/coresight-tpdm.c | 3 +- > include/linux/coresight.h | 12 +- > 13 files changed, 140 insertions(+), 154 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c > index 6cad777757f3..182bfa2420cc 100644 > --- a/drivers/hwtracing/coresight/coresight-core.c > +++ b/drivers/hwtracing/coresight/coresight-core.c > @@ -76,14 +76,14 @@ struct coresight_device *coresight_get_percpu_sink(int cpu) > } > EXPORT_SYMBOL_GPL(coresight_get_percpu_sink); > > -static struct coresight_device *coresight_get_source(struct list_head *path) > +static struct coresight_device *coresight_get_source(struct coresight_path *path) > { > struct coresight_device *csdev; > > if (!path) > return NULL; > > - csdev = list_first_entry(path, struct coresight_node, link)->csdev; > + csdev = list_first_entry(path->path_list, struct coresight_node, link)->csdev; > if (!coresight_is_device_source(csdev)) > return NULL; > > @@ -332,12 +332,12 @@ static int coresight_enable_helper(struct coresight_device *csdev, > return helper_ops(csdev)->enable(csdev, mode, data); > } > > -static void coresight_disable_helper(struct coresight_device *csdev) > +static void coresight_disable_helper(struct coresight_device *csdev, void *data) > { > - helper_ops(csdev)->disable(csdev, NULL); > + helper_ops(csdev)->disable(csdev, data); > } > > -static void coresight_disable_helpers(struct coresight_device *csdev) > +static void coresight_disable_helpers(struct coresight_device *csdev, void *data) > { > int i; > struct coresight_device *helper; > @@ -345,7 +345,7 @@ static void coresight_disable_helpers(struct coresight_device *csdev) > for (i = 0; i < csdev->pdata->nr_outconns; ++i) { > helper = csdev->pdata->out_conns[i]->dest_dev; > if (helper && coresight_is_helper(helper)) > - coresight_disable_helper(helper); > + coresight_disable_helper(helper, data); > } > } > > @@ -362,7 +362,7 @@ static void coresight_disable_helpers(struct coresight_device *csdev) > void coresight_disable_source(struct coresight_device *csdev, void *data) > { > source_ops(csdev)->disable(csdev, data); > - coresight_disable_helpers(csdev); > + coresight_disable_helpers(csdev, NULL); > } > EXPORT_SYMBOL_GPL(coresight_disable_source); > > @@ -371,16 +371,16 @@ EXPORT_SYMBOL_GPL(coresight_disable_source); > * @nd in the list. If @nd is NULL, all the components, except the SOURCE are > * disabled. > */ > -static void coresight_disable_path_from(struct list_head *path, > +static void coresight_disable_path_from(struct coresight_path *path, > struct coresight_node *nd) > { > u32 type; > struct coresight_device *csdev, *parent, *child; > > if (!nd) > - nd = list_first_entry(path, struct coresight_node, link); > + nd = list_first_entry(path->path_list, struct coresight_node, link); > > - list_for_each_entry_continue(nd, path, link) { > + list_for_each_entry_continue(nd, path->path_list, link) { > csdev = nd->csdev; > type = csdev->type; > > @@ -418,11 +418,11 @@ static void coresight_disable_path_from(struct list_head *path, > } > > /* Disable all helpers adjacent along the path last */ > - coresight_disable_helpers(csdev); > + coresight_disable_helpers(csdev, path); > } > } > > -void coresight_disable_path(struct list_head *path) > +void coresight_disable_path(struct coresight_path *path) > { > coresight_disable_path_from(path, NULL); > } > @@ -447,7 +447,7 @@ static int coresight_enable_helpers(struct coresight_device *csdev, > return 0; > } > > -int coresight_enable_path(struct list_head *path, enum cs_mode mode, > +int coresight_enable_path(struct coresight_path *path, enum cs_mode mode, > void *sink_data) > { > int ret = 0; > @@ -457,12 +457,12 @@ int coresight_enable_path(struct list_head *path, enum cs_mode mode, > struct coresight_device *source; > > source = coresight_get_source(path); > - list_for_each_entry_reverse(nd, path, link) { > + list_for_each_entry_reverse(nd, path->path_list, link) { > csdev = nd->csdev; > type = csdev->type; > > /* Enable all helpers adjacent to the path first */ > - ret = coresight_enable_helpers(csdev, mode, sink_data); > + ret = coresight_enable_helpers(csdev, mode, path); > if (ret) > goto err; > /* > @@ -510,20 +510,21 @@ int coresight_enable_path(struct list_head *path, enum cs_mode mode, > goto out; > } > > -struct coresight_device *coresight_get_sink(struct list_head *path) > +struct coresight_device *coresight_get_sink(struct coresight_path *path) > { > struct coresight_device *csdev; > > if (!path) > return NULL; > > - csdev = list_last_entry(path, struct coresight_node, link)->csdev; > + csdev = list_last_entry(path->path_list, struct coresight_node, link)->csdev; > if (csdev->type != CORESIGHT_DEV_TYPE_SINK && > csdev->type != CORESIGHT_DEV_TYPE_LINKSINK) > return NULL; > > return csdev; > } > +EXPORT_SYMBOL_GPL(coresight_get_sink); > > u32 coresight_get_sink_id(struct coresight_device *csdev) > { > @@ -654,6 +655,51 @@ static void coresight_drop_device(struct coresight_device *csdev) > } > } > > +/* > + * Links or sources will read their existing or alloc a trace ID, if their ID > + * callback is set. > + */ Please could we document the return value conditions here ? > +static int coresight_get_trace_id(struct coresight_device *csdev, > + enum cs_mode mode, > + struct coresight_device *sink) > +{ > + if (csdev->type == CORESIGHT_DEV_TYPE_LINK && link_ops(csdev)->trace_id) > + return link_ops(csdev)->trace_id(csdev, mode, sink); > + > + if (csdev->type == CORESIGHT_DEV_TYPE_SOURCE && source_ops(csdev)->trace_id) > + return source_ops(csdev)->trace_id(csdev, mode, sink); > + > + return 0; > +} > + > +/* > + * Call this after creating the path and before enabling it. This leaves > + * the trace ID set on the path and returns the ID, or an error if it > + * couldn't be assigned. > + */ > +int coresight_path_assign_trace_id(struct coresight_path *path, > + enum cs_mode mode) > +{ > + struct coresight_device *sink = coresight_get_sink(path); > + struct coresight_node *nd; > + int ret; Might be better to rename this as "trace_id" ? As we return the trace id not a status of whether it was allocated or not. Or drop it completely and return path->trace_id, below when we succeed. Or it could even be a void, as the caller can check IS_VALID(path->trace_id) > + > + list_for_each_entry(nd, path->path_list, link) { > + /* Assign a trace ID to the path for the first device that wants to do it */ > + ret = coresight_get_trace_id(nd->csdev, mode, sink); > + > + /* > + * 0 in this context is that it didn't want to assign so keep searching. > + * Non 0 is either success or fail, return it either way. > + */ > + if (ret != 0) { > + path->trace_id = ret; > + return ret; > + } > + } > + return 0; > +} > + > /** > * _coresight_build_path - recursively build a path from a @csdev to a sink. > * @csdev: The device to start from. > @@ -669,7 +715,7 @@ static void coresight_drop_device(struct coresight_device *csdev) > static int _coresight_build_path(struct coresight_device *csdev, > struct coresight_device *source, > struct coresight_device *sink, > - struct list_head *path) > + struct coresight_path *path) > { > int i, ret; > bool found = false; > @@ -722,28 +768,37 @@ static int _coresight_build_path(struct coresight_device *csdev, > return -ENOMEM; > > node->csdev = csdev; > - list_add(&node->link, path); > + list_add(&node->link, path->path_list); > > return 0; > } > > -struct list_head *coresight_build_path(struct coresight_device *source, > +struct coresight_path *coresight_build_path(struct coresight_device *source, > struct coresight_device *sink) > { > - struct list_head *path; > + struct coresight_path *path; > + struct list_head *path_list; > int rc; > > if (!sink) > return ERR_PTR(-EINVAL); > > - path = kzalloc(sizeof(struct list_head), GFP_KERNEL); > + path = kzalloc(sizeof(struct coresight_path), GFP_KERNEL); > if (!path) > return ERR_PTR(-ENOMEM); > > - INIT_LIST_HEAD(path); > + path_list = kzalloc(sizeof(struct list_head), GFP_KERNEL); > + if (!path_list) { > + kfree(path); > + return ERR_PTR(-ENOMEM); > + } > + > + INIT_LIST_HEAD(path_list); > + path->path_list = path_list; > > rc = _coresight_build_path(source, source, sink, path); > if (rc) { > + kfree(path_list); > kfree(path); > return ERR_PTR(rc); > } > @@ -758,12 +813,12 @@ struct list_head *coresight_build_path(struct coresight_device *source, > * Go through all the elements of a path and 1) removed it from the list and > * 2) free the memory allocated for each node. > */ > -void coresight_release_path(struct list_head *path) > +void coresight_release_path(struct coresight_path *path) > { > struct coresight_device *csdev; > struct coresight_node *nd, *next; > > - list_for_each_entry_safe(nd, next, path, link) { > + list_for_each_entry_safe(nd, next, path->path_list, link) { > csdev = nd->csdev; > > coresight_drop_device(csdev); > @@ -771,6 +826,7 @@ void coresight_release_path(struct list_head *path) > kfree(nd); > } > > + kfree(path->path_list); > kfree(path); > } > > diff --git a/drivers/hwtracing/coresight/coresight-dummy.c b/drivers/hwtracing/coresight/coresight-dummy.c > index c47f0382b943..d9a811d44885 100644 > --- a/drivers/hwtracing/coresight/coresight-dummy.c > +++ b/drivers/hwtracing/coresight/coresight-dummy.c > @@ -22,9 +22,8 @@ struct dummy_drvdata { > DEFINE_CORESIGHT_DEVLIST(source_devs, "dummy_source"); > DEFINE_CORESIGHT_DEVLIST(sink_devs, "dummy_sink"); > > -static int dummy_source_enable(struct coresight_device *csdev, > - struct perf_event *event, enum cs_mode mode, > - __maybe_unused struct coresight_trace_id_map *id_map) > +static int dummy_source_enable(struct coresight_device *csdev, struct perf_event *event, > + enum cs_mode mode, struct coresight_path *path) > { > if (!coresight_take_mode(csdev, mode)) > return -EBUSY; > diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c > index ad6a8f4b70b6..ebdcf56b7463 100644 > --- a/drivers/hwtracing/coresight/coresight-etm-perf.c > +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c > @@ -136,13 +136,13 @@ static const struct attribute_group *etm_pmu_attr_groups[] = { > NULL, > }; > > -static inline struct list_head ** > +static inline struct coresight_path ** > etm_event_cpu_path_ptr(struct etm_event_data *data, int cpu) > { > return per_cpu_ptr(data->path, cpu); > } > > -static inline struct list_head * > +static inline struct coresight_path * > etm_event_cpu_path(struct etm_event_data *data, int cpu) > { > return *etm_event_cpu_path_ptr(data, cpu); > @@ -226,7 +226,7 @@ static void free_event_data(struct work_struct *work) > cscfg_deactivate_config(event_data->cfg_hash); > > for_each_cpu(cpu, mask) { > - struct list_head **ppath; > + struct coresight_path **ppath; > > ppath = etm_event_cpu_path_ptr(event_data, cpu); > if (!(IS_ERR_OR_NULL(*ppath))) { > @@ -276,7 +276,7 @@ static void *alloc_event_data(int cpu) > * unused memory when dealing with single CPU trace scenarios is small > * compared to the cost of searching through an optimized array. > */ > - event_data->path = alloc_percpu(struct list_head *); > + event_data->path = alloc_percpu(struct coresight_path *); > > if (!event_data->path) { > kfree(event_data); > @@ -352,7 +352,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, > * CPUs, we can handle it and fail the session. > */ > for_each_cpu(cpu, mask) { > - struct list_head *path; > + struct coresight_path *path; > struct coresight_device *csdev; > > csdev = per_cpu(csdev_src, cpu); > @@ -407,7 +407,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, > } > > /* ensure we can allocate a trace ID for this CPU */ > - trace_id = coresight_trace_id_get_cpu_id_map(cpu, &sink->perf_sink_id_map); > + trace_id = coresight_path_assign_trace_id(path, CS_MODE_PERF); > if (!IS_VALID_CS_TRACE_ID(trace_id)) { > cpumask_clear_cpu(cpu, mask); > coresight_release_path(path); > @@ -458,9 +458,8 @@ static void etm_event_start(struct perf_event *event, int flags) > struct etm_ctxt *ctxt = this_cpu_ptr(&etm_ctxt); > struct perf_output_handle *handle = &ctxt->handle; > struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu); > - struct list_head *path; > + struct coresight_path *path; > u64 hw_id; > - u8 trace_id; > > if (!csdev) > goto fail; > @@ -503,8 +502,7 @@ static void etm_event_start(struct perf_event *event, int flags) > goto fail_end_stop; > > /* Finally enable the tracer */ > - if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF, > - &sink->perf_sink_id_map)) > + if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF, path)) > goto fail_disable_path; > > /* > @@ -514,13 +512,11 @@ static void etm_event_start(struct perf_event *event, int flags) > if (!cpumask_test_cpu(cpu, &event_data->aux_hwid_done)) { > cpumask_set_cpu(cpu, &event_data->aux_hwid_done); > > - trace_id = coresight_trace_id_read_cpu_id_map(cpu, &sink->perf_sink_id_map); > - > hw_id = FIELD_PREP(CS_AUX_HW_ID_MAJOR_VERSION_MASK, > CS_AUX_HW_ID_MAJOR_VERSION); > hw_id |= FIELD_PREP(CS_AUX_HW_ID_MINOR_VERSION_MASK, > CS_AUX_HW_ID_MINOR_VERSION); > - hw_id |= FIELD_PREP(CS_AUX_HW_ID_TRACE_ID_MASK, trace_id); > + hw_id |= FIELD_PREP(CS_AUX_HW_ID_TRACE_ID_MASK, path->trace_id); > hw_id |= FIELD_PREP(CS_AUX_HW_ID_SINK_ID_MASK, coresight_get_sink_id(sink)); > > perf_report_aux_output_id(event, hw_id); > @@ -558,7 +554,7 @@ static void etm_event_stop(struct perf_event *event, int mode) > struct etm_ctxt *ctxt = this_cpu_ptr(&etm_ctxt); > struct perf_output_handle *handle = &ctxt->handle; > struct etm_event_data *event_data; > - struct list_head *path; > + struct coresight_path *path; > > /* > * If we still have access to the event_data via handle, > diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h b/drivers/hwtracing/coresight/coresight-etm-perf.h > index 744531158d6b..5febbcdb8696 100644 > --- a/drivers/hwtracing/coresight/coresight-etm-perf.h > +++ b/drivers/hwtracing/coresight/coresight-etm-perf.h > @@ -59,7 +59,7 @@ struct etm_event_data { > cpumask_t aux_hwid_done; > void *snk_config; > u32 cfg_hash; > - struct list_head * __percpu *path; > + struct coresight_path * __percpu *path; > }; > > int etm_perf_symlink(struct coresight_device *csdev, bool link); > diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h > index e02c3ea972c9..171f1384f7c0 100644 > --- a/drivers/hwtracing/coresight/coresight-etm.h > +++ b/drivers/hwtracing/coresight/coresight-etm.h > @@ -284,6 +284,5 @@ extern const struct attribute_group *coresight_etm_groups[]; > void etm_set_default(struct etm_config *config); > void etm_config_trace_mode(struct etm_config *config); > struct etm_config *get_etm_config(struct etm_drvdata *drvdata); > -int etm_read_alloc_trace_id(struct etm_drvdata *drvdata); > void etm_release_trace_id(struct etm_drvdata *drvdata); > #endif > diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c > index a38e72ef8e79..cb8a30a3b48e 100644 > --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c > @@ -455,26 +455,6 @@ static int etm_cpu_id(struct coresight_device *csdev) > return drvdata->cpu; > } > > -int etm_read_alloc_trace_id(struct etm_drvdata *drvdata) > -{ > - int trace_id; > - > - /* > - * This will allocate a trace ID to the cpu, > - * or return the one currently allocated. > - * > - * trace id function has its own lock > - */ > - trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu); > - if (IS_VALID_CS_TRACE_ID(trace_id)) > - drvdata->traceid = (u8)trace_id; > - else > - dev_err(&drvdata->csdev->dev, > - "Failed to allocate trace ID for %s on CPU%d\n", > - dev_name(&drvdata->csdev->dev), drvdata->cpu); > - return trace_id; > -} > - > void etm_release_trace_id(struct etm_drvdata *drvdata) > { > coresight_trace_id_put_cpu_id(drvdata->cpu); > @@ -482,38 +462,22 @@ void etm_release_trace_id(struct etm_drvdata *drvdata) > > static int etm_enable_perf(struct coresight_device *csdev, > struct perf_event *event, > - struct coresight_trace_id_map *id_map) > + struct coresight_path *path) > { > struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > - int trace_id; > > if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) > return -EINVAL; > > /* Configure the tracer based on the session's specifics */ > etm_parse_event_config(drvdata, event); > - > - /* > - * perf allocates cpu ids as part of _setup_aux() - device needs to use > - * the allocated ID. This reads the current version without allocation. > - * > - * This does not use the trace id lock to prevent lock_dep issues > - * with perf locks - we know the ID cannot change until perf shuts down > - * the session > - */ > - trace_id = coresight_trace_id_read_cpu_id_map(drvdata->cpu, id_map); > - if (!IS_VALID_CS_TRACE_ID(trace_id)) { > - dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n", > - dev_name(&drvdata->csdev->dev), drvdata->cpu); > - return -EINVAL; > - } > - drvdata->traceid = (u8)trace_id; > + drvdata->traceid = path->trace_id; > > /* And enable it */ > return etm_enable_hw(drvdata); > } > > -static int etm_enable_sysfs(struct coresight_device *csdev) > +static int etm_enable_sysfs(struct coresight_device *csdev, struct coresight_path *path) > { > struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > struct etm_enable_arg arg = { }; > @@ -521,10 +485,7 @@ static int etm_enable_sysfs(struct coresight_device *csdev) > > spin_lock(&drvdata->spinlock); > > - /* sysfs needs to allocate and set a trace ID */ > - ret = etm_read_alloc_trace_id(drvdata); > - if (ret < 0) > - goto unlock_enable_sysfs; > + drvdata->traceid = path->trace_id; > > /* > * Configure the ETM only if the CPU is online. If it isn't online > @@ -545,7 +506,6 @@ static int etm_enable_sysfs(struct coresight_device *csdev) > if (ret) > etm_release_trace_id(drvdata); > > -unlock_enable_sysfs: > spin_unlock(&drvdata->spinlock); > > if (!ret) > @@ -554,7 +514,7 @@ static int etm_enable_sysfs(struct coresight_device *csdev) > } > > static int etm_enable(struct coresight_device *csdev, struct perf_event *event, > - enum cs_mode mode, struct coresight_trace_id_map *id_map) > + enum cs_mode mode, struct coresight_path *path) > { > int ret; > struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > @@ -566,10 +526,10 @@ static int etm_enable(struct coresight_device *csdev, struct perf_event *event, > > switch (mode) { > case CS_MODE_SYSFS: > - ret = etm_enable_sysfs(csdev); > + ret = etm_enable_sysfs(csdev, path); > break; > case CS_MODE_PERF: > - ret = etm_enable_perf(csdev, event, id_map); > + ret = etm_enable_perf(csdev, event, path); > break; > default: > ret = -EINVAL; > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 1a993d5380e7..3d0fc25085ea 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -233,25 +233,6 @@ static int etm4_cpu_id(struct coresight_device *csdev) > return drvdata->cpu; > } > > -int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata) > -{ > - int trace_id; > - > - /* > - * This will allocate a trace ID to the cpu, > - * or return the one currently allocated. > - * The trace id function has its own lock > - */ > - trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu); > - if (IS_VALID_CS_TRACE_ID(trace_id)) > - drvdata->trcid = (u8)trace_id; > - else > - dev_err(&drvdata->csdev->dev, > - "Failed to allocate trace ID for %s on CPU%d\n", > - dev_name(&drvdata->csdev->dev), drvdata->cpu); > - return trace_id; > -} > - > void etm4_release_trace_id(struct etmv4_drvdata *drvdata) > { > coresight_trace_id_put_cpu_id(drvdata->cpu); > @@ -788,9 +769,9 @@ static int etm4_parse_event_config(struct coresight_device *csdev, > > static int etm4_enable_perf(struct coresight_device *csdev, > struct perf_event *event, > - struct coresight_trace_id_map *id_map) > + struct coresight_path *path) > { > - int ret = 0, trace_id; > + int ret = 0; > struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > > if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) { > @@ -803,22 +784,7 @@ static int etm4_enable_perf(struct coresight_device *csdev, > if (ret) > goto out; > > - /* > - * perf allocates cpu ids as part of _setup_aux() - device needs to use > - * the allocated ID. This reads the current version without allocation. > - * > - * This does not use the trace id lock to prevent lock_dep issues > - * with perf locks - we know the ID cannot change until perf shuts down > - * the session > - */ > - trace_id = coresight_trace_id_read_cpu_id_map(drvdata->cpu, id_map); > - if (!IS_VALID_CS_TRACE_ID(trace_id)) { > - dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n", > - dev_name(&drvdata->csdev->dev), drvdata->cpu); > - ret = -EINVAL; > - goto out; > - } > - drvdata->trcid = (u8)trace_id; > + drvdata->trcid = path->trace_id; > > /* And enable it */ > ret = etm4_enable_hw(drvdata); > @@ -827,7 +793,7 @@ static int etm4_enable_perf(struct coresight_device *csdev, > return ret; > } > > -static int etm4_enable_sysfs(struct coresight_device *csdev) > +static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_path *path) > { > struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > struct etm4_enable_arg arg = { }; > @@ -844,10 +810,7 @@ static int etm4_enable_sysfs(struct coresight_device *csdev) > > spin_lock(&drvdata->spinlock); > > - /* sysfs needs to read and allocate a trace ID */ > - ret = etm4_read_alloc_trace_id(drvdata); > - if (ret < 0) > - goto unlock_sysfs_enable; > + drvdata->trcid = path->trace_id; > > /* > * Executing etm4_enable_hw on the cpu whose ETM is being enabled > @@ -864,7 +827,6 @@ static int etm4_enable_sysfs(struct coresight_device *csdev) > if (ret) > etm4_release_trace_id(drvdata); > > -unlock_sysfs_enable: > spin_unlock(&drvdata->spinlock); > > if (!ret) > @@ -873,7 +835,7 @@ static int etm4_enable_sysfs(struct coresight_device *csdev) > } > > static int etm4_enable(struct coresight_device *csdev, struct perf_event *event, > - enum cs_mode mode, struct coresight_trace_id_map *id_map) > + enum cs_mode mode, struct coresight_path *path) > { > int ret; > > @@ -884,10 +846,10 @@ static int etm4_enable(struct coresight_device *csdev, struct perf_event *event, > > switch (mode) { > case CS_MODE_SYSFS: > - ret = etm4_enable_sysfs(csdev); > + ret = etm4_enable_sysfs(csdev, path); > break; > case CS_MODE_PERF: > - ret = etm4_enable_perf(csdev, event, id_map); > + ret = etm4_enable_perf(csdev, event, path); > break; > default: > ret = -EINVAL; > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index 1119762b5cec..2b92de17b5a2 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -1066,6 +1066,5 @@ static inline bool etm4x_is_ete(struct etmv4_drvdata *drvdata) > return drvdata->arch >= ETM_ARCH_ETE; > } > > -int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata); > void etm4_release_trace_id(struct etmv4_drvdata *drvdata); > #endif > diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h > index 76403530f33e..c10dd3643854 100644 > --- a/drivers/hwtracing/coresight/coresight-priv.h > +++ b/drivers/hwtracing/coresight/coresight-priv.h > @@ -132,16 +132,16 @@ static inline void CS_UNLOCK(void __iomem *addr) > } while (0); > } > > -void coresight_disable_path(struct list_head *path); > -int coresight_enable_path(struct list_head *path, enum cs_mode mode, > +void coresight_disable_path(struct coresight_path *path); > +int coresight_enable_path(struct coresight_path *path, enum cs_mode mode, > void *sink_data); > -struct coresight_device *coresight_get_sink(struct list_head *path); > +struct coresight_device *coresight_get_sink(struct coresight_path *path); > struct coresight_device *coresight_get_sink_by_id(u32 id); > struct coresight_device * > coresight_find_default_sink(struct coresight_device *csdev); > -struct list_head *coresight_build_path(struct coresight_device *csdev, > +struct coresight_path *coresight_build_path(struct coresight_device *csdev, > struct coresight_device *sink); > -void coresight_release_path(struct list_head *path); > +void coresight_release_path(struct coresight_path *path); > int coresight_add_sysfs_link(struct coresight_sysfs_link *info); > void coresight_remove_sysfs_link(struct coresight_sysfs_link *info); > int coresight_create_conns_sysfs_group(struct coresight_device *csdev); > @@ -152,6 +152,8 @@ int coresight_make_links(struct coresight_device *orig, > void coresight_remove_links(struct coresight_device *orig, > struct coresight_connection *conn); > u32 coresight_get_sink_id(struct coresight_device *csdev); > +int coresight_path_assign_trace_id(struct coresight_path *path, > + enum cs_mode mode); > > #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X) > extern int etm_readl_cp14(u32 off, unsigned int *val); > diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c > index 64fcfa916562..0d4a9d325df4 100644 > --- a/drivers/hwtracing/coresight/coresight-stm.c > +++ b/drivers/hwtracing/coresight/coresight-stm.c > @@ -194,8 +194,7 @@ static void stm_enable_hw(struct stm_drvdata *drvdata) > } > > static int stm_enable(struct coresight_device *csdev, struct perf_event *event, > - enum cs_mode mode, > - __maybe_unused struct coresight_trace_id_map *trace_id) > + enum cs_mode mode, struct coresight_path *path) > { > struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > > diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/hwtracing/coresight/coresight-sysfs.c > index a01c9e54e2ed..c2b0a1f59d1a 100644 > --- a/drivers/hwtracing/coresight/coresight-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-sysfs.c > @@ -22,7 +22,7 @@ static DEFINE_IDR(path_idr); > * When operating Coresight drivers from the sysFS interface, only a single > * path can exist from a tracer (associated to a CPU) to a sink. > */ > -static DEFINE_PER_CPU(struct list_head *, tracer_path); > +static DEFINE_PER_CPU(struct coresight_path *, tracer_path); > > ssize_t coresight_simple_show_pair(struct device *_dev, > struct device_attribute *attr, char *buf) > @@ -53,7 +53,8 @@ ssize_t coresight_simple_show32(struct device *_dev, > EXPORT_SYMBOL_GPL(coresight_simple_show32); > > static int coresight_enable_source_sysfs(struct coresight_device *csdev, > - enum cs_mode mode, void *data) > + enum cs_mode mode, > + struct coresight_path *path) > { > int ret; > > @@ -64,7 +65,7 @@ static int coresight_enable_source_sysfs(struct coresight_device *csdev, > */ > lockdep_assert_held(&coresight_mutex); > if (coresight_get_mode(csdev) != CS_MODE_SYSFS) { > - ret = source_ops(csdev)->enable(csdev, data, mode, NULL); > + ret = source_ops(csdev)->enable(csdev, NULL, mode, path); > if (ret) > return ret; > } > @@ -167,7 +168,7 @@ int coresight_enable_sysfs(struct coresight_device *csdev) > { > int cpu, ret = 0; > struct coresight_device *sink; > - struct list_head *path; > + struct coresight_path *path; > enum coresight_dev_subtype_source subtype; > u32 hash; > > @@ -209,11 +210,15 @@ int coresight_enable_sysfs(struct coresight_device *csdev) > goto out; > } > > + ret = coresight_path_assign_trace_id(path, CS_MODE_SYSFS); > + if (ret < 0) > + goto err_path; > + > ret = coresight_enable_path(path, CS_MODE_SYSFS, NULL); > if (ret) > goto err_path; > > - ret = coresight_enable_source_sysfs(csdev, CS_MODE_SYSFS, NULL); > + ret = coresight_enable_source_sysfs(csdev, CS_MODE_SYSFS, path); > if (ret) > goto err_source; > > @@ -262,7 +267,7 @@ EXPORT_SYMBOL_GPL(coresight_enable_sysfs); > void coresight_disable_sysfs(struct coresight_device *csdev) > { > int cpu, ret; > - struct list_head *path = NULL; > + struct coresight_path *path = NULL; > u32 hash; > > mutex_lock(&coresight_mutex); > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c > index c38f9701665e..f0880a62028f 100644 > --- a/drivers/hwtracing/coresight/coresight-tpdm.c > +++ b/drivers/hwtracing/coresight/coresight-tpdm.c > @@ -439,8 +439,7 @@ static void __tpdm_enable(struct tpdm_drvdata *drvdata) > } > > static int tpdm_enable(struct coresight_device *csdev, struct perf_event *event, > - enum cs_mode mode, > - __maybe_unused struct coresight_trace_id_map *id_map) > + enum cs_mode mode, struct coresight_path *path) > { > struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > > diff --git a/include/linux/coresight.h b/include/linux/coresight.h > index 70407d61262e..03d833a15726 100644 > --- a/include/linux/coresight.h > +++ b/include/linux/coresight.h > @@ -329,6 +329,16 @@ static struct coresight_dev_list (var) = { \ > > #define to_coresight_device(d) container_of(d, struct coresight_device, dev) > > +/** > + * struct coresight_path - data needed by enable/disable path > + * @path: path from source to sink. > + * @trace_id: trace_id of the whole path. > + */ > +struct coresight_path { > + struct list_head *path_list; Minor nit: We could do struct list_head path_list; to avoid allocating/freeing the head node without multiple kzalloc/kfree Suzuki > + u8 trace_id; > +}; > + > enum cs_mode { > CS_MODE_DISABLED, > CS_MODE_SYSFS, > @@ -393,7 +403,7 @@ struct coresight_ops_link { > struct coresight_ops_source { > int (*cpu_id)(struct coresight_device *csdev); > int (*enable)(struct coresight_device *csdev, struct perf_event *event, > - enum cs_mode mode, struct coresight_trace_id_map *id_map); > + enum cs_mode mode, struct coresight_path *path); > void (*disable)(struct coresight_device *csdev, > struct perf_event *event); > int (*trace_id)(struct coresight_device *csdev, enum cs_mode mode,

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CoreSight February 2025