CoreSight May 2020

coresight@lists.linaro.org

14 participants
25 discussions

[RFC PATCH v3 0/6] Allow CoreSight to specify and select default sink

by Mike Leach

This patchset provides a proposed infrastructure to allow for the automatic selection of a sink during CoreSight tracing operations. Currently starting tracing using perf requires a sink selection on the command line:- sudo ./perf record -e cs_etm/@tmc_etr0/ --per-thread uname -a After this set the infrastructure will be able to select a default sink:- sudo ./perf record -e cs_etm// --per-thread uname -a This matches with the default operation provided with perf and intelpt. Where no sink is specified at the start of a trace session, the CoreSight system will walk the connection graph from the source ETM, to find a suitable sink using the first encountered highest priority device. The CoreSight infrastructure is updated to define sink sub_types to differentiate between sinks with built in buffers (ETB / ETF) - BUFFER type , and those that use system memory (ETR) - SYSMEM - types. SYSMEM types are considered higher priority. When two sinks are found of equal priority, then the closest sink to the source in terms of connection nodes is chosen. The automatic sink selection will also operate if an ETM is enabled using sysfs commands, and no sink is currently enabled. Applies to Linux coresight/next branch Changes since v2: 1) changed from explicit set priority value to using the sink_subtype in the coresight_device as the selection priority value. 2) Added in search depth to the find algorithm to ensure that the closest sink to the source with the highest priority is chosen. 3) A default sink is cached with the source when the search is first undertaken, reducing the need for repeat searches for a given source. Changes since v1: 1) Dropped the device-tree attribute labelling of sinks for selection and implemented the priority schema preferring first encountered ETR, after mailing list discussions. 2) Added in sysfs support for auto sink selection. Mike Leach (6): coresight: Fix comment in main header file. coresight: Add default sink selection to CoreSight base coresight: tmc: Update sink types for default selection. coresight: etm: perf: Add default sink selection to etm perf coresight: sysfs: Allow select default sink on source enable. perf: cs-etm: Allow no CoreSight sink to be specified on command line .../hwtracing/coresight/coresight-etm-perf.c | 17 +- drivers/hwtracing/coresight/coresight-priv.h | 2 + drivers/hwtracing/coresight/coresight-tmc.c | 3 +- drivers/hwtracing/coresight/coresight.c | 148 +++++++++++++++++- include/linux/coresight.h | 6 +- tools/perf/arch/arm/util/cs-etm.c | 6 +- 6 files changed, 172 insertions(+), 10 deletions(-) -- 2.17.1

6 years, 4 months

[PATCHv2 0/4] Add support for replicators which loses context on clock removal

by Sai Prakash Ranjan

This series is mainly to add support for replicators which lose context on removing AMBA clock like on SC7180 SoC where replicator in AOSS domain loses context. Patch 1 and 2 are minor cleanups to use macros. Patch 3 and 4 adds support for replicators which loses context on removing AMBA clock. Previous version is here - https://lore.kernel.org/patchwork/patch/1239923/ More discussion is found here - https://lore.kernel.org/patchwork/patch/1231182/ There were no patch 1 and patch 2 in v1. Sai Prakash Ranjan (4): coresight: replicator: Use CS_AMBA_ID macro for id table coresight: catu: Use CS_AMBA_ID macro for id table coresight: replicator: Reset replicator if context is lost dt-bindings: arm: coresight: Add optional property to replicators .../devicetree/bindings/arm/coresight.txt | 6 ++ drivers/hwtracing/coresight/coresight-catu.c | 5 +- .../coresight/coresight-replicator.c | 66 +++++++++++-------- 3 files changed, 46 insertions(+), 31 deletions(-) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

6 years, 4 months

libopencsd in debian: new git repos and 0.14.1-1 now in 'testing'

by Wookey

I updated debian to 0.14.1. I am also trying out a dgit-based workflow for the package, so the package uploaded to the archive is also available as https://browse.dgit.debian.org/libopencsd.git/ You can pull down the latest version with: From the archive, as tarball+diff: apt From the archive, as git repo: dgit From a URL, as tarball+diff: dget None of this should make much difference to any of you, but this does make it much easier for people used to a git workflow to contribute to the debian package if need be. It should also mean that the debian package matches the git history of upstream much more closely. In case anyone cares I have chosen the dgit 'merge' workflow about of about 11 possible schemes (https://wiki.debian.org/GitPackagingSurvey) (debian never has just one way of doing anything :-) For those not familiar: dgit is a tool to provide bi-direcitonal translation between the debian archive format (.dsc, tarball and debian diff) and git repositories. Package maintainers can continue to use either system and the git/tarball views of the world are synchonised at upload. I've also added a development view of the package on debian's gitlab instance: https://salsa.debian.org/wookey/libopencsd I would prefer patches as patches in bug reports, but I have left the 'merge request' thingy turned on so I guess people can use that too (but I don't know how to drive it yet :-). I reserve the right to give up with all this complicated fancy stuff and go back to uploading debianised tarballs, which is quick, simple and I understand it properly :-) but this stuff should make things a little more accessible. I'd be interested to hear if anyone actually finds it useful (nearly everyone on this list will be working with upstream primarily so rarely/never fiddle with the debian packages, I presume). ----- Forwarded message from Debian testing watch <noreply(a)release.debian.org> ----- Date: Tue, 19 May 2020 04:39:06 +0000 From: Debian testing watch <noreply(a)release.debian.org> To: libopencsd(a)packages.debian.org Subject: libopencsd 0.14.1-1 MIGRATED to testing FYI: The status of the libopencsd source package in Debian's testing distribution has changed. Previous version: 0.14.0-1 Current version: 0.14.1-1 -- This email is automatically generated once a day. As the installation of new packages into testing happens multiple times a day you will receive later changes on the next day. See https://release.debian.org/testing-watch/ for more information. ----- End forwarded message ----- Wookey -- Principal hats: Linaro, Debian, Wookware, ARM http://wookware.org/

6 years, 4 months

Re: Coresight enablement on NXP ARMv8 device

by Mathieu Poirier

Hi Poonam, Please CC the coresight mailing list (as I did) when asking questions - there is a lot of well informed people on there that can also help you. On Thu, 23 Jan 2020 at 22:33, Poonam Aggrwal <poonam.aggrwal(a)nxp.com> wrote: > > Hello Mathieu > > > > Greetings! > > > > I have started to take a look at the Linux coresight framework, and get this enabled on a NXP ARMv8 device. > > > > Can you share some documentation on the configs required to be enabled and the device tree nodes? For V8 we have to reference implementation - ARM Juno and the dragonboard 410c. I highly recommend purchasing the latter (because it is very cheap) in order to get an understanding of what a working coresight system look like. It is much easier to start from a working example than nothing at all. Other than that the coresight bindings [1] are full of good examples. I would also have a look at the DT for Juno [2] and the dragonboard[3]. The HOWTO.md [4] on github is a really good starting point when you'll get to test things out. [1]. https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bin… [2]. https://elixir.bootlin.com/linux/latest/source/arch/arm64/boot/dts/arm/juno… [3]. https://elixir.bootlin.com/linux/latest/source/arch/arm64/boot/dts/qcom/msm… [4]. https://github.com/Linaro/OpenCSD/blob/master/HOWTO.md > > To start I am looking to enable the ARMv8 ETM tracing. Before going further I advise you to look at the source and sink configuration on your platform. Up to now we've been working with configurations where sources share a single sink (N:1 topology). Newer SoC will have one source per sink (1:1 topology). At this time only the former is supported by the framework. Supporting 1:1 topologies would require a fair amount of refactoring, something we haven't had the opportunity to do for lack of HW platform to work with. Regards, Mathieu > > Is there a reference which I can check in Linux for device tree and config. > > > > Many Thanks > > Poonam

6 years, 4 months

[PATCH] coresight: etm4x: Add support to disable trace unit power up

by Sai Prakash Ranjan

From: Tingwei Zhang <tingwei(a)codeaurora.org> On some Qualcomm Technologies Inc. SoCs like SC7180, there exists a hardware errata where the APSS (Application Processor SubSystem)/CPU watchdog counter is stopped when ETM register TRCPDCR.PU=1. Since the ETMs share the same power domain as that of respective CPU cores, they are powered on when the CPU core is powered on. So we can disable powering up of the trace unit after checking for this errata via new property called "qcom,tupwr-disable". Signed-off-by: Tingwei Zhang <tingwei(a)codeaurora.org> Co-developed-by: Sai Prakash Ranjan <saiprakash.ranjan(a)codeaurora.org> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan(a)codeaurora.org> --- .../devicetree/bindings/arm/coresight.txt | 6 ++++ drivers/hwtracing/coresight/coresight-etm4x.c | 29 ++++++++++++------- 2 files changed, 25 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 846f6daae71b..d2030128fe46 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -108,6 +108,12 @@ its hardware characteristcs. * arm,cp14: must be present if the system accesses ETM/PTM management registers via co-processor 14. + * qcom,tupwr-disable: boolean. Indicates that trace unit power up can + be disabled on Qualcomm Technologies Inc. systems where ETMs are in + the same power domain as their CPU cores. This property is required + to identify such systems with hardware errata where the CPU watchdog + counter is stopped when TRCPDCR.PU=1. + * Optional property for TMC: * arm,buffer-size: size of contiguous buffer space for TMC ETR diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index fb0f5f4f3a91..6886b44f6947 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -104,6 +104,11 @@ struct etm4_enable_arg { int rc; }; +static inline bool etm4_can_disable_tupwr(struct device *dev) +{ + return fwnode_property_present(dev_fwnode(dev), "qcom,tupwr-disable"); +} + static int etm4_enable_hw(struct etmv4_drvdata *drvdata) { int i, rc; @@ -196,12 +201,14 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0); writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1); - /* - * Request to keep the trace unit powered and also - * emulation of powerdown - */ - writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU, - drvdata->base + TRCPDCR); + if (!etm4_can_disable_tupwr(etm_dev)) { + /* + * Request to keep the trace unit powered and also + * emulation of powerdown + */ + writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU, + drvdata->base + TRCPDCR); + } /* Enable the trace unit */ writel_relaxed(1, drvdata->base + TRCPRGCTLR); @@ -476,10 +483,12 @@ static void etm4_disable_hw(void *info) CS_UNLOCK(drvdata->base); - /* power can be removed from the trace unit now */ - control = readl_relaxed(drvdata->base + TRCPDCR); - control &= ~TRCPDCR_PU; - writel_relaxed(control, drvdata->base + TRCPDCR); + if (!etm4_can_disable_tupwr(etm_dev)) { + /* power can be removed from the trace unit now */ + control = readl_relaxed(drvdata->base + TRCPDCR); + control &= ~TRCPDCR_PU; + writel_relaxed(control, drvdata->base + TRCPDCR); + } control = readl_relaxed(drvdata->base + TRCPRGCTLR); -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

6 years, 4 months

[PATCH] dt-bindings: hisilicon: Add CTI bindings for hi-6220

by Mike Leach

Adds in CTI device tree information for the Hikey620 board. Tested on Linux 5.7-rc1. Signed-off-by: Mike Leach <mike.leach(a)linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> Tested-by: Leo Yan <leo.yan(a)linaro.org> --- .../boot/dts/hisilicon/hi6220-coresight.dtsi | 130 ++++++++++++++++-- 1 file changed, 122 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi index 651771a73ed6..27f067e87601 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi @@ -213,7 +213,7 @@ }; }; - etm@f659c000 { + etm0: etm@f659c000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf659c000 0 0x1000>; @@ -232,7 +232,7 @@ }; }; - etm@f659d000 { + etm1: etm@f659d000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf659d000 0 0x1000>; @@ -251,7 +251,7 @@ }; }; - etm@f659e000 { + etm2: etm@f659e000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf659e000 0 0x1000>; @@ -270,7 +270,7 @@ }; }; - etm@f659f000 { + etm3: etm@f659f000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf659f000 0 0x1000>; @@ -289,7 +289,7 @@ }; }; - etm@f65dc000 { + etm4: etm@f65dc000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf65dc000 0 0x1000>; @@ -308,7 +308,7 @@ }; }; - etm@f65dd000 { + etm5: etm@f65dd000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf65dd000 0 0x1000>; @@ -327,7 +327,7 @@ }; }; - etm@f65de000 { + etm6: etm@f65de000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf65de000 0 0x1000>; @@ -346,7 +346,7 @@ }; }; - etm@f65df000 { + etm7: etm@f65df000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf65df000 0 0x1000>; @@ -364,5 +364,119 @@ }; }; }; + + /* System CTIs */ + /* CTI 0 - TMC and TPIU connections */ + cti@f6403000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0 0xf6403000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + }; + + /* CTI - CPU-0 */ + cti@f6598000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0xf6598000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu0>; + arm,cs-dev-assoc = <&etm0>; + }; + + /* CTI - CPU-1 */ + cti@f6599000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0xf6599000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu1>; + arm,cs-dev-assoc = <&etm1>; + }; + + /* CTI - CPU-2 */ + cti@f659a000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0xf659a000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu2>; + arm,cs-dev-assoc = <&etm2>; + }; + + /* CTI - CPU-3 */ + cti@f659b000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0xf659b000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu3>; + arm,cs-dev-assoc = <&etm3>; + }; + + /* CTI - CPU-4 */ + cti@f65d8000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0xf65d8000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu4>; + arm,cs-dev-assoc = <&etm4>; + }; + + /* CTI - CPU-5 */ + cti@f65d9000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0xf65d9000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu5>; + arm,cs-dev-assoc = <&etm5>; + }; + + /* CTI - CPU-6 */ + cti@f65da000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0xf65da000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu6>; + arm,cs-dev-assoc = <&etm6>; + }; + + /* CTI - CPU-7 */ + cti@f65db000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0xf65db000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu7>; + arm,cs-dev-assoc = <&etm7>; + }; }; }; -- 2.17.1

6 years, 4 months

[PATCHv2 0/2] coresight: etm4x: Add support to skip trace unit power up

by Sai Prakash Ranjan

This series adds support to skip powering up of trace unit on systems with an errata which stops CPU watchdog counter when power up bit is set (TRCPDCR.PU = 1). Setting this bit is not required on Qualcomm Technologies Inc. chipsets where this errata exists since the ETMs are in the same power domain as their respective CPU cores. Tingwei Zhang (2): coresight: etm4x: Add support to skip trace unit power up dt-bindings: arm: coresight: Add support to skip trace unit power up .../devicetree/bindings/arm/coresight.txt | 7 +++++ drivers/hwtracing/coresight/coresight-etm4x.c | 27 ++++++++++++------- drivers/hwtracing/coresight/coresight-etm4x.h | 3 +++ 3 files changed, 27 insertions(+), 10 deletions(-) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

6 years, 4 months

[PATCH v3 0/2] Add CPU power management for CPU bound CTI devices.

by Mike Leach

Adds in power management for CPU bound CTI devices: i) CPU Hotplug - registers a new notifier for CPU start and stop events. ii) CPU idle PM event notifier to handle PM_ENTER, PM_ENTER_FAILED and PM_EXIT events. Tested with DB410c on coresight/next tree (Linux 5.7-rc1) Changes since v2: 1) removed helper functions filtering on CONFIG_CPU_PM to call cpu_pm fns directly. 2) add check for return value from cpuhp_remove_state_nocalls(). Changes since V1: (requested by Mathieu). 1) Split into separate patches for CPU pm and CPU hotplug handling. 2) Enable on hotplug has a specific function to enable the hardware, while leaving the enable reference counts unchanged. Mike Leach (2): coresight: cti: Add CPU Hotplug handling to CTI driver. coresight: cti: Add CPU idle pm notifer to CTI devices. drivers/hwtracing/coresight/coresight-cti.c | 160 ++++++++++++++++++++ include/linux/cpuhotplug.h | 1 + 2 files changed, 161 insertions(+) -- 2.17.1

6 years, 4 months

[PATCH] coresight: replicator: Reset replicator if context is lost

by Sai Prakash Ranjan

On some QCOM SoCs, replicators in Always-On domain loses its context as soon as the clock is disabled. Currently as a part of pm_runtime workqueue, clock is disabled after the replicator is initialized by amba_pm_runtime_suspend assuming that context is not lost which is not true for replicators with such limitations. Hence check the replicator idfilter registers in dynamic_replicator_enable() and reset again. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan(a)codeaurora.org> --- More info here - https://lore.kernel.org/patchwork/patch/1231182/ --- drivers/hwtracing/coresight/coresight-replicator.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c index e7dc1c31d20d..11df63f51071 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -68,6 +68,17 @@ static int dynamic_replicator_enable(struct replicator_drvdata *drvdata, int rc = 0; u32 reg; + /* + * On some QCOM SoCs with replicators in Always-On domain, disabling + * clock will result in replicator losing its context. Currently + * as a part of pm_runtime workqueue, amba_pm_runtime_suspend disables + * clock assuming the context is not lost which is not true for cases + * with hardware limitations as the above. + */ + if ((readl_relaxed(drvdata->base + REPLICATOR_IDFILTER0) == 0) && + (readl_relaxed(drvdata->base + REPLICATOR_IDFILTER1) == 0)) + dynamic_replicator_reset(drvdata); + switch (outport) { case 0: reg = REPLICATOR_IDFILTER0; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

6 years, 4 months

[PATCH] coresight: etm4x: Fix use-after-free of per-cpu etm drvdata

by Suzuki K Poulose

etm probe could be deferred due to the dependency in the trace path chain and may be retried. We need to clear the per-cpu etmdrvdata entry for the etm in case of a failure to avoid use-after-free cases as reported below: KASAN use-after-free bug in etm4_cpu_pm_notify(): [ 8.574566] coresight etm0: CPU0: ETM v4.2 initialized [ 8.581920] BUG: KASAN: use-after-free in etm4_cpu_pm_notify+0x580/0x2024 [ 8.581925] Read of size 8 at addr ffffff813304f8c8 by task swapper/3/0 [ 8.581927] [ 8.581934] CPU: 3 PID: 0 Comm: swapper/3 Tainted: G S W 5.4.28 #314 [ 8.587775] coresight etm1: CPU1: ETM v4.2 initialized [ 8.594195] Call trace: [ 8.594205] dump_backtrace+0x0/0x188 [ 8.594209] show_stack+0x20/0x2c [ 8.594216] dump_stack+0xdc/0x144 [ 8.594227] print_address_description+0x3c/0x494 [ 8.594232] __kasan_report+0x144/0x168 [ 8.601598] coresight etm2: CPU2: ETM v4.2 initialized [ 8.602563] kasan_report+0x10/0x18 [ 8.602568] check_memory_region+0x1a4/0x1b4 [ 8.602572] __kasan_check_read+0x18/0x24 [ 8.602577] etm4_cpu_pm_notify+0x580/0x2024 [ 8.665945] notifier_call_chain+0x5c/0x90 [ 8.670166] __atomic_notifier_call_chain+0x90/0xf8 [ 8.675182] cpu_pm_notify+0x40/0x6c [ 8.678858] cpu_pm_enter+0x38/0x80 [ 8.682451] psci_enter_idle_state+0x34/0x70 [ 8.686844] cpuidle_enter_state+0xb8/0x20c [ 8.691143] cpuidle_enter+0x38/0x4c [ 8.694820] call_cpuidle+0x3c/0x68 [ 8.698408] do_idle+0x1a0/0x280 [ 8.701729] cpu_startup_entry+0x24/0x28 [ 8.705768] secondary_start_kernel+0x15c/0x170 [ 8.710423] [ 8.711972] Allocated by task 242: [ 8.715473] __kasan_kmalloc+0xf0/0x1ac [ 8.719426] kasan_slab_alloc+0x14/0x1c [ 8.723375] __kmalloc_track_caller+0x23c/0x388 [ 8.728040] devm_kmalloc+0x38/0x94 [ 8.731632] etm4_probe+0x48/0x3c8 [ 8.735140] amba_probe+0xbc/0x158 [ 8.738645] really_probe+0x144/0x408 [ 8.742412] driver_probe_device+0x70/0x140 [ 8.746716] __device_attach_driver+0x9c/0x110 [ 8.751287] bus_for_each_drv+0x90/0xd8 [ 8.755236] __device_attach+0xb4/0x164 [ 8.759188] device_initial_probe+0x20/0x2c [ 8.763490] bus_probe_device+0x34/0x94 [ 8.767436] device_add+0x34c/0x3e0 [ 8.771029] amba_device_try_add+0x68/0x440 [ 8.775332] amba_deferred_retry_func+0x48/0xc8 [ 8.779997] process_one_work+0x344/0x648 [ 8.784127] worker_thread+0x2ac/0x47c [ 8.787987] kthread+0x128/0x138 [ 8.791313] ret_from_fork+0x10/0x18 [ 8.794993] [ 8.796532] Freed by task 242: [ 8.799684] __kasan_slab_free+0x15c/0x22c [ 8.803897] kasan_slab_free+0x10/0x1c [ 8.807761] kfree+0x25c/0x4bc [ 8.810913] release_nodes+0x240/0x2b0 [ 8.814767] devres_release_all+0x3c/0x54 [ 8.818887] really_probe+0x178/0x408 [ 8.822661] driver_probe_device+0x70/0x140 [ 8.826963] __device_attach_driver+0x9c/0x110 [ 8.831539] bus_for_each_drv+0x90/0xd8 [ 8.835487] __device_attach+0xb4/0x164 [ 8.839431] device_initial_probe+0x20/0x2c [ 8.843732] bus_probe_device+0x34/0x94 [ 8.847678] device_add+0x34c/0x3e0 [ 8.851274] amba_device_try_add+0x68/0x440 [ 8.855576] amba_deferred_retry_func+0x48/0xc8 [ 8.860240] process_one_work+0x344/0x648 [ 8.864366] worker_thread+0x2ac/0x47c [ 8.868228] kthread+0x128/0x138 [ 8.871557] ret_from_fork+0x10/0x18 [ 8.875231] [ 8.876782] The buggy address belongs to the object at ffffff813304f800 [ 8.876782] which belongs to the cache kmalloc-1k of size 1024 [ 8.889632] The buggy address is located 200 bytes inside of [ 8.889632] 1024-byte region [ffffff813304f800, ffffff813304fc00) [ 8.901761] The buggy address belongs to the page: [ 8.906695] page:ffffffff04ac1200 refcount:1 mapcount:0 mapping:ffffff8146c03800 index:0x0 compound_mapcount: 0 [ 8.917047] flags: 0x4000000000010200(slab|head) [ 8.921799] raw: 4000000000010200 dead000000000100 dead000000000122 ffffff8146c03800 [ 8.929753] raw: 0000000000000000 0000000000100010 00000001ffffffff 0000000000000000 [ 8.937703] page dumped because: kasan: bad access detected [ 8.943433] [ 8.944974] Memory state around the buggy address: [ 8.949903] ffffff813304f780: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 8.957320] ffffff813304f800: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ 8.964742] >ffffff813304f880: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ 8.972157] ^ [ 8.977886] ffffff813304f900: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ 8.985298] ffffff813304f980: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ 8.992713] ================================================================== Fixes: f188b5e76aae9 ( "coresight: etm4x: Save/restore state across CPU low power states ") Reported-by: Sai Prakash Ranjan <saiprakash.ranjan(a)codeaurora.org> Tested-by: Sai Prakash Ranjan <saiprakash.ranjan(a)codeaurora.org> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Mike Leach <mike.leach(a)linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> --- drivers/hwtracing/coresight/coresight-etm4x.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 0b2c7c7efacb..d7e19d91ff17 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1516,6 +1516,7 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) return 0; err_arch_supported: + etmdrvdata[drvdata->cpu] = NULL; if (--etm4_count == 0) { etm4_cpu_pm_unregister(); -- 2.24.1

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CoreSight May 2020