Tcwg-commits May 2023

tcwg-commits@lists.linaro.org

4 participants
7900 discussions

[gcc] branch master updated (6d25ea520f7 -> cf2c47b159d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 6d25ea520f7 aarch64: Improve register allocation for lane instructions new c66ed9e7e9f arm: [MVE intrinsics] add binary_maxvminv shape new 2bf22a1e1a9 arm: [MVE intrinsics] add binary_maxavminav shape new ae7d75fec88 arm: [MVE intrinsics add unspec_mve_function_exact_insn_pred_p new 16c5aca6a13 arm: [MVE intrinsics] factorize vmaxvq vminvq vmaxavq vminavq new 83fff825edb arm: [MVE intrinsics] rework vmaxvq vminvq vmaxavq vminavq new 25d0235e6ec arm: add smax/smin expanders for v*hf new 5ea7a47c858 arm: [MVE intrinsics] factorize vmaxnmq vminnmq new 9c4fea2457e arm: [MVE intrinsics] rework vmaxnmq vminnmq new d814dc9dde4 arm: [MVE intrinsics] factorize vmaxnmavq vmaxnmvq vminnmav [...] new d16321ad9ba arm: [MVE intrinsics] add support for mve_q_p_f new 400453c334a arm: [MVE intrinsics] rework vmaxnmavq vmaxnmvq vminnmavq vminnmvq new 26d6e02c42b arm: [MVE intrinsics] factorize vmaxnmaq vminnmaq new adff073bb1c arm: [MVE intrinsics] rework vmaxnmaq vminnmaq new f75909127f7 arm: [MVE intrinsics] add binary_maxamina shape new dcc05862bf3 arm: [MVE intrinsics] factorize vmaxaq vminaq new cf2c47b159d arm: [MVE intrinsics] rework vmaxaq vminaq The 16 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/arm/arm-mve-builtins-base.cc | 33 + gcc/config/arm/arm-mve-builtins-base.def | 14 + gcc/config/arm/arm-mve-builtins-base.h | 14 + gcc/config/arm/arm-mve-builtins-functions.h | 64 ++ gcc/config/arm/arm-mve-builtins-shapes.cc | 100 ++ gcc/config/arm/arm-mve-builtins-shapes.h | 3 + gcc/config/arm/arm-mve-builtins.cc | 4 + gcc/config/arm/arm_mve.h | 1578 +-------------------------- gcc/config/arm/iterators.md | 90 ++ gcc/config/arm/mve.md | 388 +------ gcc/config/arm/vec-common.md | 12 +- 11 files changed, 403 insertions(+), 1897 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu_native_fast_check_gcc/master-aarch64 updated (2ba575a5a5a -> fa2c3d18823)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_native_fast_check_gcc/master-aarch64 in repository toolchain/ci/base-artifacts. discards 2ba575a5a5a 139: onsuccess: #192: 0: [TCWG CI] https://ci.linaro.org/jo [...] discards 569c9bd753d 138: onsuccess: #191: 0: [TCWG CI] https://ci.linaro.org/jo [...] discards eb1ac574aa4 137: onsuccess: #190: 0: [TCWG CI] https://ci.linaro.org/jo [...] discards 271982d3649 136: onsuccess: #189: 0: [TCWG CI] https://ci.linaro.org/jo [...] discards ec1160acb62 135: onsuccess: #188: 0: [TCWG CI] https://ci.linaro.org/jo [...] discards d5429c48d58 134: onsuccess: #187: 0: [TCWG CI] https://ci.linaro.org/jo [...] discards 7b3f7811144 133: onsuccess: #186: 0: [TCWG CI] https://ci.linaro.org/jo [...] discards 475026b85a0 132: onsuccess: #185: 0: [TCWG CI] https://ci.linaro.org/jo [...] discards 1ad14e8789f 131: onsuccess: #184: 0: [TCWG CI] https://ci.linaro.org/jo [...] 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That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (2ba575a5a5a) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu_native_fast_check_gc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 102 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 00-sumfiles/g++.log.xz | Bin 1408 -> 1408 bytes 00-sumfiles/gcc.log.xz | Bin 374888 -> 374260 bytes 00-sumfiles/gfortran.log.xz | Bin 59420 -> 58796 bytes 00-sumfiles/libatomic.log.xz | Bin 436 -> 436 bytes 00-sumfiles/libgomp.log.xz | Bin 432 -> 432 bytes 00-sumfiles/libitm.log.xz | Bin 432 -> 432 bytes 00-sumfiles/libstdc++.log.xz | Bin 424 -> 424 bytes 01-reset_artifacts/console.log.xz | Bin 2224 -> 2212 bytes 02-prepare_abe/console.log.xz | Bin 2436 -> 2456 bytes 03-build_abe-binutils/console.log.xz | Bin 35008 -> 38164 bytes 04-build_abe-gcc/console.log.xz | Bin 207008 -> 209416 bytes 05-clean_sysroot/console.log.xz | Bin 312 -> 312 bytes 06-build_abe-linux/console.log.xz | Bin 8860 -> 8664 bytes 07-build_abe-glibc/console.log.xz | Bin 243436 -> 243668 bytes 08-build_abe-gdb/console.log.xz | Bin 36224 -> 37424 bytes 09-build_abe-dejagnu/console.log.xz | Bin 3940 -> 4144 bytes 10-build_abe-check_gcc/console.log.xz | Bin 3668 -> 3808 bytes 10-build_abe-check_gcc/flaky.xfail | 2 +- 11-check_regression/console.log.xz | Bin 1248 -> 1468 bytes 11-check_regression/results.compare | 18 +++---- 11-check_regression/results.compare2 | 33 ++++++++++--- 12-update_baseline/console.log | 88 +++++++++++++++++----------------- git/binutils_rev | 2 +- git/gcc_rev | 2 +- git/gdb_rev | 2 +- git/glibc_rev | 2 +- git/linux_rev | 2 +- mail/results.compare | 18 +++---- manifest.sh | 34 ++++++------- sumfiles/g++.sum | 2 +- sumfiles/gcc.sum | 18 ++++++- sumfiles/gfortran.sum | 2 +- sumfiles/libatomic.sum | 2 +- sumfiles/libgomp.sum | 2 +- sumfiles/libitm.sum | 2 +- 35 files changed, 133 insertions(+), 98 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu_cross_build/master-arm updated (1073fdcdbc2 -> bb702157a86)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/base-artifacts. discards 1073fdcdbc2 212: onsuccess: #137: 7: [TCWG CI] https://ci.linaro.org/jo [...] discards 03d505c61b1 212: onsuccess: #136: 7: [TCWG CI] https://ci.linaro.org/jo [...] discards 52c5d37f474 212: onsuccess: #135: 7: [TCWG CI] https://ci.linaro.org/jo [...] discards e4a59567449 212: onsuccess: #134: 7: [TCWG CI] https://ci.linaro.org/jo [...] discards f049f373f96 212: onsuccess: #133: 7: [TCWG CI] https://ci.linaro.org/jo [...] discards 49fd5cc7b39 212: onsuccess: #132: 7: [TCWG CI] https://ci.linaro.org/jo [...] discards 11e775a6dc0 212: onsuccess: #131: 7: [TCWG CI] https://ci.linaro.org/jo [...] discards d1b1fa9e1f5 212: onsuccess: #130: 7: [TCWG CI] https://ci.linaro.org/jo [...] discards 483848d32a5 212: onsuccess: #129: 7: [TCWG CI] https://ci.linaro.org/jo [...] discards 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https://ci.linaro.org/jo [...] new 833d634da7d 212: onsuccess: #135: 7: [TCWG CI] https://ci.linaro.org/jo [...] new 4dc703f63db 212: onsuccess: #136: 7: [TCWG CI] https://ci.linaro.org/jo [...] new dec5b3b3d8c 212: onsuccess: #137: 7: [TCWG CI] https://ci.linaro.org/jo [...] new bb702157a86 212: onsuccess: #142: 7: [TCWG CI] https://ci.linaro.org/jo [...] This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (1073fdcdbc2) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu_cross_build/master-a [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 202 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 2208 -> 2232 bytes 02-prepare_abe/console.log.xz | Bin 2428 -> 2400 bytes 04-build_abe-binutils/console.log.xz | Bin 27348 -> 29484 bytes 05-build_abe-stage1/console.log.xz | Bin 89624 -> 89696 bytes 07-build_abe-linux/console.log.xz | Bin 8404 -> 8792 bytes 08-build_abe-glibc/console.log.xz | Bin 231976 -> 231864 bytes 09-build_abe-stage2/console.log.xz | Bin 226028 -> 226012 bytes 10-build_abe-gdb/console.log.xz | Bin 34616 -> 36836 bytes 11-build_abe-qemu/console.log.xz | Bin 30512 -> 32260 bytes 12-check_regression/console.log.xz | Bin 460 -> 460 bytes 13-update_baseline/console.log | 686 +++++++++++++++++------------------ git/binutils_rev | 2 +- git/gcc_rev | 2 +- git/gdb_rev | 2 +- git/glibc_rev | 2 +- git/linux_rev | 2 +- git/qemu_rev | 2 +- manifest.sh | 44 +-- 18 files changed, 371 insertions(+), 371 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years

[toolchain/ci/interesting-commits] branch master updated (f10f1eb7 -> 97985b33)

by tcwg-buildslave

This is an automated email from the git hooks/post-receive script. "tcwg-buildslave pushed a change to branch master in repository toolchain/ci/interesting-commits. from f10f1eb7 Add entry d6654a4be3ba44c0d57be7c8a51d76d9721345e1 from https [...] new 97985b33 Add entry ba0ad6ed89fd5dada3b7b65ef2b08e95d449d4ab from https [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../tcwg_gnu_native_check_gdb/master-arm/build_url | 2 +- .../tcwg_gnu_native_check_gdb/master-arm/last_good | 1 + .../master-arm/summary.txt | 19 +++++++++ .../tcwg_gnu_native_check_gdb/status.txt | 48 ++++++++++++++++++++++ linux/v6.4-rc1-1-gba0ad6ed89fd | 1 + 5 files changed, 70 insertions(+), 1 deletion(-) copy {binutils/sha1/14317f7f05d0290586f456d02176dd77a81aee69 => linux/sha1/ba0ad6e [...] create mode 100644 linux/sha1/ba0ad6ed89fd5dada3b7b65ef2b08e95d449d4ab/tcwg_gnu_na [...] create mode 100644 linux/sha1/ba0ad6ed89fd5dada3b7b65ef2b08e95d449d4ab/tcwg_gnu_na [...] create mode 100644 linux/sha1/ba0ad6ed89fd5dada3b7b65ef2b08e95d449d4ab/tcwg_gnu_na [...] create mode 120000 linux/v6.4-rc1-1-gba0ad6ed89fd -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years

[gcc] branch master updated (434dade5a11 -> 6d25ea520f7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 434dade5a11 PR modula2/109779 isolib SkipLine skips the first character [...] new 84684d2c393 aarch64: Fix cut-&-pasto in aarch64-sve2-acle-asm.exp new 6d25ea520f7 aarch64: Improve register allocation for lane instructions The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/aarch64/aarch64-protos.h | 2 ++ gcc/config/aarch64/aarch64-sve.md | 2 +- gcc/config/aarch64/aarch64.cc | 38 ++++++++++++++++++++++ gcc/config/aarch64/aarch64.h | 5 +++ .../gcc.target/aarch64/sve/acle/asm/abd_f16.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/abd_f32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/abd_f64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/abd_s16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/abd_s32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/abd_s64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/abd_s8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/abd_u16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/abd_u32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/abd_u64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/abd_u8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/add_s16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/add_s32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/add_s64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/add_s8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/add_u16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/add_u32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/add_u64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/add_u8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/and_s16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/and_s32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/and_s64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/and_s8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/and_u16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/and_u32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/and_u64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/and_u8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/asr_s16.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/asr_s8.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/bic_s16.c | 6 ++-- .../gcc.target/aarch64/sve/acle/asm/bic_s32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/bic_s64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/bic_s8.c | 6 ++-- .../gcc.target/aarch64/sve/acle/asm/bic_u16.c | 6 ++-- .../gcc.target/aarch64/sve/acle/asm/bic_u32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/bic_u64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/bic_u8.c | 6 ++-- .../gcc.target/aarch64/sve/acle/asm/div_f16.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/div_f32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/div_f64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/div_s32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/div_s64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/div_u32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/div_u64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/divr_f16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/divr_f32.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/divr_f64.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/divr_s32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/divr_s64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/divr_u32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/divr_u64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/dot_s32.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/dot_s64.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/dot_u32.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/dot_u64.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/eor_s16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/eor_s32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/eor_s64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/eor_s8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/eor_u16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/eor_u32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/eor_u64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/eor_u8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/lsl_s16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/lsl_s32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/lsl_s64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/lsl_s8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/lsl_u16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/lsl_u32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/lsl_u64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/lsl_u8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/lsl_wide_s16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/lsl_wide_s32.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/lsl_wide_s8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/lsl_wide_u16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/lsl_wide_u32.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/lsl_wide_u8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/lsr_u16.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/lsr_u8.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mad_f16.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mad_f32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mad_f64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mad_s16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/mad_s32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mad_s64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mad_s8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/mad_u16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/mad_u32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mad_u64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mad_u8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/max_s16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/max_s32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/max_s64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/max_s8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/max_u16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/max_u32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/max_u64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/max_u8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/min_s16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/min_s32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/min_s64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/min_s8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/min_u16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/min_u32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/min_u64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/min_u8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/mla_f16.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mla_f32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mla_f64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mla_s16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/mla_s32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mla_s64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mla_s8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/mla_u16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/mla_u32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mla_u64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mla_u8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/mls_f16.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mls_f32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mls_f64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mls_s16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/mls_s32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mls_s64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mls_s8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/mls_u16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/mls_u32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mls_u64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mls_u8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/msb_f16.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/msb_f32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/msb_f64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/msb_s16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/msb_s32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/msb_s64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/msb_s8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/msb_u16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/msb_u32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/msb_u64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/msb_u8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/mul_f16.c | 2 +- .../aarch64/sve/acle/asm/mul_f16_notrap.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mul_f32.c | 2 +- .../aarch64/sve/acle/asm/mul_f32_notrap.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mul_f64.c | 2 +- .../aarch64/sve/acle/asm/mul_f64_notrap.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mul_s16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/mul_s32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mul_s64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mul_s8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/mul_u16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/mul_u32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mul_u64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mul_u8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/mulh_s16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/mulh_s32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mulh_s64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mulh_s8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/mulh_u16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/mulh_u32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mulh_u64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mulh_u8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/mulx_f16.c | 6 ++-- .../gcc.target/aarch64/sve/acle/asm/mulx_f32.c | 6 ++-- .../gcc.target/aarch64/sve/acle/asm/mulx_f64.c | 6 ++-- .../gcc.target/aarch64/sve/acle/asm/nmad_f16.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/nmad_f32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/nmad_f64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/nmla_f16.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/nmla_f32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/nmla_f64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/nmls_f16.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/nmls_f32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/nmls_f64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/nmsb_f16.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/nmsb_f32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/nmsb_f64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/orr_s16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/orr_s32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/orr_s64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/orr_s8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/orr_u16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/orr_u32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/orr_u64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/orr_u8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/scale_f16.c | 12 +++---- .../gcc.target/aarch64/sve/acle/asm/scale_f32.c | 6 ++-- .../gcc.target/aarch64/sve/acle/asm/scale_f64.c | 6 ++-- .../gcc.target/aarch64/sve/acle/asm/sub_s16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/sub_s32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/sub_s64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/sub_s8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/sub_u16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/sub_u32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/sub_u64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/sub_u8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/subr_f16.c | 2 +- .../aarch64/sve/acle/asm/subr_f16_notrap.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/subr_f32.c | 2 +- .../aarch64/sve/acle/asm/subr_f32_notrap.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/subr_f64.c | 2 +- .../aarch64/sve/acle/asm/subr_f64_notrap.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/subr_s16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/subr_s32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/subr_s64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/subr_s8.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/subr_u16.c | 4 +-- .../gcc.target/aarch64/sve/acle/asm/subr_u32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/subr_u64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/subr_u8.c | 4 +-- .../aarch64/sve2/acle/aarch64-sve2-acle-asm.exp | 2 +- .../gcc.target/aarch64/sve2/acle/asm/bcax_s16.c | 4 +-- .../gcc.target/aarch64/sve2/acle/asm/bcax_s32.c | 2 +- .../gcc.target/aarch64/sve2/acle/asm/bcax_s64.c | 2 +- .../gcc.target/aarch64/sve2/acle/asm/bcax_s8.c | 4 +-- .../gcc.target/aarch64/sve2/acle/asm/bcax_u16.c | 4 +-- .../gcc.target/aarch64/sve2/acle/asm/bcax_u32.c | 2 +- .../gcc.target/aarch64/sve2/acle/asm/bcax_u64.c | 2 +- .../gcc.target/aarch64/sve2/acle/asm/bcax_u8.c | 4 +-- .../gcc.target/aarch64/sve2/acle/asm/qadd_s16.c | 4 +-- .../gcc.target/aarch64/sve2/acle/asm/qadd_s32.c | 2 +- .../gcc.target/aarch64/sve2/acle/asm/qadd_s64.c | 2 +- .../gcc.target/aarch64/sve2/acle/asm/qadd_s8.c | 4 +-- .../gcc.target/aarch64/sve2/acle/asm/qadd_u16.c | 4 +-- .../gcc.target/aarch64/sve2/acle/asm/qadd_u32.c | 2 +- .../gcc.target/aarch64/sve2/acle/asm/qadd_u64.c | 2 +- .../gcc.target/aarch64/sve2/acle/asm/qadd_u8.c | 4 +-- .../gcc.target/aarch64/sve2/acle/asm/qdmlalb_s16.c | 4 +-- .../gcc.target/aarch64/sve2/acle/asm/qdmlalb_s32.c | 4 +-- .../gcc.target/aarch64/sve2/acle/asm/qdmlalb_s64.c | 2 +- .../aarch64/sve2/acle/asm/qdmlalbt_s16.c | 4 +-- .../aarch64/sve2/acle/asm/qdmlalbt_s32.c | 4 +-- .../aarch64/sve2/acle/asm/qdmlalbt_s64.c | 2 +- .../gcc.target/aarch64/sve2/acle/asm/qsub_s16.c | 4 +-- .../gcc.target/aarch64/sve2/acle/asm/qsub_s32.c | 2 +- .../gcc.target/aarch64/sve2/acle/asm/qsub_s64.c | 2 +- .../gcc.target/aarch64/sve2/acle/asm/qsub_s8.c | 4 +-- .../gcc.target/aarch64/sve2/acle/asm/qsub_u16.c | 4 +-- .../gcc.target/aarch64/sve2/acle/asm/qsub_u32.c | 2 +- .../gcc.target/aarch64/sve2/acle/asm/qsub_u64.c | 2 +- .../gcc.target/aarch64/sve2/acle/asm/qsub_u8.c | 4 +-- .../gcc.target/aarch64/sve2/acle/asm/qsubr_s16.c | 4 +-- .../gcc.target/aarch64/sve2/acle/asm/qsubr_s32.c | 2 +- .../gcc.target/aarch64/sve2/acle/asm/qsubr_s64.c | 2 +- .../gcc.target/aarch64/sve2/acle/asm/qsubr_s8.c | 4 +-- .../gcc.target/aarch64/sve2/acle/asm/qsubr_u16.c | 4 +-- .../gcc.target/aarch64/sve2/acle/asm/qsubr_u32.c | 2 +- .../gcc.target/aarch64/sve2/acle/asm/qsubr_u64.c | 2 +- .../gcc.target/aarch64/sve2/acle/asm/qsubr_u8.c | 4 +-- 252 files changed, 414 insertions(+), 369 deletions(-) -- To stop receiving notification emails like this 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2 years

[binutils-gdb] branch master updated (d9cc4b060dd -> 1fba7b3ac50)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from d9cc4b060dd Correct a spelling mistake in the binutils README file. new 1fba7b3ac50 gdb: fix use-after-free in check_longjmp_breakpoint_for_call_dummy The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gdb/breakpoint.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years

[toolchain/jenkins-scripts] branch master updated (a3d08e4e -> 1c20c394)

by Maxim Kuvyrkov

This is an automated email from the git hooks/post-receive script. "Maxim Kuvyrkov pushed a change to branch master in repository toolchain/jenkins-scripts. from a3d08e4e jenkins-helpers.sh (get_baseline_manifest): Fix unbounded var [...] new 1c20c394 jenkins-helpers.sh (get_baseline_manifest): Fix previous commit The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: jenkins-helpers.sh | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years

[linux] branch master updated (1dc3731daf1f -> 16a8829130ca)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository linux. from 1dc3731daf1f Merge tag 'for-6.4-rc1-tag' of git://git.kernel.org/pub/sc [...] new 16a8829130ca nfs: fix another case of NULL/IS_ERR confusion wrt folio pointers The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: fs/nfs/dir.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years

[toolchain/jenkins-scripts] branch master updated (8aa45047 -> a3d08e4e)

by Maxim Kuvyrkov

This is an automated email from the git hooks/post-receive script. "Maxim Kuvyrkov pushed a change to branch master in repository toolchain/jenkins-scripts. from 8aa45047 tcwg_aosp-build.sh: Fix "interestingness" score for code-size loops new a3d08e4e jenkins-helpers.sh (get_baseline_manifest): Fix unbounded var [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: jenkins-helpers.sh | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years

[gcc] branch master updated (2499540e9ab -> 434dade5a11)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 2499540e9ab c++: Reject pack expansion of assume attribute [PR109756] new 434dade5a11 PR modula2/109779 isolib SkipLine skips the first character [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/m2/gm2-libs-iso/RTgen.mod | 10 +- gcc/m2/gm2-libs-iso/TextIO.mod | 146 ++++++++++++--------- gcc/testsuite/gm2/isolib/run/pass/skiplinetest.mod | 52 ++++++++ 3 files changed, 141 insertions(+), 67 deletions(-) create mode 100644 gcc/testsuite/gm2/isolib/run/pass/skiplinetest.mod -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years

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