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unknown user pushed a change to branch master
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from bfdadcb2991 RISC-V: Bugfix for the const vector in single steps
new f5213759a7e aarch64: Validate register operands early in ldp fusion pas [...]
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Summary of changes:
gcc/config/aarch64/aarch64-ldp-fusion.cc | 11 ++++++++---
gcc/testsuite/gcc.dg/pr113062.c | 10 ++++++++++
2 files changed, 18 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.dg/pr113062.c
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unknown user pushed a change to branch master
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from 1190de7ef8b RISC-V: Fix ICE of moving SUBREG of vector mode to DImode s [...]
new bfdadcb2991 RISC-V: Bugfix for the const vector in single steps
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Summary of changes:
gcc/config/riscv/riscv-v.cc | 111 ++++++++++++++++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-7.c | 61 +++++++++++
2 files changed, 156 insertions(+), 16 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-7.c
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tcwg-buildslave pushed a change to branch master
in repository toolchain/ci/interesting-commits.
from 551a4d3de Add entry 2c3db94d9fd07681f8806dae93d555779ff4dfb1 from https [...]
new 2dccb01b2 Add entry 2c3db94d9fd07681f8806dae93d555779ff4dfb1 from https [...]
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Summary of changes:
gcc/sha1/2c3db94d9fd07681f8806dae93d555779ff4dfb1/jira/description | 4 ++++
gcc/sha1/2c3db94d9fd07681f8806dae93d555779ff4dfb1/jira/yaml | 4 ++++
gcc/sha1/2c3db94d9fd07681f8806dae93d555779ff4dfb1/status.txt | 4 ++++
.../tcwg_bmk-code_vect-spec2k6/gnu-aarch64-master-O3}/details.txt | 0
.../reproduction_instructions.txt | 4 ++--
.../gnu-aarch64-master-O3}/status-summary.txt | 0
.../tcwg_bmk-code_vect-spec2k6/gnu-aarch64-master-O3/status.txt | 6 +++---
.../tcwg_bmk-code_vect-spec2k6/status.txt | 4 ++++
8 files changed, 21 insertions(+), 5 deletions(-)
copy {binutils/sha1/18737d14799d609054994987dd75631430637a99/tcwg_bmk-code_speed-s [...]
copy gcc/sha1/2c3db94d9fd07681f8806dae93d555779ff4dfb1/tcwg_bmk-code_vect-spec2k6/ [...]
copy {binutils/sha1/18737d14799d609054994987dd75631430637a99 => gcc/sha1/2c3db94d9 [...]
copy gcc/sha1/{3d48c11ad082def8ee237e5778d8a5d569bff96d => 2c3db94d9fd07681f8806da [...]
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tcwg-buildslave pushed a change to branch master
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from e7539aaa0 Add entry f81bf08f7caaebf877956d5d09c56a5d501de08a from https [...]
new 551a4d3de Add entry 2c3db94d9fd07681f8806dae93d555779ff4dfb1 from https [...]
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Summary of changes:
.../tcwg_bmk-code_vect-spec2k6/gnu-aarch64-master-O3/build_url | 2 +-
.../gnu-aarch64-master-O3}/last_good | 0
2 files changed, 1 insertion(+), 1 deletion(-)
copy gcc/sha1/{21e2ef2dc25de318de29ec32d5390350c6717c6a => 2c3db94d9fd07681f8806da [...]
copy gcc/sha1/2c3db94d9fd07681f8806dae93d555779ff4dfb1/{tcwg_bmk-code_size-spec2k6 [...]
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unknown user pushed a change to branch master
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from 4e0a467302f strub: sparc64: unbias the stack address [PR112917]
new 1190de7ef8b RISC-V: Fix ICE of moving SUBREG of vector mode to DImode s [...]
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Summary of changes:
gcc/config/riscv/riscv.cc | 24 ++++++++++++++--------
.../riscv/rvv/autovec/bug-8.c} | 3 +++
2 files changed, 19 insertions(+), 8 deletions(-)
copy gcc/testsuite/{gcc.c-torture/compile/pr42196-1.c => gcc.target/riscv/rvv/auto [...]
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unknown user pushed a change to branch master
in repository glibc.
from 3150cc0c90 Fix elf/tst-env-setuid[-static] if test needs to be rerun.
new cc0d77ba94 aarch64: Add half-width versions of AdvSIMD f32 libmvec routines
new 667f277c78 aarch64: Add SIMD attributes to math functions with vector versions
new 980450f126 elf: Add TLS modid reuse test for bug 29039
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Summary of changes:
elf/Makefile | 15 ++++
elf/tst-tlsgap-mod0.c | 2 +
elf/tst-tlsgap-mod1.c | 2 +
elf/tst-tlsgap-mod2.c | 2 +
elf/tst-tlsgap.c | 92 ++++++++++++++++++++++
include/libc-symbols.h | 2 +
sysdeps/aarch64/fpu/Versions | 15 ++++
sysdeps/aarch64/fpu/acosf_advsimd.c | 4 +-
.../aarch64/fpu/advsimd_f32_protos.h | 31 ++++----
sysdeps/aarch64/fpu/asinf_advsimd.c | 4 +-
sysdeps/aarch64/fpu/atan2f_advsimd.c | 4 +-
sysdeps/aarch64/fpu/atanf_advsimd.c | 4 +-
sysdeps/aarch64/fpu/bits/math-vector.h | 66 ++++++++++++++++
sysdeps/aarch64/fpu/cosf_advsimd.c | 4 +-
sysdeps/aarch64/fpu/exp10f_advsimd.c | 4 +-
sysdeps/aarch64/fpu/exp2f_advsimd.c | 4 +-
sysdeps/aarch64/fpu/expf_advsimd.c | 4 +-
sysdeps/aarch64/fpu/expm1f_advsimd.c | 4 +-
sysdeps/aarch64/fpu/finclude/math-vector-fortran.h | 47 +++++++++++
sysdeps/aarch64/fpu/log10f_advsimd.c | 4 +-
sysdeps/aarch64/fpu/log1pf_advsimd.c | 2 +
sysdeps/aarch64/fpu/log2f_advsimd.c | 4 +-
sysdeps/aarch64/fpu/logf_advsimd.c | 4 +-
sysdeps/aarch64/fpu/sinf_advsimd.c | 4 +-
sysdeps/aarch64/fpu/tanf_advsimd.c | 4 +-
sysdeps/aarch64/fpu/v_math.h | 15 ++++
sysdeps/unix/sysv/linux/aarch64/libmvec.abilist | 15 ++++
27 files changed, 334 insertions(+), 28 deletions(-)
create mode 100644 elf/tst-tlsgap-mod0.c
create mode 100644 elf/tst-tlsgap-mod1.c
create mode 100644 elf/tst-tlsgap-mod2.c
create mode 100644 elf/tst-tlsgap.c
copy debug/wcslcpy_chk.c => sysdeps/aarch64/fpu/advsimd_f32_protos.h (54%)
create mode 100644 sysdeps/aarch64/fpu/finclude/math-vector-fortran.h
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tcwg-buildslave pushed a change to branch master
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from 4ca93e828 Add entry f81bf08f7caaebf877956d5d09c56a5d501de08a from https [...]
new e7539aaa0 Add entry f81bf08f7caaebf877956d5d09c56a5d501de08a from https [...]
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Summary of changes:
.../jira/description | 4 ++
.../jira/yaml | 4 ++
.../status.txt | 4 ++
.../master-arm_v7a_softfp_eabi/details.txt | 49 ++++++++++++++++++++++
.../reproduction_instructions.txt | 4 +-
.../master-arm_v7a_softfp_eabi}/status-summary.txt | 0
.../master-arm_v7a_softfp_eabi/status.txt | 3 ++
.../tcwg_gnu_embed_build/status.txt | 4 ++
8 files changed, 70 insertions(+), 2 deletions(-)
create mode 100644 newlib/sha1/f81bf08f7caaebf877956d5d09c56a5d501de08a/tcwg_gnu_e [...]
copy newlib/sha1/f81bf08f7caaebf877956d5d09c56a5d501de08a/tcwg_gnu_embed_build/{ma [...]
copy {aosp_superproject/sha1/48fc3020c25376e5b2f11aee74fcf11bdc208051 => newlib/sh [...]
create mode 100644 newlib/sha1/f81bf08f7caaebf877956d5d09c56a5d501de08a/tcwg_gnu_e [...]
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