Tcwg-commits July 2022

tcwg-commits@lists.linaro.org

6 participants
15101 discussions

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu_cross_build/master-arm updated (3118e828 -> 1cb5ff93)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/base-artifacts. discards 3118e828 2: update: binutils-gcc-linux-glibc-gdb-qemu: 4 new 1cb5ff93 2: update: binutils-a2a176c46bcb739db47c88b5641a23c1129accf0: 4 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (3118e828) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu_cross_build/master-a [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1804 -> 1580 bytes 02-prepare_abe/console.log.xz | Bin 2732 -> 2712 bytes 04-build_abe-binutils/console.log.xz | Bin 30628 -> 31168 bytes 05-build_abe-stage1/console.log.xz | Bin 91276 -> 93620 bytes 06-clean_sysroot/console.log.xz | Bin 332 -> 332 bytes 07-build_abe-linux/console.log.xz | Bin 9256 -> 11380 bytes 08-build_abe-glibc/console.log.xz | Bin 235816 -> 232516 bytes 09-build_abe-stage2/console.log.xz | Bin 193024 -> 193596 bytes 12-check_regression/console.log.xz | Bin 416 -> 416 bytes 13-update_baseline/console.log | 110 +++++++++++++++++------------------ jenkins/manifest.sh | 15 ++--- 11 files changed, 60 insertions(+), 65 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk_gnu_fx/gnu-master-aarch64-cpu2017-O3 updated (366490c8 -> 5e5ba512)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_gnu_fx/gnu-master-aarch64-cpu2017-O3 in repository toolchain/ci/base-artifacts. discards 366490c8 0: update: : 1 new 5e5ba512 0: update: : 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (366490c8) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_bmk_gnu_fx/gnu-master-aa [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1644 -> 1612 bytes 02-prepare_abe/console.log.xz | Bin 2740 -> 2736 bytes 03-build_abe-binutils/console.log.xz | Bin 30276 -> 30884 bytes 04-build_abe-stage1/console.log.xz | Bin 74752 -> 76748 bytes 05-clean_sysroot/console.log.xz | Bin 332 -> 332 bytes 06-build_abe-linux/console.log.xz | Bin 11296 -> 11080 bytes 07-build_abe-glibc/console.log.xz | Bin 237460 -> 239664 bytes 08-build_abe-stage2/console.log.xz | Bin 178004 -> 184688 bytes 09-benchmark/benchmark-build.log | 78 +- 09-benchmark/benchmark.log | 76 +- 09-benchmark/console.log.xz | Bin 3668 -> 3680 bytes 10-check_regression/console.log.xz | Bin 2924 -> 2920 bytes 10-check_regression/csv-results-0/md5sum.csv | 70 +- 10-check_regression/csv-results-0/perf.csv | 283 +- 10-check_regression/csv-results-0/results.csv | 3865 +-- 10-check_regression/csv-results-0/size.csv | 42550 +++++++++++------------- 10-check_regression/csv-results-0/vect.csv | 20 +- 10-check_regression/csv-results-1/md5sum.csv | 70 +- 10-check_regression/csv-results-1/perf.csv | 293 +- 10-check_regression/csv-results-1/results.csv | 315 +- 10-check_regression/csv-results-1/size.csv | 39030 +++++++++++----------- 10-check_regression/csv-results-1/vect.csv | 20 +- 10-check_regression/results-brief.csv | 8 +- 10-check_regression/results-full.csv | 317 +- 10-check_regression/results-internal.csv | 32 +- 10-check_regression/results.log | 620 +- 11-update_baseline/console.log | 1736 +- 11-update_baseline/csv-results-0/md5sum.csv | 70 +- 11-update_baseline/csv-results-0/perf.csv | 283 +- 11-update_baseline/csv-results-0/results.csv | 3865 +-- 11-update_baseline/csv-results-0/size.csv | 42550 +++++++++++------------- 11-update_baseline/csv-results-0/vect.csv | 20 +- 11-update_baseline/csv-results-1/md5sum.csv | 70 +- 11-update_baseline/csv-results-1/perf.csv | 293 +- 11-update_baseline/csv-results-1/results.csv | 315 +- 11-update_baseline/csv-results-1/size.csv | 39030 +++++++++++----------- 11-update_baseline/csv-results-1/vect.csv | 20 +- 11-update_baseline/results-brief.csv | 8 +- 11-update_baseline/results-full.csv | 317 +- 11-update_baseline/results-internal.csv | 32 +- 11-update_baseline/results.log | 604 +- jenkins/manifest.sh | 4 +- results | 2 +- results_id | 2 +- 44 files changed, 81473 insertions(+), 95395 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[binutils-gdb] branch master updated (a2a176c46bc -> c0abbd96b4d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from a2a176c46bc Fix pedantically invalid DWARF in gdb.trace/unavailable-dwa [...] new c0abbd96b4d gdb: fix {rs6000_nat_target,aix_thread_target}::wait to not [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gdb/aix-thread.c | 59 +++++++++++++++++++++++++--------------------------- gdb/rs6000-aix-nat.c | 7 +++---- 2 files changed, 31 insertions(+), 35 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_gnu_cross_build/master-aarch64 updated (8e9398e3b1 -> a74c66b1b9)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-aarch64 in repository toolchain/ci/qemu. from 8e9398e3b1 Merge tag 'pull-ppc-20220706' of https://gitlab.com/danielhb [...] adds c06fc7ce14 io_uring: fix short read slow path adds be6a166fde block/io_uring: clarify that short reads can happen adds a74c66b1b9 Merge tag 'block-pull-request' of https://gitlab.com/stefanh [...] No new revisions were added by this update. Summary of changes: block/io_uring.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[toolchain/ci/gdb] branch linaro-local/ci/tcwg_gnu_cross_build/master-aarch64 updated (1bb1f55d64 -> a2a176c46b)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-aarch64 in repository toolchain/ci/gdb. from 1bb1f55d64 gprofng: adjust GPROFNG_VARIANT adds 045f385d9a RISC-V: Added Zfhmin and Zhinxmin. adds 88de583569 gdb: LoongArch: Implement the push_dummy_call gdbarch method adds 309e147fbd GDB/testsuite: Add coverage for `print -elements' command adds 83f477f25a gdb: LoongArch: Fix typos in code comments adds a2a176c46b Fix pedantically invalid DWARF in gdb.trace/unavailable-dwar [...] No new revisions were added by this update. Summary of changes: bfd/elfxx-riscv.c | 97 ++-- .../gas/riscv/zfhmin-d-insn-class-fail-1.d | 3 + .../gas/riscv/zfhmin-d-insn-class-fail-1.l | 2 + .../gas/riscv/zfhmin-d-insn-class-fail-2.d | 3 + .../gas/riscv/zfhmin-d-insn-class-fail-2.l | 2 + .../gas/riscv/zfhmin-d-insn-class-fail-3.d | 3 + .../gas/riscv/zfhmin-d-insn-class-fail-3.l | 2 + .../gas/riscv/zfhmin-d-insn-class-fail-4.d | 3 + .../gas/riscv/zfhmin-d-insn-class-fail-4.l | 2 + .../gas/riscv/zfhmin-d-insn-class-fail-5.d | 3 + .../gas/riscv/zfhmin-d-insn-class-fail-5.l | 2 + gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s | 4 + .../gas/riscv/{fp-zhinx-insns.d => zhinx.d} | 35 +- .../gas/riscv/{fp-zhinx-insns.s => zhinx.s} | 32 +- gdb/loongarch-tdep.c | 596 +++++++++++++++++++++ gdb/loongarch-tdep.h | 2 + gdb/testsuite/gdb.base/printcmds.exp | 9 + .../gdb.trace/unavailable-dwarf-piece.exp | 4 +- include/opcode/riscv.h | 7 +- opcodes/riscv-opc.c | 126 ++--- 20 files changed, 792 insertions(+), 145 deletions(-) create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s rename gas/testsuite/gas/riscv/{fp-zhinx-insns.d => zhinx.d} (82%) rename gas/testsuite/gas/riscv/{fp-zhinx-insns.s => zhinx.s} (85%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu_cross_build/master-aarch64 updated (7922f5ee649 -> 9fc61fc8da9)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-aarch64 in repository toolchain/ci/gcc. from 7922f5ee649 Mips: Fix the ASAN shadow offset hook for the n32 ABI adds e5a9d603178 Speed up LC SSA rewrite adds 1e1fdb729d9 Speed up LC SSA rewrite more adds c1b1c4e58bd testsuite: Fix incorrect -mfloat128-type option adds 8bc24394376 target/106219 - proprly mark builtins pure via ix86_add_new [...] adds 99831ceb872 Adjust 'libgomp.c-c++-common/requires-3.c' adds 5647e2c3853 Enhance 'libgomp.c-c++-common/requires-4.c', 'libgomp.c-c++ [...] adds 9ef714539cb Fix Intel MIC 'mkoffload' for OpenMP 'requires' adds 9fc61fc8da9 Speedup update-ssa some more No new revisions were added by this update. Summary of changes: gcc/config/i386/i386-builtins.cc | 2 + gcc/config/i386/intelmic-mkoffload.cc | 56 +++++++--- gcc/testsuite/g++.dg/pr106219.C | 31 ++++++ .../gcc.target/powerpc/ppc-fortran/pr80108-1.f90 | 2 +- gcc/tree-into-ssa.cc | 36 ++++--- gcc/tree-ssa-loop-manip.cc | 119 +++++++++++++-------- libgomp/target.c | 4 + libgomp/testsuite/lib/libgomp.exp | 5 + .../testsuite/libgomp.c-c++-common/requires-1.c | 2 +- .../testsuite/libgomp.c-c++-common/requires-3.c | 2 +- .../testsuite/libgomp.c-c++-common/requires-4.c | 21 +++- .../testsuite/libgomp.c-c++-common/requires-5.c | 22 ++-- .../testsuite/libgomp.c-c++-common/requires-7.c | 2 +- libgomp/testsuite/libgomp.fortran/requires-1.f90 | 2 +- 14 files changed, 216 insertions(+), 90 deletions(-) create mode 100644 gcc/testsuite/g++.dg/pr106219.C -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_gnu_cross_build/master-aarch64 updated (1bb1f55d64 -> a2a176c46b)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-aarch64 in repository toolchain/ci/binutils-gdb. from 1bb1f55d64 gprofng: adjust GPROFNG_VARIANT adds 045f385d9a RISC-V: Added Zfhmin and Zhinxmin. adds 88de583569 gdb: LoongArch: Implement the push_dummy_call gdbarch method adds 309e147fbd GDB/testsuite: Add coverage for `print -elements' command adds 83f477f25a gdb: LoongArch: Fix typos in code comments adds a2a176c46b Fix pedantically invalid DWARF in gdb.trace/unavailable-dwar [...] No new revisions were added by this update. Summary of changes: bfd/elfxx-riscv.c | 97 ++-- .../gas/riscv/zfhmin-d-insn-class-fail-1.d | 3 + .../gas/riscv/zfhmin-d-insn-class-fail-1.l | 2 + .../gas/riscv/zfhmin-d-insn-class-fail-2.d | 3 + .../gas/riscv/zfhmin-d-insn-class-fail-2.l | 2 + .../gas/riscv/zfhmin-d-insn-class-fail-3.d | 3 + .../gas/riscv/zfhmin-d-insn-class-fail-3.l | 2 + .../gas/riscv/zfhmin-d-insn-class-fail-4.d | 3 + .../gas/riscv/zfhmin-d-insn-class-fail-4.l | 2 + .../gas/riscv/zfhmin-d-insn-class-fail-5.d | 3 + .../gas/riscv/zfhmin-d-insn-class-fail-5.l | 2 + gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s | 4 + .../gas/riscv/{fp-zhinx-insns.d => zhinx.d} | 35 +- .../gas/riscv/{fp-zhinx-insns.s => zhinx.s} | 32 +- gdb/loongarch-tdep.c | 596 +++++++++++++++++++++ gdb/loongarch-tdep.h | 2 + gdb/testsuite/gdb.base/printcmds.exp | 9 + .../gdb.trace/unavailable-dwarf-piece.exp | 4 +- include/opcode/riscv.h | 7 +- opcodes/riscv-opc.c | 126 ++--- 20 files changed, 792 insertions(+), 145 deletions(-) create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s rename gas/testsuite/gas/riscv/{fp-zhinx-insns.d => zhinx.d} (82%) rename gas/testsuite/gas/riscv/{fp-zhinx-insns.s => zhinx.s} (85%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu_cross_build/master-aarch64 updated (7b67e521 -> 222756e9)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-aarch64 in repository toolchain/ci/base-artifacts. discards 7b67e521 2: update: binutils-gcc-linux-glibc-gdb-qemu: 4 new 222756e9 2: update: binutils-gcc-linux-glibc-gdb-qemu: 4 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (7b67e521) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu_cross_build/master-a [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1644 -> 1684 bytes 02-prepare_abe/console.log.xz | Bin 2752 -> 2748 bytes 04-build_abe-binutils/console.log.xz | Bin 31172 -> 30896 bytes 05-build_abe-stage1/console.log.xz | Bin 73456 -> 72828 bytes 07-build_abe-linux/console.log.xz | Bin 8952 -> 8996 bytes 08-build_abe-glibc/console.log.xz | Bin 240048 -> 239924 bytes 09-build_abe-stage2/console.log.xz | Bin 160800 -> 160908 bytes 12-check_regression/console.log.xz | Bin 416 -> 416 bytes 13-update_baseline/console.log | 82 +++++++++++++++++------------------ jenkins/manifest.sh | 18 ++++---- 10 files changed, 50 insertions(+), 50 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-norov-defconfig updated (b2e9684fe4d1 -> dc969061c68e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-norov-defconfig in repository toolchain/ci/llvm-project. from b2e9684fe4d1 [RISCV] isel (shl (and X, C2), C) -> (slli (srliw X, C3), C3+C). adds 7fc4518f4a70 [MLIR] Rename FusePadOpWithLinalgConsumer -> FusePadOpWith [...] adds 23ee84f43201 [globalisel] Add test case for regbank selection. adds b0da3c6fa44b [VPlan] Move setDebugLocFromInst to VPTransformState (NFC). adds 5d787689b145 [RISCV] Match RISCVISD::ADD_LO in SelectAddrRegImm. adds 5148c685e3bb [mlir][complex] Inverse canonicalization between exp and log adds 7788b0c09754 [lsan] malloc_usable_size returns 0 for nullptr adds 7e4ab9d5b8b8 [RISCV] Add more SHXADD isel patterns. adds 1ecfc12b0c67 [Bazel] Make `builtin_headers_gen` as subset of CMake's `c [...] adds f7819ce166bc [FPEnv] Allow CompoundStmt to keep FP options adds 8679cbc29fb7 Reland "[NFC] Add a missing test for for clang-repl" adds 022bd92c78ed [LowerMatrixMultiplication] Switch dummy values from undef [...] adds 6956840b5c00 Revert "Reland "[NFC] Add a missing test for for clang-repl"" adds 0f45eaf0da1f [RISCV] Add a scavenge spill slot when use ADDI to compute [...] adds 53dc0f107877 [NFC] Switch a few uses of undef to poison as placeholders [...] adds d100a30a5406 [AArch64] Regenerate more tests. NFC adds d71a8bb157ea [MLIR][Affine] Allow affine-expr on RHS in IntegerSet adds 13d58ff9f373 [RISCV] Replace call to APInt::countTrailingZeros with uin [...] adds 2aea8af25136 [libc++] Make _LIBCPP_DEBUG_RANDOMIZE_RANGE a function adds e1f61d864214 [gn build] Port 2aea8af25136 adds c1c3134ac422 [InstCombine] add tests for and-of-negated-lowbitmask; NFC adds f9f40aa10d98 [InstCombine] fold negated low-bit-mask to cmp+select adds b1f0efc06acc [clang-format] Tweak help text a bit adds 134363208b92 [clang] Fix gcc-6 compilation error. (NFC) adds a65a3bffd31f [clang-tidy] Don't treat invalid branches as identical adds f7a80c3d08d4 [clang-tidy] Properly forward clang-tidy output when runni [...] adds 2c3784cff859 [SCEV] recognize llvm.annotation intrinsic adds e98e13ac8f38 [mlir][Vector] Fold ShuffleOp(SplatOp(X), SplatOp(X)) to S [...] adds d2a35e4d39fe [AIX] Handling the label alignment of a global variable wi [...] adds 93d6fdfc232c [Driver] Ignore the clang modules validation-related flags [...] adds 8eb4dcb73747 [RISCV] Move some SHXADD matching cases into a ComplexPatt [...] adds d36e09cfe591 [RISCV] Add more SHXADD patterns. adds 1063dfc02853 [mlir][openmp] Added omp.taskloop adds 7283f48a05de [IR] Remove support for insertvalue constant expression adds b4694229aa9d [LV] Simplify setDebugLocFromInst by using early exit (NFC). adds f0089fae1d7e [AArch64] Add additional tests for D120481. adds 7fbf55c927f2 [mlir][Tensor] Move ParallelInsertSlice to the tensor dialect adds 9604601c9394 [SimplifyCFG] Remove redundant checks for hoisting (NFCI) adds 4887d047a31f [libc++][NFC] Replace enable_if with __enable_if_t in a fe [...] adds 04f6bf482b86 Revise outdated parts of the developer policy. adds 5f0a054f8954 [pseudo] Remove duplicated code in ClangPseudo.cpp adds c9fb3c6ea6cc [mlir][Tensor] Update ParallelInsertSlicOp semantics to ma [...] adds f4dd977537dc [AST] Use canonical constraint declaration for ASTContext: [...] adds 42f5b0509ded [mlir][NFC] Fix various warnings generated by GCC 9 adds cce64e7a9cba [DAG] visitTRUNCATE - move GetDemandedBits AFTER SimplifyD [...] adds f90f0e8fe7f5 [AMDGPU][GFX10][DOC][NFC] Update assembler syntax description adds bf89d24f5319 [AArch64] NFC: Move safe predicate casting to a separate f [...] adds 740633ff08ff [flang] Add TODO for derived types with final procedure adds 4905bcac00e6 [ConstantFolding] Check return value of ConstantFoldInstOp [...] adds 8e70258b18ba [AMDGPUCodeGenPrepare] Check result of ConstantFoldBinaryO [...] adds 19a1e20b8a0f [VectorCombine] Improve shuffle select shuffle-of-shuffles adds 25607d143d1d [libc++] Implement `std::ranges::merge` adds 3912928aa891 [gn build] Port 25607d143d1d adds 32a76fc292d9 [SCEVExpander] Avoid ConstantExpr::get() (NFCI) adds 93cbdaef0455 [Reassociate] Avoid ConstantExpr::get() adds 2de05afc192d [SLP] Peek into loads when hitting the RecursionMaxDepth adds 2ab260eecfab [llvm-ar][test] Add additional MRI script testing adds 4e6c30c8354f [libc] Add a separate algorithm_test. adds d7697c175db9 [flang] Avoid segfault when defining op is not a fir::Convert adds f93cd56262d1 [BPI] Avoid ConstantExpr::get() adds aa78c5298ea3 Fix MLIR Python CMake bug causing duplicate sources target. adds 644a965c1efe [LV] Vectorize cases with larger number of RT checks, exec [...] adds c06d0b4d02ea [RISCV] Add ADDI instr for computing FrameIndex address adds c146af3f469a [LoopVectorize][NFC] Reinstate TTICapture workaround for gcc-6 adds 8471c6861992 [LTO] Update remark test after 644a965c1efef6. adds 89cb8cae606b [Bitcode] Use bitcode input for test (NFC) adds abbd684c02c7 [InstCombine] Avoid ConstantExpr::get() in phi binop fold adds 10ebaf76860e [SLP] add test for load combining + shuffling; NFC adds fdf505f3f223 [mlir][OpenMP] omp.task translation to LLVM IR adds 2bfca3561466 [X86] Disable combineVectorSizedSetCCEquality for soft float. adds 5785717e18d5 [AArch64] Add support for insert/extract for nxv1i1 types. adds 2fde26dfcabe [mlir][Linalg][NFC] Make getReassociationMapForFoldingUnit [...] adds 9eb657278611 [LV] Add back CantReorderMemOps remark. adds c3839c0b46a9 CombineContractBroadcast should not create dims unused in LHS+RHS adds bc70ba814dc1 Use add_llvm_install_targets for install-llvmlibc adds b37dafd5dc83 [pseudo] Store shift and goto actions in a compact structu [...] adds 12d26ce9b0ec [flang] Make code more homogenous in CodeGen adds 47bdf53a5dba [clang-format] Break on AfterColon only if not followed by [...] adds 1ab37d996ce3 [clang-format] Update documentation adds 2a82c15f63d4 [LV] Consider runtime checks profitable if scalar cost is zero. adds 623250b51139 [X86] Regenerate fold-tied-op.ll test checks adds a4e2c1f76295 [Orc][LLJIT] Use JITLink on RISC-V adds b6178ccfe852 [OffloadPackager] Use appropriate kind for LTO bitcode adds 4276d00b1253 [InstCombine] add helper function for sub-of-min/max folds; NFC adds 8ef053273abf [InstCombine] add tests for sub of smin/smax; NFC adds 142aca7741d5 [InstCombine] fold sub of min/max of sub with common operand adds b2b4c8721db0 [InstCombine] Make use of low zero bits to determine exact [...] adds 063500afc0b8 [RISCV][NFC] Merge the isolated decleration into foreach. adds 98c6a3c0c220 [NFC][ASTImporter] remove the unnecessary condition checks [...] adds 85318d328102 [NFC] Remove unused test inputs adds 939352b6ec31 [RISCV][Clang] Teach RISCVEmitter to generate BitCast for [...] adds 5b4851ed9113 [LoongArch] Add codegen support for load/store operations adds b940fe6fe2af [LoongArch] Add codegen support for conditional branches adds 3610d5f5d4c2 [LoongArch] Add initial support for function calls adds 0c01f42fad41 [llvm-objcopy] -O binary: align sh_offset for section chan [...] adds 3e01af093f92 [mlir] Add InferIntRangeInterface to gpu.launch adds 2028fe6fbca6 [lld-macho] Handle LOH_ARM64_ADRP_LDR_GOT optimization hints adds 4996e3f68315 [test] Check for more -fsanitize=array-bounds behavior adds 66790b70ea14 [RISCV] Rename some variables for clarity. NFC adds f27672924e36 [RISCV] Replace an explicit check with an assert. adds 7a550212e8ff [clang-tidy] Fix confusable identifiers interaction with D [...] adds b094c737cd85 [flang] Avoid opaque pointer issue with character array su [...] adds b69c75d53f8d Revert "[VectorCombine] Improve shuffle select shuffle-of- [...] adds 00927334df9a [libc++] Use __is_exactly_{input, forward}_iterator adds 0d0bd17fcfbd [libc++] Fix __split_buffer::__construct_at_end definition [...] adds 4de0680fbf4e Fix use of pointer arithmetic instead of iterators. adds df5c981be35a [mlir][Linalg] Add DropUnitDims support for tensor::Parall [...] adds 774fc6349093 [LV] Consider minimum vscale assmuption for RT check cost. adds dfb77f2e99a1 [LLD][ELF] Add FORCE_LLD_DIAGNOSTICS_CRASH to force LLD to crash adds 77b13a57a930 [AArch64][SME] Add SME addha/va intrinsics adds 00cb1c33ee2e [InstCombine] add negtive tests for (%x & C) == 0 -> %x u< [...] adds dc46ae6df5f7 [lldb] Add support to load object files from thin archives adds b6ad8cbb3575 [gn build] (manually) port dfb77f2e99a1 adds b66220f25aea [InstCombine] [NFC] use C.isNegatedPowerOf2() instead of ( [...] adds 220366d5b545 [gn build] (manually) port 6b3956e123db adds b43dd2f6c4a3 [InstCombine] improve fold for icmp_eq_and to icmp_ult adds 271b470f3f1a [IndVars] Precommit test with redundant FPToSI. adds f8e658ec9ff5 [OpenCL] Remove fast_ half geometric builtins adds f6fa9985900e Fix tests with non-default CLANG_DEFAULT_LINKER adds 1666f09933ee [ARM] Add Support for Cortex-M85 adds ba14e4d65cdd [LLDB] Disable TestGdbRemoteFork* for Arm/AArch64 Linux adds f03b876e7e95 Reland "Reland "[NFC] Add a missing test for for clang-repl"" adds 98e52e8bff52 [VE] Restructure eliminateFrameIndex adds 9ad38e5288a1 Revert "[VE] Restructure eliminateFrameIndex" adds 3897d3cf71ef [clang-tidy] By-pass portability issues in confusable-iden [...] adds bc366183a592 Correct XFAIL according to bot owner's advice adds da5a6b2bf574 [VE] Restructure eliminateFrameIndex adds 3b2496e8faae [LLDB] Skip TestTwoHitsOneActual.py on Arm/AArch64 Linux adds 989270628226 Updating office hours adds 3c043ab007a1 [MLIR][Affine] Allow `<=` in IntegerSet constraints adds b7b11091efd2 [LLDB] Fix decorator import in TestTwoHitsOneActual.py adds 04c5fed5e0c6 [NFC] Fix wrong comment. adds e6ff553979e8 [clang-extdef-mapping] Directly process .ast files adds 02ab87f54305 [SimplifyCFG] Add additional jump threading test (NFC) adds ebb78a95cede [LV] Remove stray dbgs() call after 774fc63490939. adds dc969061c68e [SimplifyCFG] Thread all predecessors with same value at once No new revisions were added by this update. Summary of changes: .../clang-tidy/bugprone/BranchCloneCheck.cpp | 11 + .../clang-tidy/misc/ConfusableIdentifierCheck.cpp | 70 +- clang-tools-extra/docs/ReleaseNotes.rst | 4 + .../pseudo/include/clang-pseudo/grammar/LRTable.h | 120 ++- clang-tools-extra/pseudo/lib/GLR.cpp | 16 +- clang-tools-extra/pseudo/lib/grammar/LRTable.cpp | 65 +- .../pseudo/lib/grammar/LRTableBuild.cpp | 61 +- clang-tools-extra/pseudo/tool/ClangPseudo.cpp | 48 +- clang-tools-extra/pseudo/unittests/LRTableTest.cpp | 2 +- .../test/clang-tidy/check_clang_tidy.py | 10 +- .../bugprone/branch-clone-unknown-expr.cpp | 9 + .../checkers/misc/confusable-identifiers.cpp | 96 ++- clang/docs/ClangFormat.rst | 84 ++- clang/docs/ReleaseNotes.rst | 11 + clang/include/clang/AST/ASTImportError.h | 1 - clang/include/clang/AST/JSONNodeDumper.h | 2 + clang/include/clang/AST/Stmt.h | 38 +- clang/include/clang/AST/TextNodeDumper.h | 1 + clang/include/clang/Basic/LangOptions.h | 13 + clang/include/clang/Basic/riscv_vector.td | 99 +-- clang/include/clang/Sema/ScopeInfo.h | 7 +- clang/include/clang/Support/RISCVVIntrinsicUtils.h | 2 + clang/lib/AST/ASTContext.cpp | 3 + clang/lib/AST/ASTImporter.cpp | 17 +- clang/lib/AST/Interp/ByteCodeExprGen.cpp | 2 +- clang/lib/AST/JSONNodeDumper.cpp | 15 + clang/lib/AST/Stmt.cpp | 24 +- clang/lib/AST/StmtPrinter.cpp | 62 ++ clang/lib/AST/TextNodeDumper.cpp | 6 + clang/lib/Analysis/BodyFarm.cpp | 3 +- clang/lib/Basic/LangOptions.cpp | 9 + clang/lib/CodeGen/CGCoroutine.cpp | 4 +- clang/lib/Driver/ToolChains/Clang.cpp | 63 +- clang/lib/Format/ContinuationIndenter.cpp | 4 +- clang/lib/Format/Format.cpp | 25 +- clang/lib/Format/TokenAnnotator.cpp | 8 +- clang/lib/Format/UnwrappedLineParser.cpp | 16 +- clang/lib/Headers/opencl-c.h | 18 - clang/lib/Sema/Sema.cpp | 3 +- clang/lib/Sema/SemaDeclCXX.cpp | 8 +- clang/lib/Sema/SemaExprCXX.cpp | 5 +- clang/lib/Sema/SemaOpenMP.cpp | 9 +- clang/lib/Sema/SemaStmt.cpp | 11 +- clang/lib/Serialization/ASTReaderStmt.cpp | 8 +- clang/lib/Serialization/ASTWriterStmt.cpp | 3 + clang/test/AST/ast-dump-fpfeatures.cpp | 46 ++ clang/test/AST/ast-dump-pragma-json.c | 485 +++++++++++++ clang/test/AST/ast-print-fp-pragmas.c | 69 ++ clang/test/Analysis/func-mapping-test.cpp | 2 + clang/test/CodeGen/arm-target-features.c | 3 + clang/test/CodeGen/bounds-checking-fam.c | 45 +- clang/test/Driver/arm-cortex-cpus-2.c | 3 + clang/test/Driver/arm-nofp-disabled-features.c | 2 + clang/test/Driver/arm-nopacbti-disabled-features.c | 7 + clang/test/Driver/instrprof-ld.c | 4 +- clang/test/Driver/modules.m | 30 +- clang/test/Frontend/optimization-remark-options.c | 2 +- clang/test/Interpreter/execute.cpp | 5 + clang/test/Misc/target-invalid-cpu-note.c | 2 +- clang/test/Modules/Inputs/concept/A.cppm | 3 - clang/test/Modules/Inputs/concept/foo.h | 13 - clang/test/Modules/concept.cppm | 50 +- .../clang-extdef-mapping/ClangExtDefMapGen.cpp | 101 ++- clang/tools/clang-format/ClangFormat.cpp | 10 +- clang/tools/clang-offload-packager/CMakeLists.txt | 1 + .../ClangOffloadPackager.cpp | 9 +- clang/unittests/Format/FormatTest.cpp | 19 + clang/utils/TableGen/RISCVVEmitter.cpp | 10 + compiler-rt/lib/lsan/lsan_allocator.cpp | 2 + .../TestCases/Linux/malloc_usable_size.c | 21 + flang/lib/Lower/ConvertType.cpp | 4 + flang/lib/Optimizer/Builder/FIRBuilder.cpp | 5 +- flang/lib/Optimizer/CodeGen/CodeGen.cpp | 77 +- flang/test/Fir/embox.fir | 2 +- flang/test/Lower/extent_triplets.f90 | 11 + libc/lib/CMakeLists.txt | 9 +- libc/test/src/string/memory_utils/CMakeLists.txt | 17 +- libcxx/docs/Status/RangesAlgorithms.csv | 10 +- libcxx/include/CMakeLists.txt | 2 + libcxx/include/__algorithm/nth_element.h | 11 +- libcxx/include/__algorithm/partial_sort.h | 9 +- libcxx/include/__algorithm/ranges_merge.h | 142 ++++ libcxx/include/__algorithm/sort.h | 7 +- libcxx/include/__debug | 16 - libcxx/include/__debug_utils/randomize_range.h | 42 ++ libcxx/include/__hash_table | 16 +- libcxx/include/__iterator/iterator_traits.h | 6 + libcxx/include/__mutex_base | 12 +- libcxx/include/__split_buffer | 26 +- libcxx/include/__tree | 32 +- libcxx/include/__tuple | 6 +- libcxx/include/algorithm | 18 + libcxx/include/array | 7 +- libcxx/include/deque | 18 +- libcxx/include/exception | 4 +- libcxx/include/forward_list | 42 +- libcxx/include/list | 16 +- libcxx/include/map | 52 +- libcxx/include/module.modulemap.in | 6 + libcxx/include/regex | 7 +- libcxx/include/tuple | 16 +- libcxx/include/unordered_map | 12 +- libcxx/include/vector | 64 +- ...ges_robust_against_copying_comparators.pass.cpp | 6 +- ...ges_robust_against_copying_projections.pass.cpp | 6 +- libcxx/test/libcxx/private_headers.verify.cpp | 2 + .../alg.sorting/alg.merge/ranges_merge.pass.cpp | 613 ++++++++++++++++ .../deque/deque.cons/assign_iter_iter.pass.cpp | 34 +- .../niebloid.compile.pass.cpp | 2 +- lld/MachO/Arch/ARM64.cpp | 16 +- lld/docs/ReleaseNotes.rst | 2 + lld/test/ELF/crash-report.test | 10 + lld/test/MachO/loh-adrp-ldr-got.s | 35 + lld/test/lit.cfg.py | 3 + lld/test/lit.site.cfg.py.in | 1 + lld/tools/lld/lld.cpp | 6 + .../BSD-Archive/ObjectContainerBSDArchive.cpp | 208 +++++- .../BSD-Archive/ObjectContainerBSDArchive.h | 22 +- lldb/test/API/functionalities/archives/Makefile | 11 +- .../functionalities/archives/TestBSDArchives.py | 7 + lldb/test/API/functionalities/archives/c.c | 11 + .../two_hits_one_actual/TestTwoHitsOneActual.py | 2 + lldb/test/API/lit.cfg.py | 4 + .../API/tools/lldb-server/TestGdbRemoteFork.py | 5 + .../tools/lldb-server/TestGdbRemoteForkNonStop.py | 5 + lldb/test/CMakeLists.txt | 1 + llvm/bindings/go/llvm/ir.go | 10 - llvm/bindings/ocaml/llvm/llvm.ml | 2 - llvm/bindings/ocaml/llvm/llvm.mli | 5 - llvm/bindings/ocaml/llvm/llvm_ocaml.c | 17 - llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst | 764 +++++++++---------- llvm/docs/AMDGPU/gfx10_hwreg.rst | 42 +- .../AMDGPU/{gfx10_opt.rst => gfx10_opt_0d447d.rst} | 4 +- .../AMDGPU/{gfx10_opt.rst => gfx10_opt_847aed.rst} | 2 +- ...soffset_c40a5a.rst => gfx10_soffset_73dae7.rst} | 6 +- ...soffset_59fade.rst => gfx10_soffset_d01a5c.rst} | 6 +- ...x10_vdata_c61803.rst => gfx10_vdata_0aba12.rst} | 4 +- ...x10_vdata_b2a787.rst => gfx10_vdata_16d321.rst} | 4 +- ...x10_vdata_325b78.rst => gfx10_vdata_35851e.rst} | 6 +- ...x10_vdata_87fb90.rst => gfx10_vdata_890652.rst} | 4 +- ...x10_vdata_4d8ecf.rst => gfx10_vdata_a9ff5a.rst} | 6 +- ...gfx10_vdst_48d3a8.rst => gfx10_vdst_2ea017.rst} | 6 +- ...gfx10_vdst_5d50a1.rst => gfx10_vdst_322561.rst} | 6 +- ...gfx10_vdst_5d50a1.rst => gfx10_vdst_709347.rst} | 4 +- llvm/docs/AMDGPU/gfx10_vdst_719833.rst | 21 - ...gfx10_vdst_a49b76.rst => gfx10_vdst_81a6ed.rst} | 4 +- ...gfx10_vdst_f47754.rst => gfx10_vdst_d71f1c.rst} | 4 +- ...gfx10_vdst_d7c57e.rst => gfx10_vdst_dd8a32.rst} | 4 +- llvm/docs/DeveloperPolicy.rst | 38 +- llvm/docs/GettingInvolved.rst | 5 + llvm/docs/LangRef.rst | 16 +- llvm/docs/ReleaseNotes.rst | 3 + llvm/include/llvm-c/Core.h | 3 - llvm/include/llvm/CodeGen/AsmPrinter.h | 7 +- llvm/include/llvm/IR/Constants.h | 11 - llvm/include/llvm/IR/IntrinsicsAArch64.td | 10 + llvm/include/llvm/Support/ARMTargetParser.def | 3 + .../Vectorize/LoopVectorizationLegality.h | 7 - llvm/lib/Analysis/BranchProbabilityInfo.cpp | 6 +- llvm/lib/Analysis/ConstantFolding.cpp | 8 +- llvm/lib/Analysis/MemoryBuiltins.cpp | 6 +- llvm/lib/Analysis/ScalarEvolution.cpp | 8 +- llvm/lib/AsmParser/LLParser.cpp | 28 +- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 3 - llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 91 ++- llvm/lib/CodeGen/PrologEpilogInserter.cpp | 2 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 24 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 9 +- .../lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h | 2 +- llvm/lib/ExecutionEngine/Orc/LLJIT.cpp | 5 +- llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 8 +- llvm/lib/IR/AsmWriter.cpp | 4 - llvm/lib/IR/Constants.cpp | 44 +- llvm/lib/IR/ConstantsContext.h | 60 +- llvm/lib/IR/Core.cpp | 12 - llvm/lib/ObjCopy/ELF/ELFObject.cpp | 7 +- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 113 ++- llvm/lib/Target/AArch64/AArch64ISelLowering.h | 8 + llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 59 +- llvm/lib/Target/AArch64/SMEInstrFormats.td | 34 + llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp | 4 +- llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 2 +- llvm/lib/Target/ARM/ARM.td | 7 + llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h | 4 + .../Target/LoongArch/LoongArchFloat32InstrInfo.td | 8 + .../Target/LoongArch/LoongArchFloat64InstrInfo.td | 8 + llvm/lib/Target/LoongArch/LoongArchFrameLowering.h | 6 + .../lib/Target/LoongArch/LoongArchISelLowering.cpp | 154 ++++ llvm/lib/Target/LoongArch/LoongArchISelLowering.h | 4 + llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp | 70 +- llvm/lib/Target/LoongArch/LoongArchInstrInfo.h | 10 + llvm/lib/Target/LoongArch/LoongArchInstrInfo.td | 143 +++- llvm/lib/Target/LoongArch/LoongArchMCInstLower.cpp | 24 +- .../lib/Target/LoongArch/LoongArchRegisterInfo.cpp | 24 +- llvm/lib/Target/NVPTX/NVPTXGenericToNVVM.cpp | 4 - llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 45 +- llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 65 +- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 175 +++-- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h | 12 +- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 6 +- llvm/lib/Target/RISCV/RISCVInstrInfo.h | 5 +- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 1 - llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 9 +- llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td | 36 +- llvm/lib/Target/RISCV/RISCVInstrInfoZb.td | 16 +- llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 2 +- llvm/lib/Target/VE/VERegisterInfo.cpp | 203 ++++-- llvm/lib/Target/X86/X86ISelLowering.cpp | 10 +- llvm/lib/Transforms/IPO/MergeFunctions.cpp | 2 +- llvm/lib/Transforms/IPO/PruneEH.cpp | 2 +- llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp | 2 +- .../Transforms/InstCombine/InstCombineAddSub.cpp | 78 +- .../Transforms/InstCombine/InstCombineAndOrXor.cpp | 10 + .../Transforms/InstCombine/InstCombineCalls.cpp | 2 +- .../Transforms/InstCombine/InstCombineCasts.cpp | 9 +- .../Transforms/InstCombine/InstCombineCompares.cpp | 11 +- .../InstCombine/InstructionCombining.cpp | 8 +- llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp | 2 +- llvm/lib/Transforms/Scalar/LoopDistribute.cpp | 2 +- llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp | 2 +- .../Transforms/Scalar/LowerMatrixIntrinsics.cpp | 28 +- llvm/lib/Transforms/Scalar/Reassociate.cpp | 21 +- .../Transforms/Scalar/TailRecursionElimination.cpp | 4 +- .../Transforms/Utils/ScalarEvolutionExpander.cpp | 3 +- llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 70 +- .../Vectorize/LoopVectorizationLegality.cpp | 1 - .../Vectorize/LoopVectorizationPlanner.h | 10 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 314 +++++--- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 14 +- llvm/lib/Transforms/Vectorize/VPlan.cpp | 24 + llvm/lib/Transforms/Vectorize/VPlan.h | 3 + .../ScalarEvolution/annotation-intrinsics.ll | 4 +- llvm/test/Assembler/insertextractvalue.ll | 28 - llvm/test/Assembler/insertvalue-invalid-type-1.ll | 7 - llvm/test/Assembler/unsupported-constexprs.ll | 17 +- .../Inputs/bitcode-parseconstant-delay-select.bc | Bin 0 -> 1420 bytes .../Bitcode/bitcode-parseconstant-delay-select.ll | 2 +- .../CodeGen/AArch64/global-merge-group-by-use.ll | 68 +- llvm/test/CodeGen/AArch64/sme-intrinsics-add.ll | 43 ++ .../CodeGen/AArch64/sve-extract-scalable-vector.ll | 336 +++++++++ .../AArch64/sve-fix-length-and-combine-512.ll | 36 +- llvm/test/CodeGen/AArch64/sve-fp-reduce.ll | 323 ++++---- llvm/test/CodeGen/AArch64/sve-insert-vector.ll | 668 +++++++++++++++++ llvm/test/CodeGen/AArch64/vector-gep.ll | 17 +- llvm/test/CodeGen/AArch64/vselect-ext.ll | 241 +++++- llvm/test/CodeGen/AArch64/win64_vararg.ll | 357 +++++---- llvm/test/CodeGen/AArch64/win64_vararg_float.ll | 197 +++-- llvm/test/CodeGen/AArch64/win64_vararg_float_cc.ll | 221 ++++-- llvm/test/CodeGen/ARM/build-attributes.ll | 19 + llvm/test/CodeGen/LoongArch/ir-instruction/br.ll | 358 +++++++++ llvm/test/CodeGen/LoongArch/ir-instruction/call.ll | 79 ++ .../CodeGen/LoongArch/ir-instruction/indirectbr.ll | 30 + .../CodeGen/LoongArch/ir-instruction/load-store.ll | 368 ++++++++++ llvm/test/CodeGen/PowerPC/aix-alias-alignment-2.ll | 79 ++ llvm/test/CodeGen/PowerPC/aix-alias-alignment.ll | 74 ++ llvm/test/CodeGen/PowerPC/aix-alias.ll | 16 +- llvm/test/CodeGen/RISCV/rv64zba.ll | 88 ++- .../RISCV/rvv/access-fixed-objects-by-rvv.ll | 16 +- .../CodeGen/RISCV/rvv/addi-rvv-stack-object.mir | 60 ++ llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll | 98 +-- llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll | 62 +- llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll | 162 ++--- llvm/test/CodeGen/RISCV/rvv/calling-conv.ll | 18 +- llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll | 24 - llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll | 12 - llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll | 24 - .../CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll | 16 +- .../RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll | 111 ++- .../RISCV/rvv/fixed-vectors-calling-conv.ll | 301 ++++---- .../CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll | 148 ++-- .../CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll | 36 +- .../RISCV/rvv/fixed-vectors-insert-subvector.ll | 5 +- .../CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll | 10 +- .../RISCV/rvv/fixed-vectors-mask-buildvec.ll | 24 +- .../RISCV/rvv/fixed-vectors-masked-gather.ll | 112 +-- .../RISCV/rvv/fixed-vectors-masked-scatter.ll | 122 ++-- .../RISCV/rvv/fixed-vectors-reduction-int-vp.ll | 32 +- .../RISCV/rvv/fixed-vectors-reduction-int.ll | 24 +- .../RISCV/rvv/fixed-vectors-setcc-int-vp.ll | 36 +- .../CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll | 16 +- .../CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll | 16 +- .../CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll | 16 +- .../CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll | 16 +- .../CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll | 16 +- .../test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll | 16 +- .../CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll | 8 +- .../CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll | 16 +- .../CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll | 16 +- .../CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll | 8 +- .../test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll | 8 +- .../test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll | 8 +- .../CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll | 16 +- .../CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll | 3 +- llvm/test/CodeGen/RISCV/rvv/localvar.ll | 68 +- llvm/test/CodeGen/RISCV/rvv/masked-tama.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/memory-args.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll | 19 +- llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll | 60 +- llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir | 22 +- llvm/test/CodeGen/RISCV/rvv/scalar-stack-align.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll | 72 +- llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll | 40 +- llvm/test/CodeGen/RISCV/rvv/stepvector.ll | 7 +- llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll | 10 +- llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll | 18 +- llvm/test/CodeGen/RISCV/rvv/vaadd.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vaaddu.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vadd.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vand-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vasub.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vasubu.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll | 8 +- .../test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll | 18 +- llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll | 18 +- llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vmul.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vmulh.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vmulhu.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vor-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll | 60 +- llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vrsub.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vsub.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll | 16 +- .../test/CodeGen/RISCV/srem-seteq-illegal-types.ll | 74 +- .../test/CodeGen/RISCV/urem-seteq-illegal-types.ll | 4 +- llvm/test/CodeGen/VE/Scalar/load_stk.ll | 795 ++++++++++++++++++++ llvm/test/CodeGen/VE/Scalar/store_stk.ll | 808 +++++++++++++++++++++ llvm/test/CodeGen/X86/fold-tied-op.ll | 119 ++- llvm/test/CodeGen/X86/nonconst-static-iv.ll | 8 - llvm/test/CodeGen/X86/pr56351.ll | 18 + llvm/test/DebugInfo/AArch64/debug-reg-bank.ll | 43 ++ llvm/test/DebugInfo/X86/debug-reg-bank.ll | 43 ++ llvm/test/LTO/X86/diagnostic-handler-remarks.ll | 4 +- .../dfa-jump-threading-transform.ll | 4 +- .../DFAJumpThreading/dfa-unfold-select.ll | 6 +- .../Transforms/IndVarSimplify/floating-point-iv.ll | 34 + llvm/test/Transforms/InstCombine/and.ll | 60 ++ .../InstCombine/lshr-and-negC-icmpeq-zero.ll | 52 +- .../Transforms/InstCombine/sadd-with-overflow.ll | 2 +- llvm/test/Transforms/InstCombine/sitofp.ll | 31 +- .../Transforms/InstCombine/ssub-with-overflow.ll | 2 +- llvm/test/Transforms/InstCombine/sub-minmax.ll | 145 +++- .../Transforms/InstCombine/uadd-with-overflow.ll | 2 +- llvm/test/Transforms/InstCombine/with_overflow.ll | 30 +- .../AArch64/runtime-check-size-based-threshold.ll | 18 +- .../AArch64/sve-tail-folding-forced.ll | 2 +- .../AArch64/sve-tail-folding-unroll.ll | 4 +- .../LoopVectorize/AArch64/sve-tail-folding.ll | 22 +- .../Transforms/LoopVectorize/X86/gather_scatter.ll | 2 +- .../X86/pointer-runtime-checks-unprofitable.ll | 60 +- llvm/test/Transforms/LoopVectorize/X86/pr23997.ll | 2 +- llvm/test/Transforms/LoopVectorize/X86/pr35432.ll | 2 +- llvm/test/Transforms/LoopVectorize/X86/pr54634.ll | 2 +- .../Transforms/LoopVectorize/X86/runtime-limit.ll | 22 +- .../bigger-expressions-double.ll | 12 +- .../multiply-right-transpose.ll | 4 +- .../LowerMatrixIntrinsics/propagate-backward.ll | 12 +- .../propagate-backwards-unsupported.ll | 18 +- .../LowerMatrixIntrinsics/propagate-forward.ll | 16 +- .../LowerMatrixIntrinsics/propagate-mixed-users.ll | 8 +- .../propagate-multiple-iterations.ll | 8 +- .../transpose-double-row-major.ll | 18 +- .../LowerMatrixIntrinsics/transpose-double.ll | 26 +- .../transpose-float-row-major.ll | 18 +- .../LowerMatrixIntrinsics/transpose-float.ll | 26 +- .../transpose-i32-row-major.ll | 18 +- .../LowerMatrixIntrinsics/transpose-i32.ll | 26 +- .../transpose-opts-iterator-invalidation.ll | 4 +- .../LowerMatrixIntrinsics/transpose-opts.ll | 12 +- .../MergeFunc/mergefunc-struct-return.ll | 2 +- .../Transforms/SLPVectorizer/AArch64/loadorder.ll | 151 ++-- .../X86/load-partial-vector-shuffle.ll | 73 ++ llvm/test/Transforms/SimplifyCFG/jump-threading.ll | 96 +++ llvm/test/Transforms/SimplifyCFG/pr55765.ll | 21 +- .../2010-06-26-MultipleReturnValues.ll | 6 +- .../Transforms/TailCallElim/accum_recursion.ll | 2 +- llvm/test/Transforms/TailCallElim/basic.ll | 2 +- .../Transforms/WholeProgramDevirt/expand-check.ll | 2 +- llvm/test/tools/llvm-ar/Inputs/mri-crlf.mri | 2 + llvm/test/tools/llvm-ar/mri-crlf.test | 9 +- llvm/test/tools/llvm-ar/mri-delete.test | 188 ++++- llvm/test/tools/llvm-ar/mri-end.test | 140 ++-- llvm/test/tools/llvm-ar/mri-nonascii.test | 37 +- .../tools/llvm-objcopy/ELF/binary-no-paddr.test | 22 +- llvm/test/tools/llvm-objcopy/ELF/binary-paddr.test | 40 + llvm/unittests/Support/TargetParserTest.cpp | 8 +- llvm/utils/UpdateTestChecks/asm.py | 3 +- llvm/utils/gn/secondary/libcxx/include/BUILD.gn | 2 + llvm/utils/gn/secondary/lld/test/BUILD.gn | 1 + .../gn/secondary/llvm/tools/llvm-reduce/BUILD.gn | 1 + mlir/cmake/modules/AddMLIRPython.cmake | 2 +- mlir/docs/Dialects/Affine.md | 5 +- mlir/include/mlir/Dialect/Complex/IR/ComplexOps.td | 4 + mlir/include/mlir/Dialect/GPU/IR/GPUDialect.h | 1 + mlir/include/mlir/Dialect/GPU/IR/GPUOps.td | 21 +- mlir/include/mlir/Dialect/Linalg/Utils/Utils.h | 9 + mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td | 180 ++++- .../mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td | 2 +- mlir/include/mlir/Dialect/SCF/IR/SCFOps.td | 109 --- mlir/include/mlir/Dialect/Tensor/IR/Tensor.h | 1 + mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td | 149 ++++ mlir/include/mlir/Dialect/Vector/IR/VectorOps.td | 1 + mlir/include/mlir/IR/AffineMap.h | 6 + mlir/lib/Dialect/Affine/IR/AffineOps.cpp | 2 +- mlir/lib/Dialect/Complex/IR/ComplexOps.cpp | 28 + mlir/lib/Dialect/GPU/CMakeLists.txt | 2 + .../Dialect/GPU/IR/InferIntRangeInterfaceImpls.cpp | 97 +++ mlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt | 2 +- .../lib/Dialect/Linalg/Transforms/DropUnitDims.cpp | 75 +- ...onsumer.cpp => FusePadOpWithLinalgProducer.cpp} | 2 +- mlir/lib/Dialect/Linalg/Utils/Utils.cpp | 28 + mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp | 55 +- mlir/lib/Dialect/SCF/IR/CMakeLists.txt | 1 - mlir/lib/Dialect/SCF/IR/SCF.cpp | 143 +--- .../SCF/Transforms/BufferizableOpInterfaceImpl.cpp | 246 +------ mlir/lib/Dialect/Tensor/IR/CMakeLists.txt | 1 + mlir/lib/Dialect/Tensor/IR/TensorOps.cpp | 256 +++++-- .../Transforms/BufferizableOpInterfaceImpl.cpp | 244 +++++++ mlir/lib/Dialect/Vector/IR/VectorOps.cpp | 37 +- .../Dialect/Vector/Transforms/VectorTransforms.cpp | 21 +- mlir/lib/ExecutionEngine/OptUtils.cpp | 2 +- mlir/lib/ExecutionEngine/SparseTensorUtils.cpp | 2 +- mlir/lib/IR/AffineMap.cpp | 19 +- mlir/lib/Parser/AffineParser.cpp | 54 +- .../Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp | 27 + mlir/test/Dialect/Complex/canonicalize.mlir | 20 + mlir/test/Dialect/GPU/int-range-interface.mlir | 128 ++++ .../test/Dialect/Linalg/drop-unit-extent-dims.mlir | 20 + mlir/test/Dialect/OpenMP/invalid.mlir | 125 ++++ mlir/test/Dialect/OpenMP/ops.mlir | 142 +++- mlir/test/Dialect/SCF/canonicalize.mlir | 25 - .../SCF/foreach-thread-canonicalization.mlir | 50 +- mlir/test/Dialect/SCF/invalid.mlir | 8 +- .../one-shot-bufferize-tensor-copy-insertion.mlir | 4 +- mlir/test/Dialect/SCF/one-shot-bufferize.mlir | 6 +- mlir/test/Dialect/SCF/ops.mlir | 4 +- mlir/test/Dialect/Tensor/canonicalize.mlir | 27 + mlir/test/Dialect/Vector/canonicalize.mlir | 14 + mlir/test/Dialect/Vector/invalid.mlir | 2 +- .../Dialect/Vector/vector-reduce-to-contract.mlir | 35 + mlir/test/IR/affine-set.mlir | 113 +++ mlir/test/IR/invalid.mlir | 24 +- mlir/test/Target/LLVMIR/openmp-llvm.mlir | 88 +++ utils/bazel/llvm-project-overlay/clang/BUILD.bazel | 6 +- utils/bazel/llvm-project-overlay/mlir/BUILD.bazel | 4 + 515 files changed, 14616 insertions(+), 5385 deletions(-) create mode 100644 clang-tools-extra/test/clang-tidy/checkers/bugprone/branch-clon [...] create mode 100644 clang/test/AST/ast-dump-pragma-json.c create mode 100644 clang/test/AST/ast-print-fp-pragmas.c create mode 100644 clang/test/Driver/arm-nopacbti-disabled-features.c delete mode 100644 clang/test/Modules/Inputs/concept/A.cppm delete mode 100644 clang/test/Modules/Inputs/concept/foo.h create mode 100644 compiler-rt/test/sanitizer_common/TestCases/Linux/malloc_usable_size.c create mode 100644 flang/test/Lower/extent_triplets.f90 create mode 100644 libcxx/include/__algorithm/ranges_merge.h create mode 100644 libcxx/include/__debug_utils/randomize_range.h create mode 100644 libcxx/test/std/algorithms/alg.sorting/alg.merge/ranges_merge.pass.cpp create mode 100644 lld/test/ELF/crash-report.test create mode 100644 lld/test/MachO/loh-adrp-ldr-got.s create mode 100644 lldb/test/API/functionalities/archives/c.c copy llvm/docs/AMDGPU/{gfx10_opt.rst => gfx10_opt_0d447d.rst} (83%) rename llvm/docs/AMDGPU/{gfx10_opt.rst => gfx10_opt_847aed.rst} (91%) rename llvm/docs/AMDGPU/{gfx10_soffset_c40a5a.rst => gfx10_soffset_73dae7.rst} (72%) rename llvm/docs/AMDGPU/{gfx10_soffset_59fade.rst => gfx10_soffset_d01a5c.rst} (61%) rename llvm/docs/AMDGPU/{gfx10_vdata_c61803.rst => gfx10_vdata_0aba12.rst} (80%) rename llvm/docs/AMDGPU/{gfx10_vdata_b2a787.rst => gfx10_vdata_16d321.rst} (80%) rename llvm/docs/AMDGPU/{gfx10_vdata_325b78.rst => gfx10_vdata_35851e.rst} (81%) rename llvm/docs/AMDGPU/{gfx10_vdata_87fb90.rst => gfx10_vdata_890652.rst} (80%) rename llvm/docs/AMDGPU/{gfx10_vdata_4d8ecf.rst => gfx10_vdata_a9ff5a.rst} (81%) rename llvm/docs/AMDGPU/{gfx10_vdst_48d3a8.rst => gfx10_vdst_2ea017.rst} (76%) copy llvm/docs/AMDGPU/{gfx10_vdst_5d50a1.rst => gfx10_vdst_322561.rst} (71%) rename llvm/docs/AMDGPU/{gfx10_vdst_5d50a1.rst => gfx10_vdst_709347.rst} (76%) delete mode 100644 llvm/docs/AMDGPU/gfx10_vdst_719833.rst rename llvm/docs/AMDGPU/{gfx10_vdst_a49b76.rst => gfx10_vdst_81a6ed.rst} (75%) rename llvm/docs/AMDGPU/{gfx10_vdst_f47754.rst => gfx10_vdst_d71f1c.rst} (75%) rename llvm/docs/AMDGPU/{gfx10_vdst_d7c57e.rst => gfx10_vdst_dd8a32.rst} (75%) delete mode 100644 llvm/test/Assembler/insertvalue-invalid-type-1.ll create mode 100644 llvm/test/Bitcode/Inputs/bitcode-parseconstant-delay-select.bc create mode 100644 llvm/test/CodeGen/AArch64/sme-intrinsics-add.ll create mode 100644 llvm/test/CodeGen/LoongArch/ir-instruction/br.ll create mode 100644 llvm/test/CodeGen/LoongArch/ir-instruction/call.ll create mode 100644 llvm/test/CodeGen/LoongArch/ir-instruction/indirectbr.ll create mode 100644 llvm/test/CodeGen/LoongArch/ir-instruction/load-store.ll create mode 100644 llvm/test/CodeGen/PowerPC/aix-alias-alignment-2.ll create mode 100644 llvm/test/CodeGen/PowerPC/aix-alias-alignment.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir create mode 100644 llvm/test/CodeGen/VE/Scalar/load_stk.ll create mode 100644 llvm/test/CodeGen/VE/Scalar/store_stk.ll delete mode 100644 llvm/test/CodeGen/X86/nonconst-static-iv.ll create mode 100644 llvm/test/CodeGen/X86/pr56351.ll create mode 100644 llvm/test/DebugInfo/AArch64/debug-reg-bank.ll create mode 100644 llvm/test/DebugInfo/X86/debug-reg-bank.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/load-partial-vector-shuffle.ll create mode 100644 mlir/lib/Dialect/GPU/IR/InferIntRangeInterfaceImpls.cpp rename mlir/lib/Dialect/Linalg/Transforms/{FusePadOpWithLinalgConsumer.cpp => Fuse [...] create mode 100644 mlir/test/Dialect/GPU/int-range-interface.mlir create mode 100644 mlir/test/IR/affine-set.mlir -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-norov-defconfig updated (87410259 -> bb5f78b6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-norov-defconfig in repository toolchain/ci/base-artifacts. from 87410259 0: update: qemu-180c2f24d5e8eada41e012a3899d29bb695aae06: boot new bb5f78b6 1: reset: llvm-dc969061c68e62328607d68215ed8b9ef4a1e4b1: 7318 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1680 -> 1616 bytes 02-prepare_abe/console.log.xz | Bin 2744 -> 2748 bytes 03-build_abe-binutils/console.log.xz | Bin 30176 -> 30420 bytes 04-build_kernel_llvm/console.log.xz | Bin 65824 -> 64200 bytes 05-build_abe-qemu/console.log.xz | Bin 32216 -> 33688 bytes 06-build_linux/console.log.xz | Bin 5472 -> 15620 bytes 07-boot_linux/console.log.xz | Bin 6232 -> 0 bytes 08-check_regression/console.log.xz | Bin 412 -> 1320 bytes 08-check_regression/jira-body.txt | 2 ++ 08-check_regression/mail-body.txt | 41 ++++++++++++++++++++++ 08-check_regression/mail-subject.txt | 1 + 08-check_regression/results.regressions | 11 ++++++ 08-check_regression/trigger-bisect | 2 ++ 09-update_baseline/console.log | 59 ++++++++++++++++++++++++-------- 09-update_baseline/results.regressions | 2 ++ jenkins/manifest.sh | 10 +++--- mail/jira-body.txt | 5 +++ mail/mail-body.txt | 44 ++++++++++++++++++++++++ mail/mail-subject.txt | 1 + reset-baseline | 0 results | 17 ++++++--- 21 files changed, 170 insertions(+), 25 deletions(-) delete mode 100644 07-boot_linux/console.log.xz create mode 100644 08-check_regression/jira-body.txt create mode 100644 08-check_regression/mail-body.txt create mode 100644 08-check_regression/mail-subject.txt create mode 100644 08-check_regression/results.regressions create mode 100644 08-check_regression/trigger-bisect create mode 100644 09-update_baseline/results.regressions create mode 100644 mail/jira-body.txt create mode 100644 mail/mail-body.txt create mode 100644 mail/mail-subject.txt create mode 100644 reset-baseline -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

Tcwg-commits July 2022