Tcwg-commits January 2022

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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk_gnu_eabi_stm32/gnu_eabi-release-arm_eabi-coremark-O3 updated (eff746d33 -> 383495351)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_gnu_eabi_stm32/gnu_eabi-release-arm_eabi-coremark-O3 in repository toolchain/ci/base-artifacts. discards eff746d33 0: update: gcc-ce3954262a621d95ca794ebbdb28cca76e867288: 1 new 383495351 0: update: binutils-5f62caec8175cf80a29f2bcab2c5077cbfae8c89: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (eff746d33) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_bmk_gnu_eabi_stm32/gnu_e [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1524 -> 1624 bytes 02-prepare_abe/console.log.xz | Bin 2756 -> 2764 bytes 03-build_abe-binutils/console.log.xz | Bin 40480 -> 41144 bytes 04-build_abe-stage1/console.log.xz | Bin 83192 -> 84756 bytes 05-clean_sysroot/console.log.xz | Bin 336 -> 336 bytes 06-build_abe-newlib/console.log.xz | Bin 17264 -> 17484 bytes 07-build_abe-stage2/console.log.xz | Bin 157564 -> 158808 bytes 08-benchmark/benchmark-build.log | 36 +++++++++---------- 08-benchmark/benchmark.log | 34 +++++++++--------- 08-benchmark/console.log.xz | Bin 3072 -> 3064 bytes 09-check_regression/console.log.xz | Bin 1648 -> 1644 bytes 09-check_regression/results.log | 36 +++++++++---------- 10-update_baseline/console.log | 66 +++++++++++++++++------------------ 10-update_baseline/results.log | 36 +++++++++---------- jenkins/manifest.sh | 8 ++--- results | 2 +- results_id | 2 +- 17 files changed, 110 insertions(+), 110 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 7 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allmodconfig updated (47fa1ad534 -> aeb0ae95b7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allmodconfig in repository toolchain/ci/qemu. from 47fa1ad534 Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-7 [...] adds 95ea96e8b1 hw/arm/virt: KVM: Enable PAuth when supported by the host adds 9adfbf1b61 hw: Move MARVELL_88W8618 Kconfig from audio/ to arm/ adds 8ede0245e2 hw/arm/musicpal: Fix coding style of code related to MV88W86 [...] adds 6d81f4887f hw/net: Move MV88W8618 network device out of hw/arm/ directory adds d55c316f91 hw/arm/virt: Support CPU cluster on ARM virt machine adds 28a60a59c0 hw/arm/virt: Support cluster level in DT cpu-map adds 11b9eb1b8a hw/acpi/aml-build: Improve scalability of PPTT generation adds 291f6dd566 tests/acpi/bios-tables-test: Allow changes to virt/PPTT file adds 88d0278aa7 hw/acpi/aml-build: Support cluster level in PPTT generation adds 3cda85b203 tests/acpi/bios-table-test: Update expected virt/PPTT file adds 87f14eaa51 docs/can: convert to restructuredText adds 1263615efe virtio-mem: Correct default THP size for ARM64 adds b1b87327a9 hw/arm/virt: Support for virtio-mem-pci adds a66a24585f hw/intc/arm_gic: Implement read of GICC_IIDR adds 5e66daec9e hw/intc/arm_gic: Allow reset of the running priority adds c8f008c40f hw/arm/virt: Add a control for the the highmem PCIe MMIO adds a63618b147 hw/arm/virt: Add a control for the the highmem redistributors adds 0152b169ce hw/arm/virt: Honor highmem setting when computing the memory map adds 3715c251cc hw/arm/virt: Use the PA range to compute the memory map adds d9afe24c29 hw/arm/virt: Disable highmem devices that don't fit in the PA range adds 2dcb74e5c2 hw/arm/virt: Drop superfluous checks against highmem adds 0419e6a867 hw/arm: kudo add lm75s behind bus 1 switch at 75 adds 119df56bf0 hw/misc/aspeed_i3c.c: Introduce a dummy AST2600 I3C model. adds 3222165dcb hw/arm/aspeed: Add the i3c device to the AST2600 SoC adds 8f809f6992 hw/intc/arm_gicv3_its: Fix event ID bounds checks adds 905720f18d hw/intc/arm_gicv3_its: Convert int ID check to num_intids co [...] adds 7d62b2dcdb hw/intc/arm_gicv3_its: Fix handling of process_its_cmd() ret [...] adds f0b4b2a28c hw/intc/arm_gicv3_its: Don't use data if reading command failed adds ef011555da hw/intc/arm_gicv3_its: Use enum for return value of process_ [...] adds 593a7cc2d3 hw/intc/arm_gicv3_its: Fix return codes in process_its_cmd() adds be0ed8fb7f hw/intc/arm_gicv3_its: Refactor process_its_cmd() to reduce nesting adds 0241f73160 hw/intc/arm_gicv3_its: Fix return codes in process_mapti() adds f667519614 hw/intc/arm_gicv3_its: Fix return codes in process_mapc() adds 00d46e72e9 hw/intc/arm_gicv3_its: Fix return codes in process_mapd() adds d050f80f8c hw/intc/arm_gicv3_its: Factor out "find address of table ent [...] adds b13148d918 hw/intc/arm_gicv3_its: Check indexes before use, not after adds 58b88779f0 hw/intc/arm_gicv3_its: Range-check ICID before indexing into [...] adds b9d383ab79 hw/intc/arm_gicv3: Check for !MEMTX_OK instead of MEMTX_ERROR adds 2c89b5af5e Merge remote-tracking branch 'remotes/pmaydell/tags/pull-tar [...] adds 28ca4689ae hw: timer: ibex_timer: Fixup reading w/o register adds 0df470c388 riscv: opentitan: fixup plic stride len adds dda94e5c66 hw: timer: ibex_timer: update/add reg address adds b91a0fa70c update-linux-headers: Add asm-riscv/kvm.h adds 91654e613b target/riscv: Add target/riscv/kvm.c to place the public kvm [...] adds 0a312b85cb target/riscv: Implement function kvm_arch_init_vcpu adds 937f0b4512 target/riscv: Implement kvm_arch_get_registers adds 9997cc1e19 target/riscv: Implement kvm_arch_put_registers adds ad40be2708 target/riscv: Support start kernel directly by KVM adds 2b650fbbcc target/riscv: Support setting external interrupt by KVM adds 4eb471258b target/riscv: Handle KVM_EXIT_RISCV_SBI exit adds 10f1ca27e0 target/riscv: Add host cpu type adds 27abe66f31 target/riscv: Add kvm_riscv_get/put_regs_timer adds 9ad3e016ae target/riscv: Implement virtual time adjusting with vm state [...] adds 1eb9a5da31 target/riscv: Support virtual time context synchronization adds fbf43c7dbf target/riscv: enable riscv kvm accel adds cfeeeb482a softmmu/device_tree: Silence compiler warning with --enable- [...] adds 22599b795c softmmu/device_tree: Remove redundant pointer assignment adds b4a99d4027 target/riscv: rvv-1.0: Add Zve64f extension into RISC-V adds c7a26fb2f6 target/riscv: rvv-1.0: Add Zve64f support for configuration insns adds 494104093f target/riscv: rvv-1.0: Add Zve64f support for load and store insns adds aaae69942f target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns adds 13dbc826fd target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and v [...] adds 40d78c85f6 target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns adds 193fb5c9bd target/riscv: rvv-1.0: Add Zve64f support for single-width f [...] adds 235d1161d4 target/riscv: rvv-1.0: Add Zve64f support for widening type- [...] adds 68fa38970e target/riscv: rvv-1.0: Add Zve64f support for narrowing type [...] adds bfefe406b7 target/riscv: rvv-1.0: Allow Zve64f extension to be turned on adds 32e579b8c5 target/riscv: rvv-1.0: Add Zve32f extension into RISC-V adds da61f1256f target/riscv: rvv-1.0: Add Zve32f support for configuration insns adds abe2d74032 target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns adds 8527b5db72 target/riscv: rvv-1.0: Add Zve32f support for single-width f [...] adds f4dcf51cdc target/riscv: rvv-1.0: Add Zve32f support for widening type- [...] adds 6db02328a7 target/riscv: rvv-1.0: Add Zve32f support for narrowing type [...] adds 2fc1b44dd0 target/riscv: rvv-1.0: Allow Zve32f extension to be turned on adds 8d8897accb hw/riscv: spike: Allow using binary firmware as bios adds 092dc6df92 hw/riscv: Remove macros for ELF BIOS image names adds 4211fc5532 roms/opensbi: Remove ELF images adds 79f26b3b95 target/riscv: Adjust pmpcfg access with mxl adds b655dc7cd9 target/riscv: Don't save pc when exception return adds a14db52f7f target/riscv: Sign extend link reg for jal and jalr adds 40f0c2046c target/riscv: Sign extend pc for different XLEN adds 440544e1cf target/riscv: Create xl field in env adds 8c796f1a15 target/riscv: Ignore the pc bits above XLEN adds bf9e776ec1 target/riscv: Extend pc for runtime pc write adds 1191be09a9 target/riscv: Use gdb xml according to max mxlen adds 47bdec821b target/riscv: Relax debug check for pm write adds 83b519b8a4 target/riscv: Adjust csr write mask with XLEN adds 40bfa5f695 target/riscv: Create current pm fields in env adds 0cff460de9 target/riscv: Alloc tcg global for cur_pm[mask|base] adds 4302bef9e1 target/riscv: Calculate address according to XLEN adds 4208dc7e9e target/riscv: Split pm_enabled into mask and base adds d96a271a8d target/riscv: Split out the vill from vtype adds 31961cfe50 target/riscv: Adjust vsetvl according to XLEN adds eef11ce325 target/riscv: Remove VILL field in VTYPE adds 01d09525da target/riscv: Fix check range for first fault only adds d6b9d93023 target/riscv: Adjust vector address with mask adds d8c40c24fd target/riscv: Adjust scalar reg in vector with XLEN adds 5a2ae2350e target/riscv: Set default XLEN for hypervisor adds f310df58bd target/riscv: Enable uxl field write adds f297245f6a target/riscv: Relax UXL field for debugging adds 5e9d14f2be Merge remote-tracking branch 'remotes/alistair/tags/pull-ris [...] adds 1e4d8b31be python: pin setuptools below v60.0.0 adds 57a6b4478c python: use avocado's "new" runner adds dc6877bd2e python/aqmp: fix docstring typo adds 3bc72e3aed python/aqmp: add __del__ method to legacy interface adds 3b5bf136f5 python/aqmp: handle asyncio.TimeoutError on execute() adds 0e6bfd8b96 python/aqmp: copy type definitions from qmp adds 728dcac5e3 python/aqmp: add SocketAddrT to package root adds 6e7751dc38 python/aqmp: rename AQMPError to QMPError adds 7017f3853a python/qemu-ga-client: don't use deprecated CLI syntax in us [...] adds 26db07516f python/qmp: switch qemu-ga-client to AQMP adds 8d6cdc5118 python/qmp: switch qom tools to AQMP adds f3efd12930 python/qmp: switch qmp-shell to AQMP adds 0347c4c4cf python: move qmp utilities to python/qemu/utils adds fd9c3a6219 python: move qmp-shell under the AQMP package adds 9922125615 scripts/cpu-x86-uarch-abi: fix CLI parsing adds 0665410dcf scripts/cpu-x86-uarch-abi: switch to AQMP adds 0590860242 scripts/render-block-graph: switch to AQMP adds aeb0ae95b7 Merge remote-tracking branch 'remotes/jsnow-gitlab/tags/pyth [...] No new revisions were added by this update. Summary of changes: .gitlab-ci.d/opensbi.yml | 2 - MAINTAINERS | 2 + docs/system/arm/cpu-features.rst | 4 - docs/system/device-emulation.rst | 1 + docs/{can.txt => system/devices/can.rst} | 92 ++--- hw/acpi/aml-build.c | 68 +++- hw/arm/Kconfig | 4 + hw/arm/aspeed_ast2600.c | 16 + hw/arm/musicpal.c | 381 +----------------- hw/arm/npcm7xx_boards.c | 10 +- hw/arm/virt-acpi-build.c | 10 +- hw/arm/virt.c | 184 ++++++++- hw/audio/Kconfig | 3 - hw/char/riscv_htif.c | 33 +- hw/intc/arm_gic.c | 11 + hw/intc/arm_gicv3_its.c | 452 ++++++++++----------- hw/intc/arm_gicv3_redist.c | 4 +- hw/intc/sifive_plic.c | 20 +- hw/misc/aspeed_i3c.c | 384 ++++++++++++++++++ hw/misc/meson.build | 1 + hw/misc/trace-events | 6 + hw/net/meson.build | 1 + hw/net/mv88w8618_eth.c | 403 +++++++++++++++++++ hw/riscv/boot.c | 16 +- hw/riscv/opentitan.c | 2 +- hw/riscv/spike.c | 45 ++- hw/riscv/virt.c | 83 ++-- hw/timer/ibex_timer.c | 25 +- hw/virtio/virtio-mem.c | 36 +- include/hw/arm/aspeed_soc.h | 3 + include/hw/arm/virt.h | 5 +- include/hw/char/riscv_htif.h | 5 +- include/hw/misc/aspeed_i3c.h | 48 +++ include/hw/net/mv88w8618_eth.h | 12 + include/hw/riscv/boot.h | 3 +- include/hw/riscv/spike.h | 1 + include/hw/timer/ibex_timer.h | 1 - linux-headers/asm-riscv/kvm.h | 128 ++++++ meson.build | 2 + pc-bios/meson.build | 2 - pc-bios/opensbi-riscv32-generic-fw_dynamic.elf | Bin 838904 -> 0 bytes pc-bios/opensbi-riscv64-generic-fw_dynamic.elf | Bin 934696 -> 0 bytes python/Makefile | 2 + python/README.rst | 2 +- python/avocado.cfg | 2 +- python/qemu/aqmp/__init__.py | 16 +- python/qemu/aqmp/error.py | 12 +- python/qemu/aqmp/events.py | 4 +- python/qemu/aqmp/legacy.py | 41 +- python/qemu/aqmp/protocol.py | 24 +- python/qemu/aqmp/qmp_client.py | 16 +- python/qemu/{qmp => aqmp}/qmp_shell.py | 31 +- python/qemu/{qmp => utils}/qemu_ga_client.py | 24 +- python/qemu/{qmp => utils}/qom.py | 5 +- python/qemu/{qmp => utils}/qom_common.py | 3 +- python/qemu/{qmp => utils}/qom_fuse.py | 11 +- python/setup.cfg | 19 +- qemu-options.hx | 10 + roms/Makefile | 2 - scripts/cpu-x86-uarch-abi.py | 7 +- scripts/qmp/qemu-ga-client | 2 +- scripts/qmp/qmp-shell | 2 +- scripts/qmp/qom-fuse | 2 +- scripts/qmp/qom-get | 2 +- scripts/qmp/qom-list | 2 +- scripts/qmp/qom-set | 2 +- scripts/qmp/qom-tree | 2 +- scripts/render_block_graph.py | 8 +- softmmu/device_tree.c | 11 +- target/arm/cpu.c | 16 +- target/arm/cpu.h | 1 + target/arm/cpu64.c | 31 +- target/arm/kvm64.c | 21 + target/riscv/cpu.c | 77 +++- target/riscv/cpu.h | 58 ++- target/riscv/cpu_bits.h | 3 + target/riscv/cpu_helper.c | 99 ++--- target/riscv/csr.c | 90 ++++- target/riscv/gdbstub.c | 71 +++- target/riscv/helper.h | 4 +- target/riscv/insn_trans/trans_privileged.c.inc | 9 +- target/riscv/insn_trans/trans_rva.c.inc | 9 +- target/riscv/insn_trans/trans_rvd.c.inc | 19 +- target/riscv/insn_trans/trans_rvf.c.inc | 19 +- target/riscv/insn_trans/trans_rvi.c.inc | 39 +- target/riscv/insn_trans/trans_rvv.c.inc | 225 +++++++++-- target/{rx/cpu-param.h => riscv/kvm-stub.c} | 26 +- target/riscv/kvm.c | 535 +++++++++++++++++++++++++ target/{rx/cpu-param.h => riscv/kvm_riscv.h} | 17 +- target/riscv/machine.c | 46 ++- target/riscv/meson.build | 1 + target/riscv/op_helper.c | 7 +- target/riscv/pmp.c | 12 +- target/riscv/sbi_ecall_interface.h | 72 ++++ target/riscv/translate.c | 94 +++-- target/riscv/vector_helper.c | 39 +- tests/data/acpi/virt/PPTT | Bin 76 -> 96 bytes 97 files changed, 3180 insertions(+), 1233 deletions(-) rename docs/{can.txt => system/devices/can.rst} (68%) create mode 100644 hw/misc/aspeed_i3c.c create mode 100644 hw/net/mv88w8618_eth.c create mode 100644 include/hw/misc/aspeed_i3c.h create mode 100644 include/hw/net/mv88w8618_eth.h create mode 100644 linux-headers/asm-riscv/kvm.h delete mode 100644 pc-bios/opensbi-riscv32-generic-fw_dynamic.elf delete mode 100644 pc-bios/opensbi-riscv64-generic-fw_dynamic.elf rename python/qemu/{qmp => aqmp}/qmp_shell.py (96%) rename python/qemu/{qmp => utils}/qemu_ga_client.py (94%) rename python/qemu/{qmp => utils}/qom.py (98%) rename python/qemu/{qmp => utils}/qom_common.py (98%) rename python/qemu/{qmp => utils}/qom_fuse.py (97%) copy target/{rx/cpu-param.h => riscv/kvm-stub.c} (67%) create mode 100644 target/riscv/kvm.c copy target/{rx/cpu-param.h => riscv/kvm_riscv.h} (70%) create mode 100644 target/riscv/sbi_ecall_interface.h -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 7 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allmodconfig updated (be7e938e2712 -> 50999e82e884)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allmodconfig in repository toolchain/ci/llvm-project. from be7e938e2712 AMDGPU/GlobalISel: Stop handling llvm.amdgcn.buffer.atomic.fadd adds 75017db08cd3 [RISCV] Add tests for commuted vector/scalar VP patterns adds 81cbbe3e17a4 [flang][NFC] Remove unused/duplicated kStridePosInDim adds 191a6e9dfa1a optimize icmp-ugt-ashr adds feddf1150227 [lld][WebAssemlby] Convert test to check disassembly output. NFC adds 1455eddcf71d [NFC][SimplifyCFG] Add some tests for `invoke` merging adds 48224475222d [libc++] basic_string::resize_and_overwrite: Adopt LWG3645 [...] adds 2e49e0cfde43 AMDGPU/GlobalISel: Directly diagnose return value use for [...] adds c0f9592daae3 add tsan shared library adds 08549ba51e11 AMDGPU/GlobalISel: Explicitly set -global-isel-abort in fa [...] adds 2d1f9aa27dc4 AMDGPU/GlobalISel: Regenerate test checks with -NEXT adds 064cea9c9a02 AMDGPU/GlobalISel: Try to use s_and_b64 in ptrmask selection adds 237502c1a478 AMDGPU: Fix asm in test using wrong IR type for physical register adds 5af2433e1794 [clang-cl] Support the /HOTPATCH flag adds 5abf11632245 [mlir][vector] Allow values outside of [0; dim-size] in cr [...] adds af5600420b93 [OpenMP] Don't pass empty files to nvlink adds aad04534c419 [libc] Implement correct rounding with all rounding modes [...] adds b80db150cdba Add `isConsteval` matcher adds eb6c6e60585d [NFC][InstCombine] Add test showing failure to sink into ` [...] adds 9abc593e9889 [TargetLowering][InstCombine] Simplify BSwap demanded bits [...] adds b58cc9fb2348 [NFC][RISCV] Add end-of-line symbol in target-feature testcases adds 587dccfb1238 [InstCombine] avoid 'tmp' usage in test files; NFC adds 2d031ec5e53f [InstCombine] add one-use check to opposite shift folds adds c65186c89f35 [clang] Improve -Wdeclaration-after-statement adds df31ff1b29bc [cmake] Make include(GNUInstallDirs) always below project(..) adds 792853cb786b [SystemZ] Remove the ManipulatesSP flag from backend (NFC). adds 5fa4cf82dfa0 [Clang] Separate the 'debug-info-hotpatch' test in two par [...] adds 94a0660c14da [AMDGPU] Regenerate remat-vop.mir. NFC. adds 493c85648401 [clang][NFC] Small mangler cleanups adds 6b92bb47901f [Support] [DebugInfo] Lazily create cache dir. adds 94e69fbb4f3a [RISCV] Add DAG combine to fold (fp_to_int_sat (ffloor X)) [...] adds 63a991d03589 [libc++] Eliminate the `__function_like` helper. adds ba8eb31bd954 [InstCombine] Instruction sinking: fix check for function [...] adds 8105e404f186 [demangler][NFC] Small cleanups and sync adds 864b5b49fd3f [libcxx] chrono::month_weekday should not be default const [...] adds 57ebfea38c03 [lldb] Surround LLDB_API-defining code with #ifndef LLDB_API adds 83d59e05b201 Re-land [LLD] Remove global state in lldCommon adds d4baf3b1322b [libc] Use get_round() instead of floating point tricks in [...] adds 8b4fa2c98e07 clang: Auto-cleanup left-over file from before 3da69fb5a26 [...] adds 9122b5072aa7 [llvm] Remove an old bot cleanup command adds 608a9c0e7909 [gn build] Port 63a991d03589 adds 14a296469864 [gn build] Port 83d59e05b201 adds 860038e0d775 [SLP] Rename a couple lambdas to be more clearly separate [...] adds 82452be5cbd7 [clang-format] Refactor: add FormatToken::hasWhitespaceBef [...] adds f84023a812b6 [lld][macho] Stop grouping symbols by sections in mapfile. adds b8d38e8b4fca [libcxx][test] view_interface need not derive from view_base adds d0cace508714 [mlir][pdl] Some ops are missing `NoSideEffect` adds 7c471b56f2c2 [mlir][pdl] OperationOp should not be side-effect free adds e99835ffedc2 [mlir][pdl] Make `pdl` the default dialect when parsing/printing adds 7a275dc35411 [RISCV] Remove Zvlsseg extension. adds 118babe67adf [SLP] Use for loops for walking bundle elements adds 40aef79db0b0 [MLIR][GPU] Add debug output to enable dumping GPU assembly adds dd7b69a61fa3 [RISCV] Remove HadStdExtV and HasStdZve* Predicates from t [...] adds 4c1dc65015ae [InstCombine] add/adjust tests for multiply with extended [...] adds a7a2860d0eee [InstCombine] convert mul with sexted bool and constant to select adds 60f61918795b [SLP] Extract formBundle helper for readability [NFC] adds 5ef7abbc6f99 [mlir:TiingInterface] Remove unnecessary include of Tensor.h adds 1f3f90ab8869 [libc] Make log2f correctly rounded for all rounding modes [...] adds 8c9f62ea90c7 [compiler-rt][cmake] Use HandleOutOfTreeLLVM like libcxx a [...] adds 4af11272f57a [cmake] Duplicate `{llvm,compiler_rt}_check_linker_flag` f [...] adds 36cb29cbbe1b Work around a module build failure on the bots. adds 5a670f1378ae [SLP] Kill an unused param and use a for-loop in calculate [...] adds 41ebd1968165 [AMDGPU] Do not ignore exec use where exec is read as data adds c0906f6b21a1 [SLP] Remove stray semicolon to make bots happy adds 1d4ca42b4380 [OpenMPIRBuilder] Detect ambiguous InsertPoints for apply* [...] adds 39f779afb354 [clang-tidy][NFC] Remove redundant string creation for comparison adds c95afac89e00 [clang-format][NFC] Clean up tryMergeLessLess() adds cd2d7369639e [mlir][tosa] Limit right-shift to 31 bits adds fa8bb224661d [RISCV] Optimize vector_shuffles that are interleaving the [...] adds 284cd693f1c6 [libc] Move the remaining public types to their own type headers. adds 5e88f527da21 [RISCV] Remove RISCVSubtarget::hasStdExtV() and hasStdExtZ [...] adds a5684114445a [clang-tidy] Update bugprone-stringview-nullptr to consist [...] adds 8457b61699e8 [test] Add tests for bswap combining. NFC adds ac2f3df8396a [lld][WebAssembly] Remove redundant config setting adds d92e5412ea57 [libc] Use __builtin_clz to find leading 1 in hypot adds 5501c16edf0f [flang] Fix OPEN/WRITE(SIGN='SUPPRESS') adds 9ddd07922f65 [flang] Handle FLUSH(unknown unit) adds e1b7bd911d9e [OpenCL] opencl-c.h: add __opencl_c_images and __opencl_c [...] adds d3b188a2d72f [clang-tidy] Include constructor initializers in `bugprone [...] adds 7bf9065ad7d9 [Attributor][NFC] Clang format adds 37e0c58559ad [Attributor][FIX] AAValueConstantRange should not loop unc [...] adds 1d7604fdcebd [InstCombine] Simplify bswap -> shift adds cfae2c65dbbe [RISCV] Factor Zve32 support into RISCVSubtarget::getMaxEL [...] adds 922c29ccf143 [flang] Allow explicit '+' in NAMELIST input subscripts adds d1123e36922d [flang] Extension: skip over NAMELIST groups adds ad06e65dc4da [RISCV] Fix the bug in the register allocator caused by re [...] adds f811cb82a6cd [lldb] Revive lldb-instr adds 1755f5b1d7b7 [lldb] Decouple instrumentation from the reproducers adds 156b997251db [lldb] Instrument SB API with signposts adds 0dfe953294ba [OpenMP] Change default visibility to protected for device [...] adds 26feef084616 [Libomptarget] Change visibility to hidden for device RTL adds 58580e922a69 [llvm][cmake] Make `llvm_install_symlink` robust to absolu [...] adds a65934241c22 [gn build] Port 1755f5b1d7b7 adds cac164ff9cb6 [lldb] Update the modulemap adds d93a11c138bb Revert "[llvm][cmake] Make `llvm_install_symlink` robust t [...] adds 82af95029ec9 [X86] Enable ibt-seal optimization when LTO is used in Kernel adds 7ee1c162cc53 [RISCV][RFC] add inst support of zbkb adds 7b3d30728816 [RISCV] Add isel patterns for grevi, shfli, and unshfli to [...] adds 26167cae4515 Print the `// ----` separator between modules when using - [...] adds 308d8b8c6618 [mlir][python] 8b/16b DenseIntElements access adds 9006bf424847 Remove obsolete `getAsmResultNames` from OpAsmDialectInterface adds a7f8aea71485 [clang-tidy] Fix wrong FixIt in performance-move-const-arg adds 82bb8a588dde [CSKY] Add codegen support of GlobalTLSAddress lowering adds 8def89b5dc82 [RISCV] Set CostPerUse to 1 iff RVC is enabled adds 75184f14aecd [DebugInfo] Fix handling '# line "file"' for DWARFv5 adds 86b08ed6bb16 [DebugInfo][NFC] Do not call 'isRootFile' for DWARF Version < 5 adds 7f0f4cab18a9 [libc][NFC] Add 'struct_' prefix to type headers defining [...] adds e6de53b4de4a [RISCV] Bump rvv-related extensions from 0.10 to 1.0 adds a99e06aa869b [mlir][Linalg] Avoid generating illegal operations during [...] adds 05cd9a0596d8 [ConstantFold] Simplify type check in reinterpret load fol [...] adds 6a19cb837c9b [ConstantFold] Support pointers in reinterpret load folding adds 7950010e4983 [VE][NFC] Factor out helper functions adds 3f9d1f516e19 [InstSimplify] Add tests for reinterpret load of floats (NFC) adds b4900296e4a5 [ConstantFold] Allow all float types in reinterpret load folding adds 99b5a8049be4 Match bazel config with cmake after f29256a64 adds 69825f369302 [fir] Add array operations documentation adds d03c5bc8d437 [mlir] Fully qualify return types in OpAsmInterface.td and [...] adds a2f6921ef2a1 [llvm] Remove unused headers in LLVMDemangle adds c0cf209076a2 [VPlan] Add VPWidenIntOrFpInductionRecipe::isCanonical, us [...] adds 55689904d2e5 [VPlan] Move ::isCanonical outside ifdef. adds 1f9e18b6565f [llvm] Remove (some) LLVMDemangle header dependencies adds e7762653d3b0 [Attributor] Avoid some pointer element type accesses adds 065044c443f4 Fix 1f9e18b6565fd1bb69c4b649b9efd3467b3c7c7d adds 329feeb938ac [ORC][docs] Describe removing JITDylibs, using custom prog [...] adds b351ac3873db [AMDGPU][NFC] Regenerate InstCombine test adds 0530fdbbbb84 [AMDGPU] Fix LOD bias in A16 combine adds 603d18033c51 [AMDGPU][InstCombine] Remove zero LOD bias adds ae2f9c8be897 [AMDGPU] Remove lz and nomip combine from codegen adds f53d359816e6 Fix 1f9e18b6565fd1bb69c4b649b9efd3467b3c7c7d adds 9c5b856dac5c [CoroSplit] Avoid pointer element type accesses adds 0ca426d6ac65 [llvm-mca] Improve barriers for strict region marking (PR52198) adds bfbdb5e43e50 [Coroutines] Avoid some pointer element type accesses adds 597eae998a87 [clangd][Background] Make index validation logs verbose adds b6a41fddcfd3 [DWARF][DebugInfo] Fix off-by-one error in size of DW_TAG_ [...] adds 357f2d9ccf20 [mlir][LangRef] Add top-level production to the MLIR grammar adds 4d268dc94a6b [RISCV] Enable CGP to sink splat operands of VP intrinsics adds 825a3cd6b697 [clangd] Fail inlayHints requests on content changes adds 4727d29d908f [X86] Remove __builtin_ia32_pabs intrinsics and use generi [...] adds ced077e1ba52 [clang][deps] NFC: Simplify handling of cached FS errors adds 5daeada33051 [clang][deps] Ensure filesystem cache consistency adds 8cc2a1372704 [clang][deps] Handle symlinks in minimizing FS adds 68db0e25df4b [flang] Update tco tool pipline and add translation to LLVM IR adds 8ee135dcf8ff [X86] Remove `__builtin_ia32_pmax/min` intrinsics and use [...] adds 3ef88b31843e Revert rG8ee135dcf8ff060656ad481c3e980fe8763576f5 "[X86] R [...] adds 0abaf6458092 Revert rG4727d29d908f9dd608dd97a58c0af1ad579fd3ca "[X86] R [...] adds 75e164f61d39 [llvm] Cleanup header dependencies in ADT and Support adds 2b8e4c6e5fbd Add missing header in Support/ConvertUTF.h adds 38ac4093d9d2 [NFCI][Support] Avoid ASSERT_/EXPECT_TRUE(A <op> B) adds 51c53a0791cd Add apple-specific missing include adds 2a9e33db4f0a Add ms-specific missing header in Support/InitLLVM.cpp adds 622354a52207 [llvm][ADT] Implement `BitVector::{pop_,}back` adds 7e3bcae5069f Add apple-specific missing header in Support/GraphWriter.cpp adds d5ae039ed7b8 [SystemZ] Properly register machine passes. adds e9211e039377 Remove dependency from raw_ostream on <chrono> adds ad43217a0466 [InstCombine] Fold for masked gather when loading the same [...] adds 4d82ae67b208 Add security group 2021 transparency report. adds b8102449a72c [clang-tidy] Avoid binding nullptr to a reference adds e5fd3a7df917 Try to unbreak build on Windows after e9211e03937 adds 8bc661894299 Add missing llvm/support/Regex.h include in polly/lib/Anal [...] adds 3c9e3dada916 Try to unbreak build on Windows more after e9211e03937 adds 9900acacfb3f [libcxx][doc][nfc] Fixed typo in doc adds 9d3437fbf341 [ADT] [NFC] Add StringRef::detectEOL adds 5597ec2dc4f8 Include missing "llvm/Support/Path.h" in "flang/lib/Fronte [...] adds f24fe96f469b [ifs] Use a tmp file instead of "-" adds cab961693802 [libc++] Use addressof in unordered_map. adds b7fd91c84b4e Upstream MLIR PyTACO implementation. adds e4a556268ea9 Revert "[libc++] Use addressof in unordered_map." adds 23a7bb541dae [clang-format] Fix comment in spaceRequiredBefore. NFC. adds 565963841880 Revert "[compiler-rt][cmake] Use HandleOutOfTreeLLVM like [...] adds 26cbc430197a [flang] Remove target and require shell adds 10e5c513b59b Revert "[cmake] Duplicate `{llvm,compiler_rt}_check_linker [...] adds 5061eb6b0121 [Sparc] Don't define __sparcv9 and __sparcv9__ when targeting V8+ adds e6ceec9c1d19 [Clang][RISCV] Restrict rvv builtins with zve macros adds 754d6af7c359 [NFC] Improve code reuse. adds 11754a4dbbad [RISCV] Use RVBUnary in more places to simplify some table [...] adds 4710750854ce [mlir][spirv] Support size-1 vector inserts during conversion adds fd0c6f53913f [mlir] Move linalg::PadTensorOp to tensor::PadOp. adds 3c90ae5d0b71 Revert "[flang] Update tco tool pipline and add translatio [...] adds 48132bb1e437 [RISCV] Simplify interface to combineMUL_VLToVWMUL. NFC adds d6e2c95d2252 [libc++] Use addressof in unordered_map. adds 4d0a18d06e8e [mlir][sparse] Adding assertions for overhead storage types adds cb8b94f6efa9 [AArch64] Add extra tests useful in testing hadd. NFC adds f18fcdabda72 [BOLT][NFC] Expand auto types pt.2 adds 5a654b01133f [BOLT] Make ICP target selection (more) deterministic adds f8c7fb499be6 [BOLT][NFC] Reduce includes with include-what-you-use adds 2f9f9afa4e12 [mlir] Add polynomial approximation for atan and atan2 adds 0d9cc6995401 [Support] Update missed tests with lazy caching behavior. adds cd4e600f5f5c [Sema] Warn about printf %n on Android and Fuchsia adds 0379459fc586 [RISCV] Strengthen a SDTypeProfile. Fix formatting. adds 4f8ea3c84f3d [SystemZ][z/OS][NFC] Remove extra symbol adds d84d1135d80c Emit swift5 reflection section data in dsym bundle generat [...] adds 9f4cc5a6bb56 [gn build] Set HAVE_MALLINFO2=1 adds 6103b2d45bfb Revert "Emit swift5 reflection section data in dsym bundle [...] adds e39c262979e6 Revert "[gn build] Set HAVE_MALLINFO2=1" adds 705d8c49f9be [x86] regenerate smul-with-overflow.ll; add test which fai [...] adds 6df05697ca1d [gn build] Set HAVE_MALLINFO2=1 adds 653b007dc186 [CodeComplete] fix nullptr crash in 612f5ed8823120 adds b796709a62da Only run MLIR PyTACO tests when python bindings are enabled. adds ba093fe58b15 Fix a commit. adds 6ba1fb04214b [llvm-pdbutil] Fix gaps ouput. adds 58ee14e29e98 [lldb] Fix timer logging inverted quiet condition adds efa15f417847 [mlir][sparse] add ability for sparse tensor output adds 10d0d8c0c1db [clang][cmake] Use `GNUInstallDirs` to support custom inst [...] adds 1613f8b8d7d5 NFC (build fix): Add header for llvm::errs(). adds 08574ce4d625 [mlir][tosa] Add clamp + clamp as single clamp canonicalization adds 13fa17db3a72 [split-file] Respect input file's line endings adds 4f547ee8b8a7 [libc++][test] Add const and reference tests for enable_vi [...] adds 9cddfe3085c4 [CMake] Passthrough OSX CMake options to builtins and runtimes adds e6cdef187ed3 [XRay][test] Clean up llc RUN lines adds 04eb93b1d559 [flang] Fix repeated "DT" editing adds db07e082abaf [TSan] Omit vfork interceptor iOS simulator runtime adds 3726626a26ec [flang] Fix crash from USE-associated defined I/O subprograms adds b95150418fb6 [lldb] Allow aliases to aliases of raw input commands adds e796eaf2af65 [RISCV][RFC] add MC support for zbkc subextension adds b1856009fbc1 [flang] Allow INQUIRE() on a child unit in user-defined I/ [...] adds 55d887b83364 [time-trace] Add optimizer and codegen regions to NPM adds b6098c07cb20 [MLIR] Fix negative gcd in `normalizeDivisionByGCD` function. adds de8723829515 [JITLink] Add anonymous symbols in LinkGraph for unnamed t [...] adds fdb6578514dd Revert "[JITLink] Add anonymous symbols in LinkGraph for u [...] adds f7d4cafe5a6a [JITLink][RISCV] Support R_RISCV_SET* and R_RISCV_32_PCREL [...] adds 26544b98f7bf [libc++] Use addressof in unordered_set. adds 4041354b4c12 [mlir] Add SingleBlockImplicitTerminator<"tensor::YieldOp" [...] adds 93deac2e2ba9 [AArch64] Optimize add/sub with immediate through MIPeepholeOpt adds 0283b07746e8 reapply de872382951 "[JITLink] Add anonymous symbols in Li [...] adds b27e5459d51f [DAG] Convert truncstore(extend(x)) back to store(x) adds 8dedf9b58bff [PowerPC] Change CTR clobber estimation for 128-bit floati [...] adds 00d68c3824bf [PowerPC] Support parsing GNU attributes in MC adds 5f2854f1daa7 [LV] Always create VPWidenCanonicalIVRecipe, optimize away later. adds 26fffc1b8e75 [libc++] [test] {cpo,niebloid}.compile.pass.cpp: Also test [...] adds e9d0f8baf236 [flang] Don't drop format string for external child I/O adds 896a543e72fd [flang] Support DECIMAL='COMMA' mode in namelist I/O adds 0a6b4258ab0e [openmp][cmake] Use `GNUInstallDirs` to support custom ins [...] adds d44b6be6eaa8 [RISCV] Don't Custom legalize f16/f32/f64 bitcasts if thos [...] adds 39e602b6c433 [InstCombine] try to fold binop with phi operands adds 7c16647c3676 [clang-tools-extra][cmake] Use `GNUInstallDirs` to support [...] adds c1988dbf2d19 [openmp] Allow x87 fp functions only in Openmp runtime for x86. adds b8467952404c [docs] [clang] Small documentation change for compilation [...] adds 37d1d02200b9 [X86][MS] Change the alignment of f80 to 16 bytes on Windo [...] adds 2513b7903063 [libc++] Implement LWG3549: view_interface need not inheri [...] adds 3cf15af2daa9 [RISCV] Remove experimental prefix from rvv-related extensions. adds 85e42db1b6db [RISCV] Merge some rvv intrinsic test cases that only diff [...] adds be6070c290e2 [RISCV] Use FP ABI for some RVV intrinsic tests. NFC adds 3dc6fd515135 [llvm-objcopy][MachO] Implement --update-section adds a4f202549208 [X86] Regenerate avx512-mask-op.ll adds ff05b93a02d1 [llvm-objdump] Use cast<> instead of dyn_cast<> to avoid d [...] adds 20d46fbd4a51 [CodeGenPrepare] Use dyn_cast result to check for null pointers adds 946f29028e06 [llvm-objdump] Use cast<> instead of dyn_cast<> to avoid d [...] adds 86497026a266 [clang-tidy] Use cast<>/castAs<> instead of dyn_cast<>/get [...] adds df0fd1c301d6 [clangd] Use castAs<> instead of getAs<> to avoid derefere [...] adds c93491352cf3 [lldb] CxxModuleHandler - use cast<> instead of dyn_cast<> [...] adds d7aa402b4b8a [lldb] PdbAstBuilder - use cast<> instead of dyn_cast<> to [...] adds d13847bbe5e6 [lldb] TerminalState::Save - fix unused variable warning adds 49d38b1d618c Fix "not all control paths return a value" warning. NFC. adds 938944445a1b [libc++] Mark LWG3541 as "Complete". NFC. adds 5d78fef6db15 [libc++] Fix LWG3437 "__cpp_lib_polymorphic_allocator is i [...] adds d4ed3eff9f9c [X86] Add vector signbit parity checks for non-popcnt targets adds eb3f20e8fa4b [clang-tidy] Remove gsl::at suggestion from cppcoreguideli [...] adds 153359180a9d [AVR] Remove regalloc workaround for LDDWRdPtrQ adds 116ab78694dd [AVR] Make use of the constant value 0 in R1 adds 7c66aaddb128 [DAG] Fold (X & Y) != 0 --> zextOrTrunc(X & Y) iff everyth [...] adds 2e26633af0c8 [IR] document and update ctlz/cttz intrinsics to optionall [...] adds d2e8fb331835 [clang-tidy] Add readability-duplicate-include check adds 6605057992b1 Revert rG7c66aaddb128dc0f342830c1efaeb7a278bfc48c "[DAG] F [...] adds 631f3e621586 [gn build] Port d2e8fb331835 adds accc07e65465 [DAG] Fold (X & Y) != 0 --> zextOrTrunc(X & Y) iff everyth [...] adds 0b799791807e [RISCV] Merge some rvv intrinsic test cases that only diff [...] adds f69379d0a43b [InstCombine] Add test coverage for PR48683 adds 818cfb10c574 [libcxx][test] Make MSVC `<charconv>` test compile when te [...] adds 8e382ae91b97 [Support] Simplify parallelForEach{,N} adds 1a5dea9e2b97 [NewGVN][NFC] precommit tests for PR53277 adds 7a29b0b58383 [llvm] Fix header guards (NFC) adds abb0ed44957c [Commands] Remove redundant member initialization (NFC) adds f8ddcb413125 [Object] Remove a redundant return statement (NFC) adds ad36f37ce2b4 [MLIR][Presburger] Clean PresburgerSet identifier interfac [...] adds 413684313d9d [RISCV] Adjust the header comment in RISCVInstrInfoZb.td t [...] adds 32dc14f876c4 [X86] LowerFunnelShift - use supportedVectorShiftWithBaseA [...] adds ab1add6adc44 [clang] Move the definition of ASTDiff (NFC) adds ee591a64a795 [clang] Forward-declare DynTypedNode (NFC) adds e59964b67e02 [clang] Remove unused forward declarations (NFC) adds 4762c077e710 [X86] LowerFunnelShift - always lower vXi8 fshl by constan [...] adds 88f33cff4bee [RISCV] Add bitreverse tests to bswap-ctlz-cttz-ctpop.ll. [...] adds 3575700b286f [RISCV] Add tests that do a bitreverse before or after a b [...] adds 47d7e922d843 [mlir] Ensure a newline at the end of a file (NFC) adds fa90fc6e0566 [Sema] Fix a bugprone argument comment (NFC) adds 448d0dfab701 [Analysis] Remove a redundant const from a return type (NFC) adds ab4756338c5b DebugInfo: Don't put types in type units if they reference [...] adds 7c77df1528c8 [X86] Add some basic tests for PR46809 adds 2e58a1891086 DebugInfo: Include template parameters for simplified temp [...] adds 3a3af2bbc97e [C++20] [Module] fix bug 47716 and implement [module.inter [...] adds 3f24cdec2572 [RISCV][NFC] Remove tailing whitespaces in RISCVInstrInfoV [...] adds b574048239bc [NFC] [Coroutines] Rename tests in coro-align adds 943aa1bfacaa Add modernize-use-default-member-init.UseAssignment to .cl [...] adds f63a9cd99db7 [Vectorize] Remove unused variables (NFC) adds b752eb887f7e [Analysis] Use default member initialization (NFC) adds d3b26dea1610 Clang: Change the default DWARF version to 5 adds 90abe181da7c Add missing function implementation from DWARF default change adds 68b70d17d8de [GlobalISel] Fold or of shifts with constant amount to fun [...] adds 8b280df504b9 Rough guess at fixing lldb tests to handle Clang defaultin [...] adds 1f4a0531b3fd [TSan] Mark test unsupported on Darwin adds e29d8fb16978 [RISCV] Initially support the K-extension instructions on [...] adds bf039a8620f1 [Target] Use range-based for loops (NFC) adds ba16e3c31f66 [RISCV] Decouple Zve* extensions and the V extension. adds c5590396d041 [PowerPC] Emit warning for ieeelongdouble on older GNU toolchain adds ea2112ea15a0 [clang-format] Remove unused assignment. NFC. adds 3519dcfec229 Added OpenMP 5.0 specification based semantic checks for a [...] adds 670a721de2a1 [clang-format] Assert Line->First. NFC. adds f53301125257 [Hexagon] Use llvm::Register instead of unsigned in Hexago [...] adds d6f8f56da04b [MLIR][Presburger] Silence -Wdangling-else warning (NFC) adds 81793bd276af [clang-format] Assert Line->First and State.NextToken->Pre [...] adds 9aaa74aeeff3 [RISCV] Add patterns of SET[U]LT_VI for STECC forms adds ba845787b3fd [clang][sema] Add missing diagnostic parameter adds 3ad6de31c0cf [clang][tests] Fix a c++/libc++ -stdlib value typo adds d29e319263de [OpaquePtrs] Add getNonOpaquePointerElementType() method (NFC) adds 67346b43e0ed [Attributor] Use MemoryLocation to get pointer operand and [...] adds 7ccacaf4428d [flang][examples] Add missing CMake dependencies adds 4f8fdf78279f [ISEL] Canonicalise constant splats to RHS. adds e7c9a6cae09d [SDAG] Don't move DBG_VALUE instructions after insertion p [...] adds 0d1308a7b77c [AArch64][GlobalISel] Support returned argument with multi [...] adds a08447d0de5d [LLD][ELF][AArch64] Update test with incorrect REQUIRES li [...] adds 906ebd5830e6 [AMDGPU][GlobalISel] Regenerate checks in inst-select-*ext.mir adds aa50b93e7cf9 [AMDGPU][GlobalISel] Add more sign/zero/any-extension tests adds 7d19566c3bfb [lldb] Ignore non-address bits in "memory find" arguments adds 022600334dcb [flang] Update the description of `!fir.coordinate_of` adds 912af6b570d6 [AMDGPU][GlobalISel] Remove the post ':' part of vreg oper [...] new 577a6dc9a186 [X86] getVectorMaskingNode - fix indentation. NFC. new e7926e8d972e [RISCV] Match VF variants for masked VFRDIV/VFRSUB new af773a18181d [RISCV][VP] Lower VP_MERGE to RVV instructions new 3e6be0241b31 [lldb] Update release notes with non-address bit handling changes new 12a499eb00e3 Pre-commit test case for trunc+lshr+load folds new 46cacdbb21c2 [DAGCombiner] Adjust some checks in DAGCombiner::reduceLoadWidth new e5147f82e1cb [X86] Remove __builtin_ia32_pabs intrinsics and use generi [...] new b2499bf3e851 [mlir][bufferize][NFC] Refactor createAlloc function signature new 3e50593b1884 [X86] Remove `__builtin_ia32_pmax/min` intrinsics and use [...] new 3696c70e67d9 [clang-tidy] Add `readability-container-contains` check new e4074432d5bf [X86] Remove avx512f integer and/or/xor/min/max reduction [...] new 8082ab2fc391 [LoopVectorize] Support epilogue vectorisation of loops wi [...] new 54f1d950667c [gn build] Port 3696c70e67d9 new b7f69b8d4650 [LV] Name values and blocks in same induction tests (NFC). new 70f83f308449 [RISCV] add support for zbkx subextension in MC layer. new b754d09fde0b [MLIR][Presburger] Refactor duplicate division merging to Utils new b4b6d6374e2e [NFC] New test case for BasicAA and memcy/memmove with deopt new f1e36474b9e5 [AMDGPU][NFC] Fix debug prints new 0e70dd858eb7 [X86] Add PR46249 test case showing poorly widened select [...] new b2a8eff45c55 [LV] Make some tests more robust by adding missing users. new 5f290c090a24 Move STLFunctionalExtras out of STLExtras new 853e79d8d8af [flang] Update tco tool pipline and add translation to LLVM IR new 38ffea9b4c1f [demangler] Resync demangler sources new 897d1bb659c2 [demangler] write-protect non-canonical source new 6184e565ad40 [demangler][NFC] Refactor some parsing new 589a93907222 Add `isConstinit` matcher new a0d5e938fe9c Add missing include llvm/ADT/STLExtras new f6ac8088b0e8 [LoopFlatten] Added comments about usage of various Loop A [...] new ada6d78a7802 [LoopFlatten] Address FIXME about getTripCountFromExitCount. NFC. new d42678b453bc [RISCV] Add side-effect-free vsetvli intrinsics new 25e8f5f827bf Add missing STLExtras.h include from lldb/unittests/Testin [...] new f7079bf9ee68 [X86] Fix v8i8 -> v8i16 typo in bool reductions new 4436d4cd7c86 [X86] Rename cmp-with-zero bool reductions new 0553f5e61ac7 [X86] Add cmp-equality bool reductions new 34aedbe90d76 [AArch64] Regenerate CHECK lines for llvm/test/CodeGen/AAr [...] new 5e5efd8a91f2 [clang-format] Fix SeparateDefinitionBlocks issues new 7a5b0a2934f3 Reapply "IR: Make getRetAlign check callee function attributes" new 99e8e17313e7 Reapply "Revert "GlobalISel: Add G_ASSERT_ALIGN hint instruction" new 354b2c36ee46 Pre-commit test cases for (sra (load)) -> (sextload) folds. NFC new 18aabae8e2b6 AMDGPU: Fix assertion on fixed stack objects with VGPR->AG [...] new 49e37000691a [mlir][tensor] Move BufferizableOpInterface impl to tensor [...] new 473aa8e10c49 [llvm][docs] Fix code-block in the testing guide new 2d9ed1aba236 [mlir] Fix broken __repr__ implementation in Linalg OpDSL new d193f7be7898 [libc++][AIX] Do not assert chmod return value is non-zero. new fc08d1c29406 [mlir][tensor][bufferize] Support tensor.rank in Bufferiza [...] new 4d53f88d1a18 [flang] Add MemoryAllocation pass to the pipeline new 3ad35ba4dea5 [Templight] Don't display empty strings for names of unnam [...] new c30d2893a43d [mlir][bufferize] Change insertion point for ToTensorOps new 217570b03bbe [MLIR][OpenMP] Suppress -Wreturn-type warnings (NFC) new c1335166b265 Don't run test/ClangScanDeps/modules-symlink.c on Windows new cd2a9ff39788 [RISCV] Select int_riscv_vsll with shift of 1 to vadd.vv. new b8c7cdcc81a0 [SelectionDAG][RISCV] Teach getNode to fold bswap(bswap(x))->x. new b00ee46b5e4b [mlir][bufferize][NFC] Implement BufferizableOpInterface o [...] new a43ed49f5b16 [DAGCombiner][RISCV] Canonicalize (bswap(bitreverse(x))->b [...] new e494278ceeb7 [mlir][linalg] Add transpose support to hoist padding. new cfe17986c952 [libcxx][test] {move,reverse}_iterator cannot be instantia [...] new 699e22a083f2 [ISEL] Move trivial step_vector folds to FoldConstantArithmetic. new 6997f4d07fa4 [X86] combineSetCCMOVMSK - fold allof(cmpeq(x,y)) -> ptest [...] new c03fdd340356 [ELF] Fix the branch range computation when reusing a thunk new a2afc8249a99 [libc++] Fix benchmark failure new 6be77561f82d [SLP][NFC] Add debug logs for entry. new 7cd441ff537e [clang][NFC] Wrap TYPE_SWITCH in "do while (0)" in the int [...] new 80532ebb508d [AMDGPU][InstCombine] Remove zero image offset new 74db5c8c95e2 Revert rG6a605b97a200 due to excessive memory use new 50999e82e884 [clang-format] Space between attribute closing parenthesis [...] The 65 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .clang-tidy | 2 + bolt/include/bolt/Core/BinaryContext.h | 3 +- bolt/include/bolt/Core/BinaryData.h | 1 - bolt/include/bolt/Core/DebugData.h | 3 - bolt/include/bolt/Passes/AllocCombiner.h | 2 - bolt/include/bolt/Rewrite/DWARFRewriter.h | 3 +- bolt/lib/Core/BinaryFunction.cpp | 5 +- bolt/lib/Core/DebugData.cpp | 7 +- bolt/lib/Core/JumpTable.cpp | 1 - bolt/lib/Passes/IndirectCallPromotion.cpp | 24 +- bolt/lib/Passes/ThreeWayBranch.cpp | 2 - bolt/lib/Profile/YAMLProfileWriter.cpp | 2 +- bolt/lib/Rewrite/DWARFRewriter.cpp | 4 +- bolt/lib/Rewrite/MachORewriteInstance.cpp | 2 - bolt/lib/Rewrite/RewriteInstance.cpp | 2 - bolt/lib/Utils/Utils.cpp | 1 - clang-tools-extra/CMakeLists.txt | 1 + clang-tools-extra/clang-doc/tool/CMakeLists.txt | 4 +- .../find-all-symbols/tool/CMakeLists.txt | 2 +- .../clang-include-fixer/tool/CMakeLists.txt | 4 +- clang-tools-extra/clang-tidy/CMakeLists.txt | 2 +- clang-tools-extra/clang-tidy/GlobList.cpp | 1 + .../abseil/DurationFactoryScaleCheck.cpp | 2 +- .../clang-tidy/bugprone/StringviewNullptrCheck.cpp | 19 +- .../ProBoundsConstantArrayIndexCheck.cpp | 3 +- .../clang-tidy/performance/MoveConstArgCheck.cpp | 119 +- .../clang-tidy/performance/MoveConstArgCheck.h | 2 + .../clang-tidy/readability/CMakeLists.txt | 2 + .../readability/ContainerContainsCheck.cpp | 144 ++ .../readability/ContainerContainsCheck.h | 40 + .../readability/DuplicateIncludeCheck.cpp | 116 + .../clang-tidy/readability/DuplicateIncludeCheck.h | 35 + .../clang-tidy/readability/FunctionSizeCheck.cpp | 3 +- .../readability/ReadabilityTidyModule.cpp | 6 + .../readability/SuspiciousCallArgumentCheck.cpp | 4 +- clang-tools-extra/clang-tidy/tool/CMakeLists.txt | 4 +- .../clang-tidy/utils/ExceptionAnalyzer.cpp | 18 + .../clang-tidy/utils/IncludeSorter.cpp | 17 +- clang-tools-extra/clangd/ClangdServer.cpp | 2 +- clang-tools-extra/clangd/DumpAST.h | 1 + clang-tools-extra/clangd/HeuristicResolver.cpp | 5 +- clang-tools-extra/clangd/Hover.cpp | 2 +- clang-tools-extra/clangd/SourceCode.cpp | 3 +- clang-tools-extra/clangd/index/Background.cpp | 2 +- clang-tools-extra/docs/ReleaseNotes.rst | 20 + .../checks/bugprone-stringview-nullptr.rst | 4 +- ...eguidelines-pro-bounds-constant-array-index.rst | 2 + clang-tools-extra/docs/clang-tidy/checks/list.rst | 2 + .../checks/readability-container-contains.rst | 25 + .../checks/readability-duplicate-include.rst | 35 + clang-tools-extra/modularize/CMakeLists.txt | 2 +- .../readability-duplicate-include.h | 15 + .../readability-duplicate-include2.h | 1 + .../readability-duplicate-include/system/iostream | 1 + .../readability-duplicate-include/system/string.h | 1 + .../system/sys/types.h | 1 + .../readability-duplicate-include/system/types.h | 1 + .../checkers/bugprone-exception-escape.cpp | 43 + .../checkers/bugprone-stringview-nullptr.cpp | 22 +- ...s-pro-bounds-constant-array-index-gslheader.cpp | 6 +- ...eguidelines-pro-bounds-constant-array-index.cpp | 6 +- .../checkers/performance-move-const-arg.cpp | 94 + .../checkers/readability-container-contains.cpp | 230 ++ .../checkers/readability-duplicate-include.cpp | 72 + clang/CMakeLists.txt | 14 +- clang/cmake/modules/AddClang.cmake | 5 +- clang/cmake/modules/CMakeLists.txt | 4 +- clang/docs/JSONCompilationDatabase.rst | 4 + clang/docs/LibASTMatchersReference.html | 45 + clang/docs/ReleaseNotes.rst | 27 + clang/include/clang/AST/ASTContext.h | 1 - clang/include/clang/AST/DeclBase.h | 14 + clang/include/clang/AST/FormatString.h | 3 +- clang/include/clang/ASTMatchers/ASTMatchers.h | 36 + clang/include/clang/Basic/BuiltinsX86.def | 72 - clang/include/clang/Basic/CodeGenOptions.def | 5 + clang/include/clang/Basic/DiagnosticDriverKinds.td | 3 + clang/include/clang/Basic/DiagnosticSemaKinds.td | 10 +- clang/include/clang/Basic/DirectoryEntry.h | 1 + clang/include/clang/Basic/RISCVVTypes.def | 4 +- clang/include/clang/Basic/riscv_vector.td | 6 +- clang/include/clang/Driver/Options.td | 8 +- clang/include/clang/Driver/ToolChain.h | 2 +- clang/include/clang/Sema/Sema.h | 2 + clang/include/clang/Tooling/ASTDiff/ASTDiff.h | 28 +- .../clang/Tooling/ASTDiff/ASTDiffInternal.h | 3 - .../DependencyScanningFilesystem.h | 347 ++- clang/lib/AST/Decl.cpp | 13 - clang/lib/AST/DeclBase.cpp | 9 + clang/lib/AST/Interp/PrimType.h | 50 +- clang/lib/AST/ItaniumMangle.cpp | 22 +- clang/lib/AST/OSLog.cpp | 4 +- clang/lib/AST/PrintfFormatString.cpp | 2 +- clang/lib/ASTMatchers/Dynamic/Registry.cpp | 2 + clang/lib/Basic/Targets/AArch64.h | 1 + clang/lib/Basic/Targets/ARM.h | 1 + clang/lib/Basic/Targets/RISCV.cpp | 2 +- clang/lib/Basic/Targets/Sparc.cpp | 2 - clang/lib/Basic/Targets/X86.h | 11 +- clang/lib/CodeGen/BackendUtil.cpp | 15 +- clang/lib/CodeGen/CGBuiltin.cpp | 103 - clang/lib/CodeGen/CodeGenFunction.cpp | 7 + clang/lib/CodeGen/CodeGenModule.cpp | 3 + clang/lib/Driver/SanitizerArgs.cpp | 1 + clang/lib/Driver/ToolChains/Arch/AArch64.cpp | 1 + clang/lib/Driver/ToolChains/Arch/ARM.cpp | 1 + clang/lib/Driver/ToolChains/Arch/ARM.h | 1 + clang/lib/Driver/ToolChains/Clang.cpp | 11 + clang/lib/Driver/ToolChains/Linux.cpp | 6 + clang/lib/Driver/ToolChains/Linux.h | 1 + clang/lib/Driver/ToolChains/MSVC.cpp | 12 + clang/lib/Driver/ToolChains/PPCLinux.cpp | 56 + clang/lib/Driver/ToolChains/PPCLinux.h | 7 +- clang/lib/Format/AffectedRangeManager.cpp | 2 + clang/lib/Format/ContinuationIndenter.cpp | 9 +- clang/lib/Format/DefinitionBlockSeparator.cpp | 86 +- clang/lib/Format/DefinitionBlockSeparator.h | 2 +- clang/lib/Format/Format.cpp | 8 +- clang/lib/Format/FormatToken.cpp | 1 + clang/lib/Format/FormatToken.h | 7 + clang/lib/Format/FormatTokenLexer.cpp | 27 +- clang/lib/Format/QualifierAlignmentFixer.cpp | 4 +- clang/lib/Format/SortJavaScriptImports.cpp | 1 + clang/lib/Format/TokenAnnotator.cpp | 44 +- clang/lib/Format/UnwrappedLineFormatter.cpp | 3 +- clang/lib/Format/UnwrappedLineParser.cpp | 10 +- clang/lib/Format/UnwrappedLineParser.h | 3 +- clang/lib/Frontend/CompilerInvocation.cpp | 3 + clang/lib/Frontend/FrontendActions.cpp | 95 +- clang/lib/Frontend/Rewrite/InclusionRewriter.cpp | 20 +- clang/lib/Headers/avx2intrin.h | 30 +- clang/lib/Headers/avx512bwintrin.h | 20 +- clang/lib/Headers/avx512fintrin.h | 72 +- clang/lib/Headers/avx512vlintrin.h | 20 +- clang/lib/Headers/emmintrin.h | 8 +- clang/lib/Headers/opencl-c.h | 94 +- clang/lib/Headers/smmintrin.h | 16 +- clang/lib/Headers/tmmintrin.h | 6 +- clang/lib/Sema/SemaChecking.cpp | 72 +- clang/lib/Sema/SemaCodeComplete.cpp | 7 +- clang/lib/Sema/SemaDecl.cpp | 49 +- clang/lib/Sema/SemaDeclCXX.cpp | 2 +- clang/lib/Sema/SemaModule.cpp | 2 +- clang/lib/Sema/SemaStmt.cpp | 8 +- clang/lib/Sema/SemaTemplate.cpp | 2 +- clang/lib/Sema/SemaTemplateDeduction.cpp | 2 +- .../DependencyScanningFilesystem.cpp | 255 +- clang/test/CXX/module/module.interface/p2-2.cpp | 37 + clang/test/CXX/module/module.interface/p6.cpp | 93 + clang/test/ClangScanDeps/modules-symlink.c | 55 + .../CodeGen/RISCV/riscv-attr-builtin-alias-err.c | 2 +- .../test/CodeGen/RISCV/riscv-attr-builtin-alias.c | 2 +- clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c | 4 +- clang/test/CodeGen/RISCV/riscv-v-debuginfo.c | 2 +- clang/test/CodeGen/RISCV/riscv-v-lifetime.cpp | 2 +- .../RISCV/rvb-intrinsics/riscv32-zbb-error.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vaadd.c | 2 +- .../CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c | 2 +- .../CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c | 2 +- .../CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vasub.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vcompress.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vcpop.c | 2 +- .../CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfabs.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfadd.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfclass.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfcvt.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfdiv.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfirst.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfmacc.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfmadd.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfmax.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfmerge.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfmin.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfmsac.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfmsub.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfmul.c | 2 +- .../CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfncvt.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfneg.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfnmacc.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfnmadd.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfnmsac.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfnmsub.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfrdiv.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfrec7.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfredmax.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfredmin.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfredsum.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfrsub.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfsgnj.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfslide1down.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfslide1up.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfsqrt.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfsub.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfwadd.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfwcvt.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfwmacc.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfwmsac.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfwmul.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfwnmacc.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfwnmsac.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfwredsum.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vfwsub.c | 2 +- .../CodeGen/RISCV/rvv-intrinsics-overloaded/vget.c | 2 +- .../CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/viota.c | 2 +- .../CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vlmul.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vloxei.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vloxseg.c | 4 +- .../CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vlseg.c | 8 +- .../RISCV/rvv-intrinsics-overloaded/vlsegff.c | 8 +- .../RISCV/rvv-intrinsics-overloaded/vlsseg.c | 4 +- .../RISCV/rvv-intrinsics-overloaded/vluxei.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vluxseg.c | 4 +- .../RISCV/rvv-intrinsics-overloaded/vmacc.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vmadc.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vmadd.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vmand.c | 2 +- .../CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vmerge.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vmfeq.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vmfge.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vmfgt.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vmfle.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vmflt.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vmfne.c | 2 +- .../CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c | 2 +- .../CodeGen/RISCV/rvv-intrinsics-overloaded/vmmv.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vmnand.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vmnor.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vmnot.c | 2 +- .../CodeGen/RISCV/rvv-intrinsics-overloaded/vmor.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vmsbc.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vmsbf.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vmseq.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vmsge.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vmsgt.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vmsif.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vmsle.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vmslt.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vmsne.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vmsof.c | 2 +- .../CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c | 2 +- .../CodeGen/RISCV/rvv-intrinsics-overloaded/vmv.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vmxnor.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vmxor.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vnclip.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vncvt.c | 2 +- .../CodeGen/RISCV/rvv-intrinsics-overloaded/vneg.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vnmsac.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vnmsub.c | 2 +- .../CodeGen/RISCV/rvv-intrinsics-overloaded/vnot.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vnsra.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vnsrl.c | 2 +- .../CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vredand.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vredmax.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vredmin.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vredor.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vredsum.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vredxor.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vreinterpret.c | 2 +- .../CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vrgather.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vrsub.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vsadd.c | 2 +- .../CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c | 2 +- .../CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c | 2 +- .../CodeGen/RISCV/rvv-intrinsics-overloaded/vset.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vsext.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vslide1down.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vslide1up.c | 2 +- .../RISCV/rvv-intrinsics-overloaded/vslidedown.c | 2 +- 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llvm/test/CodeGen/RISCV/attributes.ll | 69 +- .../RISCV/bswap-bitreverse-ctlz-cttz-ctpop.ll | 2441 ++++++++++++++++++++ llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll | 1032 --------- llvm/test/CodeGen/RISCV/callee-saved-gprs.ll | 796 +++---- .../calling-conv-ilp32-ilp32f-ilp32d-common.ll | 76 +- .../RISCV/calling-conv-lp64-lp64f-lp64d-common.ll | 38 +- llvm/test/CodeGen/RISCV/double-arith-strict.ll | 92 +- llvm/test/CodeGen/RISCV/double-arith.ll | 208 +- llvm/test/CodeGen/RISCV/double-convert.ll | 186 +- llvm/test/CodeGen/RISCV/double-fcmp-strict.ll | 64 +- llvm/test/CodeGen/RISCV/double-fcmp.ll | 32 +- llvm/test/CodeGen/RISCV/double-round-conv-sat.ll | 940 ++++++++ llvm/test/CodeGen/RISCV/float-arith-strict.ll | 32 +- llvm/test/CodeGen/RISCV/float-arith.ll | 124 +- llvm/test/CodeGen/RISCV/float-convert.ll | 88 +- llvm/test/CodeGen/RISCV/float-round-conv-sat.ll | 940 ++++++++ llvm/test/CodeGen/RISCV/fp128.ll | 32 +- llvm/test/CodeGen/RISCV/fpclamptosat.ll | 414 ++-- llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll | 1177 +++++----- llvm/test/CodeGen/RISCV/half-arith.ll | 708 +++--- llvm/test/CodeGen/RISCV/half-convert.ll | 112 +- llvm/test/CodeGen/RISCV/half-intrinsics.ll | 152 +- llvm/test/CodeGen/RISCV/half-round-conv-sat.ll | 970 ++++++++ llvm/test/CodeGen/RISCV/mul.ll | 388 ++-- llvm/test/CodeGen/RISCV/remat.ll | 44 +- llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll | 24 +- llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll | 30 +- llvm/test/CodeGen/RISCV/rv32zbb.ll | 96 +- llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll | 18 + llvm/test/CodeGen/RISCV/rv32zbp.ll | 620 +++-- llvm/test/CodeGen/RISCV/rv32zbt.ll | 28 +- llvm/test/CodeGen/RISCV/rv64i-complex-float.ll | 8 +- llvm/test/CodeGen/RISCV/rv64zbp.ll | 130 +- llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll | 4 +- .../RISCV/rvv/access-fixed-objects-by-rvv.ll | 2 +- .../CodeGen/RISCV/rvv/addi-scalable-offset.mir | 2 +- llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll | 2 +- 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86 +- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll | 38 +- .../RISCV/rvv/fixed-vectors-emergency-slot.mir | 2 +- .../RISCV/rvv/fixed-vectors-extload-truncstore.ll | 8 +- .../CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll | 4 +- .../RISCV/rvv/fixed-vectors-extract-subvector.ll | 4 +- .../CodeGen/RISCV/rvv/fixed-vectors-extract.ll | 4 +- .../CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll | 4 +- .../CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll | 8 +- .../CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll | 8 +- .../RISCV/rvv/fixed-vectors-fp-interleave.ll | 378 +++ .../CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll | 4 +- .../CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll | 4 +- .../CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll | 8 +- .../CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll | 56 +- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll | 8 +- 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llvm/test/CodeGen/RISCV/rvv/vadd-policy.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll | 58 +- llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vand-vp.ll | 18 +- llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vcpop-rv32.ll | 282 --- llvm/test/CodeGen/RISCV/rvv/vcpop-rv64.ll | 282 --- llvm/test/CodeGen/RISCV/rvv/vcpop.ll | 284 +++ llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vexts-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll | 1417 ------------ llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll | 1386 ----------- llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll | 34 +- llvm/test/CodeGen/RISCV/rvv/vfadd.ll | 1357 +++++++++++ llvm/test/CodeGen/RISCV/rvv/vfclass-rv32.ll | 692 ------ llvm/test/CodeGen/RISCV/rvv/vfclass-rv64.ll | 692 ------ llvm/test/CodeGen/RISCV/rvv/vfclass.ll | 694 ++++++ llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv32.ll | 617 ----- llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv64.ll | 617 ----- llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll | 619 +++++ llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv32.ll | 617 ----- llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv64.ll | 617 ----- llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll | 619 +++++ llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv32.ll | 617 ----- llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv64.ll | 617 ----- llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f.ll | 619 +++++ llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv32.ll | 617 ----- llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv64.ll | 617 ----- llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f.ll | 619 +++++ llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv32.ll | 617 ----- llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv64.ll | 617 ----- llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll | 619 +++++ llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv32.ll | 617 ----- llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv64.ll | 617 ----- llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll | 619 +++++ llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll | 1417 ------------ llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll | 1385 ----------- llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfdiv.ll | 1357 +++++++++++ llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll | 282 --- llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll | 282 --- llvm/test/CodeGen/RISCV/rvv/vfirst.ll | 284 +++ llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll | 1154 --------- llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll | 1130 --------- llvm/test/CodeGen/RISCV/rvv/vfmacc.ll | 1108 +++++++++ llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll | 1154 --------- llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll | 1130 --------- llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfmadd.ll | 1108 +++++++++ llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll | 1417 ------------ llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll | 1385 ----------- llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfmax.ll | 1357 +++++++++++ llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll | 933 -------- llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll | 917 -------- llvm/test/CodeGen/RISCV/rvv/vfmerge.ll | 904 ++++++++ llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll | 1417 ------------ llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll | 1385 ----------- llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfmin.ll | 1357 +++++++++++ llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll | 1154 --------- llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll | 1130 --------- llvm/test/CodeGen/RISCV/rvv/vfmsac.ll | 1108 +++++++++ llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll | 1154 --------- llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll | 1130 --------- llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfmsub.ll | 1108 +++++++++ llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll | 1417 ------------ llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll | 1385 ----------- llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfmul.ll | 1357 +++++++++++ llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv32.ll | 197 -- llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv64.ll | 197 -- llvm/test/CodeGen/RISCV/rvv/vfmv.s.f.ll | 200 ++ llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll | 482 ---- llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll | 482 ---- llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll | 484 ++++ llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll | 380 --- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll | 380 --- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll | 382 +++ llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll | 380 --- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll | 380 --- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll | 382 +++ llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll | 380 --- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll | 380 --- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll | 382 +++ llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll | 380 --- llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll | 380 --- llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f.ll | 382 +++ llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll | 632 ----- llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll | 632 ----- llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f.ll | 634 +++++ .../test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll | 632 ----- .../test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll | 632 ----- llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f.ll | 634 +++++ llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll | 632 ----- llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll | 632 ----- llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll | 634 +++++ llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll | 632 ----- llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll | 632 ----- llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll | 634 +++++ llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll | 1154 --------- llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll | 1130 --------- llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll | 1108 +++++++++ llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll | 1154 --------- llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll | 1130 --------- llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll | 1108 +++++++++ llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll | 1154 --------- llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll | 1130 --------- llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll | 1108 +++++++++ llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll | 1154 --------- llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll | 1130 --------- llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll | 1108 +++++++++ llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll | 739 ------ llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll | 707 ------ llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll | 679 ++++++ llvm/test/CodeGen/RISCV/rvv/vfrec7-rv32.ll | 617 ----- llvm/test/CodeGen/RISCV/rvv/vfrec7-rv64.ll | 617 ----- llvm/test/CodeGen/RISCV/rvv/vfrec7.ll | 619 +++++ llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll | 692 ------ llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll | 692 ------ llvm/test/CodeGen/RISCV/rvv/vfredmax.ll | 694 ++++++ llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll | 692 ------ llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll | 692 ------ llvm/test/CodeGen/RISCV/rvv/vfredmin.ll | 694 ++++++ llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll | 692 ------ llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll | 692 ------ llvm/test/CodeGen/RISCV/rvv/vfredosum.ll | 694 ++++++ llvm/test/CodeGen/RISCV/rvv/vfredusum-rv32.ll | 692 ------ llvm/test/CodeGen/RISCV/rvv/vfredusum-rv64.ll | 692 ------ llvm/test/CodeGen/RISCV/rvv/vfredusum.ll | 694 ++++++ llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv32.ll | 617 ----- llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv64.ll | 617 ----- llvm/test/CodeGen/RISCV/rvv/vfrsqrt7.ll | 619 +++++ llvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll | 739 ------ llvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll | 708 ------ llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfrsub.ll | 679 ++++++ llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll | 1417 ------------ llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll | 1385 ----------- llvm/test/CodeGen/RISCV/rvv/vfsgnj.ll | 1357 +++++++++++ llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll | 1417 ------------ llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll | 1385 ----------- llvm/test/CodeGen/RISCV/rvv/vfsgnjn.ll | 1357 +++++++++++ llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll | 1417 ------------ llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll | 1385 ----------- llvm/test/CodeGen/RISCV/rvv/vfsgnjx.ll | 1357 +++++++++++ llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll | 739 ------ llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll | 707 ------ llvm/test/CodeGen/RISCV/rvv/vfslide1down.ll | 679 ++++++ llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll | 754 ------ llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll | 722 ------ llvm/test/CodeGen/RISCV/rvv/vfslide1up.ll | 694 ++++++ llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll | 548 ----- llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv64.ll | 707 ------ llvm/test/CodeGen/RISCV/rvv/vfsqrt-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll | 619 +++++ llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll | 1417 ------------ llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll | 1386 ----------- llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfsub.ll | 1357 +++++++++++ llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll | 848 ------- llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll | 848 ------- llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfwadd.ll | 832 +++++++ llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll | 1275 ---------- llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll | 1275 ---------- llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll | 1250 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll | 380 --- llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll | 380 --- llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll | 382 +++ llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll | 632 ----- llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll | 632 ----- llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll | 634 +++++ llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll | 632 ----- llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll | 632 ----- llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll | 634 +++++ llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll | 380 --- llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll | 380 --- llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f.ll | 382 +++ .../test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll | 380 --- .../test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll | 380 --- llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f.ll | 382 +++ llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll | 380 --- llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll | 380 --- llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll | 382 +++ llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll | 380 --- llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll | 380 --- llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll | 382 +++ llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll | 848 ------- llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll | 848 ------- llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll | 832 +++++++ llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll | 848 ------- llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll | 848 ------- llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll | 832 +++++++ llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll | 848 ------- llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll | 848 ------- llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfwmul.ll | 832 +++++++ llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll | 848 ------- llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll | 848 ------- llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll | 832 +++++++ llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll | 848 ------- llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll | 848 ------- llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll | 832 +++++++ llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll | 508 ---- llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll | 508 ---- llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll | 510 ++++ llvm/test/CodeGen/RISCV/rvv/vfwredusum-rv32.ll | 508 ---- llvm/test/CodeGen/RISCV/rvv/vfwredusum-rv64.ll | 508 ---- llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll | 510 ++++ llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll | 848 ------- llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll | 848 ------- llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vfwsub.ll | 832 +++++++ llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll | 1275 ---------- llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll | 1275 ---------- llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll | 1250 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vid-rv32.ll | 758 ------ llvm/test/CodeGen/RISCV/rvv/vid-rv64.ll | 758 ------ llvm/test/CodeGen/RISCV/rvv/vid.ll | 760 ++++++ llvm/test/CodeGen/RISCV/rvv/viota-rv32.ll | 882 ------- llvm/test/CodeGen/RISCV/rvv/viota-rv64.ll | 882 ------- llvm/test/CodeGen/RISCV/rvv/viota.ll | 884 +++++++ llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vle-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vle-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vlm-rv32.ll | 94 - llvm/test/CodeGen/RISCV/rvv/vlm-rv64.ll | 94 - llvm/test/CodeGen/RISCV/rvv/vlm.ll | 96 + llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vlse-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vlse-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmadc-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll | 142 -- llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll | 142 -- llvm/test/CodeGen/RISCV/rvv/vmand.ll | 144 ++ llvm/test/CodeGen/RISCV/rvv/vmandn-rv32.ll | 142 -- llvm/test/CodeGen/RISCV/rvv/vmandn-rv64.ll | 142 -- llvm/test/CodeGen/RISCV/rvv/vmandn.ll | 144 ++ llvm/test/CodeGen/RISCV/rvv/vmarith-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vmclr-rv32.ll | 114 - llvm/test/CodeGen/RISCV/rvv/vmclr-rv64.ll | 114 - llvm/test/CodeGen/RISCV/rvv/vmclr.ll | 116 + llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmin-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vminu-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll | 142 -- llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll | 142 -- llvm/test/CodeGen/RISCV/rvv/vmnand.ll | 144 ++ llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll | 142 -- llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll | 142 -- llvm/test/CodeGen/RISCV/rvv/vmnor.ll | 144 ++ llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll | 142 -- llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll | 142 -- llvm/test/CodeGen/RISCV/rvv/vmor.ll | 144 ++ llvm/test/CodeGen/RISCV/rvv/vmorn-rv32.ll | 142 -- llvm/test/CodeGen/RISCV/rvv/vmorn-rv64.ll | 142 -- llvm/test/CodeGen/RISCV/rvv/vmorn.ll | 144 ++ llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmsbc-rv64.ll | 2 +- .../test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll | 2 +- .../test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmset-rv32.ll | 114 - llvm/test/CodeGen/RISCV/rvv/vmset-rv64.ll | 114 - llvm/test/CodeGen/RISCV/rvv/vmset.ll | 116 + llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll | 296 --- llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll | 296 --- llvm/test/CodeGen/RISCV/rvv/vmsif.ll | 298 +++ llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll | 296 --- llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll | 296 --- llvm/test/CodeGen/RISCV/rvv/vmsof.ll | 298 +++ llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll | 18 +- llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll | 142 -- llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll | 142 -- llvm/test/CodeGen/RISCV/rvv/vmxnor.ll | 144 ++ llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll | 142 -- llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll | 142 -- llvm/test/CodeGen/RISCV/rvv/vmxor.ll | 144 ++ llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vor-vp.ll | 32 +- llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vpload.ll | 54 +- llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll | 1280 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vpstore.ll | 56 +- llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll | 2 +- .../CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll | 4 +- .../test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll | 2 +- .../test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll | 10 +- llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vrsub-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsbc-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vse-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vse-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vselect-mask.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vsetvl-ext.ll | 2 +- .../CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll | 2 +- .../CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir | 4 +- llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir | 4 +- llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll | 34 +- llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll | 34 +- llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll | 137 -- llvm/test/CodeGen/RISCV/rvv/vsm-rv64.ll | 137 -- llvm/test/CodeGen/RISCV/rvv/vsm.ll | 139 ++ llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsoxei-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vsse-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsse-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vsuxei-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll | 2 +- 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.../test/CodeGen/RISCV/srem-seteq-illegal-types.ll | 88 +- llvm/test/CodeGen/RISCV/srem-vector-lkk.ll | 948 ++++---- llvm/test/CodeGen/RISCV/ssub_sat.ll | 14 +- llvm/test/CodeGen/RISCV/ssub_sat_plus.ll | 16 +- llvm/test/CodeGen/RISCV/stack-store-check.ll | 84 +- llvm/test/CodeGen/RISCV/tail-calls.ll | 8 +- .../RISCV/umulo-128-legalisation-lowering.ll | 146 +- .../test/CodeGen/RISCV/urem-seteq-illegal-types.ll | 16 +- llvm/test/CodeGen/RISCV/urem-vector-lkk.ll | 950 ++++---- llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll | 20 +- llvm/test/CodeGen/RISCV/xaluo.ll | 840 ++++--- llvm/test/CodeGen/X86/avx512-mask-op.ll | 112 +- llvm/test/CodeGen/X86/combine-sra-load.ll | 107 + llvm/test/CodeGen/X86/dpbusd_const.ll | 17 +- llvm/test/CodeGen/X86/extractelement-fp.ll | 8 +- llvm/test/CodeGen/X86/fp-round.ll | 14 +- llvm/test/CodeGen/X86/fp128-cast.ll | 2 +- .../hoist-and-by-const-from-shl-in-eqcmp-zero.ll | 16 +- llvm/test/CodeGen/X86/ibtseal-kernel.ll | 19 + llvm/test/CodeGen/X86/ibtseal-large.ll | 19 + llvm/test/CodeGen/X86/ibtseal-small.ll | 19 + llvm/test/CodeGen/X86/long-double-abi-align.ll | 4 +- llvm/test/CodeGen/X86/movmsk-cmp.ll | 10 +- llvm/test/CodeGen/X86/parity-vec.ll | 165 +- llvm/test/CodeGen/X86/pr43509.ll | 8 +- .../test/CodeGen/X86/pr53243-tail-call-fastisel.ll | 39 + llvm/test/CodeGen/X86/scalar-fp-to-i32.ll | 219 +- llvm/test/CodeGen/X86/scalar-fp-to-i64.ll | 32 +- llvm/test/CodeGen/X86/select-lea.ll | 177 ++ llvm/test/CodeGen/X86/shift-folding.ll | 25 + llvm/test/CodeGen/X86/smul-with-overflow.ll | 734 +++++- ...nfold-masked-merge-vector-variablemask-const.ll | 47 +- llvm/test/CodeGen/X86/vector-compare-all_of.ll | 15 +- llvm/test/CodeGen/X86/vector-compare-any_of.ll | 10 +- llvm/test/CodeGen/X86/vector-fshl-128.ll | 165 +- llvm/test/CodeGen/X86/vector-fshl-256.ll | 117 +- llvm/test/CodeGen/X86/vector-fshl-512.ll | 130 +- llvm/test/CodeGen/X86/vector-reduce-and-bool.ll | 1090 ++++++++- llvm/test/CodeGen/X86/vector-reduce-or-bool.ll | 1063 ++++++++- llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll | 1159 +++++++++- llvm/test/CodeGen/X86/vselect-avx512.ll | 111 + .../CodeGen/X86/xray-attribute-instrumentation.ll | 7 +- llvm/test/CodeGen/X86/xray-custom-log.ll | 4 +- llvm/test/CodeGen/X86/xray-empty-firstmbb.mir | 2 +- .../test/CodeGen/X86/xray-ignore-loop-detection.ll | 4 +- llvm/test/CodeGen/X86/xray-log-args.ll | 4 +- llvm/test/CodeGen/X86/xray-loop-detection.ll | 4 +- .../CodeGen/X86/xray-multiplerets-in-blocks.mir | 2 +- .../X86/xray-partial-instrumentation-skip-entry.ll | 7 +- .../X86/xray-partial-instrumentation-skip-exit.ll | 6 +- llvm/test/CodeGen/X86/xray-section-group.ll | 6 +- .../CodeGen/X86/xray-selective-instrumentation.ll | 2 +- llvm/test/CodeGen/X86/xray-tail-call-sled.ll | 4 +- .../DebugInfo/COFF/ARMNT/arm-register-variables.ll | 3 +- llvm/test/DebugInfo/X86/base-type-size.ll | 50 + llvm/test/DebugInfo/X86/instr-ref-flag.ll | 4 + llvm/test/DebugInfo/X86/tu-to-non-tu.ll | 330 ++- .../JITLink/RISCV/ELF_pc_relative.s | 19 + .../ExecutionEngine/JITLink/RISCV/ELF_reloc_set.s | 31 + .../JITLink/RISCV/anonymous_symbol.s | 21 + llvm/test/MC/AArch64/coff-debug.ll | 3 +- llvm/test/MC/ELF/debug-hash-file.s | 20 +- llvm/test/MC/PowerPC/gnu-attribute.s | 11 + llvm/test/MC/RISCV/attribute-arch-invalid.s | 6 - llvm/test/MC/RISCV/attribute-arch.s | 124 +- llvm/test/MC/RISCV/rv32zbkb-only-valid.s | 16 + llvm/test/MC/RISCV/rv32zbkb-valid.s | 45 + llvm/test/MC/RISCV/rv32zbkc-invalid.s | 9 + llvm/test/MC/RISCV/rv32zbkc-valid.s | 23 + llvm/test/MC/RISCV/rv32zbkx-invalid.s | 9 + llvm/test/MC/RISCV/rv32zbkx-valid.s | 17 + llvm/test/MC/RISCV/rv32zbp-aliases-valid.s | 10 +- llvm/test/MC/RISCV/rv32zbp-only-valid.s | 6 + llvm/test/MC/RISCV/rv32zbp-valid.s | 2 +- llvm/test/MC/RISCV/rv32zknd-only-invalid.s | 17 + llvm/test/MC/RISCV/rv32zknd-only-valid.s | 13 + llvm/test/MC/RISCV/rv32zkne-only-invalid.s | 17 + llvm/test/MC/RISCV/rv32zkne-only-valid.s | 13 + llvm/test/MC/RISCV/rv32zknh-only-valid.s | 29 + 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llvm/test/MC/RISCV/rvv/fdiv.s | 8 +- llvm/test/MC/RISCV/rvv/fmacc.s | 8 +- llvm/test/MC/RISCV/rvv/fminmax.s | 8 +- llvm/test/MC/RISCV/rvv/fmul.s | 8 +- llvm/test/MC/RISCV/rvv/fmv.s | 8 +- llvm/test/MC/RISCV/rvv/fothers.s | 8 +- llvm/test/MC/RISCV/rvv/freduction.s | 8 +- llvm/test/MC/RISCV/rvv/fsub.s | 8 +- llvm/test/MC/RISCV/rvv/invalid-eew.s | 2 +- llvm/test/MC/RISCV/rvv/invalid.s | 2 +- llvm/test/MC/RISCV/rvv/load.s | 8 +- llvm/test/MC/RISCV/rvv/macc.s | 8 +- llvm/test/MC/RISCV/rvv/mask.s | 8 +- llvm/test/MC/RISCV/rvv/minmax.s | 8 +- llvm/test/MC/RISCV/rvv/mul.s | 8 +- llvm/test/MC/RISCV/rvv/mv.s | 8 +- llvm/test/MC/RISCV/rvv/or.s | 8 +- llvm/test/MC/RISCV/rvv/others.s | 8 +- llvm/test/MC/RISCV/rvv/reduction.s | 8 +- llvm/test/MC/RISCV/rvv/shift.s | 8 +- llvm/test/MC/RISCV/rvv/sign-injection.s | 8 +- llvm/test/MC/RISCV/rvv/snippet.s | 4 +- llvm/test/MC/RISCV/rvv/store.s | 8 +- llvm/test/MC/RISCV/rvv/sub.s | 8 +- llvm/test/MC/RISCV/rvv/vsetvl-invalid.s | 4 +- llvm/test/MC/RISCV/rvv/vsetvl.s | 8 +- llvm/test/MC/RISCV/rvv/xor.s | 8 +- llvm/test/MC/RISCV/rvv/zvlsseg.s | 1020 ++++---- llvm/test/ThinLTO/X86/cache.ll | 2 +- llvm/test/ThinLTO/X86/empty_module_with_cache.ll | 2 +- llvm/test/Transforms/Attributor/range.ll | 433 ++-- .../CodeGenPrepare/AArch64/large-offset-gep.ll | 5 +- .../{coro-align-03.ll => coro-align16.ll} | 0 llvm/test/Transforms/Coroutines/coro-align32.ll | 60 + .../{coro-align-05.ll => coro-align64-02.ll} | 0 .../{coro-align-04.ll => coro-align64.ll} | 0 .../{coro-align-02.ll => coro-align8-02.ll} | 0 .../{coro-align-01.ll => coro-align8.ll} | 0 .../InstCombine/AMDGPU/amdgcn-intrinsics.ll | 1610 +++++++++++-- .../Transforms/InstCombine/binop-phi-operands.ll | 122 +- llvm/test/Transforms/InstCombine/bswap-fold.ll | 268 +++ .../canonicalize-lshr-shl-to-masking.ll | 216 +- .../canonicalize-shl-lshr-to-masking.ll | 230 +- llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll | 15 +- llvm/test/Transforms/InstCombine/icmp-shr.ll | 20 +- .../Transforms/InstCombine/intrinsic-select.ll | 2 +- llvm/test/Transforms/InstCombine/intrinsics.ll | 56 +- .../Transforms/InstCombine/masked_intrinsics.ll | 62 + .../test/Transforms/InstCombine/mul-masked-bits.ll | 47 +- llvm/test/Transforms/InstCombine/mul.ll | 49 +- llvm/test/Transforms/InstCombine/shift.ll | 2 +- .../InstCombine/sink-into-resume-block.ll | 63 + llvm/test/Transforms/InstCombine/zext-or-icmp.ll | 12 +- .../Transforms/InstSimplify/ConstProp/bitcount.ll | 36 +- .../Transforms/InstSimplify/ConstProp/loads.ll | 58 +- .../LoopVectorize/AArch64/induction-trunc.ll | 8 +- .../Transforms/LoopVectorize/AArch64/pr31900.ll | 12 +- .../AArch64/sve-epilog-vect-inloop-reductions.ll | 121 + .../AArch64/sve-epilog-vect-reductions.ll | 121 + .../AArch64/sve-epilog-vect-strict-reductions.ll | 116 + .../LoopVectorize/RISCV/masked_gather_scatter.ll | 4 +- .../Transforms/LoopVectorize/RISCV/reg-usage.ll | 8 +- .../LoopVectorize/RISCV/riscv-interleaved.ll | 2 +- .../Transforms/LoopVectorize/RISCV/riscv-unroll.ll | 8 +- .../LoopVectorize/RISCV/scalable-reductions.ll | 2 +- .../LoopVectorize/RISCV/scalable-vf-hint.ll | 2 +- .../RISCV/unroll-in-loop-vectorizer.ll | 2 +- .../X86/invariant-store-vectorization.ll | 106 +- llvm/test/Transforms/LoopVectorize/X86/pr35432.ll | 2 +- llvm/test/Transforms/LoopVectorize/X86/pr42674.ll | 2 +- .../epilog-vectorization-reductions.ll | 529 +++++ llvm/test/Transforms/LoopVectorize/induction.ll | 138 +- .../optimal-epilog-vectorization-limitations.ll | 33 - .../LoopVectorize/single-value-blend-phis.ll | 96 +- .../tail-folding-vectorization-factor-1.ll | 96 +- .../LoopVectorize/vector-intrinsic-call-cost.ll | 26 +- llvm/test/Transforms/NewGVN/phi-of-ops-loads.ll | 148 ++ .../SLPVectorizer/RISCV/rvv-min-vector-size.ll | 6 +- ...e-compatible-invokes-of-landingpad-debuginfo.ll | 103 + .../X86/merge-compatible-invokes-of-landingpad.ll | 1367 +++++++++++ llvm/test/tools/gold/X86/cache.ll | 4 +- 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llvm/unittests/ADT/StringMapTest.cpp | 1 + llvm/unittests/ADT/StringRefTest.cpp | 30 + llvm/unittests/ADT/StringSetTest.cpp | 1 + llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp | 2 +- .../unittests/CodeGen/GlobalISel/KnownBitsTest.cpp | 55 + llvm/unittests/Debuginfod/DebuginfodTests.cpp | 24 +- llvm/unittests/Support/Casting.cpp | 34 +- llvm/unittests/Support/CommandLineTest.cpp | 89 +- .../Support/DynamicLibrary/DynamicLibraryTest.cpp | 42 +- llvm/unittests/Support/ErrorTest.cpp | 23 +- llvm/unittests/Support/FSUniqueIDTest.cpp | 6 +- llvm/unittests/Support/IndexedAccessorTest.cpp | 2 +- llvm/unittests/Support/JSONTest.cpp | 4 +- llvm/unittests/Support/MemoryBufferTest.cpp | 20 +- llvm/unittests/Support/Path.cpp | 3 +- llvm/unittests/Support/ProgramTest.cpp | 4 +- llvm/unittests/Support/ReverseIterationTest.cpp | 1 + llvm/unittests/Support/TarWriterTest.cpp | 4 +- llvm/unittests/Support/TargetParserTest.cpp | 29 +- llvm/unittests/Support/TimerTest.cpp | 2 +- llvm/unittests/Support/UnicodeTest.cpp | 6 +- llvm/unittests/Support/VirtualFileSystemTest.cpp | 76 +- llvm/unittests/Support/YAMLIOTest.cpp | 86 +- llvm/unittests/Support/YAMLParserTest.cpp | 24 +- llvm/unittests/Support/raw_ostream_test.cpp | 3 +- .../clang-tidy/readability/BUILD.gn | 2 + llvm/utils/gn/secondary/libcxx/include/BUILD.gn | 1 - llvm/utils/gn/secondary/lld/Common/BUILD.gn | 1 + .../gn/secondary/lldb/source/Utility/BUILD.gn | 2 +- .../gn/secondary/llvm/include/llvm/Config/BUILD.gn | 3 +- mlir/CMakeLists.txt | 9 +- mlir/docs/LangRef.md | 13 + mlir/include/mlir-c/BuiltinAttributes.h | 8 + .../mlir/Analysis/Presburger/PresburgerSet.h | 18 +- mlir/include/mlir/Analysis/Presburger/Utils.h | 17 + .../mlir/Conversion/GPUCommon/GPUCommonPass.h | 1 + .../Bufferization/IR/BufferizableOpInterface.h | 16 +- .../mlir/Dialect/Bufferization/IR/Bufferization.h | 1 + .../Bufferization/IR/BufferizationInterfaceImpl.h | 25 - .../Dialect/Bufferization/IR/BufferizationOps.td | 95 +- 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(100%) create mode 100644 llvm/test/Transforms/Coroutines/coro-align32.ll rename llvm/test/Transforms/Coroutines/{coro-align-05.ll => coro-align64-02.ll} (100%) rename llvm/test/Transforms/Coroutines/{coro-align-04.ll => coro-align64.ll} (100%) rename llvm/test/Transforms/Coroutines/{coro-align-02.ll => coro-align8-02.ll} (100%) rename llvm/test/Transforms/Coroutines/{coro-align-01.ll => coro-align8.ll} (100%) create mode 100644 llvm/test/Transforms/InstCombine/sink-into-resume-block.ll create mode 100644 llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-inlo [...] create mode 100644 llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-redu [...] create mode 100644 llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-stri [...] create mode 100644 llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll create mode 100644 llvm/test/Transforms/NewGVN/phi-of-ops-loads.ll create mode 100644 llvm/test/Transforms/SimplifyCFG/X86/merge-compatible-invokes-o [...] create mode 100644 llvm/test/Transforms/SimplifyCFG/X86/merge-compatible-invokes-o [...] create mode 100644 llvm/test/tools/llvm-objcopy/MachO/update-section.test copy llvm/test/tools/split-file/Inputs/{basic-aa.txt => basic-aa.crlf} (100%) create mode 100644 llvm/test/tools/split-file/Inputs/basic-bb.crlf create mode 100644 llvm/test/tools/split-file/basic.crlf.test delete mode 100644 mlir/include/mlir/Dialect/Bufferization/IR/BufferizationInterfa [...] delete mode 100644 mlir/include/mlir/Dialect/Linalg/ComprehensiveBufferize/TensorI [...] create mode 100644 mlir/include/mlir/Dialect/Tensor/IR/TensorTilingInterfaceImpl.h create mode 100644 mlir/include/mlir/Dialect/Tensor/Transforms/BufferizableOpInter [...] create mode 100644 mlir/include/mlir/Dialect/Tensor/Utils/Utils.h delete mode 100644 mlir/lib/Dialect/Bufferization/IR/BufferizationInterfaceImpl.cpp delete mode 100644 mlir/lib/Dialect/Linalg/ComprehensiveBufferize/TensorInterfaceImpl.cpp create mode 100644 mlir/lib/Dialect/Tensor/IR/TensorTilingInterfaceImpl.cpp create mode 100644 mlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp create mode 100644 mlir/lib/Dialect/Tensor/Utils/CMakeLists.txt create mode 100644 mlir/lib/Dialect/Tensor/Utils/Utils.cpp create mode 100644 mlir/test/Dialect/PDL/canonicalize.mlir create mode 100644 mlir/test/Integration/Dialect/SparseTensor/taco/README.md create mode 100644 mlir/test/Integration/Dialect/SparseTensor/taco/data/gold_A.tns create mode 100644 mlir/test/Integration/Dialect/SparseTensor/taco/data/gold_y.tns create mode 100644 mlir/test/Integration/Dialect/SparseTensor/taco/data/nell-2.tns create mode 100644 mlir/test/Integration/Dialect/SparseTensor/taco/data/pwtk.mtx create mode 100644 mlir/test/Integration/Dialect/SparseTensor/taco/lit.local.cfg create mode 100644 mlir/test/Integration/Dialect/SparseTensor/taco/test_MTTKRP.py create mode 100644 mlir/test/Integration/Dialect/SparseTensor/taco/test_SpMV.py create mode 100644 mlir/test/Integration/Dialect/SparseTensor/taco/test_simple_ten [...] copy mlir/test/Integration/Dialect/SparseTensor/{python => taco}/tools/lit.local.c [...] create mode 100644 mlir/test/Integration/Dialect/SparseTensor/taco/tools/mlir_pytaco.py create mode 100644 mlir/test/Integration/Dialect/SparseTensor/taco/tools/mlir_pyta [...] create mode 100644 mlir/test/Integration/Dialect/SparseTensor/taco/tools/mlir_pyta [...] create mode 100644 mlir/test/Integration/Dialect/SparseTensor/taco/tools/mlir_pyta [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 7 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allmodconfig updated (6d263fe46e -> 965c919f98)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allmodconfig in repository toolchain/ci/binutils-gdb. from 6d263fe46e Avoid bad breakpoints with --gc-sections adds df9d50bb22 Automatic date update in version.in adds 7bf5587873 gdbsupport/gdb_regex.cc: replace defs.h include with common-defs.h adds ec7194506d drop old unused stamp-h.in file adds b13d7831eb gdb/doc: fill in two missing @r adds e901223d53 Updated Serbian translation for the ld sub-directory adds ed09c325ec gdb: include gdbsupport/buildargv.h in ser-mingw.c adds 5b4ea8a740 Automatic date update in version.in adds cb2562f553 RISC-V: create new frag after alignment. adds a74e1cb344 Add markers for 2.38 branch adds f908e960c5 Change version number to 2.38.50 and regenerate files adds 5f7a57f131 Update release makeing script with new release numbers adds cc5e40736d Adjust default page sizes for haiku arm. adds 58de646be2 Allow inferring tmp_prefix from the dll name from a def file. adds 3dd8e5b615 bfd: replace doc header generation with pattern rules adds cb803d3749 bfd: rename core.texi to corefile.texi adds bd32be01c9 bfd: merge doc subdir up a level adds 35638469cb Automatic date update in version.in adds 31b0378d53 Regenerate configure files with autoconf 2.69 adds ad69b6b861 Regenerate Makefile.in files with automake 1.15.1 adds 0e3839bde6 bfd: Properly install library and header files adds 451c003d5f bfd: Partially revert commit 0e3839bde6f adds f10522c0e7 Simplify some Rust expression-evaluation code adds 2b1ca85cf8 Automatic date update in version.in adds 5fe73d4624 Update Bulgarian, French, Romaniam and Ukranian translation [...] adds 965c919f98 gdb/doc: improve description for Window.click on Python TUI windows No new revisions were added by this update. Summary of changes: ChangeLog | 4 + bfd/.gitignore | 2 +- bfd/ChangeLog | 16 + bfd/Makefile.am | 22 +- bfd/Makefile.in | 508 +- bfd/configure | 42 +- bfd/configure.ac | 3 +- bfd/doc/Makefile.am | 217 - bfd/doc/Makefile.in | 1021 --- bfd/doc/bfd.texi | 2 +- bfd/doc/local.mk | 152 + bfd/po/bfd.pot | 112 +- bfd/po/fr.po | 3116 ++++---- bfd/po/ro.po | 10194 ++++++++++++++++++++----- bfd/po/uk.po | 3102 ++++---- bfd/stamp-h.in | 1 - bfd/version.h | 2 +- bfd/version.m4 | 2 +- binutils/BRANCHES | 1 + binutils/ChangeLog | 21 + binutils/Makefile.in | 1 - binutils/NEWS | 2 + binutils/README-how-to-make-a-release | 35 +- binutils/configure | 20 +- binutils/dlltool.c | 34 +- binutils/po/bg.po | 6039 +++++++++------ binutils/po/binutils.pot | 4084 +++++----- binutils/po/fr.po | 4192 +++++----- binutils/po/ro.po | 13085 +++++++++++++++++++++++++------- binutils/po/uk.po | 4202 +++++----- binutils/stamp-h.in | 1 - config/ChangeLog | 4 + cpu/ChangeLog | 4 + elfcpp/ChangeLog | 4 + gas/ChangeLog | 13 + gas/Makefile.in | 1 - gas/NEWS | 2 + gas/config/tc-riscv.c | 6 + gas/configure | 20 +- gas/po/gas.pot | 20 +- gas/po/uk.po | 4880 ++++++------ gas/stamp-h.in | 1 - gdb/doc/python.texi | 10 +- gdb/rust-exp.h | 39 +- gdb/rust-lang.c | 44 +- gdb/ser-mingw.c | 1 + gdbsupport/gdb_regex.cc | 2 +- gold/ChangeLog | 15 + gold/po/gold.pot | 248 +- gold/po/uk.po | 257 +- gprof/ChangeLog | 14 + gprof/configure | 20 +- gprof/po/gprof.pot | 4 +- gprof/po/ro.po | 386 +- gprof/stamp-h.in | 1 - include/ChangeLog | 4 + ld/ChangeLog | 24 + ld/Makefile.in | 1 - ld/NEWS | 2 + ld/configure | 20 +- ld/configure.tgt | 2 +- ld/emulparams/armelf_haiku.sh | 4 +- ld/po/bg.po | 4373 ++++++----- ld/po/ld.pot | 218 +- ld/po/sr.po | 4255 ++++++----- ld/po/uk.po | 3264 ++++---- ld/stamp-h.in | 1 - libctf/ChangeLog | 4 + libiberty/ChangeLog | 4 + opcodes/ChangeLog | 14 + opcodes/Makefile.in | 1 - opcodes/configure | 20 +- opcodes/po/de.po | 512 +- opcodes/po/opcodes.pot | 2 +- opcodes/po/ro.po | 2948 +++++-- opcodes/po/uk.po | 530 +- opcodes/stamp-h.in | 1 - 77 files changed, 45812 insertions(+), 26623 deletions(-) delete mode 100644 bfd/doc/Makefile.am delete mode 100644 bfd/doc/Makefile.in create mode 100644 bfd/doc/local.mk delete mode 100644 bfd/stamp-h.in delete mode 100644 binutils/stamp-h.in delete mode 100644 gas/stamp-h.in delete mode 100644 gprof/stamp-h.in delete mode 100644 ld/stamp-h.in delete mode 100644 opcodes/stamp-h.in -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 7 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allmodconfig updated (8b96541ed -> 78a5496ad)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allmodconfig in repository toolchain/ci/base-artifacts. discards 8b96541ed 4: update: llvm-be7e938e2712f3d84d1775ecdb1bc6784ea114f7: 20623 new 78a5496ad 4: update: binutils-llvm-linux-qemu: 20623 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (8b96541ed) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-s [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1628 -> 1728 bytes 02-prepare_abe/console.log.xz | Bin 2768 -> 2760 bytes 03-build_abe-binutils/console.log.xz | Bin 29568 -> 30116 bytes 04-build_llvm/console.log.xz | Bin 58672 -> 59712 bytes 05-build_abe-qemu/console.log.xz | Bin 31168 -> 30460 bytes 06-build_linux/console.log.xz | Bin 42168 -> 40648 bytes 08-check_regression/console.log.xz | Bin 476 -> 480 bytes 09-update_baseline/console.log | 83 ++++++++++++++++++++++++++--------- jenkins/manifest.sh | 17 ++++--- 9 files changed, 73 insertions(+), 27 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 7 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig updated (47fa1ad534 -> aeb0ae95b7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig in repository toolchain/ci/qemu. from 47fa1ad534 Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-7 [...] adds 95ea96e8b1 hw/arm/virt: KVM: Enable PAuth when supported by the host adds 9adfbf1b61 hw: Move MARVELL_88W8618 Kconfig from audio/ to arm/ adds 8ede0245e2 hw/arm/musicpal: Fix coding style of code related to MV88W86 [...] adds 6d81f4887f hw/net: Move MV88W8618 network device out of hw/arm/ directory adds d55c316f91 hw/arm/virt: Support CPU cluster on ARM virt machine adds 28a60a59c0 hw/arm/virt: Support cluster level in DT cpu-map adds 11b9eb1b8a hw/acpi/aml-build: Improve scalability of PPTT generation adds 291f6dd566 tests/acpi/bios-tables-test: Allow changes to virt/PPTT file adds 88d0278aa7 hw/acpi/aml-build: Support cluster level in PPTT generation adds 3cda85b203 tests/acpi/bios-table-test: Update expected virt/PPTT file adds 87f14eaa51 docs/can: convert to restructuredText adds 1263615efe virtio-mem: Correct default THP size for ARM64 adds b1b87327a9 hw/arm/virt: Support for virtio-mem-pci adds a66a24585f hw/intc/arm_gic: Implement read of GICC_IIDR adds 5e66daec9e hw/intc/arm_gic: Allow reset of the running priority adds c8f008c40f hw/arm/virt: Add a control for the the highmem PCIe MMIO adds a63618b147 hw/arm/virt: Add a control for the the highmem redistributors adds 0152b169ce hw/arm/virt: Honor highmem setting when computing the memory map adds 3715c251cc hw/arm/virt: Use the PA range to compute the memory map adds d9afe24c29 hw/arm/virt: Disable highmem devices that don't fit in the PA range adds 2dcb74e5c2 hw/arm/virt: Drop superfluous checks against highmem adds 0419e6a867 hw/arm: kudo add lm75s behind bus 1 switch at 75 adds 119df56bf0 hw/misc/aspeed_i3c.c: Introduce a dummy AST2600 I3C model. adds 3222165dcb hw/arm/aspeed: Add the i3c device to the AST2600 SoC adds 8f809f6992 hw/intc/arm_gicv3_its: Fix event ID bounds checks adds 905720f18d hw/intc/arm_gicv3_its: Convert int ID check to num_intids co [...] adds 7d62b2dcdb hw/intc/arm_gicv3_its: Fix handling of process_its_cmd() ret [...] adds f0b4b2a28c hw/intc/arm_gicv3_its: Don't use data if reading command failed adds ef011555da hw/intc/arm_gicv3_its: Use enum for return value of process_ [...] adds 593a7cc2d3 hw/intc/arm_gicv3_its: Fix return codes in process_its_cmd() adds be0ed8fb7f hw/intc/arm_gicv3_its: Refactor process_its_cmd() to reduce nesting adds 0241f73160 hw/intc/arm_gicv3_its: Fix return codes in process_mapti() adds f667519614 hw/intc/arm_gicv3_its: Fix return codes in process_mapc() adds 00d46e72e9 hw/intc/arm_gicv3_its: Fix return codes in process_mapd() adds d050f80f8c hw/intc/arm_gicv3_its: Factor out "find address of table ent [...] adds b13148d918 hw/intc/arm_gicv3_its: Check indexes before use, not after adds 58b88779f0 hw/intc/arm_gicv3_its: Range-check ICID before indexing into [...] adds b9d383ab79 hw/intc/arm_gicv3: Check for !MEMTX_OK instead of MEMTX_ERROR adds 2c89b5af5e Merge remote-tracking branch 'remotes/pmaydell/tags/pull-tar [...] adds 28ca4689ae hw: timer: ibex_timer: Fixup reading w/o register adds 0df470c388 riscv: opentitan: fixup plic stride len adds dda94e5c66 hw: timer: ibex_timer: update/add reg address adds b91a0fa70c update-linux-headers: Add asm-riscv/kvm.h adds 91654e613b target/riscv: Add target/riscv/kvm.c to place the public kvm [...] adds 0a312b85cb target/riscv: Implement function kvm_arch_init_vcpu adds 937f0b4512 target/riscv: Implement kvm_arch_get_registers adds 9997cc1e19 target/riscv: Implement kvm_arch_put_registers adds ad40be2708 target/riscv: Support start kernel directly by KVM adds 2b650fbbcc target/riscv: Support setting external interrupt by KVM adds 4eb471258b target/riscv: Handle KVM_EXIT_RISCV_SBI exit adds 10f1ca27e0 target/riscv: Add host cpu type adds 27abe66f31 target/riscv: Add kvm_riscv_get/put_regs_timer adds 9ad3e016ae target/riscv: Implement virtual time adjusting with vm state [...] adds 1eb9a5da31 target/riscv: Support virtual time context synchronization adds fbf43c7dbf target/riscv: enable riscv kvm accel adds cfeeeb482a softmmu/device_tree: Silence compiler warning with --enable- [...] adds 22599b795c softmmu/device_tree: Remove redundant pointer assignment adds b4a99d4027 target/riscv: rvv-1.0: Add Zve64f extension into RISC-V adds c7a26fb2f6 target/riscv: rvv-1.0: Add Zve64f support for configuration insns adds 494104093f target/riscv: rvv-1.0: Add Zve64f support for load and store insns adds aaae69942f target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns adds 13dbc826fd target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and v [...] adds 40d78c85f6 target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns adds 193fb5c9bd target/riscv: rvv-1.0: Add Zve64f support for single-width f [...] adds 235d1161d4 target/riscv: rvv-1.0: Add Zve64f support for widening type- [...] adds 68fa38970e target/riscv: rvv-1.0: Add Zve64f support for narrowing type [...] adds bfefe406b7 target/riscv: rvv-1.0: Allow Zve64f extension to be turned on adds 32e579b8c5 target/riscv: rvv-1.0: Add Zve32f extension into RISC-V adds da61f1256f target/riscv: rvv-1.0: Add Zve32f support for configuration insns adds abe2d74032 target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns adds 8527b5db72 target/riscv: rvv-1.0: Add Zve32f support for single-width f [...] adds f4dcf51cdc target/riscv: rvv-1.0: Add Zve32f support for widening type- [...] adds 6db02328a7 target/riscv: rvv-1.0: Add Zve32f support for narrowing type [...] adds 2fc1b44dd0 target/riscv: rvv-1.0: Allow Zve32f extension to be turned on adds 8d8897accb hw/riscv: spike: Allow using binary firmware as bios adds 092dc6df92 hw/riscv: Remove macros for ELF BIOS image names adds 4211fc5532 roms/opensbi: Remove ELF images adds 79f26b3b95 target/riscv: Adjust pmpcfg access with mxl adds b655dc7cd9 target/riscv: Don't save pc when exception return adds a14db52f7f target/riscv: Sign extend link reg for jal and jalr adds 40f0c2046c target/riscv: Sign extend pc for different XLEN adds 440544e1cf target/riscv: Create xl field in env adds 8c796f1a15 target/riscv: Ignore the pc bits above XLEN adds bf9e776ec1 target/riscv: Extend pc for runtime pc write adds 1191be09a9 target/riscv: Use gdb xml according to max mxlen adds 47bdec821b target/riscv: Relax debug check for pm write adds 83b519b8a4 target/riscv: Adjust csr write mask with XLEN adds 40bfa5f695 target/riscv: Create current pm fields in env adds 0cff460de9 target/riscv: Alloc tcg global for cur_pm[mask|base] adds 4302bef9e1 target/riscv: Calculate address according to XLEN adds 4208dc7e9e target/riscv: Split pm_enabled into mask and base adds d96a271a8d target/riscv: Split out the vill from vtype adds 31961cfe50 target/riscv: Adjust vsetvl according to XLEN adds eef11ce325 target/riscv: Remove VILL field in VTYPE adds 01d09525da target/riscv: Fix check range for first fault only adds d6b9d93023 target/riscv: Adjust vector address with mask adds d8c40c24fd target/riscv: Adjust scalar reg in vector with XLEN adds 5a2ae2350e target/riscv: Set default XLEN for hypervisor adds f310df58bd target/riscv: Enable uxl field write adds f297245f6a target/riscv: Relax UXL field for debugging adds 5e9d14f2be Merge remote-tracking branch 'remotes/alistair/tags/pull-ris [...] adds 1e4d8b31be python: pin setuptools below v60.0.0 adds 57a6b4478c python: use avocado's "new" runner adds dc6877bd2e python/aqmp: fix docstring typo adds 3bc72e3aed python/aqmp: add __del__ method to legacy interface adds 3b5bf136f5 python/aqmp: handle asyncio.TimeoutError on execute() adds 0e6bfd8b96 python/aqmp: copy type definitions from qmp adds 728dcac5e3 python/aqmp: add SocketAddrT to package root adds 6e7751dc38 python/aqmp: rename AQMPError to QMPError adds 7017f3853a python/qemu-ga-client: don't use deprecated CLI syntax in us [...] adds 26db07516f python/qmp: switch qemu-ga-client to AQMP adds 8d6cdc5118 python/qmp: switch qom tools to AQMP adds f3efd12930 python/qmp: switch qmp-shell to AQMP adds 0347c4c4cf python: move qmp utilities to python/qemu/utils adds fd9c3a6219 python: move qmp-shell under the AQMP package adds 9922125615 scripts/cpu-x86-uarch-abi: fix CLI parsing adds 0665410dcf scripts/cpu-x86-uarch-abi: switch to AQMP adds 0590860242 scripts/render-block-graph: switch to AQMP adds aeb0ae95b7 Merge remote-tracking branch 'remotes/jsnow-gitlab/tags/pyth [...] No new revisions were added by this update. Summary of changes: .gitlab-ci.d/opensbi.yml | 2 - MAINTAINERS | 2 + docs/system/arm/cpu-features.rst | 4 - docs/system/device-emulation.rst | 1 + docs/{can.txt => system/devices/can.rst} | 92 ++--- hw/acpi/aml-build.c | 68 +++- hw/arm/Kconfig | 4 + hw/arm/aspeed_ast2600.c | 16 + hw/arm/musicpal.c | 381 +----------------- hw/arm/npcm7xx_boards.c | 10 +- hw/arm/virt-acpi-build.c | 10 +- hw/arm/virt.c | 184 ++++++++- hw/audio/Kconfig | 3 - hw/char/riscv_htif.c | 33 +- hw/intc/arm_gic.c | 11 + hw/intc/arm_gicv3_its.c | 452 ++++++++++----------- hw/intc/arm_gicv3_redist.c | 4 +- hw/intc/sifive_plic.c | 20 +- hw/misc/aspeed_i3c.c | 384 ++++++++++++++++++ hw/misc/meson.build | 1 + hw/misc/trace-events | 6 + hw/net/meson.build | 1 + hw/net/mv88w8618_eth.c | 403 +++++++++++++++++++ hw/riscv/boot.c | 16 +- hw/riscv/opentitan.c | 2 +- hw/riscv/spike.c | 45 ++- hw/riscv/virt.c | 83 ++-- hw/timer/ibex_timer.c | 25 +- hw/virtio/virtio-mem.c | 36 +- include/hw/arm/aspeed_soc.h | 3 + include/hw/arm/virt.h | 5 +- include/hw/char/riscv_htif.h | 5 +- include/hw/misc/aspeed_i3c.h | 48 +++ include/hw/net/mv88w8618_eth.h | 12 + include/hw/riscv/boot.h | 3 +- include/hw/riscv/spike.h | 1 + include/hw/timer/ibex_timer.h | 1 - linux-headers/asm-riscv/kvm.h | 128 ++++++ meson.build | 2 + pc-bios/meson.build | 2 - pc-bios/opensbi-riscv32-generic-fw_dynamic.elf | Bin 838904 -> 0 bytes pc-bios/opensbi-riscv64-generic-fw_dynamic.elf | Bin 934696 -> 0 bytes python/Makefile | 2 + python/README.rst | 2 +- python/avocado.cfg | 2 +- python/qemu/aqmp/__init__.py | 16 +- python/qemu/aqmp/error.py | 12 +- python/qemu/aqmp/events.py | 4 +- python/qemu/aqmp/legacy.py | 41 +- python/qemu/aqmp/protocol.py | 24 +- python/qemu/aqmp/qmp_client.py | 16 +- python/qemu/{qmp => aqmp}/qmp_shell.py | 31 +- python/qemu/{qmp => utils}/qemu_ga_client.py | 24 +- python/qemu/{qmp => utils}/qom.py | 5 +- python/qemu/{qmp => utils}/qom_common.py | 3 +- python/qemu/{qmp => utils}/qom_fuse.py | 11 +- python/setup.cfg | 19 +- qemu-options.hx | 10 + roms/Makefile | 2 - scripts/cpu-x86-uarch-abi.py | 7 +- scripts/qmp/qemu-ga-client | 2 +- scripts/qmp/qmp-shell | 2 +- scripts/qmp/qom-fuse | 2 +- scripts/qmp/qom-get | 2 +- scripts/qmp/qom-list | 2 +- scripts/qmp/qom-set | 2 +- scripts/qmp/qom-tree | 2 +- scripts/render_block_graph.py | 8 +- softmmu/device_tree.c | 11 +- target/arm/cpu.c | 16 +- target/arm/cpu.h | 1 + target/arm/cpu64.c | 31 +- target/arm/kvm64.c | 21 + target/riscv/cpu.c | 77 +++- target/riscv/cpu.h | 58 ++- target/riscv/cpu_bits.h | 3 + target/riscv/cpu_helper.c | 99 ++--- target/riscv/csr.c | 90 ++++- target/riscv/gdbstub.c | 71 +++- target/riscv/helper.h | 4 +- target/riscv/insn_trans/trans_privileged.c.inc | 9 +- target/riscv/insn_trans/trans_rva.c.inc | 9 +- target/riscv/insn_trans/trans_rvd.c.inc | 19 +- target/riscv/insn_trans/trans_rvf.c.inc | 19 +- target/riscv/insn_trans/trans_rvi.c.inc | 39 +- target/riscv/insn_trans/trans_rvv.c.inc | 225 +++++++++-- target/{rx/cpu-param.h => riscv/kvm-stub.c} | 26 +- target/riscv/kvm.c | 535 +++++++++++++++++++++++++ target/{rx/cpu-param.h => riscv/kvm_riscv.h} | 17 +- target/riscv/machine.c | 46 ++- target/riscv/meson.build | 1 + target/riscv/op_helper.c | 7 +- target/riscv/pmp.c | 12 +- target/riscv/sbi_ecall_interface.h | 72 ++++ target/riscv/translate.c | 94 +++-- target/riscv/vector_helper.c | 39 +- tests/data/acpi/virt/PPTT | Bin 76 -> 96 bytes 97 files changed, 3180 insertions(+), 1233 deletions(-) rename docs/{can.txt => system/devices/can.rst} (68%) create mode 100644 hw/misc/aspeed_i3c.c create mode 100644 hw/net/mv88w8618_eth.c create mode 100644 include/hw/misc/aspeed_i3c.h create mode 100644 include/hw/net/mv88w8618_eth.h create mode 100644 linux-headers/asm-riscv/kvm.h delete mode 100644 pc-bios/opensbi-riscv32-generic-fw_dynamic.elf delete mode 100644 pc-bios/opensbi-riscv64-generic-fw_dynamic.elf rename python/qemu/{qmp => aqmp}/qmp_shell.py (96%) rename python/qemu/{qmp => utils}/qemu_ga_client.py (94%) rename python/qemu/{qmp => utils}/qom.py (98%) rename python/qemu/{qmp => utils}/qom_common.py (98%) rename python/qemu/{qmp => utils}/qom_fuse.py (97%) copy target/{rx/cpu-param.h => riscv/kvm-stub.c} (67%) create mode 100644 target/riscv/kvm.c copy target/{rx/cpu-param.h => riscv/kvm_riscv.h} (70%) create mode 100644 target/riscv/sbi_ecall_interface.h -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 7 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig updated (5c12507f5d0 -> 2a908f3da07)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig in repository toolchain/ci/gcc. from 5c12507f5d0 middle-end/100786 - constant folding from incompatible alias adds 2f34d7ef3d0 c++: add testcase for recently fixed PR [PR103631] adds 30b38394b48 c++: Add test for fixed PR [PR102338] adds cc01cd9397f c++: designator for base class member [PR101405] adds d2ad748eeef Fortran: Fix scope for OMP AFFINITY clause iterator variabl [...] adds f5a9d76be84 analyzer: add regression test [PR103685] adds c4b8f3730a8 analyzer: reject ((i + 1 > 0) && (i < 0)) for integers [PR94362] adds 5fa55d55abd Daily bump. adds 39cd3cce525 runtime: build panic32.go on amd64p32 adds 6f45deb2aed [committed] Fix expected output for various MIPS multiplica [...] adds c2d9159717b optabs: Don't create pseudos in prepare_cmp_insn when not a [...] adds eb5ee646480 Reset relations when crossing backedges. adds 3e0b19f1d67 warn-access: Fix up warning_at arguments adds 1ad72811242 tree-optimization/104152 - add missing check for SLP consta [...] adds f953c8bc5bf tree-optimization/104156 - fix unswitching compare-debug issue adds bab0f691d52 aarch64: Adjust spellcheck tests for recent quotation-mark changes adds 9d7a84b9698 [ARM] Add support for TLS register based stack protector ca [...] adds caca8eddd93 sanitizer/99673 - bad -Wstringop-overread diagnostic with asan adds 7d47aae7cd4 libstdc++: Fix constexpr constructor for atomic<shared_ptr<T>> adds 199cd0e0f87 tree-optimization/100089 - BB vectorization of if-converted [...] adds 97f81909343 Enable configure detection of ld.mold. adds 2da1ef06ff4 libstdc++: Fix condition for __cpp_lib_shared_ptr_arrays adds b8806796ec6 libstdc++: Ensure all feature test macros have type long [PR87193] adds 45cae5b6392 libstdc++: Fix typo in comment adds 23be9f83bbd c++: [[no_unique_address]] and virtual base [PR104139] adds 087e545747c Strengthen a few OpenACC test cases adds 3abcbf24323 c++: ICE with noexcept and canonical types [PR101715] adds 85419ac5972 [PR103676] LRA: Calculate and exclude some start hard regis [...] adds 886e9779581 PR middle-end/104140: bootstrap ICE on riscv. adds 518aad6a161 rs6000: Fix bootstrap adds afe91e2566f rs6000: Support vector float/double for vec_sldw adds c163647ffbc Disable -fsplit-stack support on non-glibc targets adds 847a8301add c++: class array new checking [PR104084] adds 2e01fde49ea c++: explain failing static_assert adds f36efe71bef c-family: Fix up a -Wformat regression [PR104148] adds 60953a23d57 x86: Properly disable -fsplit-stack support on non-glibc targets adds f9063d12633 Mark XXSPLTIW/XXSPLTIDP as prefixed -- PR 104136 adds 9dd443578f3 Daily bump. adds abe3a4f0e9c Fix fold-vec-splat-floatdouble testsuite failure on power10 adds 0f4f9c0085e toplevel: Remove accedentally checked in file adds 6c1a93102b4 Fortran: fix simplification of TRANSFER for zero-sized char [...] adds 45b999f642a analyzer: fix ICE on vector casts [PR104159] adds a1fb81bda97 testsuite: guard usage of _Float16 in analyzer test [PR104150] adds 9ea451e2793 ootstrap: Fix bootstrap with --disable-plugin [PR104176] adds d43be9dcc1b Daily bump. adds 053bcc97f4a c++: constexpr and -fno-elide-constructors [PR101072] adds 9718bc4b03c c++: array temporary at file scope [PR104182] adds 603a9ab41f4 contrib: filter out one more Clang warning. adds cbcf4a50fa2 [aarch64/64821]: Simplify __builtin_aarch64_sqrt* into inte [...] adds 2da90ad39bf c++: designated init of char array by string constant [PR55227] adds 2d8a9ad4a92 libstdc++: Fix aliasing violation in std::shared_ptr [PR104019] adds 084680db9af libstdc++: Restore support for unordered_map<const T, ...> [...] adds 416b6fc7483 libstdc++: Use fast_float for long double if it uses binary [...] adds 51631875a2f libstdc++: Fix std::spanstream move assignment [PR104032] adds 0c940703f00 Daily bump. adds 4d2321314a6 x86: Also check mode of memory broadcast in bcst_mem_operand adds 7b84fa2a2dd testsuite: Ignore pr104159 psabi warning. adds add6bb52e34 RISC-V: Update testcases info with new implement info adds 634de54f9c4 Update the type of control.base after changed adds 98416dbb0a6 RISC-V: Change default ISA version into 20191213 adds ca2bbb88f99 RISC-V: Do not emit zcisr and zifencei if i-ext is 2.0 adds c106529eb21 RISC-V: Fix testcase after bump isa spec version adds 2c31a8be4a5 properly disable -fsplit-stack on non-glibc targets [PR104170] adds 385196adb52 options: Add EnumSet and Set property support [PR104158] adds cd0377a460d options: Fix up -fsanitize-coverage= [PR104158] adds 9acd5a01175 fortran: Extend -fconvert= option for ppc64le r16_ieee and r16_ibm adds 0ebb09f5e49 options: Add EnumBitSet property support [PR104158] adds 2755037e40a acinclude.m4: Remove duplicite AC_DEFUN. adds f1af8528d34 tree-optimization/102131 - fix niter analysis wrt overflow adds 978abe918f8 gcc-changelog: Be stricter for top-level dir. adds 2a908f3da07 c++: value category of compound object expr [PR104173] No new revisions were added by this update. Summary of changes: ChangeLog | 9 + build.log | 0 contrib/ChangeLog | 5 + contrib/filter-clang-warnings.py | 3 +- contrib/gcc-changelog/git_commit.py | 12 +- contrib/gcc-changelog/test_email.py | 5 + contrib/gcc-changelog/test_patches.txt | 82 ++++++ gcc/ChangeLog | 315 +++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/analyzer/ChangeLog | 32 +++ gcc/analyzer/constraint-manager.cc | 172 ++++++++++- gcc/analyzer/constraint-manager.h | 15 +- gcc/analyzer/region-model-manager.cc | 11 + gcc/analyzer/region-model.cc | 5 +- gcc/c-family/ChangeLog | 12 + gcc/c-family/c-common.cc | 25 +- gcc/c-family/c-common.h | 3 +- gcc/c-family/c-format.cc | 2 +- gcc/common.opt | 6 +- gcc/common/config/i386/i386-common.cc | 17 +- gcc/common/config/riscv/riscv-common.cc | 14 +- gcc/common/config/s390/s390-common.cc | 14 +- gcc/config.gcc | 8 +- gcc/config/aarch64/aarch64-builtins.cc | 7 + gcc/config/alpha/linux.h | 25 +- gcc/config/arm/arm-opts.h | 6 + gcc/config/arm/arm-protos.h | 2 + gcc/config/arm/arm.cc | 55 ++++ gcc/config/arm/arm.md | 71 ++++- gcc/config/arm/arm.opt | 22 ++ gcc/config/fuchsia.h | 2 + gcc/config/glibc-stdint.h | 3 + gcc/config/i386/predicates.md | 2 + gcc/config/linux.h | 25 +- gcc/config/riscv/riscv-c.cc | 3 + gcc/config/rs6000/linux.h | 25 +- gcc/config/rs6000/linux64.h | 25 +- gcc/config/rs6000/rs6000-overload.def | 4 + gcc/config/rs6000/rs6000-protos.h | 1 - gcc/config/rs6000/rs6000.cc | 40 +-- gcc/config/rs6000/rs6000.md | 24 +- gcc/config/rs6000/vsx.md | 12 +- gcc/configure | 18 ++ gcc/configure.ac | 16 ++ gcc/cp/ChangeLog | 83 ++++++ gcc/cp/call.cc | 32 ++- gcc/cp/class.cc | 4 +- gcc/cp/cp-gimplify.cc | 6 +- gcc/cp/cp-tree.h | 1 + gcc/cp/decl.cc | 49 ++-- gcc/cp/init.cc | 2 +- gcc/cp/pt.cc | 9 - gcc/cp/semantics.cc | 42 ++- gcc/cp/tree.cc | 25 +- gcc/cp/typeck.cc | 19 +- gcc/doc/generic.texi | 9 + gcc/doc/invoke.texi | 11 + gcc/doc/options.texi | 33 +++ gcc/fortran/ChangeLog | 20 ++ gcc/fortran/dump-parse-tree.cc | 4 +- gcc/fortran/gfortran.h | 3 + gcc/fortran/lang.opt | 18 +- gcc/fortran/openmp.cc | 6 +- gcc/fortran/simplify.cc | 13 +- gcc/fortran/trans-decl.cc | 3 + gcc/fortran/trans-openmp.cc | 2 +- gcc/fortran/trans-types.cc | 3 + gcc/gimple-range-path.cc | 48 +++- gcc/gimple-range-path.h | 3 +- gcc/gimple-ssa-warn-access.cc | 5 +- gcc/go/gofrontend/MERGE | 2 +- gcc/ira.cc | 14 +- gcc/ira.h | 7 + gcc/lra-assigns.cc | 2 +- gcc/lra-constraints.cc | 148 ++++++---- gcc/lra-int.h | 8 +- gcc/lra-remat.cc | 2 +- gcc/lra.cc | 18 +- gcc/lra.h | 2 - gcc/opt-functions.awk | 7 +- gcc/opt-read.awk | 4 + gcc/optabs.cc | 8 +- gcc/optc-gen.awk | 2 + gcc/opts-common.cc | 180 ++++++++++-- gcc/opts-global.cc | 6 +- gcc/opts.cc | 59 +++- gcc/opts.h | 24 +- gcc/testsuite/ChangeLog | 221 +++++++++++++++ gcc/testsuite/c-c++-common/Wformat-pr104148.c | 33 +++ gcc/testsuite/g++.dg/abi/no_unique_address2.C | 27 ++ gcc/testsuite/g++.dg/cpp0x/constexpr-empty14a.C | 11 + gcc/testsuite/g++.dg/cpp0x/initlist127.C | 39 +++ gcc/testsuite/g++.dg/cpp0x/noexcept72.C | 21 ++ gcc/testsuite/g++.dg/cpp0x/noexcept73.C | 13 + gcc/testsuite/g++.dg/cpp0x/ref-qual21.C | 23 ++ gcc/testsuite/g++.dg/cpp1y/noexcept2.C | 20 ++ gcc/testsuite/g++.dg/cpp2a/desig20.C | 20 ++ gcc/testsuite/g++.dg/cpp2a/desig21.C | 48 ++++ gcc/testsuite/g++.dg/cpp2a/nontype-class51.C | 26 ++ gcc/testsuite/g++.dg/init/new50.C | 9 + gcc/testsuite/g++.dg/template/explicit-args6.C | 2 + gcc/testsuite/g++.target/arm/pr103676.C | 32 +++ gcc/testsuite/gcc.dg/analyzer/pr104089.c | 2 + gcc/testsuite/gcc.dg/analyzer/pr94362-1.c | 60 ++++ gcc/testsuite/gcc.dg/analyzer/pr94362-2.c | 42 +++ gcc/testsuite/gcc.dg/analyzer/torture/pr103685.c | 33 +++ gcc/testsuite/gcc.dg/analyzer/torture/pr104159.c | 18 ++ gcc/testsuite/gcc.dg/asan/pr99673.c | 27 ++ gcc/testsuite/gcc.dg/loop-unswitch-6.c | 32 +++ gcc/testsuite/gcc.dg/pr102087_1.c | 13 + gcc/testsuite/gcc.dg/pr102478.c | 29 ++ gcc/testsuite/gcc.dg/pr103721-2.c | 28 ++ gcc/testsuite/gcc.dg/pr103721.c | 25 ++ gcc/testsuite/gcc.dg/sancov/pr104158-1.c | 11 + gcc/testsuite/gcc.dg/sancov/pr104158-2.c | 11 + gcc/testsuite/gcc.dg/sancov/pr104158-3.c | 11 + gcc/testsuite/gcc.dg/sancov/pr104158-4.c | 11 + gcc/testsuite/gcc.dg/sancov/pr104158-5.c | 11 + gcc/testsuite/gcc.dg/sancov/pr104158-6.c | 11 + gcc/testsuite/gcc.dg/sancov/pr104158-7.c | 11 + gcc/testsuite/gcc.dg/spellcheck-options-24.c | 5 + gcc/testsuite/gcc.dg/torture/pr100740.c | 12 + gcc/testsuite/gcc.dg/torture/pr101508.c | 13 + gcc/testsuite/gcc.dg/torture/pr101972.c | 39 +++ gcc/testsuite/gcc.dg/torture/pr102131-1.c | 16 ++ gcc/testsuite/gcc.dg/torture/pr102131-2.c | 15 + gcc/testsuite/gcc.dg/torture/pr102131-3.c | 11 + gcc/testsuite/gcc.dg/torture/pr102131-4.c | 15 + gcc/testsuite/gcc.dg/vect/pr104152.c | 40 +++ gcc/testsuite/gcc.target/aarch64/spellcheck_1.c | 2 +- gcc/testsuite/gcc.target/aarch64/spellcheck_2.c | 2 +- gcc/testsuite/gcc.target/aarch64/spellcheck_3.c | 2 +- gcc/testsuite/gcc.target/aarch64/spellcheck_7.c | 2 +- gcc/testsuite/gcc.target/aarch64/vsqrt-1.c | 17 ++ gcc/testsuite/gcc.target/aarch64/vsqrt-2.c | 28 ++ gcc/testsuite/gcc.target/arm/stack-protector-7.c | 12 + gcc/testsuite/gcc.target/arm/stack-protector-8.c | 7 + gcc/testsuite/gcc.target/i386/pr104188.c | 70 +++++ gcc/testsuite/gcc.target/mips/fix-r4000-2.c | 4 +- gcc/testsuite/gcc.target/mips/fix-r4000-3.c | 6 +- gcc/testsuite/gcc.target/mips/fix-r4000-7.c | 4 +- gcc/testsuite/gcc.target/mips/fix-r4000-8.c | 6 +- gcc/testsuite/gcc.target/powerpc/builtins-4.c | 34 ++- .../powerpc/fold-vec-splat-floatdouble.c | 5 +- gcc/testsuite/gcc.target/riscv/arch-10.c | 2 +- gcc/testsuite/gcc.target/riscv/arch-12.c | 2 +- gcc/testsuite/gcc.target/riscv/arch-9.c | 2 +- gcc/testsuite/gcc.target/riscv/attribute-19.c | 2 +- gcc/testsuite/gcc.target/riscv/pr104140.c | 11 + .../gfortran.dg/gomp/affinity-clause-3.f90 | 2 +- gcc/testsuite/gfortran.dg/gomp/pr102621.f90 | 12 + gcc/testsuite/gfortran.dg/gomp/pr103695.f90 | 18 ++ gcc/testsuite/gfortran.dg/transfer_simplify_11.f90 | 2 +- gcc/testsuite/gfortran.dg/transfer_simplify_13.f90 | 34 +++ gcc/tree-ssa-loop-niter.cc | 49 +++- gcc/tree-ssa-loop-unswitch.cc | 50 ++-- gcc/tree-ssa-math-opts.cc | 4 + gcc/tree-ssa-threadbackward.cc | 4 + gcc/tree-vect-slp.cc | 20 +- gcc/tree.def | 14 +- gcc/value-relation.cc | 4 +- gcc/value-relation.h | 1 + libatomic/acinclude.m4 | 102 ------- libatomic/configure | 6 +- libgo/go/runtime/panic32.go | 4 +- libgomp/ChangeLog | 18 ++ .../libgomp.oacc-c-c++-common/loop-gwv-1.c | 25 +- .../libgomp.oacc-c-c++-common/loop-gwv-2.c | 34 ++- .../libgomp.oacc-c-c++-common/loop-red-gwv-1.c | 22 +- .../libgomp.oacc-c-c++-common/loop-red-v-1.c | 11 +- .../libgomp.oacc-c-c++-common/loop-red-v-2.c | 11 +- .../libgomp.oacc-c-c++-common/loop-red-w-1.c | 13 +- .../libgomp.oacc-c-c++-common/loop-red-w-2.c | 13 +- .../libgomp.oacc-c-c++-common/loop-red-wv-1.c | 19 +- .../testsuite/libgomp.oacc-c-c++-common/loop-v-1.c | 13 +- .../testsuite/libgomp.oacc-c-c++-common/loop-w-1.c | 13 +- .../libgomp.oacc-c-c++-common/loop-wv-1.c | 19 +- .../libgomp.oacc-c-c++-common/routine-gwv-1.c | 21 +- .../libgomp.oacc-c-c++-common/routine-v-1.c | 13 +- .../libgomp.oacc-c-c++-common/routine-w-1.c | 13 +- .../libgomp.oacc-c-c++-common/routine-wv-1.c | 19 +- libstdc++-v3/ChangeLog | 123 ++++++++ libstdc++-v3/include/bits/alloc_traits.h | 2 +- libstdc++-v3/include/bits/allocator.h | 2 +- libstdc++-v3/include/bits/basic_string.h | 2 +- libstdc++-v3/include/bits/chrono.h | 4 +- libstdc++-v3/include/bits/hashtable_policy.h | 11 + libstdc++-v3/include/bits/move.h | 2 +- libstdc++-v3/include/bits/node_handle.h | 2 +- libstdc++-v3/include/bits/range_access.h | 2 +- libstdc++-v3/include/bits/shared_ptr.h | 2 +- libstdc++-v3/include/bits/shared_ptr_atomic.h | 4 +- libstdc++-v3/include/bits/shared_ptr_base.h | 2 +- libstdc++-v3/include/bits/stl_algo.h | 4 +- libstdc++-v3/include/bits/stl_algobase.h | 2 +- libstdc++-v3/include/bits/stl_function.h | 2 +- libstdc++-v3/include/bits/stl_iterator.h | 2 +- libstdc++-v3/include/bits/stl_map.h | 2 +- libstdc++-v3/include/bits/stl_tree.h | 2 +- libstdc++-v3/include/bits/unique_ptr.h | 2 +- libstdc++-v3/include/bits/unordered_map.h | 2 +- libstdc++-v3/include/c_global/cmath | 2 +- libstdc++-v3/include/c_global/cstddef | 2 +- libstdc++-v3/include/std/atomic | 2 +- libstdc++-v3/include/std/complex | 2 +- libstdc++-v3/include/std/filesystem | 2 +- libstdc++-v3/include/std/functional | 4 +- libstdc++-v3/include/std/iomanip | 2 +- libstdc++-v3/include/std/mutex | 2 +- libstdc++-v3/include/std/numeric | 6 +- libstdc++-v3/include/std/spanstream | 15 +- libstdc++-v3/include/std/tuple | 4 +- libstdc++-v3/include/std/type_traits | 22 +- libstdc++-v3/include/std/version | 102 +++---- libstdc++-v3/libsupc++/new | 2 +- libstdc++-v3/src/c++17/floating_from_chars.cc | 38 ++- .../20_util/shared_ptr/atomic/atomic_shared_ptr.cc | 3 + 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gcc/testsuite/g++.target/arm/pr103676.C create mode 100644 gcc/testsuite/gcc.dg/analyzer/pr94362-1.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/pr94362-2.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/torture/pr103685.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/torture/pr104159.c create mode 100644 gcc/testsuite/gcc.dg/asan/pr99673.c create mode 100644 gcc/testsuite/gcc.dg/loop-unswitch-6.c create mode 100644 gcc/testsuite/gcc.dg/pr102087_1.c create mode 100644 gcc/testsuite/gcc.dg/pr102478.c create mode 100644 gcc/testsuite/gcc.dg/pr103721-2.c create mode 100644 gcc/testsuite/gcc.dg/pr103721.c create mode 100644 gcc/testsuite/gcc.dg/sancov/pr104158-1.c create mode 100644 gcc/testsuite/gcc.dg/sancov/pr104158-2.c create mode 100644 gcc/testsuite/gcc.dg/sancov/pr104158-3.c create mode 100644 gcc/testsuite/gcc.dg/sancov/pr104158-4.c create mode 100644 gcc/testsuite/gcc.dg/sancov/pr104158-5.c create mode 100644 gcc/testsuite/gcc.dg/sancov/pr104158-6.c create mode 100644 gcc/testsuite/gcc.dg/sancov/pr104158-7.c create mode 100644 gcc/testsuite/gcc.dg/spellcheck-options-24.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr100740.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr101508.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr101972.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr102131-1.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr102131-2.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr102131-3.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr102131-4.c create mode 100644 gcc/testsuite/gcc.dg/vect/pr104152.c create mode 100644 gcc/testsuite/gcc.target/aarch64/vsqrt-1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/vsqrt-2.c create mode 100644 gcc/testsuite/gcc.target/arm/stack-protector-7.c create mode 100644 gcc/testsuite/gcc.target/arm/stack-protector-8.c create mode 100644 gcc/testsuite/gcc.target/i386/pr104188.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr104140.c create mode 100644 gcc/testsuite/gfortran.dg/gomp/pr102621.f90 create mode 100644 gcc/testsuite/gfortran.dg/gomp/pr103695.f90 create mode 100644 gcc/testsuite/gfortran.dg/transfer_simplify_13.f90 create mode 100644 libstdc++-v3/testsuite/23_containers/unordered_map/104174.cc create mode 100644 libstdc++-v3/testsuite/27_io/spanstream/2.cc -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 7 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig updated (6d263fe46e -> 965c919f98)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig in repository toolchain/ci/binutils-gdb. from 6d263fe46e Avoid bad breakpoints with --gc-sections adds df9d50bb22 Automatic date update in version.in adds 7bf5587873 gdbsupport/gdb_regex.cc: replace defs.h include with common-defs.h adds ec7194506d drop old unused stamp-h.in file adds b13d7831eb gdb/doc: fill in two missing @r adds e901223d53 Updated Serbian translation for the ld sub-directory adds ed09c325ec gdb: include gdbsupport/buildargv.h in ser-mingw.c adds 5b4ea8a740 Automatic date update in version.in adds cb2562f553 RISC-V: create new frag after alignment. adds a74e1cb344 Add markers for 2.38 branch adds f908e960c5 Change version number to 2.38.50 and regenerate files adds 5f7a57f131 Update release makeing script with new release numbers adds cc5e40736d Adjust default page sizes for haiku arm. adds 58de646be2 Allow inferring tmp_prefix from the dll name from a def file. adds 3dd8e5b615 bfd: replace doc header generation with pattern rules adds cb803d3749 bfd: rename core.texi to corefile.texi adds bd32be01c9 bfd: merge doc subdir up a level adds 35638469cb Automatic date update in version.in adds 31b0378d53 Regenerate configure files with autoconf 2.69 adds ad69b6b861 Regenerate Makefile.in files with automake 1.15.1 adds 0e3839bde6 bfd: Properly install library and header files adds 451c003d5f bfd: Partially revert commit 0e3839bde6f adds f10522c0e7 Simplify some Rust expression-evaluation code adds 2b1ca85cf8 Automatic date update in version.in adds 5fe73d4624 Update Bulgarian, French, Romaniam and Ukranian translation [...] adds 965c919f98 gdb/doc: improve description for Window.click on Python TUI windows No new revisions were added by this update. Summary of changes: ChangeLog | 4 + bfd/.gitignore | 2 +- bfd/ChangeLog | 16 + bfd/Makefile.am | 22 +- bfd/Makefile.in | 508 +- bfd/configure | 42 +- bfd/configure.ac | 3 +- bfd/doc/Makefile.am | 217 - bfd/doc/Makefile.in | 1021 --- bfd/doc/bfd.texi | 2 +- bfd/doc/local.mk | 152 + bfd/po/bfd.pot | 112 +- bfd/po/fr.po | 3116 ++++---- bfd/po/ro.po | 10194 ++++++++++++++++++++----- bfd/po/uk.po | 3102 ++++---- bfd/stamp-h.in | 1 - bfd/version.h | 2 +- bfd/version.m4 | 2 +- binutils/BRANCHES | 1 + binutils/ChangeLog | 21 + binutils/Makefile.in | 1 - binutils/NEWS | 2 + binutils/README-how-to-make-a-release | 35 +- binutils/configure | 20 +- binutils/dlltool.c | 34 +- binutils/po/bg.po | 6039 +++++++++------ binutils/po/binutils.pot | 4084 +++++----- binutils/po/fr.po | 4192 +++++----- binutils/po/ro.po | 13085 +++++++++++++++++++++++++------- binutils/po/uk.po | 4202 +++++----- binutils/stamp-h.in | 1 - config/ChangeLog | 4 + cpu/ChangeLog | 4 + elfcpp/ChangeLog | 4 + gas/ChangeLog | 13 + gas/Makefile.in | 1 - gas/NEWS | 2 + gas/config/tc-riscv.c | 6 + gas/configure | 20 +- gas/po/gas.pot | 20 +- gas/po/uk.po | 4880 ++++++------ gas/stamp-h.in | 1 - gdb/doc/python.texi | 10 +- gdb/rust-exp.h | 39 +- gdb/rust-lang.c | 44 +- gdb/ser-mingw.c | 1 + gdbsupport/gdb_regex.cc | 2 +- gold/ChangeLog | 15 + gold/po/gold.pot | 248 +- gold/po/uk.po | 257 +- gprof/ChangeLog | 14 + gprof/configure | 20 +- gprof/po/gprof.pot | 4 +- gprof/po/ro.po | 386 +- gprof/stamp-h.in | 1 - include/ChangeLog | 4 + ld/ChangeLog | 24 + ld/Makefile.in | 1 - ld/NEWS | 2 + ld/configure | 20 +- ld/configure.tgt | 2 +- ld/emulparams/armelf_haiku.sh | 4 +- ld/po/bg.po | 4373 ++++++----- ld/po/ld.pot | 218 +- ld/po/sr.po | 4255 ++++++----- ld/po/uk.po | 3264 ++++---- ld/stamp-h.in | 1 - libctf/ChangeLog | 4 + libiberty/ChangeLog | 4 + opcodes/ChangeLog | 14 + opcodes/Makefile.in | 1 - opcodes/configure | 20 +- opcodes/po/de.po | 512 +- opcodes/po/opcodes.pot | 2 +- opcodes/po/ro.po | 2948 +++++-- opcodes/po/uk.po | 530 +- opcodes/stamp-h.in | 1 - 77 files changed, 45812 insertions(+), 26623 deletions(-) delete mode 100644 bfd/doc/Makefile.am delete mode 100644 bfd/doc/Makefile.in create mode 100644 bfd/doc/local.mk delete mode 100644 bfd/stamp-h.in delete mode 100644 binutils/stamp-h.in delete mode 100644 gas/stamp-h.in delete mode 100644 gprof/stamp-h.in delete mode 100644 ld/stamp-h.in delete mode 100644 opcodes/stamp-h.in -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 7 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig updated (034d80ead -> faeb8e7ce)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig in repository toolchain/ci/base-artifacts. discards 034d80ead 4: update: binutils-gcc-linux-qemu: 21102 new faeb8e7ce 4: update: binutils-gcc-linux-qemu: 21102 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (034d80ead) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-arm-lt [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1616 -> 1796 bytes 02-prepare_abe/console.log.xz | Bin 2772 -> 2788 bytes 03-build_abe-binutils/console.log.xz | Bin 30476 -> 30616 bytes 04-build_abe-stage1/console.log.xz | Bin 89912 -> 91172 bytes 05-build_abe-qemu/console.log.xz | Bin 29980 -> 30724 bytes 06-build_linux/console.log.xz | Bin 46180 -> 47252 bytes 08-check_regression/console.log.xz | Bin 476 -> 484 bytes 09-update_baseline/console.log | 224 +++++++++++++++++------------------ jenkins/manifest.sh | 16 +-- 9 files changed, 120 insertions(+), 120 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 7 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_bmk_gnu_eabi_stm32/gnu_eabi-release-arm_eabi-coremark-O3 updated (806d0ce8cb0 -> ce3954262a6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_gnu_eabi_stm32/gnu_eabi-release-arm_eabi-coremark-O3 in repository toolchain/ci/gcc. from 806d0ce8cb0 ipa: "naked" attribute implies "noipa" attribute adds 1b9037dd4ef Daily bump. adds 15eae6020dc git scripts: sync from master. adds 892c58d9311 [Ada] Compile s-mmap and 128bit on x86_64-linux-gnux32 adds 1d3f5f5e52a [Ada] Set target_cpu to x32 for x86_64-linux-gnux32 adds f953701576b Daily bump. adds 0351d851f79 Fortran: handle expansion of zero-sized array constructors adds 448e9a53939 Daily bump. adds 99566992720 Daily bump. adds 8adfe466f55 Daily bump. adds a8c23451936 Fortran: fix ICE and wrong code with TRANSFER and CHARACTER [...] adds 11581a272eb Daily bump. adds 520147ba19d x86: Also check mode of memory broadcast in bcst_mem_operand adds c239267759b c: Fix ICE on deferred pragma in unknown attribute argument [...] adds 2712f1249e0 optabs: Fix up checking for CALLs in newly added code by do [...] adds 06142a317a4 loop-invariant: Fix -fcompare-debug failure [PR103837] adds fbc542de1bc fold-const: Fix up fold_truth_andor_1 shift handling [PR103813] adds a4e45a579e2 shrink-wrapping: Fix up prologue block discovery [PR103860] adds be66fad59a7 c-family: Use BULTINS_LOCATION for predefined macros change [...] adds 533695ca333 libcpp: Fix up ##__VA_OPT__ handling [PR89971] adds 27cfe106823 objc: Fix handling of break stmt inside of switch inside of [...] adds 0dd533da49c ifcvt: Check for asm goto at the end of then_bb/else_bb in [...] adds 18abe529d09 c++: Ensure some more that immediate functions aren't gimpl [...] adds 777b73e4598 c-family: Fix up -W*conversion on bitwise &/|/^ [PR101537] adds cb4998fcdf2 c++: Silence -Wuseless-cast warnings during move [PR103480] adds 91ac88cada3 c++: Fix handling of temporaries with consteval ctors and n [...] adds 8e4c410bb02 i386: Fix *aes<aeswideklvariant>u8 adds baf18a6d47c match.pd, optabs: Avoid vectorization of {FLOOR,CEIL,ROUND} [...] adds 3991e4c752b dwarf2out: Fix -gsplit-dwarf on riscv [PR103874] adds 505b418a40a optabs: Don't create pseudos in prepare_cmp_insn when not a [...] adds ce3954262a6 gcc-changelog: sync from master. No new revisions were added by this update. Summary of changes: contrib/ChangeLog | 6 ++ contrib/gcc-changelog/git_commit.py | 12 ++- contrib/gcc-changelog/test_email.py | 5 + contrib/gcc-changelog/test_patches.txt | 82 +++++++++++++++ contrib/git-backport.py | 50 +--------- contrib/git-commit-mklog.py | 6 ++ contrib/{git-backport.py => git-fix-changelog.py} | 59 ++++++----- gcc/ChangeLog | 9 ++ gcc/DATESTAMP | 2 +- gcc/ada/ChangeLog | 22 +++++ gcc/ada/Makefile.rtl | 5 + gcc/ada/gcc-interface/Makefile.in | 7 ++ gcc/c-family/c-cppbuiltin.c | 6 ++ gcc/c-family/c-warn.c | 28 ++++++ gcc/c/c-parser.c | 5 + gcc/c/c-typeck.c | 3 +- gcc/config/aarch64/aarch64-c.c | 2 + gcc/config/arm/arm-c.c | 2 + gcc/config/i386/i386-c.c | 4 + gcc/config/i386/predicates.md | 2 + gcc/config/i386/sse.md | 2 +- gcc/config/s390/s390-c.c | 2 + gcc/cp/constexpr.c | 6 +- gcc/cp/decl2.c | 1 + gcc/cp/semantics.c | 11 +++ gcc/cp/tree.c | 2 + gcc/dwarf2out.c | 5 +- gcc/fold-const.c | 14 ++- gcc/fortran/ChangeLog | 21 ++++ gcc/fortran/array.c | 3 + gcc/fortran/target-memory.c | 2 +- gcc/fortran/trans-intrinsic.c | 17 +++- gcc/ifcvt.c | 6 ++ gcc/loop-invariant.c | 19 +++- gcc/match.pd | 15 +-- gcc/optabs-tree.c | 21 +++- gcc/optabs.c | 16 ++- gcc/shrink-wrap.c | 5 +- gcc/testsuite/ChangeLog | 17 ++++ gcc/testsuite/c-c++-common/cpp/va-opt-9.c | 20 ++++ gcc/testsuite/c-c++-common/pr101537.c | 26 +++++ gcc/testsuite/c-c++-common/pr103881.c | 20 ++++ gcc/testsuite/g++.dg/cpp/pr103012.C | 18 ++++ gcc/testsuite/g++.dg/cpp2a/consteval26.C | 39 ++++++++ gcc/testsuite/g++.dg/cpp2a/consteval27.C | 18 ++++ gcc/testsuite/g++.dg/warn/Wuseless-cast2.C | 24 +++++ gcc/testsuite/g++.target/i386/pr103012.C | 19 ++++ gcc/testsuite/gcc.c-torture/compile/pr103813.c | 10 ++ gcc/testsuite/gcc.dg/debug/dwarf2/pr103874.c | 12 +++ gcc/testsuite/gcc.dg/pr102478.c | 29 ++++++ gcc/testsuite/gcc.dg/pr103587.c | 7 ++ gcc/testsuite/gcc.dg/pr103837.c | 19 ++++ gcc/testsuite/gcc.dg/pr103838.c | 28 ++++++ gcc/testsuite/gcc.dg/pr103860.c | 31 ++++++ gcc/testsuite/gcc.target/i386/pr103908.c | 24 +++++ gcc/testsuite/gcc.target/i386/pr104188.c | 70 +++++++++++++ gcc/testsuite/gfortran.dg/pr102520.f90 | 6 +- gcc/testsuite/gfortran.dg/pr102860.f90 | 10 ++ gcc/testsuite/gfortran.dg/pr103692.f90 | 23 +++++ gcc/testsuite/gfortran.dg/transfer_char_kind4.f90 | 115 ++++++++++++++++++++++ gcc/testsuite/objc.dg/pr103639.m | 101 +++++++++++++++++++ libcpp/macro.c | 5 + 62 files changed, 1071 insertions(+), 105 deletions(-) copy contrib/{git-backport.py => git-fix-changelog.py} (53%) create mode 100644 gcc/testsuite/c-c++-common/cpp/va-opt-9.c create mode 100644 gcc/testsuite/c-c++-common/pr101537.c create mode 100644 gcc/testsuite/c-c++-common/pr103881.c create mode 100644 gcc/testsuite/g++.dg/cpp/pr103012.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/consteval26.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/consteval27.C create mode 100644 gcc/testsuite/g++.dg/warn/Wuseless-cast2.C create mode 100644 gcc/testsuite/g++.target/i386/pr103012.C create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr103813.c create mode 100644 gcc/testsuite/gcc.dg/debug/dwarf2/pr103874.c create mode 100644 gcc/testsuite/gcc.dg/pr102478.c create mode 100644 gcc/testsuite/gcc.dg/pr103587.c create mode 100644 gcc/testsuite/gcc.dg/pr103837.c create mode 100644 gcc/testsuite/gcc.dg/pr103838.c create mode 100644 gcc/testsuite/gcc.dg/pr103860.c create mode 100644 gcc/testsuite/gcc.target/i386/pr103908.c create mode 100644 gcc/testsuite/gcc.target/i386/pr104188.c create mode 100644 gcc/testsuite/gfortran.dg/pr102860.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr103692.f90 create mode 100644 gcc/testsuite/gfortran.dg/transfer_char_kind4.f90 create mode 100644 gcc/testsuite/objc.dg/pr103639.m -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 7 months

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