Tcwg-commits January 2021

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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-defconfig updated (7827b7c6 -> ceb83ad0)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-defconfig in repository toolchain/ci/base-artifacts. discards 7827b7c6 0: update: llvm-linux-qemu: boot new ceb83ad0 0: update: llvm-linux-qemu: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (7827b7c6) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 129 +- 02-prepare_abe/console.log | 438 +- 03-build_llvm/console.log | 13686 +++++++++++------------ 04-build_linux/console.log | 787 +- 05-build_abe-qemu/console.log | 6826 ++++++------ 06-boot_linux/console.log | 488 +- 07-check_regression/console.log | 14 +- 08-update_baseline/console.log | 10 +- console.log | 22378 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 10 files changed, 22376 insertions(+), 22388 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allmodconfig updated (7b09f12773 -> b3f846c59d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allmodconfig in repository toolchain/ci/qemu. from 7b09f12773 Merge remote-tracking branch 'remotes/pmaydell/tags/pull-tar [...] adds b115ea3a0d gitlab-ci.yml: Add openSUSE Leap 15.2 for gitlab CI/CD adds 661465c2e0 qtest/libqtest: fix heap-buffer-overflow in qtest_cb_for_eve [...] adds 124bd3e0a8 util/oslib-win32: Fix _aligned_malloc() arguments order adds 22ec0c696f fuzz: accelerate non-crash detection adds 7b339f287f fuzz: double the IOs to remove for every loop adds e72203abec fuzz: split write operand using binary approach adds 247ab240c2 fuzz: remove IO commands iteratively adds 9d20f2af53 fuzz: set bits in operand of write/out to zero adds dd21ed0edf fuzz: add minimization options adds 4cc5752303 fuzz: heuristic split write based on past IOs adds 4d306e59cb bsd-user: regenerate FreeBSD's system call numbers adds ea1ab4cf2c bsd-user: move strace OS/arch dependent code to host/arch dirs adds f6eb4a0841 bsd-user: Update strace.list for FreeBSD's latest syscalls adds 333168efe5 tests/acceptance: Fix race conditions in s390x tests & skip [...] adds b677001d70 fuzz: map all BARs and enable PCI devices adds b3f846c59d Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull- [...] No new revisions were added by this update. Summary of changes: .gitlab-ci.d/containers.yml | 5 + .gitlab-ci.yml | 31 ++ bsd-user/arm/target_arch_sysarch.h | 78 +++ bsd-user/arm/target_syscall.h | 36 ++ bsd-user/{signal.c => freebsd/os-strace.h} | 17 +- bsd-user/freebsd/strace.list | 65 ++- bsd-user/freebsd/syscall_nr.h | 695 ++++++++++++++------------ bsd-user/i386/target_arch_sysarch.h | 77 +++ bsd-user/i386/target_syscall.h | 19 + bsd-user/mips/target_arch_sysarch.h | 69 +++ bsd-user/mips/target_syscall.h | 52 ++ bsd-user/mips64/target_arch_sysarch.h | 69 +++ bsd-user/mips64/target_syscall.h | 53 ++ bsd-user/netbsd/os-strace.h | 1 + bsd-user/openbsd/os-strace.h | 1 + bsd-user/sparc/target_arch_sysarch.h | 52 ++ bsd-user/sparc/target_syscall.h | 24 +- bsd-user/sparc64/target_arch_sysarch.h | 52 ++ bsd-user/sparc64/target_syscall.h | 24 +- bsd-user/strace.c | 11 + bsd-user/x86_64/target_arch_sysarch.h | 76 +++ bsd-user/x86_64/target_syscall.h | 21 +- meson.build | 1 + scripts/oss-fuzz/minimize_qtest_trace.py | 260 ++++++++-- tests/acceptance/machine_s390_ccw_virtio.py | 14 +- tests/docker/dockerfiles/opensuse-leap.docker | 55 ++ tests/qtest/fuzz/generic_fuzz.c | 24 + tests/qtest/libqtest.c | 2 +- util/oslib-win32.c | 2 +- 29 files changed, 1500 insertions(+), 386 deletions(-) create mode 100644 bsd-user/arm/target_arch_sysarch.h create mode 100644 bsd-user/arm/target_syscall.h copy bsd-user/{signal.c => freebsd/os-strace.h} (60%) create mode 100644 bsd-user/i386/target_arch_sysarch.h create mode 100644 bsd-user/mips/target_arch_sysarch.h create mode 100644 bsd-user/mips/target_syscall.h create mode 100644 bsd-user/mips64/target_arch_sysarch.h create mode 100644 bsd-user/mips64/target_syscall.h create mode 100644 bsd-user/netbsd/os-strace.h create mode 100644 bsd-user/openbsd/os-strace.h create mode 100644 bsd-user/sparc/target_arch_sysarch.h create mode 100644 bsd-user/sparc64/target_arch_sysarch.h create mode 100644 bsd-user/x86_64/target_arch_sysarch.h create mode 100644 tests/docker/dockerfiles/opensuse-leap.docker -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allmodconfig updated (c161775decd -> 93b54b7c673)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allmodconfig in repository toolchain/ci/llvm-project. from c161775decd [FastISel] Flush local value map on every instruction adds 4214ca96145 [X86][AVX] Attempt to fold vpermf128(op(x,i),op(y,i)) -> op [...] adds 9c0dc0b2c1c [mlir][Linalg] Fold init_tensor -> linalg.tensor_reshape. adds c15b0e2229e [Clang][Docs] Fix ambiguity in clang-offload-bundler docs adds 7200d2cf089 [NFC] Disallow unused prefixes in CodeGen/PowerPC tests. adds 3d693bd0bd7 [mlir][vector] Add memory effects to transfer_read transfer [...] adds c4486cfd556 [mlir][Linalg] Fix reshape fusion to reshape the outs inste [...] adds be179b9946f [FastISel] NFC: Remove obsolete -fast-isel-sink-local-value [...] adds ac2224c0228 [ELF] --exclude-libs: localize defined libcall symbols refe [...] adds 171771e0780 [SystemZ] Minor NFC fix in SchedModels. adds 1f9c29228ce [FastISel] NFC: Clean up unnecessary bookkeeping adds 072714b9619 [X86] Regenerate vector-constrained-fp-intrinsics.ll tests adds 35c9baa11e4 [attributes] Add a facility for enforcing a Trusted Comput [...] adds a90214760d0 [Hexagon] Custom-widen SETCC's operands adds bcec0f27a2c [AMDGPU] Deduplicate VOP tablegen asm & ins adds 74628c43053 [mlir] Add Python bindings for AffineExpr adds e79bd0b4f25 [mlir] More Python bindings for AffineMap adds 547e3eef14a [mlir] Expose MemRef layout in Python bindings adds 47567ca5fac [flang][openxx][NFC] Remove duplicated function to check re [...] adds d8c6d24359f -funique-internal-linkage-names appends a hex md5hash suffi [...] adds 43a830ed941 Introduce new quiet mode and new option handling for -print [...] adds 5464baaae8c Fix minor build issue (NFC) adds 1027a22ccd7 [SystemZ][z/OS] Fix Permission denied pattern matching adds 195728c75aa [mlir] Add structural conversion to async dialect lowering. adds 37b41bd0879 [RISCV] Add scalable vector fcmp ISel patterns adds 30a7d430e86 [libc++] Turn off auto-formatting of generated files. NFC. adds 72f1f084670 [NFC][AMDGPU] Clarify memory model support for volatile adds 20741773013 [mlir][ODS] Add a C++ abstraction for OpBuilders adds 948be58258d [mlir][TypeDefGen] Add support for adding builders when gen [...] adds d79642b3db1 [mlir][IR][NFC] Move the definitions of Complex/Function/In [...] adds d3ff24cbf87 [ADT] Add makeIntrusiveRefCnt helper function adds 8ad998a6115 [tools] Mark output of tools as text if it is really text adds 05e90cefeb4 [NFC] Disallow unused prefixes under llvm/test/CodeGen adds c1ae378205d [mlir][vector] Add side-effect information to different loa [...] adds 53c866c286a Enable python bindings for tensor, shape and linalg dialects. adds cceb1bfcbbc [mlir][CAPI] Introduce standard source layout for mlir-c di [...] adds 110775809ad Revert "[mlir][linalg] Support parsing attributes in named [...] adds 288f3fc5dfe [InstCombine] reduce icmp(ashr X, C1), C2 to sign-bit test adds 32c073acb32 [GlobalISel] Map extractelt to G_EXTRACT_VECTOR_ELT adds aefeb5f136e [libc][NFC] Make __support/common.h an in tree header. adds 9b222b108a2 [c++20] Don't consider string literal operator templates fo [...] adds f4cec703ec8 Add an assert to CGDebugInfo::getTypeOrNull adds 7989684a2e4 [RISCV] Add scalable vector fadd/fsub/fmul/fdiv ISel patterns adds 046612d29d7 [mlir][vector] verify memref of vector memory ops adds a808d89d355 [PredicateInfo] Add test for one unknown condition in and/or (NFC) adds 00f773cf424 [SCCP] Fix misclassified conditions in test (NFC) adds b88c8f1aab5 CGDebugInfo: Delete unused parameters adds 32bcfcda4e2 Rename debug linkage name with -funique-internal-linkage-names adds a81c68ae6be [OpenMP] Take elf_common.c as a interface library adds 9ecc991c559 [RISCV] Add scalable vector vselect ISel patterns adds 0a23fbd28c7 clang: Always pass PowerPC endian information to GNU as adds 762ffc95550 Update syntax for tensor and memref types to match parser. adds 278a3ea1b27 [RISCV] Use vmv.v.i vd, 0 instead of vmv.v.x vd, x0 for llv [...] adds c22bc5f1f8b [SimplifyCFG] SwitchToLookupTable(): don't insert a DomTree [...] adds c0de0a1b72c [SimplifyCFG] SimplifyBranchOnICmpChain(): don't insert a D [...] adds f9ba3477063 [SimplifyCFG] FoldValueComparisonIntoPredecessors(): don't [...] adds 90a92f8b4d7 [NFCI][Utils/Local] removeUnreachableBlocks(): cleanup supp [...] adds 81afeacd379 [SimplifyCFGPass] mergeEmptyReturnBlocks(): skip blocks sch [...] adds ec8a6c11db4 [SimplifyCFGPass] iterativelySimplifyCFG(): support lazy Do [...] adds 5ccff5aaa68 ADT: Fix pointer comparison UB in SmallVector adds 7470017f247 [RISCV] Define the vfclass RVV intrinsics adds f635bcd1610 NFC: Pre-commit test: -Wpointer-sign with plain char to [un [...] adds c6ffe4d76fb [clang] Fix message text for `-Wpointer-sign` to account fo [...] adds eefd420e003 [github] Move repo lockdown config into llvm-project repo adds f75f391fc68 [MLIR][Linalg] Refactor transforms to use linalg::getDynOpe [...] adds f9902514fe5 [MC] Make getEHFrameSection const like every other getter (NFC) adds ef50c07b1fa [JITLink] Add a new PostAllocationPasses list. adds 70474dfebcd [VE][compiler-rt] Add VE as a target of crt adds 9f8b25769ef [WebAssembly] Ensure terminate pads are a single BB adds 905623b64df [NFC][LICM] Minor improvements to debug output adds 0871d6d5164 [OpenMP] Move memory manager to plugin and make it a common [...] adds 89e8eb946d8 [llvm] Use llvm::find_if (NFC) adds 8590a3e3adc [llvm] Use *Set::contains (NFC) adds e5b4dbab041 [llvm] Simplify string comparisons (NFC) adds b1c304c4946 [CodeGen] Try to make the print of memory operand alignment [...] adds edde2eb1d20 Add unconditional logging to debugserver for launch/attach [...] adds f9ef3a60037 [SelectionDAG] Make isConstantIntBuildVectorOrConstantInt a [...] adds b688c5875d0 [CMake] Split the target side of runtimes build adds df74c001fa5 [DAGCombiner] Replace static helper function isConstantFPBu [...] adds 93ad0edf674 [ELF] Drop .rel[a].debug_gnu_pub{names,types} for --gdb-ind [...] adds 1cc5235712f [WebAssembly] Misc. refactoring in CFGStackify (NFC) adds 215ed9b33cc Adapt CastExpr::getSubExprAsWritten to ConstantExpr adds c8a914db5c6 [LiveDebugValues] Fix comparison operator in VarLocBasedImpl adds 6a195491b60 [AMDGPU] Fix failing assert with scratch ST mode adds 7ab803095ae [clang][cli] Remove -f[no-]trapping-math from -cc1 command line adds bd30a796fc4 [mlir] use built-in vector types instead of LLVM dialect ty [...] adds e8287cb2b29 [Test] Add failing test for PR48725 adds c93b9559390 [WebAssembly] Remove more unnecessary brs in CFGStackify adds 9ec72cfc61a [llvm-readef/obj] - Change the design structure of ELF dump [...] adds 1e11402aa8e [llvm-readobj] - Add 'override' to fix build bots. adds cc91efdabee [llvm-readobj] - An attempt to fix BB. adds 4744478b99f [mlir][openmp][NFCI] Rename `continuationIP` to `continuati [...] adds 891b4873c12 [llvm-readobj] - One more attempt to fix BB. adds c1e08f0073e [clang][AST] Get rid of an alignment hack in DeclObjC.h [NFCI] adds f264f9ad7df [SlotIndexes] Fix and simplify basic block splitting adds 794e3d94d5a [AMDGPU][GlobalISel] Remove some duplicate RUN lines adds 60df7c08b1f [obj2yaml,yaml2obj] - Fix issues with creating/dumping grou [...] adds c15a57cc1a8 [obj2yaml] - Don't crash when an object has an empty symbol table. adds a06aa1037c1 Revert "[Test] Add failing test for PR48725" adds ace516fb33d Change the LLVM_ATTRIBUTE_DEPRECATED macro to use C++14 attribute. adds 09db958e37b [RISCV] Improve scalable-vector shift tests (NFC) adds a5212b5c91c [X86][SSE] combineSubToSubus - remove SSE2 early-out. adds c4944a6f53f [Fixed Point] Add codegen for conversion between fixed-poin [...] adds 7e44208115b [X86][SSE] combineSubToSubus - add v16i32 handling on pre-A [...] adds 2ed914cb7e9 [X86][SSE] getFauxShuffleMask - handle PACKSS(SRAI(),SRAI() [...] adds 80f07854886 [mlir][Linalg] NFC - Refactor fusion APIs adds a6759477129 [TableGen] Improve error message for semicolon after braced body. adds 0bd9a136911 [mlir][openacc] Use TableGen information for default enum adds 07605ea1f3c [X86] Improved lowering for saturating float to int. adds 24faa87075a [VE] Update VELIntrinsic tests adds 2f7ec77e3cd [mlir][spirv] NFC: place ops in the proper file for their c [...] adds dd07d60ec33 [SLP] Add test case showing a bug when dealing with padded types adds 3f7b4ce9606 [PowerPC] Add support for embedded devices with EFPU2 adds 4086072f8a9 Reland "[mlir][linalg] Support parsing attributes in named [...] adds 4fa01f72de6 [mlir][CAPI] Fix inline function declaration adds 9667d15e749 [mlir] Fix for LIT tests adds 1f1250151f2 [libc++] [C++2b] [P1048] Add is_scoped_enum and is_scoped_enum_v. adds 8349fa0fdd3 [mlir][spirv] NFC: split deserialization into multiple sour [...] adds 93b54b7c673 [PowerPC][NFCI] PassSubtarget to ASMWriter No new revisions were added by this update. Summary of changes: .github/lockdown.yml | 8 + clang/docs/ClangCommandLineReference.rst | 2 + clang/docs/ClangOffloadBundler.rst | 4 +- clang/include/clang/AST/DeclObjC.h | 30 +- clang/include/clang/Basic/Attr.td | 16 + clang/include/clang/Basic/AttrDocs.td | 25 + clang/include/clang/Basic/DiagnosticSemaKinds.td | 25 +- clang/include/clang/Driver/Options.td | 5 +- clang/include/clang/Sema/Sema.h | 5 + clang/lib/AST/DeclObjC.cpp | 4 +- clang/lib/AST/Expr.cpp | 2 +- clang/lib/Basic/Targets/PPC.cpp | 6 +- clang/lib/CodeGen/CGDebugInfo.cpp | 12 +- clang/lib/CodeGen/CGDebugInfo.h | 8 +- clang/lib/CodeGen/CGExprScalar.cpp | 37 +- clang/lib/CodeGen/CodeGenFunction.cpp | 3 +- clang/lib/Driver/ToolChains/Clang.cpp | 4 +- clang/lib/Driver/ToolChains/Gnu.cpp | 2 + clang/lib/Frontend/CompilerInvocation.cpp | 8 - clang/lib/Sema/SemaChecking.cpp | 38 + clang/lib/Sema/SemaDecl.cpp | 4 + clang/lib/Sema/SemaDeclAttr.cpp | 77 + clang/lib/Sema/SemaExpr.cpp | 10 + clang/lib/Sema/SemaLookup.cpp | 7 + clang/test/CodeGen/fpconstrained.c | 4 +- clang/test/CodeGen/fpconstrained.cpp | 4 +- clang/test/CodeGen/noexceptionsfpmath.c | 2 +- .../test/CodeGen/unique-internal-linkage-names.cpp | 20 +- clang/test/CodeGenCUDA/propagate-metadata.cu | 12 +- clang/test/Driver/fast-math.c | 4 - clang/test/Driver/fp-model.c | 8 - clang/test/Driver/ppc-features.cpp | 30 +- clang/test/Frontend/fixed_point_compound.c | 110 + clang/test/Frontend/fixed_point_conversions.c | 299 ++ clang/test/Frontend/fixed_point_conversions_half.c | 309 ++ ...pragma-attribute-supported-attributes-list.test | 2 + clang/test/Parser/fp-floatcontrol-syntax.cpp | 4 +- clang/test/Sema/attr-enforce-tcb-errors.cpp | 80 + clang/test/Sema/attr-enforce-tcb.c | 65 + clang/test/Sema/attr-enforce-tcb.cpp | 70 + clang/test/Sema/incompatible-sign.c | 18 + clang/test/Sema/incompatible-sign.cpp | 14 + clang/test/SemaCXX/cxx2a-user-defined-literals.cpp | 29 + clang/test/SemaObjC/objc-cf-audited-warning.m | 2 +- clang/unittests/Tooling/CastExprTest.cpp | 20 + compiler-rt/cmake/config-ix.cmake | 3 +- flang/lib/Semantics/check-directive-structure.h | 15 +- flang/lib/Semantics/check-omp-structure.cpp | 3 +- flang/test/Semantics/omp-device-constructs.f90 | 2 +- libc/src/__support/CMakeLists.txt | 10 +- libc/src/__support/{common.h.def => common.h} | 18 +- libcxx/docs/Cxx2bStatusPaperStatus.csv | 2 +- libcxx/docs/FeatureTestMacroTable.rst | 2 +- libcxx/include/type_traits | 22 + libcxx/include/version | 2 +- .../algorithm.version.pass.cpp | 2 + .../support.limits.general/any.version.pass.cpp | 2 + .../support.limits.general/array.version.pass.cpp | 2 + .../support.limits.general/atomic.version.pass.cpp | 2 + .../barrier.version.pass.cpp | 2 + .../support.limits.general/bit.version.pass.cpp | 2 + .../support.limits.general/chrono.version.pass.cpp | 2 + .../support.limits.general/cmath.version.pass.cpp | 2 + .../compare.version.pass.cpp | 2 + .../complex.version.pass.cpp | 2 + .../concepts.version.pass.cpp | 2 + .../cstddef.version.pass.cpp | 2 + .../support.limits.general/deque.version.pass.cpp | 2 + .../exception.version.pass.cpp | 2 + .../execution.version.pass.cpp | 2 + .../filesystem.version.pass.cpp | 2 + .../forward_list.version.pass.cpp | 2 + .../functional.version.pass.cpp | 2 + .../iomanip.version.pass.cpp | 2 + .../istream.version.pass.cpp | 2 + .../iterator.version.pass.cpp | 2 + .../support.limits.general/latch.version.pass.cpp | 2 + .../support.limits.general/limits.version.pass.cpp | 2 + .../support.limits.general/list.version.pass.cpp | 2 + .../support.limits.general/locale.version.pass.cpp | 2 + .../support.limits.general/map.version.pass.cpp | 2 + .../support.limits.general/memory.version.pass.cpp | 2 + .../support.limits.general/mutex.version.pass.cpp | 2 + .../support.limits.general/new.version.pass.cpp | 2 + .../numbers.version.pass.cpp | 2 + .../numeric.version.pass.cpp | 2 + .../optional.version.pass.cpp | 2 + .../ostream.version.pass.cpp | 2 + .../support.limits.general/regex.version.pass.cpp | 2 + .../scoped_allocator.version.pass.cpp | 2 + .../semaphore.version.pass.cpp | 2 + .../support.limits.general/set.version.pass.cpp | 2 + .../shared_mutex.version.pass.cpp | 2 + .../support.limits.general/span.version.pass.cpp | 2 + .../support.limits.general/string.version.pass.cpp | 2 + .../string_view.version.pass.cpp | 2 + .../support.limits.general/thread.version.pass.cpp | 2 + .../support.limits.general/tuple.version.pass.cpp | 2 + .../type_traits.version.pass.cpp | 18 +- .../unordered_map.version.pass.cpp | 2 + .../unordered_set.version.pass.cpp | 2 + .../utility.version.pass.cpp | 2 + .../variant.version.pass.cpp | 2 + .../support.limits.general/vector.version.pass.cpp | 2 + .../version.version.pass.cpp | 18 +- .../meta.unary.prop/is_scoped_enum.pass.cpp | 120 + .../generate_feature_test_macro_components.py | 3 +- lld/ELF/Driver.cpp | 11 +- lld/ELF/SyntheticSections.cpp | 7 + lld/test/ELF/debug-gnu-pubnames.s | 18 - lld/test/ELF/gdb-index.s | 15 +- lld/test/ELF/lto/exclude-libs-libcall.ll | 28 + .../tools/debugserver/source/MacOSX/MachProcess.mm | 139 +- lldb/tools/debugserver/source/MacOSX/MachTask.mm | 11 +- lldb/tools/debugserver/source/RNBRemote.cpp | 19 +- lldb/tools/debugserver/source/debugserver.cpp | 46 +- llvm/docs/AMDGPUUsage.rst | 48 +- llvm/include/llvm/ADT/IntrusiveRefCntPtr.h | 6 + llvm/include/llvm/ADT/SmallVector.h | 41 +- llvm/include/llvm/Analysis/LoopCacheAnalysis.h | 6 +- llvm/include/llvm/CodeGen/FastISel.h | 4 - llvm/include/llvm/CodeGen/LiveIntervals.h | 5 +- llvm/include/llvm/CodeGen/SelectionDAG.h | 6 +- llvm/include/llvm/CodeGen/SlotIndexes.h | 45 +- llvm/include/llvm/CodeGen/TargetInstrInfo.h | 7 +- .../include/llvm/ExecutionEngine/JITLink/JITLink.h | 20 +- llvm/include/llvm/Frontend/OpenACC/ACC.td | 4 +- llvm/include/llvm/IR/DebugInfoMetadata.h | 4 + llvm/include/llvm/IR/FixedPointBuilder.h | 59 + llvm/include/llvm/IR/IntrinsicsRISCV.td | 30 +- llvm/include/llvm/IR/Value.h | 4 + llvm/include/llvm/MC/MCObjectFileInfo.h | 4 +- .../include/llvm/Passes/StandardInstrumentations.h | 14 +- llvm/include/llvm/Support/Compiler.h | 16 +- .../llvm/Target/GlobalISel/SelectionDAGCompat.td | 2 +- llvm/lib/CodeGen/InlineSpiller.cpp | 10 +- .../CodeGen/LiveDebugValues/VarLocBasedImpl.cpp | 5 +- llvm/lib/CodeGen/MIRParser/MILexer.cpp | 1 + llvm/lib/CodeGen/MIRParser/MILexer.h | 1 + llvm/lib/CodeGen/MIRParser/MIParser.cpp | 8 +- llvm/lib/CodeGen/MachineBasicBlock.cpp | 2 +- llvm/lib/CodeGen/MachineOperand.cpp | 6 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 84 +- llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 36 - llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 6 +- .../lib/ExecutionEngine/JITLink/JITLinkGeneric.cpp | 12 +- llvm/lib/ExecutionEngine/Orc/Core.cpp | 25 +- llvm/lib/IR/LegacyPassManager.cpp | 3 +- llvm/lib/IR/Value.cpp | 12 + llvm/lib/MC/MCSectionMachO.cpp | 20 +- llvm/lib/ObjectYAML/ELFEmitter.cpp | 5 +- llvm/lib/Option/OptTable.cpp | 2 +- llvm/lib/Passes/StandardInstrumentations.cpp | 52 +- llvm/lib/TableGen/TGParser.cpp | 19 +- llvm/lib/Target/AArch64/AArch64InstrGISel.td | 2 + .../Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp | 2 +- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 14 +- llvm/lib/Target/AMDGPU/SIInstrInfo.td | 195 +- llvm/lib/Target/AMDGPU/VOP3Instructions.td | 1 + llvm/lib/Target/Hexagon/HexagonISelLowering.h | 1 + llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp | 87 +- .../Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp | 94 +- .../Target/PowerPC/MCTargetDesc/PPCInstPrinter.h | 85 +- llvm/lib/Target/PowerPC/PPC.td | 11 + llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 2 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 4 +- llvm/lib/Target/PowerPC/PPCSubtarget.cpp | 1 + llvm/lib/Target/PowerPC/PPCSubtarget.h | 2 + llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 42 + llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 16 +- llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td | 161 + llvm/lib/Target/SystemZ/SystemZScheduleZ13.td | 2 +- llvm/lib/Target/SystemZ/SystemZScheduleZ14.td | 2 +- llvm/lib/Target/SystemZ/SystemZScheduleZ15.td | 2 +- llvm/lib/Target/SystemZ/SystemZScheduleZ196.td | 2 +- llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td | 2 +- .../Target/WebAssembly/WebAssemblyCFGStackify.cpp | 102 +- .../WebAssembly/WebAssemblyLateEHPrepare.cpp | 77 + .../Target/WebAssembly/WebAssemblyUtilities.cpp | 14 + llvm/lib/Target/WebAssembly/WebAssemblyUtilities.h | 5 + llvm/lib/Target/X86/X86ISelLowering.cpp | 243 +- llvm/lib/Target/X86/X86ISelLowering.h | 1 + .../Transforms/InstCombine/InstCombineCompares.cpp | 15 + llvm/lib/Transforms/Scalar/LICM.cpp | 16 +- llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp | 17 +- llvm/lib/Transforms/Utils/Local.cpp | 44 +- llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 5 +- .../Utils/UniqueInternalLinkageNames.cpp | 20 +- llvm/runtimes/CMakeLists.txt | 939 ++-- .../CodeGen/AArch64/GlobalISel/inline-memcpy.mir | 4 +- .../GlobalISel/legalize-non-pow2-load-store.mir | 4 +- llvm/test/CodeGen/AArch64/arm64-abi_align.ll | 4 +- llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll | 6 +- llvm/test/CodeGen/AArch64/arm64-fast-isel-gv.ll | 2 +- .../CodeGen/AArch64/arm64-fast-isel-intrinsic.ll | 2 +- llvm/test/CodeGen/AArch64/arm64-fast-isel.ll | 2 +- .../AArch64/arm64-patchpoint-webkit_jscc.ll | 6 +- llvm/test/CodeGen/AArch64/swifterror.ll | 8 +- .../GlobalISel/legalize-extract-vector-elt.mir | 252 +- .../GlobalISel/legalize-insert-vector-elt.mir | 126 +- .../AMDGPU/GlobalISel/legalize-load-constant.mir | 5111 -------------------- .../AMDGPU/GlobalISel/legalize-load-flat.mir | 4359 ----------------- .../regbankselect-amdgcn.s.buffer.load.ll | 48 +- .../AMDGPU/GlobalISel/regbankselect-load.mir | 36 +- llvm/test/CodeGen/AMDGPU/lit.local.cfg | 10 - llvm/test/CodeGen/AMDGPU/memory_clause.ll | 278 ++ llvm/test/CodeGen/ARM/fast-isel-call.ll | 18 +- llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll | 12 +- llvm/test/CodeGen/ARM/fast-isel-select.ll | 8 +- llvm/test/CodeGen/ARM/fast-isel-vararg.ll | 6 +- llvm/test/CodeGen/ARM/speculation-hardening-sls.ll | 12 +- llvm/test/CodeGen/ARM/swifterror.ll | 6 +- llvm/test/CodeGen/Hexagon/autohvx/widen-setcc.ll | 21 + .../MIR/X86/expected-align-in-memory-operand.mir | 4 +- ...ted-alignment-after-align-in-memory-operand.mir | 4 +- .../expected-positive-alignment-after-align.mir | 4 +- llvm/test/CodeGen/MIR/X86/memory-operands.mir | 36 +- llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll | 4 +- llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll | 4 +- llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll | 4 +- .../store_split_because_of_memsize_or_align.mir | 28 +- .../CodeGen/Mips/GlobalISel/regbankselect/load.mir | 2 +- .../regbankselect/long_ambiguous_chain_s32.mir | 18 +- .../regbankselect/long_ambiguous_chain_s64.mir | 18 +- .../Mips/GlobalISel/regbankselect/store.mir | 2 +- llvm/test/CodeGen/NVPTX/f16-instructions.ll | 4 +- llvm/test/CodeGen/PowerPC/aix-cc-abi.ll | 52 +- llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll | 4 +- llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll | 4 +- llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll | 4 +- llvm/test/CodeGen/PowerPC/lower-massv.ll | 2 +- llvm/test/CodeGen/PowerPC/popcnt-zext.ll | 4 +- llvm/test/CodeGen/PowerPC/ppc32-pic.ll | 6 +- llvm/test/CodeGen/PowerPC/spe.ll | 2032 +++++--- llvm/test/CodeGen/PowerPC/srem-lkk.ll | 4 +- llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll | 8 +- llvm/test/CodeGen/PowerPC/testComparesigeuc.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesigeui.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesigeull.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesigeus.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesileuc.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesileui.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesileull.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesileus.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesiltsc.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesiltsi.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesiltsll.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesiltss.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesiltuc.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesiltui.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesiltus.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllgeui.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllgeull.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllgeus.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllleuc.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllleui.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllleull.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllleus.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllltsll.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllltuc.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllltus.ll | 6 +- llvm/test/CodeGen/PowerPC/urem-lkk.ll | 4 +- llvm/test/CodeGen/PowerPC/vec_splat.ll | 4 +- .../CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll | 10 +- llvm/test/CodeGen/PowerPC/vmladduhm.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll | 2748 +++++++++++ llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll | 2748 +++++++++++ llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv32.ll | 380 ++ llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv64.ll | 380 ++ llvm/test/CodeGen/RISCV/rvv/vfclass-rv32.ll | 512 ++ llvm/test/CodeGen/RISCV/rvv/vfclass-rv64.ll | 698 +++ llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv32.ll | 380 ++ llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv64.ll | 380 ++ llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv32.ll | 380 ++ llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv64.ll | 380 ++ llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll | 86 +- llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll | 86 +- llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv32.ll | 380 ++ llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv64.ll | 380 ++ llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll | 379 ++ llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll | 379 ++ llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll | 783 +++ llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll | 755 +++ llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll | 286 +- llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll | 286 +- llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll | 109 + llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll | 286 +- llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv64.ll | 286 +- llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll | 286 +- llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll | 286 +- llvm/test/CodeGen/VE/VELIntrinsics/vand.ll | 4 +- llvm/test/CodeGen/VE/VELIntrinsics/vld.ll | 130 +- llvm/test/CodeGen/WebAssembly/cfg-stackify-eh.ll | 95 +- llvm/test/CodeGen/WebAssembly/exception.ll | 68 + llvm/test/CodeGen/X86/avoid-sfb-offset.mir | 6 +- llvm/test/CodeGen/X86/avx512-mask-zext-bugfix.ll | 2 +- llvm/test/CodeGen/X86/bmi-intrinsics-fast-isel.ll | 4 +- llvm/test/CodeGen/X86/bug47278.mir | 8 +- llvm/test/CodeGen/X86/fast-isel-call-cleanup.ll | 2 +- llvm/test/CodeGen/X86/fptosi-sat-scalar.ll | 495 +- llvm/test/CodeGen/X86/fptoui-sat-scalar.ll | 441 +- llvm/test/CodeGen/X86/inreg.ll | 4 +- llvm/test/CodeGen/X86/lit.local.cfg | 8 - llvm/test/CodeGen/X86/pr32241.ll | 2 +- llvm/test/CodeGen/X86/pr32284.ll | 8 +- llvm/test/CodeGen/X86/pr32340.ll | 2 +- llvm/test/CodeGen/X86/pr32345.ll | 8 +- llvm/test/CodeGen/X86/pr32484.ll | 2 +- llvm/test/CodeGen/X86/psubus.ll | 510 +- llvm/test/CodeGen/X86/sink-local-value.ll | 2 +- llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll | 16 +- .../X86/vector-constrained-fp-intrinsics.ll | 766 +-- llvm/test/CodeGen/X86/vector-trunc.ll | 8 +- llvm/test/CodeGen/{X86 => }/lit.local.cfg | 3 - llvm/test/DebugInfo/Mips/delay-slot.ll | 2 +- llvm/test/DebugInfo/X86/prologue-stack.ll | 2 +- llvm/test/Other/change-printer.ll | 151 + llvm/test/TableGen/spurious-semi.td | 39 + llvm/test/Transforms/InstCombine/icmp-shr.ll | 78 +- llvm/test/Transforms/SCCP/conditions-ranges.ll | 48 +- .../test/Transforms/SLPVectorizer/X86/bad_types.ll | 34 +- .../unique-internal-linkage-names.ll | 50 + .../unique_symbol_names.ll | 4 +- .../unique-internal-linkage-names.ll | 24 - .../Transforms/Util/PredicateInfo/testandor.ll | 74 + llvm/test/tools/llvm-elfabi/fail-file-write.test | 2 +- llvm/test/tools/llvm-profdata/csprof-dump.test | 2 +- llvm/test/tools/llvm-profdata/instr-remap.test | 2 +- llvm/test/tools/obj2yaml/ELF/no-symtab.yaml | 34 + llvm/test/tools/obj2yaml/ELF/section-group.yaml | 29 +- llvm/test/tools/yaml2obj/ELF/group.yaml | 14 +- llvm/tools/llvm-cfi-verify/lib/FileAnalysis.cpp | 6 +- llvm/tools/llvm-exegesis/lib/Analysis.cpp | 9 +- .../llvm-exegesis/lib/SchedClassResolution.cpp | 10 +- llvm/tools/llvm-link/llvm-link.cpp | 3 +- llvm/tools/llvm-mca/llvm-mca.cpp | 2 +- llvm/tools/llvm-objcopy/COFF/Object.cpp | 4 +- llvm/tools/llvm-objcopy/MachO/MachOObjcopy.cpp | 8 +- llvm/tools/llvm-profdata/llvm-profdata.cpp | 6 +- llvm/tools/llvm-readobj/ELFDumper.cpp | 1042 ++-- llvm/tools/obj2yaml/dwarf2yaml.cpp | 4 +- llvm/tools/obj2yaml/elf2yaml.cpp | 51 +- llvm/unittests/ADT/IntrusiveRefCntPtrTest.cpp | 16 + llvm/unittests/MI/LiveIntervalTest.cpp | 41 + llvm/utils/TableGen/GlobalISelEmitter.cpp | 6 +- mlir/cmake/modules/AddMLIRPythonExtension.cmake | 26 +- mlir/docs/ConversionToLLVMDialect.md | 4 +- mlir/docs/Dialects/LLVM.md | 4 +- mlir/docs/LangRef.md | 12 +- mlir/docs/OpDefinitions.md | 165 + mlir/docs/SPIRVToLLVMDialectConversion.md | 18 +- mlir/include/mlir-c/AffineExpr.h | 23 +- mlir/include/mlir-c/AffineMap.h | 16 +- mlir/include/mlir-c/Bindings/Python/Interop.h | 21 + mlir/include/mlir-c/BuiltinTypes.h | 8 +- mlir/include/mlir-c/Dialect/Linalg.h | 25 + mlir/include/mlir-c/Dialect/SCF.h | 25 + mlir/include/mlir-c/Dialect/Shape.h | 25 + .../{StandardDialect.h => Dialect/Standard.h} | 22 +- mlir/include/mlir-c/Dialect/Tensor.h | 25 + mlir/include/mlir-c/Registration.h | 55 +- mlir/include/mlir/CAPI/Registration.h | 40 + .../mlir/Conversion/AsyncToLLVM/AsyncToLLVM.h | 16 + mlir/include/mlir/Dialect/ArmSVE/ArmSVE.td | 2 +- mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td | 8 +- mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td | 10 +- mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h | 49 +- mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td | 8 + .../Linalg/IR/LinalgStructuredOpsInterface.td | 12 + .../mlir/Dialect/Linalg/Transforms/Transforms.h | 14 +- mlir/include/mlir/Dialect/Linalg/Utils/Utils.h | 31 +- mlir/include/mlir/Dialect/OpenACC/CMakeLists.txt | 6 +- mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td | 14 +- .../mlir/Dialect/SPIRV/IR/SPIRVBarrierOps.td | 141 + .../SPIRV/IR/{SPIRVOps.td => SPIRVMemoryOps.td} | 248 +- mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td | 61 + mlir/include/mlir/Dialect/SPIRV/IR/SPIRVOps.td | 494 +- .../mlir/Dialect/SPIRV/IR/SPIRVStructureOps.td | 50 + .../include/mlir/Dialect/StandardOps/Utils/Utils.h | 32 + mlir/include/mlir/Dialect/Vector/VectorOps.td | 18 +- mlir/include/mlir/IR/BuiltinTypes.h | 219 +- mlir/include/mlir/IR/BuiltinTypes.td | 240 + mlir/include/mlir/IR/OpBase.td | 82 + mlir/include/mlir/TableGen/Builder.h | 85 + mlir/include/mlir/TableGen/Operator.h | 7 + mlir/include/mlir/TableGen/TypeDef.h | 43 +- .../LLVMIR/CPU/test-vector-reductions-fp.mlir | 32 +- .../LLVMIR/CPU/test-vector-reductions-int.mlir | 30 +- mlir/lib/Bindings/Python/CMakeLists.txt | 20 +- mlir/lib/Bindings/Python/IRModules.cpp | 579 ++- mlir/lib/Bindings/Python/IRModules.h | 29 + mlir/lib/Bindings/Python/LinalgOps.td | 16 + mlir/lib/Bindings/Python/ShapeOps.td | 15 + mlir/lib/Bindings/Python/TensorOps.td | 15 + mlir/lib/CAPI/CMakeLists.txt | 2 +- mlir/lib/CAPI/Dialect/CMakeLists.txt | 48 + mlir/lib/CAPI/Dialect/Linalg.cpp | 14 + mlir/lib/CAPI/Dialect/SCF.cpp | 13 + mlir/lib/CAPI/Dialect/Shape.cpp | 13 + mlir/lib/CAPI/Dialect/Standard.cpp | 13 + mlir/lib/CAPI/Dialect/Tensor.cpp | 14 + mlir/lib/CAPI/IR/AffineExpr.cpp | 20 + mlir/lib/CAPI/IR/AffineMap.cpp | 17 +- mlir/lib/CAPI/IR/BuiltinTypes.cpp | 11 + mlir/lib/CAPI/Standard/CMakeLists.txt | 7 - mlir/lib/CAPI/Standard/StandardDialect.cpp | 25 - mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp | 65 + mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp | 4 +- .../Conversion/StandardToLLVM/StandardToLLVM.cpp | 19 +- .../VectorToLLVM/ConvertVectorToLLVM.cpp | 7 +- .../lib/Conversion/VectorToROCDL/VectorToROCDL.cpp | 16 +- mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp | 54 +- mlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp | 14 +- mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp | 143 +- mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp | 2 +- mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp | 4 +- mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp | 126 +- mlir/lib/Dialect/Linalg/Transforms/Bufferize.cpp | 13 +- .../Linalg/Transforms/ElementwiseToLinalg.cpp | 17 +- mlir/lib/Dialect/Linalg/Transforms/Fusion.cpp | 135 +- .../Dialect/Linalg/Transforms/FusionOnTensors.cpp | 123 +- mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp | 5 +- mlir/lib/Dialect/StandardOps/CMakeLists.txt | 1 + mlir/lib/Dialect/StandardOps/Utils/Utils.cpp | 28 + mlir/lib/Dialect/Vector/VectorOps.cpp | 48 +- mlir/lib/IR/BuiltinTypes.cpp | 46 +- mlir/lib/IR/MLIRContext.cpp | 8 - mlir/lib/IR/TypeDetail.h | 43 - mlir/lib/Parser/TypeParser.cpp | 6 +- mlir/lib/TableGen/Builder.cpp | 74 + mlir/lib/TableGen/CMakeLists.txt | 1 + mlir/lib/TableGen/Operator.cpp | 12 + mlir/lib/TableGen/TypeDef.cpp | 53 + mlir/lib/Target/CMakeLists.txt | 51 +- mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp | 14 +- mlir/lib/Target/LLVMIR/ModuleTranslation.cpp | 8 +- mlir/lib/Target/LLVMIR/TypeTranslation.cpp | 15 +- mlir/lib/Target/SPIRV/CMakeLists.txt | 28 + .../Target/SPIRV/Deserialization/CMakeLists.txt | 17 + .../SPIRV/Deserialization/Deserialization.cpp | 23 + .../SPIRV/Deserialization/DeserializeOps.cpp | 565 +++ .../Deserializer.cpp} | 1303 +---- .../Target/SPIRV/Deserialization/Deserializer.h | 613 +++ mlir/lib/Target/SPIRV/Serialization/CMakeLists.txt | 15 + .../SPIRV/{ => Serialization}/Serialization.cpp | 0 mlir/lib/Transforms/BufferDeallocation.cpp | 10 +- mlir/lib/Transforms/PipelineDataTransfer.cpp | 10 +- mlir/test/Bindings/Python/CMakeLists.txt | 4 +- mlir/test/Bindings/Python/ir_affine_expr.py | 275 ++ mlir/test/Bindings/Python/ir_affine_map.py | 148 + mlir/test/Bindings/Python/ir_types.py | 16 +- mlir/test/CAPI/ir.c | 52 +- mlir/test/CMakeLists.txt | 1 + .../Conversion/ArmNeonToLLVM/convert-to-llvm.mlir | 6 +- .../SPIRVToLLVM/arithmetic-ops-to-llvm.mlir | 26 +- .../SPIRVToLLVM/bitwise-ops-to-llvm.mlir | 94 +- .../Conversion/SPIRVToLLVM/cast-ops-to-llvm.mlir | 28 +- .../SPIRVToLLVM/comparison-ops-to-llvm.mlir | 44 +- .../SPIRVToLLVM/constant-op-to-llvm.mlir | 12 +- .../Conversion/SPIRVToLLVM/func-ops-to-llvm.mlir | 8 +- .../Conversion/SPIRVToLLVM/glsl-ops-to-llvm.mlir | 24 +- .../SPIRVToLLVM/logical-ops-to-llvm.mlir | 12 +- .../Conversion/SPIRVToLLVM/memory-ops-to-llvm.mlir | 8 +- .../Conversion/SPIRVToLLVM/misc-ops-to-llvm.mlir | 10 +- .../Conversion/SPIRVToLLVM/shift-ops-to-llvm.mlir | 36 +- .../SPIRVToLLVM/spirv-types-to-llvm.mlir | 6 +- .../StandardToLLVM/convert-to-llvmir.mlir | 140 +- .../StandardToLLVM/standard-to-llvm.mlir | 20 +- .../VectorToLLVM/vector-mask-to-llvm.mlir | 40 +- .../VectorToLLVM/vector-reduction-to-llvm.mlir | 16 +- .../Conversion/VectorToLLVM/vector-to-llvm.mlir | 726 +-- .../Conversion/VectorToROCDL/vector-to-rocdl.mlir | 8 +- .../Conversion/VectorToSCF/vector-to-loops.mlir | 16 +- mlir/test/Dialect/LLVMIR/dialect-cast.mlir | 17 +- mlir/test/Dialect/LLVMIR/invalid.mlir | 62 +- mlir/test/Dialect/LLVMIR/nvvm.mlir | 8 +- mlir/test/Dialect/LLVMIR/rocdl.mlir | 164 +- mlir/test/Dialect/LLVMIR/roundtrip.mlir | 36 +- mlir/test/Dialect/LLVMIR/types-invalid.mlir | 12 +- mlir/test/Dialect/LLVMIR/types.mlir | 8 +- mlir/test/Dialect/Linalg/canonicalize.mlir | 36 + mlir/test/Dialect/Linalg/reshape_fusion.mlir | 166 +- .../Linalg/reshape_linearization_fusion.mlir | 145 +- mlir/test/Dialect/SPIRV/IR/barrier-ops.mlir | 49 + mlir/test/Dialect/SPIRV/IR/bit-ops.mlir | 130 + mlir/test/Dialect/SPIRV/IR/cast-ops.mlir | 262 + mlir/test/Dialect/SPIRV/IR/group-ops.mlir | 13 +- mlir/test/Dialect/SPIRV/IR/logical-ops.mlir | 211 + mlir/test/Dialect/SPIRV/IR/memory-ops.mlir | 629 +++ mlir/test/Dialect/SPIRV/IR/misc-ops.mlir | 29 + mlir/test/Dialect/SPIRV/IR/ops.mlir | 1355 ------ mlir/test/Dialect/SPIRV/IR/structure-ops.mlir | 35 + mlir/test/Dialect/Vector/canonicalize.mlir | 35 + mlir/test/Dialect/Vector/invalid.mlir | 31 + .../SPIRV/{barrier.mlir => barrier-ops.mlir} | 0 mlir/test/Target/arm-neon.mlir | 22 +- mlir/test/Target/arm-sve.mlir | 56 +- mlir/test/Target/avx512.mlir | 20 +- mlir/test/Target/import.ll | 6 +- mlir/test/Target/llvmir-intrinsics.mlir | 172 +- mlir/test/Target/llvmir-types.mlir | 10 +- mlir/test/Target/llvmir.mlir | 84 +- mlir/test/Target/nvvmir.mlir | 6 +- mlir/test/Target/rocdl.mlir | 110 +- mlir/test/lib/Dialect/Test/TestTypeDefs.td | 20 +- mlir/test/lib/Dialect/Test/TestTypes.cpp | 2 +- .../lib/Transforms/TestLinalgFusionTransforms.cpp | 14 +- .../{openmp-common.td => directive-common.td} | 7 +- mlir/test/mlir-tblgen/typedefs.td | 24 +- .../mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp | 3 +- mlir/tools/mlir-tblgen/CMakeLists.txt | 2 +- ...{OpenMPCommonGen.cpp => DirectiveCommonGen.cpp} | 32 +- mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp | 98 +- mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp | 13 +- mlir/tools/mlir-tblgen/TypeDefGen.cpp | 245 +- openmp/libomptarget/plugins/CMakeLists.txt | 33 +- openmp/libomptarget/plugins/amdgpu/CMakeLists.txt | 1 + openmp/libomptarget/plugins/amdgpu/src/rtl.cpp | 2 +- openmp/libomptarget/plugins/common/CMakeLists.txt | 14 + .../plugins/common/MemoryManager/CMakeLists.txt | 11 + .../plugins/common/MemoryManager/MemoryManager.h | 341 ++ .../plugins/common/elf_common/CMakeLists.txt | 15 + .../{elf_common.c => elf_common/elf_common.h} | 6 +- openmp/libomptarget/plugins/cuda/CMakeLists.txt | 2 + openmp/libomptarget/plugins/cuda/src/rtl.cpp | 102 +- .../plugins/generic-elf-64bit/src/rtl.cpp | 2 +- openmp/libomptarget/plugins/ve/CMakeLists.txt | 1 + openmp/libomptarget/plugins/ve/src/rtl.cpp | 2 +- openmp/libomptarget/src/CMakeLists.txt | 1 - openmp/libomptarget/src/MemoryManager.cpp | 262 - openmp/libomptarget/src/MemoryManager.h | 95 - openmp/libomptarget/src/device.cpp | 24 +- openmp/libomptarget/src/device.h | 4 - runtimes/CMakeLists.txt | 200 + {llvm/runtimes => runtimes}/Components.cmake.in | 0 536 files changed, 28490 insertions(+), 21998 deletions(-) create mode 100644 .github/lockdown.yml create mode 100644 clang/test/Frontend/fixed_point_conversions_half.c create mode 100644 clang/test/Sema/attr-enforce-tcb-errors.cpp create mode 100644 clang/test/Sema/attr-enforce-tcb.c create mode 100644 clang/test/Sema/attr-enforce-tcb.cpp create mode 100644 clang/test/Sema/incompatible-sign.cpp rename libc/src/__support/{common.h.def => common.h} (54%) create mode 100644 libcxx/test/std/utilities/meta/meta.unary/meta.unary.prop/is_sc [...] delete mode 100644 lld/test/ELF/debug-gnu-pubnames.s create mode 100644 lld/test/ELF/lto/exclude-libs-libcall.ll create mode 100644 llvm/test/CodeGen/Hexagon/autohvx/widen-setcc.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfclass-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfclass-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll copy llvm/test/CodeGen/{X86 => }/lit.local.cfg (82%) create mode 100644 llvm/test/TableGen/spurious-semi.td create mode 100644 llvm/test/Transforms/UniqueInternalLinkageNames/unique-internal [...] delete mode 100644 llvm/test/Transforms/UniqueLinkageNames/unique-internal-linkage [...] create mode 100644 mlir/include/mlir-c/Dialect/Linalg.h create mode 100644 mlir/include/mlir-c/Dialect/SCF.h create mode 100644 mlir/include/mlir-c/Dialect/Shape.h rename mlir/include/mlir-c/{StandardDialect.h => Dialect/Standard.h} (52%) create mode 100644 mlir/include/mlir-c/Dialect/Tensor.h create mode 100644 mlir/include/mlir/CAPI/Registration.h create mode 100644 mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBarrierOps.td copy mlir/include/mlir/Dialect/SPIRV/IR/{SPIRVOps.td => SPIRVMemoryOps.td} (53%) create mode 100644 mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td create mode 100644 mlir/include/mlir/Dialect/StandardOps/Utils/Utils.h create mode 100644 mlir/include/mlir/TableGen/Builder.h create mode 100644 mlir/lib/Bindings/Python/LinalgOps.td create mode 100644 mlir/lib/Bindings/Python/ShapeOps.td create mode 100644 mlir/lib/Bindings/Python/TensorOps.td create mode 100644 mlir/lib/CAPI/Dialect/CMakeLists.txt create mode 100644 mlir/lib/CAPI/Dialect/Linalg.cpp create mode 100644 mlir/lib/CAPI/Dialect/SCF.cpp create mode 100644 mlir/lib/CAPI/Dialect/Shape.cpp create mode 100644 mlir/lib/CAPI/Dialect/Standard.cpp create mode 100644 mlir/lib/CAPI/Dialect/Tensor.cpp delete mode 100644 mlir/lib/CAPI/Standard/CMakeLists.txt delete mode 100644 mlir/lib/CAPI/Standard/StandardDialect.cpp create mode 100644 mlir/lib/Dialect/StandardOps/Utils/Utils.cpp create mode 100644 mlir/lib/TableGen/Builder.cpp create mode 100644 mlir/lib/Target/SPIRV/CMakeLists.txt create mode 100644 mlir/lib/Target/SPIRV/Deserialization/CMakeLists.txt create mode 100644 mlir/lib/Target/SPIRV/Deserialization/Deserialization.cpp create mode 100644 mlir/lib/Target/SPIRV/Deserialization/DeserializeOps.cpp rename mlir/lib/Target/SPIRV/{Deserialization.cpp => Deserialization/Deserializer. [...] create mode 100644 mlir/lib/Target/SPIRV/Deserialization/Deserializer.h create mode 100644 mlir/lib/Target/SPIRV/Serialization/CMakeLists.txt rename mlir/lib/Target/SPIRV/{ => Serialization}/Serialization.cpp (100%) create mode 100644 mlir/test/Bindings/Python/ir_affine_expr.py create mode 100644 mlir/test/Dialect/SPIRV/IR/barrier-ops.mlir create mode 100644 mlir/test/Dialect/SPIRV/IR/cast-ops.mlir create mode 100644 mlir/test/Dialect/SPIRV/IR/memory-ops.mlir create mode 100644 mlir/test/Dialect/SPIRV/IR/misc-ops.mlir delete mode 100644 mlir/test/Dialect/SPIRV/IR/ops.mlir rename mlir/test/Target/SPIRV/{barrier.mlir => barrier-ops.mlir} (100%) rename mlir/test/mlir-tblgen/{openmp-common.td => directive-common.td} (83%) rename mlir/tools/mlir-tblgen/{OpenMPCommonGen.cpp => DirectiveCommonGen.cpp} (72%) create mode 100644 openmp/libomptarget/plugins/common/CMakeLists.txt create mode 100644 openmp/libomptarget/plugins/common/MemoryManager/CMakeLists.txt create mode 100644 openmp/libomptarget/plugins/common/MemoryManager/MemoryManager.h create mode 100644 openmp/libomptarget/plugins/common/elf_common/CMakeLists.txt rename openmp/libomptarget/plugins/common/{elf_common.c => elf_common/elf_common.h} (93%) delete mode 100644 openmp/libomptarget/src/MemoryManager.cpp delete mode 100644 openmp/libomptarget/src/MemoryManager.h create mode 100644 runtimes/CMakeLists.txt rename {llvm/runtimes => runtimes}/Components.cmake.in (100%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allmodconfig updated (105f3ad2 -> f102b470)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allmodconfig in repository toolchain/ci/base-artifacts. discards 105f3ad2 0: update: llvm-linux-qemu: all new f102b470 0: update: llvm-linux-qemu: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (105f3ad2) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-s [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 18 +- 02-prepare_abe/console.log | 434 +- 03-build_llvm/console.log | 13734 ++++++++++++------------ 04-build_linux/console.log | 884 +- 05-build_abe-qemu/console.log | 6753 ++++++------ 06-boot_linux/console.log | 2 +- 07-check_regression/console.log | 16 +- 08-update_baseline/console.log | 14 +- console.log | 21855 +++++++++++++++++++------------------- jenkins/manifest.sh | 12 +- 10 files changed, 21854 insertions(+), 21868 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu/gnu-release-arm-bootstrap_O1 updated (678ea9ba72b -> 71878c08e96)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-release-arm-bootstrap_O1 in repository toolchain/ci/gcc. from 678ea9ba72b Daily bump. adds fd02aeeab1c Daily bump. adds 0fd6247a301 tree-optimization/97623 - avoid excessive insert iteration [...] adds eddcb627ccf tree-optimization/97623 - Avoid PRE hoist insertion iteration adds 69894ce1724 tree-optimization/98117 - fix range set by vectorization on [...] adds f0e81957b2b libstdc++: Remove accidental -std=gnu++17 from test adds 4fd49da23bf libstdc++: Fix std::any pretty printer [PR 68735] adds 93beee71a5b libstdc++: Only use __builtin_sprintf if supported [PR 96083] adds cb02e1d8a00 libstdc++: Fix filesystem::path pretty printer test failure adds eebaeb8c596 Daily bump. adds ecab0d9106a tree-optimization/98221 - fix wrong unpack operation used f [...] adds c97c4eb81b1 aarch64: Extend aarch64-autovec-preference==2 to 128-bit SVE adds 85239c475ee aarch64: Improve vcombine codegen [PR89057] adds 20a88b29f4a vect: Fix missing alias checks for 128-bit SVE [PR98371] adds f36a9d20ecb vect: Avoid generating out-of-range shifts [PR98302] adds 134d80cba22 genmodes: Update GET_MODE_MASK when changing NUNITS [PR98214] adds ad15ddcbf45 recog: Fix a constrain_operands corner case [PR97144] adds 4e07a6f33be vect, aarch64: Fix alignment units for IFN_MASK* [PR95401] adds 2a8ca3e6ec5 vect: Fix bogus alignment assumption in alias checks [PR94994] adds edb7dbc25de tree-optimization/98282 - classify V_C_E<constant> as nary adds 71878c08e96 tree-optimization/98513 - fix bug in range intersection code No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 27 ++++++++ gcc/DATESTAMP | 2 +- gcc/config/aarch64/aarch64-simd.md | 15 +++- gcc/config/aarch64/aarch64-sve-builtins.cc | 2 +- gcc/config/aarch64/aarch64.c | 9 +-- gcc/genmodes.c | 22 +++++- gcc/gimple-fold.c | 2 +- gcc/machmode.h | 3 +- gcc/recog.c | 8 +-- gcc/testsuite/ChangeLog | 23 +++++++ gcc/testsuite/g++.dg/opt/pr98282.C | 80 ++++++++++++++++++++++ gcc/testsuite/g++.dg/vect/pr95401.cc | 13 ++++ gcc/testsuite/g++.dg/vect/pr95401a.cc | 13 ++++ gcc/testsuite/gcc.c-torture/compile/pr97144.c | 24 +++++++ gcc/testsuite/gcc.dg/torture/pr98117.c | 19 +++++ gcc/testsuite/gcc.dg/tree-ssa/pr98513.c | 47 +++++++++++++ gcc/testsuite/gcc.dg/tree-ssa/ssa-hoist-3.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-hoist-7.c | 54 +++++++++++++++ gcc/testsuite/gcc.dg/tree-ssa/ssa-pre-30.c | 2 +- gcc/testsuite/gcc.dg/vect/pr94994.c | 61 +++++++++++++++++ gcc/testsuite/gcc.dg/vect/pr98302.c | 22 ++++++ gcc/testsuite/gcc.target/aarch64/pr89057.c | 16 +++++ gcc/testsuite/gcc.target/aarch64/sve/pr97144.c | 26 +++++++ gcc/testsuite/gcc.target/aarch64/sve/pr98214.c | 21 ++++++ gcc/tree-ssa-forwprop.c | 21 +++--- gcc/tree-ssa-pre.c | 33 +++++++-- gcc/tree-ssa-sccvn.c | 3 +- gcc/tree-vect-data-refs.c | 2 +- gcc/tree-vect-loop-manip.c | 28 ++++++-- gcc/tree-vect-loop.c | 61 ++++++++++++++++- gcc/tree-vect-patterns.c | 13 +++- gcc/tree-vect-stmts.c | 9 +-- gcc/value-range.cc | 6 +- libstdc++-v3/ChangeLog | 39 +++++++++++ libstdc++-v3/include/ext/throw_allocator.h | 16 +++++ libstdc++-v3/python/libstdcxx/v6/printers.py | 42 +++++++++--- .../filesystem/filesystem_error/cons.cc | 2 +- .../libstdc++-prettyprinters/filesystem-ts.cc | 39 +++++++++++ 38 files changed, 764 insertions(+), 63 deletions(-) create mode 100644 gcc/testsuite/g++.dg/opt/pr98282.C create mode 100644 gcc/testsuite/g++.dg/vect/pr95401.cc create mode 100644 gcc/testsuite/g++.dg/vect/pr95401a.cc create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr97144.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr98117.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr98513.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/ssa-hoist-7.c create mode 100644 gcc/testsuite/gcc.dg/vect/pr94994.c create mode 100644 gcc/testsuite/gcc.dg/vect/pr98302.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr89057.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr97144.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr98214.c create mode 100644 libstdc++-v3/testsuite/libstdc++-prettyprinters/filesystem-ts.cc -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu/gnu-release-arm-bootstrap_O1 updated (c0c829d6 -> 88ed59c5)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-release-arm-bootstrap_O1 in repository toolchain/ci/base-artifacts. discards c0c829d6 0: update: gcc-678ea9ba72bea2dba531cd8dcdf5c03a3710115d: 1 new 88ed59c5 0: update: gcc-71878c08e967997b570b1acbd9ffef4234e94698: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (c0c829d6) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu/gnu-release-arm-boot [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 130 +- 02-prepare_abe/console.log | 434 +- 04-build_abe-bootstrap_O1/console.log | 95845 +++++++++++++++---------------- 05-check_regression/console.log | 2 +- 06-update_baseline/console.log | 2 +- console.log | 96449 ++++++++++++++++---------------- jenkins/manifest.sh | 8 +- 7 files changed, 96475 insertions(+), 96395 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allnoconfig updated (cbe9758ff49 -> 248feb2fa2c)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allnoconfig in repository toolchain/ci/gcc. from cbe9758ff49 Properly release symtab::m_clones. adds b81fbfe1eb5 aarch64: Add support for unpacked SVE shifts adds 48c7f5b8811 aarch64: Add support for unpacked SVE mult, max and min adds ab76e3db6b8 aarch64: Add general unpacked SVE conditional binary arithmetic adds 3f8b0bba035 aarch64: Add support for unpacked SVE ADR adds 907ea379559 aarch64: Add support for unpacked SVE ABD adds 7446de5a2af aarch64: Add support for unpacked SVE MULH adds 37426e0f060 aarch64: Add support for unpacked SVE conditional BIC adds a958b2fc6da aarch64: Add support for unpacked SVE ASRD adds 67fbb7f0fda Daily bump. adds ab88f360723 analyzer: fix ICE merging dereferencing unknown ptrs [PR98628] adds 640296c367f make FOR_EACH_IMM_USE_STMT safe for early exits adds 240f0a490da Delete dead code in ix86_expand_sse_comi. adds 814299a9d49 c++: -Wmissing-field-initializers in unevaluated ctx [PR98620] adds ab96073df00 MAINTAINERS: Add myself for write after approval adds ff99d05f40f configure, make: Fix up --enable-link-serialization adds 13d47c37a2c reassoc: Optimize in reassoc x < 0 && y < 0 to (x | y) < 0 [...] adds 24ea113f75c widening_mul: Fix up ICE caused by my signed multiplication [...] adds b2230210f17 gcov: add more debugging facility adds e91910d3576 options: properly compare string arguments adds 52a170b1a18 tree-optimization/98550 - fix BB vect unrolling check adds e0bec6ceac4 c++: Fix ICE with CTAD in concept [PR98611] new cf2ac1c30af [PR97969] LRA: Transform pattern `plus (plus (hard reg, con [...] new 25bef68902f arm: Add movmisalign patterns for MVE (PR target/97875) new 1aff68d54c3 Fix typo in function-abi.h new 248feb2fa2c gcov: fix printf format for 32-bit hosts The 4 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: MAINTAINERS | 1 + contrib/ChangeLog | 5 + gcc/ChangeLog | 176 +++++++++ gcc/DATESTAMP | 2 +- gcc/analyzer/store.cc | 7 +- gcc/config/aarch64/aarch64-sve.md | 413 ++++++++++++--------- gcc/config/aarch64/iterators.md | 4 + gcc/config/arm/arm.h | 40 ++ gcc/config/arm/mve.md | 23 ++ gcc/config/arm/neon.md | 25 -- gcc/config/arm/vec-common.md | 23 ++ gcc/config/i386/i386-builtins.h | 4 - gcc/config/i386/i386-expand.c | 5 - gcc/configure | 7 +- gcc/configure.ac | 7 +- gcc/cp/ChangeLog | 10 + gcc/cp/tree.c | 5 +- gcc/cp/typeck2.c | 2 + gcc/d/ChangeLog | 10 + gcc/doc/tree-ssa.texi | 16 +- gcc/function-abi.h | 2 +- gcc/gcov.c | 43 ++- gcc/gimple-ssa-strength-reduction.c | 2 +- gcc/graphite-scop-detection.c | 4 +- gcc/ipa-modref.c | 4 +- gcc/ipa-pure-const.c | 8 +- gcc/ipa-sra.c | 22 +- gcc/lra-eliminations.c | 28 +- gcc/optc-save-gen.awk | 6 +- gcc/profile.c | 5 + gcc/ssa-iterators.h | 39 +- gcc/testsuite/ChangeLog | 97 +++++ gcc/testsuite/g++.dg/cpp2a/concepts-ctad1.C | 16 + gcc/testsuite/g++.dg/cpp2a/concepts-ctad2.C | 13 + gcc/testsuite/g++.dg/opt/pr98550.C | 96 +++++ .../g++.dg/warn/Wmissing-field-initializers-2.C | 44 +++ gcc/testsuite/g++.target/aarch64/sve/abd_1.C | 38 ++ gcc/testsuite/g++.target/aarch64/sve/cond_abd_1.C | 60 +++ gcc/testsuite/g++.target/aarch64/sve/cond_abd_2.C | 60 +++ gcc/testsuite/g++.target/aarch64/sve/cond_abd_3.C | 49 +++ gcc/testsuite/g++.target/aarch64/sve/cond_abd_4.C | 43 +++ .../g++.target/aarch64/sve/cond_arith_1.C | 89 +++++ .../g++.target/aarch64/sve/cond_arith_2.C | 89 +++++ .../g++.target/aarch64/sve/cond_arith_3.C | 91 +++++ .../g++.target/aarch64/sve/cond_arith_4.C | 91 +++++ gcc/testsuite/g++.target/aarch64/sve/cond_bic_1.C | 40 ++ gcc/testsuite/g++.target/aarch64/sve/cond_bic_2.C | 31 ++ gcc/testsuite/g++.target/aarch64/sve/cond_bic_3.C | 36 ++ gcc/testsuite/g++.target/aarch64/sve/cond_bic_4.C | 36 ++ .../g++.target/aarch64/sve/cond_shift_1.C | 92 +++++ .../g++.target/aarch64/sve/cond_shift_2.C | 91 +++++ .../g++.target/aarch64/sve/cond_shift_3.C | 94 +++++ .../g++.target/aarch64/sve/cond_shift_4.C | 94 +++++ gcc/testsuite/g++.target/aarch64/sve/max_1.C | 73 ++++ gcc/testsuite/g++.target/aarch64/sve/min_1.C | 73 ++++ gcc/testsuite/gcc.c-torture/compile/pr98629.c | 11 + gcc/testsuite/gcc.c-torture/execute/pr95731.c | 40 ++ gcc/testsuite/gcc.dg/analyzer/pr98628.c | 19 + gcc/testsuite/gcc.dg/tree-ssa/pr95731.c | 22 ++ gcc/testsuite/gcc.target/aarch64/sve/adr_6.c | 43 +++ gcc/testsuite/gcc.target/aarch64/sve/asrdiv_4.c | 29 ++ gcc/testsuite/gcc.target/aarch64/sve/cond_asrd_1.c | 32 ++ .../gcc.target/aarch64/sve/cond_asrd_1_run.c | 26 ++ gcc/testsuite/gcc.target/aarch64/sve/cond_asrd_2.c | 35 ++ .../gcc.target/aarch64/sve/cond_asrd_2_run.c | 26 ++ gcc/testsuite/gcc.target/aarch64/sve/cond_asrd_3.c | 35 ++ .../gcc.target/aarch64/sve/cond_asrd_3_run.c | 26 ++ gcc/testsuite/gcc.target/aarch64/sve/mul_2.c | 52 +++ .../gcc.target/aarch64/sve/mul_highpart_3.c | 34 ++ gcc/testsuite/gcc.target/aarch64/sve/shift_2.c | 81 ++++ gcc/testsuite/gcc.target/arm/pr97969.c | 54 +++ gcc/testsuite/gcc.target/arm/simd/mve-vneg.c | 3 + gcc/tree-predcom.c | 2 +- gcc/tree-ssa-ccp.c | 2 +- gcc/tree-ssa-dce.c | 2 +- gcc/tree-ssa-dse.c | 8 +- gcc/tree-ssa-loop-ivopts.c | 2 +- gcc/tree-ssa-math-opts.c | 37 +- gcc/tree-ssa-phiprop.c | 2 +- gcc/tree-ssa-reassoc.c | 62 +++- gcc/tree-ssa.c | 2 +- gcc/tree-vect-slp.c | 44 ++- 82 files changed, 2901 insertions(+), 314 deletions(-) create mode 100644 gcc/testsuite/g++.dg/cpp2a/concepts-ctad1.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/concepts-ctad2.C create mode 100644 gcc/testsuite/g++.dg/opt/pr98550.C create mode 100644 gcc/testsuite/g++.dg/warn/Wmissing-field-initializers-2.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/abd_1.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/cond_abd_1.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/cond_abd_2.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/cond_abd_3.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/cond_abd_4.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/cond_arith_1.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/cond_arith_2.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/cond_arith_3.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/cond_arith_4.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/cond_bic_1.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/cond_bic_2.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/cond_bic_3.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/cond_bic_4.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/cond_shift_1.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/cond_shift_2.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/cond_shift_3.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/cond_shift_4.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/max_1.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/min_1.C create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr98629.c create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr95731.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/pr98628.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr95731.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/adr_6.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/asrdiv_4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_asrd_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_asrd_1_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_asrd_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_asrd_2_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_asrd_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_asrd_3_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/mul_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/mul_highpart_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/shift_2.c create mode 100644 gcc/testsuite/gcc.target/arm/pr97969.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allnoconfig updated (6abd4cf281 -> 3f94e58859)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allnoconfig in repository toolchain/ci/binutils-gdb. from 6abd4cf281 gdb: check for empty strings in get_standard_cache_dir/get_s [...] adds 8fc48b7961 Pass void_context_p to parse_expression adds 46f900c065 sim: require a C11 compiler adds a7e906e8f5 Automatic date update in version.in adds 6430704567 configure regen adds aae7fcb8d7 POWER10: Add Return-Oriented Programming instructions adds b1b29aa51a elf: Verify section size for mixed ordered/unordered inputs adds ba9e922fa0 ld/x86-64: Also set LAM_U57 when setting LAM_U48 adds ce0be4070f sim: common: add missing stdlib.h for abort() adds 055bc77a80 Add Changelog entries and NEWS entries for 2.36 branch adds 573fe3fbc1 Change version number to 2.36.50 and regenerate files adds be2c78856d Update release howto with 2.37 numbers adds b5a4a01af4 sim: hw: rework code to avoid gcc warnings adds f41464416a sim: pru: fix include ordering with sim-main.h adds 0a94990bf6 ld/x86-64: Properly Handle -z lam-u48/lam-u57 adds bf470982f9 sim: enable -Werror by default for some arches adds 50df264dae sim: clean up stale AC_PREREQ refs adds f8cab0b995 sim: sh64: delete port adds f074c07d8d sim: common: clean up asprintf includes a bit adds 7eb99e5e27 sim: cr16/d10v: move storage out of header adds a9fd212a24 sim: replace rindex with strrchr adds 50ad1254d5 GCC: Pass --plugin to AR and RANLIB adds a4966cd965 Binutils: Pass --plugin to AR and RANLIB adds af019bfde9 Support the PGO build for binutils+gdb adds 66beed0227 Fix erroneous agent expression test adds bc167b6b3e Remove a use of print_expression adds 54585eee2e Avoid crash in compile_to_object adds 5834526f4b Automatic date update in version.in adds 46b1518d4c Automatic date update in version.in adds a8aa72b913 Updated translations for multiple subdirectories adds 68ed285428 sim: clean up C11 header includes adds 933306703a sim: rl78: move storage out of header adds 90e123dd60 sim: common: fix printf formats adds a0c38f0d70 sim: or1k: fix include ordering with sim-main.h adds 5c1008a41f sim: call SIM_AC_OPTION_WARNINGS(no) in remaining ports adds 9c70334dee sim: always call SIM_AC_OPTION_WARNINGS adds c0f6e439cc Add support for more MIPS variants to the linker command line. adds 82c70b08df aarch64: Remove support for CSRE adds 10dadadc5b [gdb/testsuite] Fix gdb.arch/amd64-stap-three-arg-disp.S adds 062eaacbac gdb: change jit_debug to a bool adds eef401dce1 gdb: convert solib-aix to new-style debug macros adds c6185dce03 gdb: convert aarch64 to new-style debug macros adds 254c3783fe sim: tests: get common tests working again adds eabdd87b2e Automatic date update in version.in adds 03c02f3116 GCC: Check if AR works with --plugin and rc adds 83b33c6cb9 Binutils: Check if AR works with --plugin and rc adds 44124a4683 binuitils: Check if AR is usable for LTO build adds f631b79abe sim: or1k: delete redundant SIM_AC_OPTION_INLINE call adds f220ef633c sim: common: use #error properly adds 68895f7d7e sim: README-HACKING: clean up stale run references adds 5e9e2f41eb sim: or1k: clean up stale build entries adds e998918e98 sim: or1k: fix mixing of code & decl warning adds 7c654b719d gdb/fortran: add symbol base comparison operators adds ce38f5edf1 gdb: fix debug dump of OP_BOOL expressions adds 6d104cac0a Updated translations for some subdirectories adds c2e9a4a3ed elf/x86-64: Adjust R_AMD64_DIR64/R_AMD64_DIR32 for PE/x86-64 inputs adds 18bfb5057f [gdb/testsuite] Require is_amd64_regs_target in gdb.base/dis [...] adds d546b61084 Implement a workaround for GNU mak jobserver adds 5291fe3cd1 aarch64: Add support for bfloat16 in gdb. adds b2f2ae0d6f gdb: remove pre_init_ui_hook from top.c adds 3f94e58859 [gdb/testsuite] Add have_mpx in lib/gdb.exp No new revisions were added by this update. Summary of changes: ChangeLog | 50 + Makefile.in | 68 +- Makefile.tpl | 63 +- bfd/ChangeLog | 61 + bfd/aclocal.m4 | 1 + bfd/configure | 73 +- bfd/configure.ac | 2 + bfd/elflink.c | 8 + bfd/elfxx-x86.c | 22 +- bfd/po/bfd.pot | 2574 +-- bfd/po/fr.po | 2666 +-- bfd/po/pt.po | 2681 ++-- bfd/po/sr.po | 2687 ++-- bfd/po/uk.po | 2666 +-- bfd/reloc.c | 7 + bfd/version.h | 2 +- bfd/version.m4 | 2 +- binutils/BRANCHES | 1 + binutils/ChangeLog | 42 + binutils/NEWS | 2 + binutils/README-how-to-make-a-release | 40 +- binutils/aclocal.m4 | 1 + binutils/configure | 73 +- binutils/configure.ac | 2 + binutils/po/binutils.pot | 3317 ++-- binutils/po/fr.po | 3826 +++-- binutils/po/pt.po | 3943 ++--- binutils/po/sr.po | 3845 +++-- binutils/po/uk.po | 3840 +++-- config/ChangeLog | 19 + config/gcc-plugin.m4 | 40 + config/jobserver.m4 | 24 + configure | 246 +- configure.ac | 84 + cpu/ChangeLog | 4 + elfcpp/ChangeLog | 4 + gas/ChangeLog | 63 + gas/NEWS | 10 +- gas/aclocal.m4 | 1 + gas/config/tc-aarch64.c | 31 - gas/configure | 73 +- gas/configure.ac | 2 + gas/doc/c-aarch64.texi | 2 - gas/po/fr.po | 7239 ++++----- gas/po/gas.pot | 2131 +-- gas/po/uk.po | 7237 ++++----- gas/testsuite/gas/aarch64/csre-invalid.d | 3 - gas/testsuite/gas/aarch64/csre-invalid.s | 6 - gas/testsuite/gas/aarch64/csre.d | 29 - gas/testsuite/gas/aarch64/csre_csr-invalid.d | 3 - gas/testsuite/gas/aarch64/csre_csr-invalid.l | 2 - gas/testsuite/gas/aarch64/csre_csr-invalid.s | 4 - gas/testsuite/gas/aarch64/csre_csr.d | 10 - gas/testsuite/gas/aarch64/csre_csr.s | 4 - gas/testsuite/gas/ppc/ppc.exp | 2 + gas/testsuite/gas/ppc/rop-checks.d | 3 + gas/testsuite/gas/ppc/rop-checks.l | 17 + gas/testsuite/gas/ppc/rop-checks.s | 18 + gas/testsuite/gas/ppc/rop.d | 27 + gas/testsuite/gas/ppc/rop.s | 21 + gdb/ChangeLog | 62 + gdb/aarch64-tdep.c | 94 +- gdb/arch/aarch64-insn.c | 9 +- gdb/arch/aarch64-insn.h | 5 + gdb/compile/compile.c | 4 +- gdb/expprint.c | 9 +- gdb/expression.h | 3 +- gdb/f-exp.y | 36 +- gdb/features/aarch64-fpu.c | 5 + gdb/features/aarch64-fpu.xml | 2 + gdb/jit.c | 18 +- gdb/parse.c | 15 +- gdb/printcmd.c | 10 +- gdb/solib-aix.c | 23 +- gdb/testsuite/ChangeLog | 52 + gdb/testsuite/gdb.ada/voidctx.exp | 40 + gdb/testsuite/gdb.ada/voidctx/pck.adb | 27 + gdb/testsuite/gdb.ada/voidctx/pck.ads | 23 + gdb/testsuite/gdb.ada/voidctx/voidctx.adb | 31 + gdb/testsuite/gdb.arch/aarch64-fp.exp | 25 + gdb/testsuite/gdb.arch/amd64-stap-three-arg-disp.S | 5 +- gdb/testsuite/gdb.arch/i386-mpx-call.c | 78 +- gdb/testsuite/gdb.arch/i386-mpx-call.exp | 17 +- gdb/testsuite/gdb.arch/i386-mpx-map.c | 45 +- gdb/testsuite/gdb.arch/i386-mpx-map.exp | 23 +- gdb/testsuite/gdb.arch/i386-mpx-sigsegv.c | 80 +- gdb/testsuite/gdb.arch/i386-mpx-sigsegv.exp | 15 +- gdb/testsuite/gdb.arch/i386-mpx-simple_segv.c | 40 +- gdb/testsuite/gdb.arch/i386-mpx-simple_segv.exp | 15 +- gdb/testsuite/gdb.arch/i386-mpx.c | 98 +- gdb/testsuite/gdb.arch/i386-mpx.exp | 22 +- gdb/testsuite/gdb.base/disasm-optim.exp | 2 +- gdb/testsuite/gdb.fortran/debug-expr.exp | 8 + gdb/testsuite/gdb.fortran/dot-ops.exp | 30 + gdb/testsuite/gdb.trace/ax.exp | 2 +- gdb/testsuite/lib/gdb.exp | 52 + gdb/top.c | 5 - gdb/tracepoint.c | 17 +- gdb/tracepoint.h | 2 +- gold/ChangeLog | 9 + gold/po/sr.po | 729 +- gold/po/uk.po | 730 +- gprof/ChangeLog | 29 + gprof/aclocal.m4 | 1 + gprof/configure | 73 +- gprof/configure.ac | 2 + gprof/po/gprof.pot | 4 +- include/ChangeLog | 9 + include/opcode/aarch64.h | 2 - ld/ChangeLog | 61 + ld/Makefile.in | 1 - ld/NEWS | 2 + ld/aclocal.m4 | 1 + ld/configure | 85 +- ld/configure.ac | 2 + ld/ldmain.c | 4 + ld/po/ld.pot | 2266 +-- ld/po/pt_BR.po | 3715 +++-- ld/po/uk.po | 3703 +++-- ld/testsuite/ld-x86-64/lam-u48.rd | 6 + ld/testsuite/ld-x86-64/lam-u57.rd | 6 + ld/testsuite/ld-x86-64/pe-x86-64-5.obj.bz2 | Bin 0 -> 685 bytes ld/testsuite/ld-x86-64/pe-x86-64-5.od | 34 + ld/testsuite/ld-x86-64/pe-x86-64-5.rd | 19 + ld/testsuite/ld-x86-64/pe-x86-64.exp | 10 + ld/testsuite/ld-x86-64/property-x86-lam-u48-4.d | 2 +- ld/testsuite/ld-x86-64/property-x86-lam-u48-5.d | 2 +- ld/testsuite/ld-x86-64/x86-64.exp | 16 + libctf/ChangeLog | 24 + libctf/aclocal.m4 | 1 + libctf/configure | 53 +- libctf/configure.ac | 2 + libiberty/ChangeLog | 15 + libiberty/Makefile.in | 5 +- libiberty/aclocal.m4 | 1 + libiberty/configure | 140 + libiberty/configure.ac | 12 + libtool.m4 | 32 +- opcodes/ChangeLog | 59 + opcodes/aarch64-asm-2.c | 248 +- opcodes/aarch64-dis-2.c | 2579 ++- opcodes/aarch64-opc-2.c | 16 +- opcodes/aarch64-opc.c | 4 - opcodes/aarch64-tbl.h | 7 - opcodes/aclocal.m4 | 1 + opcodes/configure | 73 +- opcodes/configure.ac | 2 + opcodes/po/de.po | 514 +- opcodes/po/fr.po | 514 +- opcodes/po/opcodes.pot | 505 +- opcodes/po/pt_BR.po | 619 +- opcodes/po/sr.po | 515 +- opcodes/po/sv.po | 516 +- opcodes/po/uk.po | 516 +- opcodes/ppc-opc.c | 46 +- sim/ChangeLog | 19 + sim/MAINTAINERS | 2 +- sim/README-HACKING | 31 +- sim/aarch64/ChangeLog | 12 + sim/aarch64/config.in | 6 - sim/aarch64/configure | 124 +- sim/arm/ChangeLog | 12 + sim/arm/config.in | 6 - sim/arm/configure | 124 +- sim/avr/ChangeLog | 13 + sim/avr/config.in | 6 - sim/avr/configure | 124 +- sim/avr/interp.c | 3 +- sim/bfin/ChangeLog | 12 + sim/bfin/config.in | 6 - sim/bfin/configure | 124 +- sim/bpf/ChangeLog | 17 + sim/bpf/config.in | 6 - sim/bpf/configure | 221 +- sim/bpf/configure.ac | 1 + sim/common/ChangeLog | 55 + sim/common/Make-common.in | 3 +- sim/common/acinclude.m4 | 61 +- sim/common/callback.c | 10 - sim/common/cgen-par.c | 1 + sim/common/cgen-scache.c | 2 - sim/common/cgen-trace.c | 1 + sim/common/dv-glue.c | 6 - sim/common/dv-pal.c | 9 - sim/common/dv-sockser.c | 8 - sim/common/hw-alloc.c | 3 - sim/common/hw-base.c | 21 +- sim/common/hw-device.c | 5 - sim/common/hw-events.c | 3 +- sim/common/hw-handles.c | 2 - sim/common/hw-ports.c | 10 - sim/common/hw-properties.c | 6 - sim/common/hw-tree.c | 10 - sim/common/nrun.c | 7 - sim/common/sim-abort.c | 1 + sim/common/sim-arange.c | 5 - sim/common/sim-basics.h | 5 - sim/common/sim-core.c | 4 +- sim/common/sim-events.c | 10 - sim/common/sim-fpu.c | 2 - sim/common/sim-hw.c | 9 - sim/common/sim-load.c | 2 - sim/common/sim-memopt.c | 10 - sim/common/sim-options.c | 8 - sim/common/sim-profile.c | 9 - sim/common/sim-profile.h | 2 +- sim/common/sim-trace.c | 8 - sim/common/sim-utils.c | 13 - sim/common/sim-watch.c | 11 +- sim/common/syscall.c | 6 - sim/configure | 8 - sim/configure.tgt | 3 - sim/cr16/ChangeLog | 23 + sim/cr16/config.in | 6 - sim/cr16/configure | 121 +- sim/cr16/configure.ac | 2 +- sim/cr16/cr16_sim.h | 4 +- sim/cr16/interp.c | 2 + sim/cr16/simops.c | 4 - sim/cris/ChangeLog | 20 + sim/cris/config.in | 9 - sim/cris/configure | 123 +- sim/cris/configure.ac | 4 +- sim/cris/dv-rv.c | 14 - sim/cris/rvdummy.c | 7 - sim/cris/sim-if.c | 2 - sim/cris/traps.c | 2 - sim/d10v/ChangeLog | 24 + sim/d10v/config.in | 6 - sim/d10v/configure | 121 +- sim/d10v/configure.ac | 2 +- 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4 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allnoconfig updated (b810e812 -> f17220c0)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allnoconfig in repository toolchain/ci/base-artifacts. discards b810e812 0: update: qemu-b3f846c59d8405bb87c551187721fc92ff2f1b92: boot new f17220c0 0: update: binutils-gcc-linux-qemu: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (b810e812) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-aarch6 [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 100 +- 02-prepare_abe/console.log | 440 +- 03-build_abe-binutils/console.log | 11776 +++++----- 04-build_abe-stage1/console.log | 16295 +++++++------- 05-build_linux/console.log | 633 +- 06-build_abe-qemu/console.log | 6822 +++--- 08-check_regression/console.log | 10 +- 08-check_regression/results.regressions | 2 +- 09-update_baseline/console.log | 12 +- 09-update_baseline/results.regressions | 2 +- console.log | 36088 +++++++++++++++--------------- jenkins/manifest.sh | 16 +- 12 files changed, 36917 insertions(+), 35279 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[binutils-gdb] branch master updated (3f94e588596 -> fe7a351a8eb)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from 3f94e588596 [gdb/testsuite] Add have_mpx in lib/gdb.exp new 16e9019ef73 gdb: move baud_rate and serial_parity declarations to serial.h new fe7a351a8eb gdb: move read{now,never}_symbol_files declarations to symfile.h The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gdb/ChangeLog | 14 ++++++++++++++ gdb/main.c | 1 + gdb/serial.c | 7 ++----- gdb/serial.h | 8 ++++++++ gdb/symfile.c | 10 ++++++++-- gdb/symfile.h | 8 ++++++++ gdb/target.h | 6 ------ gdb/top.h | 4 ---- 8 files changed, 41 insertions(+), 17 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

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