Tcwg-commits January 2021

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[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_bmk_tk1/llvm-master-arm-spec2k6-Os_LTO updated (a46982a2551 -> e8049dc3c8a)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/llvm-master-arm-spec2k6-Os_LTO in repository toolchain/ci/llvm-project. from a46982a2551 [X86] Add nounwind to lzcnt-cmp tests adds a0f82749f4f [X86] Extend lzcnt-cmp tests to test on non-lzcnt targets adds dbd5fa1e75d [ARM] Update existing test case with +pauth targets adds a2dbf3443af [clangd] Fix -check mode doesn't respect any tidy configs. adds 97517055128 [OpenMPOpt][WIP] Expand parallel region merging adds 31732e6f52c [clangd] Remove ScratchFS from tests adds e5eb5c8a7f3 NFC: Use -LABEL more adds c161775decd [FastISel] Flush local value map on every instruction adds 4214ca96145 [X86][AVX] Attempt to fold vpermf128(op(x,i),op(y,i)) -> op [...] adds 9c0dc0b2c1c [mlir][Linalg] Fold init_tensor -> linalg.tensor_reshape. adds c15b0e2229e [Clang][Docs] Fix ambiguity in clang-offload-bundler docs adds 7200d2cf089 [NFC] Disallow unused prefixes in CodeGen/PowerPC tests. adds 3d693bd0bd7 [mlir][vector] Add memory effects to transfer_read transfer [...] adds c4486cfd556 [mlir][Linalg] Fix reshape fusion to reshape the outs inste [...] adds be179b9946f [FastISel] NFC: Remove obsolete -fast-isel-sink-local-value [...] adds ac2224c0228 [ELF] --exclude-libs: localize defined libcall symbols refe [...] adds 171771e0780 [SystemZ] Minor NFC fix in SchedModels. adds 1f9c29228ce [FastISel] NFC: Clean up unnecessary bookkeeping adds 072714b9619 [X86] Regenerate vector-constrained-fp-intrinsics.ll tests adds 35c9baa11e4 [attributes] Add a facility for enforcing a Trusted Comput [...] adds a90214760d0 [Hexagon] Custom-widen SETCC's operands adds bcec0f27a2c [AMDGPU] Deduplicate VOP tablegen asm & ins adds 74628c43053 [mlir] Add Python bindings for AffineExpr adds e79bd0b4f25 [mlir] More Python bindings for AffineMap adds 547e3eef14a [mlir] Expose MemRef layout in Python bindings adds 47567ca5fac [flang][openxx][NFC] Remove duplicated function to check re [...] adds d8c6d24359f -funique-internal-linkage-names appends a hex md5hash suffi [...] adds 43a830ed941 Introduce new quiet mode and new option handling for -print [...] adds 5464baaae8c Fix minor build issue (NFC) adds 1027a22ccd7 [SystemZ][z/OS] Fix Permission denied pattern matching adds 195728c75aa [mlir] Add structural conversion to async dialect lowering. adds 37b41bd0879 [RISCV] Add scalable vector fcmp ISel patterns adds 30a7d430e86 [libc++] Turn off auto-formatting of generated files. NFC. adds 72f1f084670 [NFC][AMDGPU] Clarify memory model support for volatile adds 20741773013 [mlir][ODS] Add a C++ abstraction for OpBuilders adds 948be58258d [mlir][TypeDefGen] Add support for adding builders when gen [...] adds d79642b3db1 [mlir][IR][NFC] Move the definitions of Complex/Function/In [...] adds d3ff24cbf87 [ADT] Add makeIntrusiveRefCnt helper function adds 8ad998a6115 [tools] Mark output of tools as text if it is really text adds 05e90cefeb4 [NFC] Disallow unused prefixes under llvm/test/CodeGen adds c1ae378205d [mlir][vector] Add side-effect information to different loa [...] adds 53c866c286a Enable python bindings for tensor, shape and linalg dialects. adds cceb1bfcbbc [mlir][CAPI] Introduce standard source layout for mlir-c di [...] adds 110775809ad Revert "[mlir][linalg] Support parsing attributes in named [...] adds 288f3fc5dfe [InstCombine] reduce icmp(ashr X, C1), C2 to sign-bit test adds 32c073acb32 [GlobalISel] Map extractelt to G_EXTRACT_VECTOR_ELT adds aefeb5f136e [libc][NFC] Make __support/common.h an in tree header. adds 9b222b108a2 [c++20] Don't consider string literal operator templates fo [...] adds f4cec703ec8 Add an assert to CGDebugInfo::getTypeOrNull adds 7989684a2e4 [RISCV] Add scalable vector fadd/fsub/fmul/fdiv ISel patterns adds 046612d29d7 [mlir][vector] verify memref of vector memory ops adds a808d89d355 [PredicateInfo] Add test for one unknown condition in and/or (NFC) adds 00f773cf424 [SCCP] Fix misclassified conditions in test (NFC) adds b88c8f1aab5 CGDebugInfo: Delete unused parameters adds 32bcfcda4e2 Rename debug linkage name with -funique-internal-linkage-names adds a81c68ae6be [OpenMP] Take elf_common.c as a interface library adds 9ecc991c559 [RISCV] Add scalable vector vselect ISel patterns adds 0a23fbd28c7 clang: Always pass PowerPC endian information to GNU as adds 762ffc95550 Update syntax for tensor and memref types to match parser. adds 278a3ea1b27 [RISCV] Use vmv.v.i vd, 0 instead of vmv.v.x vd, x0 for llv [...] adds c22bc5f1f8b [SimplifyCFG] SwitchToLookupTable(): don't insert a DomTree [...] adds c0de0a1b72c [SimplifyCFG] SimplifyBranchOnICmpChain(): don't insert a D [...] adds f9ba3477063 [SimplifyCFG] FoldValueComparisonIntoPredecessors(): don't [...] adds 90a92f8b4d7 [NFCI][Utils/Local] removeUnreachableBlocks(): cleanup supp [...] adds 81afeacd379 [SimplifyCFGPass] mergeEmptyReturnBlocks(): skip blocks sch [...] adds ec8a6c11db4 [SimplifyCFGPass] iterativelySimplifyCFG(): support lazy Do [...] adds 5ccff5aaa68 ADT: Fix pointer comparison UB in SmallVector adds 7470017f247 [RISCV] Define the vfclass RVV intrinsics adds f635bcd1610 NFC: Pre-commit test: -Wpointer-sign with plain char to [un [...] adds c6ffe4d76fb [clang] Fix message text for `-Wpointer-sign` to account fo [...] adds eefd420e003 [github] Move repo lockdown config into llvm-project repo adds f75f391fc68 [MLIR][Linalg] Refactor transforms to use linalg::getDynOpe [...] adds f9902514fe5 [MC] Make getEHFrameSection const like every other getter (NFC) adds ef50c07b1fa [JITLink] Add a new PostAllocationPasses list. adds 70474dfebcd [VE][compiler-rt] Add VE as a target of crt adds 9f8b25769ef [WebAssembly] Ensure terminate pads are a single BB adds 905623b64df [NFC][LICM] Minor improvements to debug output adds 0871d6d5164 [OpenMP] Move memory manager to plugin and make it a common [...] adds 89e8eb946d8 [llvm] Use llvm::find_if (NFC) adds 8590a3e3adc [llvm] Use *Set::contains (NFC) adds e5b4dbab041 [llvm] Simplify string comparisons (NFC) adds b1c304c4946 [CodeGen] Try to make the print of memory operand alignment [...] adds edde2eb1d20 Add unconditional logging to debugserver for launch/attach [...] adds f9ef3a60037 [SelectionDAG] Make isConstantIntBuildVectorOrConstantInt a [...] adds b688c5875d0 [CMake] Split the target side of runtimes build adds df74c001fa5 [DAGCombiner] Replace static helper function isConstantFPBu [...] adds 93ad0edf674 [ELF] Drop .rel[a].debug_gnu_pub{names,types} for --gdb-ind [...] adds 1cc5235712f [WebAssembly] Misc. refactoring in CFGStackify (NFC) adds 215ed9b33cc Adapt CastExpr::getSubExprAsWritten to ConstantExpr adds c8a914db5c6 [LiveDebugValues] Fix comparison operator in VarLocBasedImpl adds 6a195491b60 [AMDGPU] Fix failing assert with scratch ST mode adds 7ab803095ae [clang][cli] Remove -f[no-]trapping-math from -cc1 command line adds bd30a796fc4 [mlir] use built-in vector types instead of LLVM dialect ty [...] adds e8287cb2b29 [Test] Add failing test for PR48725 adds c93b9559390 [WebAssembly] Remove more unnecessary brs in CFGStackify adds 9ec72cfc61a [llvm-readef/obj] - Change the design structure of ELF dump [...] adds 1e11402aa8e [llvm-readobj] - Add 'override' to fix build bots. adds cc91efdabee [llvm-readobj] - An attempt to fix BB. adds 4744478b99f [mlir][openmp][NFCI] Rename `continuationIP` to `continuati [...] adds 891b4873c12 [llvm-readobj] - One more attempt to fix BB. adds c1e08f0073e [clang][AST] Get rid of an alignment hack in DeclObjC.h [NFCI] adds f264f9ad7df [SlotIndexes] Fix and simplify basic block splitting adds 794e3d94d5a [AMDGPU][GlobalISel] Remove some duplicate RUN lines adds 60df7c08b1f [obj2yaml,yaml2obj] - Fix issues with creating/dumping grou [...] adds c15a57cc1a8 [obj2yaml] - Don't crash when an object has an empty symbol table. adds a06aa1037c1 Revert "[Test] Add failing test for PR48725" adds ace516fb33d Change the LLVM_ATTRIBUTE_DEPRECATED macro to use C++14 attribute. adds 09db958e37b [RISCV] Improve scalable-vector shift tests (NFC) adds a5212b5c91c [X86][SSE] combineSubToSubus - remove SSE2 early-out. adds c4944a6f53f [Fixed Point] Add codegen for conversion between fixed-poin [...] adds 7e44208115b [X86][SSE] combineSubToSubus - add v16i32 handling on pre-A [...] adds 2ed914cb7e9 [X86][SSE] getFauxShuffleMask - handle PACKSS(SRAI(),SRAI() [...] adds 80f07854886 [mlir][Linalg] NFC - Refactor fusion APIs adds a6759477129 [TableGen] Improve error message for semicolon after braced body. adds 0bd9a136911 [mlir][openacc] Use TableGen information for default enum adds 07605ea1f3c [X86] Improved lowering for saturating float to int. adds 24faa87075a [VE] Update VELIntrinsic tests adds 2f7ec77e3cd [mlir][spirv] NFC: place ops in the proper file for their c [...] adds dd07d60ec33 [SLP] Add test case showing a bug when dealing with padded types adds 3f7b4ce9606 [PowerPC] Add support for embedded devices with EFPU2 adds 4086072f8a9 Reland "[mlir][linalg] Support parsing attributes in named [...] adds 4fa01f72de6 [mlir][CAPI] Fix inline function declaration adds 9667d15e749 [mlir] Fix for LIT tests adds 1f1250151f2 [libc++] [C++2b] [P1048] Add is_scoped_enum and is_scoped_enum_v. adds 8349fa0fdd3 [mlir][spirv] NFC: split deserialization into multiple sour [...] adds 93b54b7c673 [PowerPC][NFCI] PassSubtarget to ASMWriter adds 67a339e9683 [MLIR] Disallow `sym_visibility`, `sym_name` and `type` att [...] adds 85aaa3e310c [X86] Regenerate sdiv_fix_sat.ll + udiv_fix_sat.ll tests adds dd955771240 Fix typo in diagnostic message adds a4931d4fe38 [AMDGPU] Regenerate umax crash test adds 3d9c51d111d [SVE][NFC] Regenerate a few CodeGen tests adds 348471575d9 Add -ansi option to CompileOnly group adds b117d17d264 [doc] Place sha256 in lld/README.md into backticks adds ef3800e8216 Return false from __has_declspec_attribute() if not explici [...] adds 5aefc8dc4d1 [llvm] [cmake] Remove obsolete /usr/local hack for *BSD adds bb9ebf6baf7 [Tests] Add tests for new InstCombine OR transformation, NFC adds 0529946b5ba [instCombine] Add (A ^ B) | ~(A | B) -> ~(A & B) adds 6f4d4607620 [Flang][openmp][openacc] Extend CheckNoBranching to handle [...] adds 03c8d6a0c4b [LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve [...] adds 4718ec01669 [clangd] Avoid recursion in TargetFinder::add() adds f748e922955 [NewPM] Run non-trivial loop unswitching under -O2/3/s/z adds a14040bd4d9 [RISCV] Use vmerge.vim for llvm.riscv.vfmerge with a 0.0 sc [...] adds 08d4a50467e [FunctionAttrs] Precommit tests for willreturn inference. adds eef4bdbb34d [libc++] Add a missing `<_Compare>` template argument. adds 79f99ba65d9 [libcxx] Port to OpenBSD adds 7ecad2e4ced [InstSimplify] Don't fold gep p, -p to null adds bdd1ad5e5c5 [OpenMP] Fixed include directories for OpenMP when building [...] adds 33e2494bea6 [libomptarget][amdgpu][nfc] Fix build on centos adds e5f51fdd650 [clang][aarch64] Precondition isHomogeneousAggregate on isC [...] adds 6cd44b204c6 [FunctionAttrs] Derive willreturn for fns with readonly` & [...] adds e53bbd99516 [IR] move nomerge attribute from function declaration/defin [...] adds 922a5b89411 [clang-tidy] Add test for Transformer-based checks with dia [...] adds d49974f9c98 [InstCombine] Regenerate test checks (NFC) adds 9f61fbd75ae [LV] Relax assumption that LCSSA implies single entry adds f706486eaf0 Fix for crash in __builtin_return_address in template context. adds fb063c933f0 [InstCombine] Duplicate tests for logical and/or (NFC) adds caafdf07bbc [LV] Weaken spuriously strong assert in LoopVersioning adds 46507a96fc1 [SLP] reduce code duplication while matching reductions; NFC adds 554be30a428 [SLP] reduce code duplication in processing reductions; NFC adds 92fb5c49e8a [SLP] rename variable to improve readability; NFC adds 9e7895a8682 [SLP] reduce code duplication while processing reductions; NFC adds 7583ae48a3c [RISCV] Add double test cases to vfmerge-rv32.ll. NFC adds e15f3ddcae6 [InstCombine] Add tests for logical and/or poison implicati [...] adds 71ed4b6ce57 [RISCV] Legalize select when Zbt extension available adds 23390e7a131 [InstCombine] Handle logical and/or in assume optimization adds 7fd18508134 [mlir] Update LLVM dialect type documentation adds 2a49b7c64a3 [Inliner] Change inline remark format and update ReplayInli [...] adds 68ff52ffead [OpenMP] Fixed the link error that cannot find static data member adds d1fa7afc7ae [AArch64] [Windows] Properly add :lo12: reloc specifiers wh [...] adds 02f1d28ed6b [libcxx] Avoid overflows in the windows __libcpp_steady_clo [...] adds 01f1273fe2f [OpenMP] Fixed a typo in openmp/CMakeLists.txt adds 3d397091591 AMDGPU: Remove wrapper only call limitation adds cf45731f0ea [Driver] Fix assertion failure when -fprofile-generate -fcs [...] adds 55f2eeebc96 [NFC] Disallow unused prefixes in MC/AMDGPU adds a7130d85e4b [ADT][NFC] Use empty base optimisation in BumpPtrAllocatorImpl adds 1730b0f66ad [RISCV] Remove '.mask' from vcompress intrinsic name. NFC adds 6166b91e837 [ELF][NFCI] small cleanup to OutputSections.h adds 175288a1afe Add sample-profile-suffix-elision-policy attribute with -fu [...] adds ddcb0aae8b0 [MIPatternMatch] Add matcher for G_PTR_ADD adds 8f5ec459375 [Sanitizer][Darwin] Fix test for macOS 11+ point releases adds 585612355cd [NFC] Disallow unused prefixes under MC/AMDGPU adds 0d88d7d82bc Delete unused function (was breaking the -Werror build) adds 314e29ed2b7 [AMDGPU] Add _e64 suffix to VOP3 Insts adds 04edcc02638 [libc] add isascii and toascii implementations adds 0c8466c0015 [libc][NFC] Use more specific comparison macros in LdExpTest.h. adds 76643c48cdd [LangRef] State that a nocapture pointer cannot be returned adds 25eb7b08ba7 [DAGCombiner] Fold BRCOND(FREEZE(COND)) to BRCOND(COND) adds 82655c15145 [MSan] Tweak CopyOrigin adds 25b3921f2fc [gn build] (manually) port 79f99ba65d96 adds c0f3ea8a08c [mlir][Python] Add checking process before create an Affine [...] adds 055644cc459 [X86][AMX] Prohibit pointer cast on load. adds 5c7dcd7aead [Coroutine] Update promise object's final layout index adds 6529d7c5a45 [PDB] Defer relocating .debug$S until commit time and paral [...] adds 6f0f0220380 [OpenMP] Update allocator trait key/value definitions adds acea470c167 [gn build] Reorganize libcxx/include/BUILD.gn a bit adds 0066a09579c [libc++] Give extern templates default visibility on gcc adds bba3a82b56c [OpenMP] Use persistent memory for omp_large_cap_mem adds 914e2f5a02f [NFC] Use generic name for scalable vector stack ID. adds e5553b9a6ab [dsymutil] Warn on timestmap mismatch between object file a [...] adds cd8a80de960 [Orc] Add a unit test for asynchronous definition generation. adds f454c9f102a [InlineSpiller] Re-tie operands if folding failed adds 8a47d875b07 [dsymutil] Copy eh_frame content into the dSYM companion file. adds 84e0b14a0a4 [libomptarget][nvptx] Include omp_data.cu in bitcode deviceRTL adds ad735badb69 [dsymutil] s/dwarfdump/llvm-dwarfdump/ in test adds 35e4998f0c9 [dsymutil] Fix spurious space in REQUIRES: line adds 790c75c1637 [AMDGPU] Add SI_EARLY_TERMINATE_SCC0 for early terminating shader adds 157efd84abf [Statepoint Lowering] Add an option to allow use gc values [...] adds fba9805ba34 [Verifier] Extend statepoint verifier to cover more constants adds 12fc9ca3a40 [llvm] Remove redundant string initialization (NFC) adds 2c2d489b78c [CodeGen] Remove unused function isRegLiveInExitBlocks (NFC) adds 8a20e2b3d3e [llvm] Use Optional::getValueOr (NFC) adds f1d5cbbdee5 [dsymutil] Add preliminary support for DWARF 5. adds 0b99385e151 [MSan] Partially revert some changes from D94552 adds 8f8c207b8f2 [Verifier] Add tied-ness verification to statepoint intsruction adds 3aeb30d1a68 [ARM] Additional tests for different interleaving patterns. NFC adds 141906fa149 [llvm-readelf/obj] - Add support of multiple SHT_SYMTAB_SHN [...] adds c29ca8551af [ARM] Update isVMOVNOriginalMask to handle single input shu [...] adds 6d3098e7ff9 [obj2yaml,yaml2obj] - Refine how we set/dump the sh_entsize field. adds cbea6737d51 [clang][driver] Restore the original help text for `-I` adds f638c2eb4ee [LTO] Replace anonymous namespace with static functions (NFC). adds 4cd48535eca [NFC][InstructionCost] Use InstructionCost in Transforms/Sc [...] adds 3122c66aee7 [AArch64][SVE] Remove chains of unnecessary SVE reinterpret [...] adds 0f59d099571 [X86][AVX] combineVectorSignBitsTruncation - limit AVX512 t [...] adds ad85e396706 [SVE] Add ISel pattern for addvl adds 1854594b80b Hwasan InitPrctl check for error using internal_iserror adds ceb9379a90f [ADT] Fix join_impl using the wrong size when calculating t [...] adds ada96fa6217 [LTO] Add test to ensure objc-arc-contract is executed. adds af1bb4bc823 Fix build errors after ceb9379a9 adds c6e341c8995 Revert "[dsymutil] Warn on timestmap mismatch between objec [...] adds 2170e0ee60d [SVE][CodeGen] CTLZ, CTTZ & CTPOP operations (predicates) adds f8cece18630 [ValueTracking] Fix one s/dyn_cast/dyn_cast_or_null/ adds 704831fe1f1 Revert "Hwasan InitPrctl check for error using internal_iserror" adds d307d892ade [Tests] Added test for memcpy loop idiom recognization adds 0a0ee7f5a5a [X86] canonicalizeShuffleMaskWithHorizOp - minor refactor t [...] adds ab577807165 [libc] Refresh benchmark progress bar when needed. adds 7c77b536efd [OpenCL] Improve OpenCL operator tests adds b7b1e8c37a9 [X86] Add tests for rv_marker lowering. adds 3bc7555ffac [mlir][linalg] Use attributes in named ops' indexing maps adds 90164ba957a [clangd] Split out a base class for delegating GlobalCompil [...] adds dda60035e9f [AArch64] Attempt to sink mul operands adds d55d592a921 GlobalISel: Do not set observer of MachineIRBuilder in Lega [...] adds 350c0552c66 [NFC][RISCV] Add double type in RISC-V V CodeGen test cases [...] adds 4e8e888905a [AArch64][GlobalISel] Add support for FCONSTANT of FP128 type adds 07b6aeb5685 [lld][WebAssembly] Fix for TLS + --relocatable adds f0abe2aeaca [Frontend] Add pragma align natural and sort out pragma pac [...] adds a957634942a [OpenMP] Add documentation for error messages and release notes adds 4fe17ada55a [OpenMP] Fix hierarchical barrier adds 66d5994bd38 [clangd] Explicitly avoid background-indexing the same file twice. adds 466acd69486 [clangd] Avoid reallocating buffers for each message read: adds e433ca28ec9 [SLP] add reduction test for FMF; NFC adds 17863614da1 [InstCombine] Fold select -> and/or using impliesPoison adds a4f38668823 [clangd] Remove "decision-forest-base" experimental flag. adds 0bbc6a6bb64 [clangd] Remove some old CodeCompletion options that are ne [...] adds 05b1a15f703 [IROutliner] Adapting to hoisted bitcasts in CodeExtractor adds 48d2068fb73 [dsymutil] Warn on timestmap mismatch between object file a [...] adds cbbfc825861 [X86][SSE] canonicalizeShuffleMaskWithHorizOp - simplify sh [...] adds efb6e45d2be [X86][AVX] Add test for another 'reverse HADD' pattern ment [...] adds 993c488ed2b [DAG] visitVECTOR_SHUFFLE - use all_of to check for all-und [...] adds 60fda8ebb6d [ARM] Add a pass that re-arranges blocks when there is a ba [...] adds 14f322f074b [gn build] Port 60fda8ebb6d adds a50bb84ec0c [flang] Fix classification of shape inquiries in specificat [...] adds a2e6506c47b [Hexagon] Improve legalizing of ISD::SETCC result adds 123674a8167 [SLP] simplify type check for reductions adds 166e5c335cb [flang] Do not create HostAssoc symbols in derived type scopes adds b3154d11bc6 [CSSPGO][llvm-profgen] Pseudo probe decoding and disassembling adds 414930b91bf [CSSPGO][llvm-profgen] Refactor to unify hashable interface [...] adds c681400b25a [CSSPGO][llvm-profgen] Virtual unwinding with pseudo probe adds 33a8466531e [NFC] fix missing SectionName declaration adds 3bd620d4504 [mlir] Correct 2 places that result in corrupted conversion [...] adds e7a371f9fd0 [LLD][COFF] Avoid std::vector resizes during type merging adds bb72adcaee7 [NFC] Use correct ssa.copy spelling when referring to the i [...] adds f4f158b2f89 [mlir][sparse] add vectorization strategies to sparse compiler adds 01c3135850d [LTO] Add test for freestanding LTO option. adds 18278ff1aac [flang] Fix accessibility of USEd name in .mod file adds 4cfccd51335 [libc][NFC] add macro for fuchsia to switch test backend to zxtest adds fb98a1be436 Fix the warnings on unused variables (NFC) adds f711cb9a8ad [FuncAttrs] Add additional willreturn tests (NFC) adds 6077d55381a [DSE] Add tests with stores of existing values. adds ea8034ec35a [libc][NFC] change isblank and iscntrl from implicit casting adds 74a42aedfe1 [test] Add Clang side tests for -fdebug-info-for-profiling adds 35debdfcaca [NFC] Fix build break by a initializer list converting error adds 82c4153e66f Revert "[AsmParser] make .ascii support spaces as separators" adds 39e6d242378 [NewPM] Only non-trivially loop unswitch at -O3 and for non [...] adds 7ec8f436598 [SPARC] Fix fp128 load/stores adds 854f0984f0b Fix llvm::Optional build breaks in MSVC using std::is_trivi [...] adds 86341247c4a [NFC] Rename ThinLTOPhase to ThinOrFullLTOPhase and move it [...] adds ddd03842c34 [SystemZ] Clear Available set in SystemZPostRASchedStrateg [...] adds c82deed6764 [libunwind] Unwind through aarch64/Linux sigreturn frame adds 3de92ca78cd [flang] Add tests for procedure arguments with implicit interfaces adds dfc1901d513 [RISCV] Custom lower ISD::VSCALE. adds cd4c55c9740 Fix grammar in diagnostic for wrong arity in a structured binding. adds 336ab2d51df [Support] On Windows, take the affinity mask into account adds ff40fb07ad6 [PowerPC] Try to fold sqrt/sdiv test results with the branch. adds eec856848cc Revert "[Support] On Windows, take the affinity mask into account" adds 9abac603090 ADT: Fix reference invalidation in SmallVector::push_back a [...] adds b196dc66072 [NFC] Remove unused entry in PassRegistry.def adds 56d1ffb927d Revert "ADT: Fix reference invalidation in SmallVector::pus [...] adds 5c1c39e8d80 [llvm] Use *Set::contains (NFC) adds 125ea20d55c [llvm] Use llvm::stable_sort (NFC) adds 4c1617dac8f [llvm] Use std::any_of (NFC) adds 49142991a68 Reapply "ADT: Fix reference invalidation in SmallVector::pu [...] adds 3043e5a5c33 ADT: Fix reference invalidation in N-element SmallVector::a [...] adds 752fafda3db [NFC] Fix -Wsometimes-uninitialized adds 260a856c2ab ADT: Fix reference invalidation in SmallVector::resize adds c224a834583 ADT: Reduce code duplication in SmallVector::resize by usin [...] adds 3f98b66f23f ADT: Reduce code duplication in SmallVector by reusing rese [...] adds 53b34601abf [Driver] -gsplit-dwarf: Produce .dwo regardless of -gN for [...] adds 6ed3083a965 ADT: Reduce code duplication in SmallVector by calling rese [...] adds ff5e8964255 Fix unused variable in CoroFrame.cpp when building Release [...] adds 885eae9d85d Add func call so we don't instruction-step into the builtin_trap adds 7ad54d19387 [lldb][wasm] Parse DWO section names adds 2bbf724feea Implement vAttachWait in lldb-server adds ed205f63b4a [mlir] Update doc to omit the usage of LLVMIntegerType adds 4b284b9ca80 [lldb] Fix TestPlatformProcessConnect.py adds 259936f4910 [NFC][AsmPrinter] Windows warning: Use explicit cast adds 2b1e25befef [AArch64] Adding ACLE intrinsics for the LS64 extension adds 4bb11b3eafb [LTO] Expose opt() in LTOBackend (NFC). adds 53e3b81faaf [lld][WebAssembly] Add support for handling table symbols adds d58512b2e31 [SLP] Don't vectorize stores of non-packed types (like i1, i2) adds 17f8c458de6 [clang] Use SourceLocations in unions [NFCI] adds af8d27a7a82 [DAG] visitVECTOR_SHUFFLE - pull out shuffle merging code i [...] adds 8f1d7f3753c [X86] Improve sum-of-reductions v4f32 test coverage adds a997a1d7fbe [lldb/test] Ensure launched processes are ready to be attached adds 7c30c05ff71 [DAG] visitVECTOR_SHUFFLE - MergeInnerShuffle - reset shuff [...] adds 2e25be0b613 [clangd] Add main file macros into the main-file index. adds 19297a41711 Change XCore code owner. adds 3bccd87a588 [clang][cli] NFC: Remove SSPBufferSize assignment adds fa2fe9608c1 [clang][cli] Port more CodeGenOptions to marshalling infras [...] adds 6abbba3fca9 Revert "Fix llvm::Optional build breaks in MSVC using std:: [...] adds 176f5e95e1a [clang-tidy] Use DenseSet<SourceLocation> in UpgradeDuratio [...] adds a1bbd1ef1db [flang][driver] Unify f18_version.h.in and Version.inc.in adds c23e34e606b [InferFunctionAttrs] Improve CHECK variable names (NFC). adds a1cba5b7a1f [SelectionDAG] Make use of KnownBits::commonBits. NFC. adds 517196e5691 [Analysis,CodeGen] Make use of KnownBits::makeConstant. NFC. adds 90b310f6caf [Support] Simplify KnownBits::icmp helpers. NFC. adds e8622d27c0e [Support] Add KnownBits::sextInReg exhaustive tests adds 332e220ef42 [docs] Update DebuggingJITedCode page after fix in LLDB adds 0b46f19a9ec [Support] Ensure KnownBits::sextInReg can handle the src == [...] adds 3e41ab18db2 [flang] Fix dangling pointer in LabelEnforce adds adb77a74569 [OpenCL] Improve online documentation. adds 6b9fa8a50d0 [mlir][linalg] Add docstring support for named op spec adds c0939fddf80 [Support] Simplify KnownBits::sextInReg implementation. adds a022be62538 [TableGen] Enhance !cast<string> to handle bit and bits types. adds dbaa6a1858a Revert "[AArch64] Attempt to sink mul operands" adds d0dbb0468c2 [Support] Remove redundant sign bit tests from KnownBits::g [...] adds 0a59647ee40 [SystemZ] misched-cutoff tests can only be tested on non-ND [...] adds 17fb21f875f [clangd] Remove another option that was effectively always [...] adds 7c9c2a2ea5e Revert "[RISCV] Legalize select when Zbt extension available" adds 0afdbb4d2de [flang][driver] Use __FLANG_VERISION__ in f18.cpp (nfc) adds e21bf875c0f [NFC] Disallow unused prefixes under MC/ARM adds 2f395b7092b [clangd] Make AST-based signals available to runWithPreamble. adds 8b09cf7956d [clangd] Trivial: Documentation fix in ASTSignals. adds b4e083b0ef7 [gn build] Port 2f395b7092bd adds 4864d9f7e91 [flang] Fix some module file issues exposed by Whizard adds 35c8a6cbf5f [NFC] Disallow unused prefixes under MC/AArch64 adds a03ffa98503 [NewPM] Fix placement of LoopFlatten adds b99782cf785 [X86][AVX] Adjust unsigned saturation downconvert negative test adds 5d165f0b893 [libomptarget][amdgpu] Fix kernel launch tracing to match p [...] adds 868da2ea939 [SelectionDAG] Remove an early-out from computeKnownBits fo [...] adds 85dfcaadc5f [LLDB] MinidumpParser: Prefer executable module even at hig [...] adds be40c12040a [HIP] Add signbit(long double) decl adds 6ebeba88f51 Support emptiness checks for unbounded FlatAffineConstraints. adds 763c1f99334 [OpenMP] Drop the static library libomptarget-nvptx adds 4fffbc150cc [clang][MSVC] Fix missing MSInheritanceAttr in template spe [...] adds 202d359753d [X86] Add the FSRM feature (Fast Short Rep Mov) to Zen3. adds 64e9e9aeee0 [OpenMP] Dropped unnecessary define when compiling deviceRT [...] adds a8520f6970f [GWP-ASan] Minor refactor of optional components. adds ca98baa0425 [openacc] Rename generated file from ACC.cpp.inc to ACC.inc [...] adds 9e53c94d8dd [NFC] Update test to not check for 'opaque' in the file name. adds 1d973b7ded1 [MLIR][TOSA] First lowerings from Tosa to Linalg adds d8113cda782 Add newline to terminate debug message (NFC) adds a3904cc77f1 [BasicAA] Handle recursive queries more efficiently adds 00a61b327dd [mlir][ODS] Add new RangedTypesMatchWith operation predicate adds 93592b726c7 [mlir][OpFormatGen] Format enum attribute cases as keywords [...] adds e3b9af92a48 [Driver] -gsplit-dwarf: Produce .dwo regardless of -gN for [...] adds 387d3c24792 [RISCV] Merge Utils library into MCTargetDesc adds c8fb6ee3415 [mlir][PatternRewriter] Add a new hook to selectively repla [...] adds 5cf2696317a [mlir] Remove TosaToLinalg dependency on all Passes adds a71877edfbb [clang] Do not crash when CXXRecordDecl has a non-CXXRecord [...] adds e2d7d3cb0ea [mlir][docs] Bring bufferization docs up to date. adds 0f588ac03e1 [PowerPC] Only use some extend mne if assembler is modern enough adds 0975604cc01 [gn build] (manually) port 387d3c24792f adds e7228062b2b [libc] Use #undef isascii in specific header adds f85b1531666 Add -fexceptions to test as it uses them and fails on platf [...] adds b894a9fb237 [RISCV] Optimize select_cc after fp compare expansion adds 4fcb25583c3 Re-land [Support] On Windows, take the affinity mask into account adds 5b42fd8dd4e [LTO] Test format fix (NFC) adds 8a53a7375a8 [RISCV][NFC] Regenerate Calling Convention Tests adds a55a0a3056b [mlir] Remove over specified memory effects adds 4183999e0fe [clangd] Reduce logspam for CDB scanning adds 722ae10907e [mlir][Linalg] Add canonicalization to remove no-op linalg [...] adds b21905dfe37 [SLP] remove unnecessary state in matching reductions adds 547b032ccc8 [OpenMP] Remove omptarget-nvptx from deps as it is no longe [...] adds 774c9c6ef3a [mlir][Linalg] Add canonicalization of linalg op -> dim op. adds 42444d0cf0c [mlir][Linalg] NFC: Verify tiling on linalg.generic operati [...] adds 6e7094c14b2 [libomptarget][nvptx][nfc] Move target_impl functions out o [...] adds d6acf3c2012 [flang] Fix use-associated procedure in generic adds 036bc798f2a [AArch64][GlobalISel] Assign FPR banks to loads which are u [...] adds 9dfeec85300 Reland "[AsmParser] make .ascii support spaces as separators" adds 214387c2c69 [libomptarget][nvptx] Reduce calls to cuda header adds 1fabe6e5191 [libTooling] Change `addInclude` to use expansion locs. adds 8f283cafddf [AArch64][GlobalISel] Add selection support for fpr bank so [...] adds 2423ec58376 [libc] Add memmove implementation. adds 9bcc0d1040d [CodeGen, Transforms] Use llvm::sort (NFC) adds 2efcbe24a75 [llvm] Use llvm::drop_begin (NFC) adds 7dc3575ef2d [llvm] Remove redundant return and continue statements (NFC) adds 39665d9aabb Add Semantic check for Flang OpenMP 4.5 - 2.7.1 Do Loop re [...] adds 5508516b066 [mlir][sparse] retry sparse-only for cyclic iteration graphs adds c495dfe0268 [clang][cli] NFC: Decrease the scope of ParseLangArgs parameters adds 1a49944b59d [clang][cli] NFC: Decrease the scope of ParseCodeGenArgs pa [...] adds b6575bfd0ee [clang][cli] Specify KeyPath prefixes via TableGen classes adds b54337070b1 [AArch64] Add Fujitsu A64FX scheduling model adds 38dfce706f7 [WebAssembly] Add support for table linking to wasm-ld adds 33be50daa9c Revert "Reapply "ADT: Fix reference invalidation in SmallVe [...] adds 168be420830 [Clang] Mutate long-double math builtins into f128 under IEEE-quad adds 1185d3f43d2 [llvm-readobj] - Fix the compilation with GCC < 7.0. adds 89e84dec187 [AArch64][GlobalISel] Fix fallbacks introduced for G_SITOFP [...] adds 78036360573 [libcxx testing] Fix UB in tests for std::lock_guard adds 104a9f99cca [Debuginfo][DW_OP_implicit_pointer] (1/7) Support for DW_OP [...] adds bfb8f45ef3f [llvm-nm] - Move MachO specific logic out from the dumpSymb [...] adds a10300a2b27 [libc] Allow customization of memcpy via flags. adds 021ea78a97e [llvm-nm] - Simplify the code in dumpSymbolNamesFromObject. NFC. adds 3676ef10538 [ARM][GISel] Treat calls as variadic even if only fixed arg [...] adds d9afe8588e4 [yaml2obj/obj2yaml] - Refine handling of SHT_GNU_verdef sections. adds 45ef053bd70 [llvm-readobj][test] - Remove excessive YAML fields from tests. adds 9cc221b99be [clangd] exclude symbols from document outline which do not [...] adds 4fd77668b2c [LLDB] Add per-thread register infos shared pointer in gdb-remote adds b9993fcbf53 DynamicRegisterInfo calculate offsets in separate function adds 141e45b99ca [RISCV] Optimize Branch Comparisons adds 2b8db40c921 [SVE] Restrict the usage of REINTERPRET_CAST. adds a5eb9df1e3b [Orc][NFC] Turn LLJIT member ObjTransformLayer into unique_ptr adds cf905274c6f [Orc] Allow LLJITBuilder's CreateObjectLinkingLayer to retu [...] adds 619eb147759 [NFC][RISCV] Remove useless code in RISCVRegisterInfo.td. adds bab121a1b66 [lldb][docs] Use sphinx instead of epydoc to generate LLDB' [...] adds 6edc3fe598a [Orc] Fix OrcV2Examples after D94690 adds 9d2053f61aa Revert "[lldb][docs] Use sphinx instead of epydoc to genera [...] adds aeaeb9e6bdc [clangd] Make ExpandAutoType not available on template params. adds c77c3d1d18c [clangd] Set correct CWD when using compile_flags.txt adds 4017c6fe7f1 [lldb][docs] Translate ASCII art to restructured text formatting adds 1dfd5c9ad8c [X86][AVX] combineHorizOpWithShuffle - support target shuff [...] adds e9f1ed2306b [WebAssembly] MC layer writes table symbols to object files adds 5e4480b6c0f [ARM] Don't run the block placement pass at O0 adds 0acc260b574 [mlir][linalg] Support generating builders for named op attributes adds 061d1520858 [SVE] Fix unused variable. adds d1862a16310 [OpenCL][Docs] Fixed malformed table in OpenCLSupport adds 791634b999e [clang][cli] Parse & generate options necessary for LangOpt [...] adds 5183a13d378 [X86] Add umin knownbits/demandedbits ult test for D94532 adds 17d0fb7f574 Set option default for enabling memory ssa for new pass man [...] adds 46aa3c6c331 [DAG] visitVECTOR_SHUFFLE - MergeInnerShuffle - improve shu [...] adds cf0173de69a [mlir] Add better support for f80 and f128 adds 5bf47e142b6 [libc] CopyAlignedBlocks can now specify alignment on top o [...] adds bf1aa5db5c7 [RISCV][NFC] Fix order of parameters in cmov ge/le tests adds 38326293304 [clang][cli] NFC: Add PIE parsing for precompiled input and IR adds a7dcd3aeb0f [clang][cli] NFC: Parse some LangOpts after the defaults are set adds 1744f4c6764 [clang][cli] NFC: Promote ParseLangArgs and ParseCodeGenArg [...] adds 1a497ae9b83 [ARM][Block placement] Check the predecessor exists before [...] adds be69e66b1cd [X86][SSE] Attempt to fold shuffle(binop(),binop()) -> bino [...] adds 1e1a011b09d [flang] Disallow INTENT attribute on procedure dummy arguments adds 4c5066b0789 [TargetLowering] Don't speculatively call ComputeNumSignBits. NFC adds b6e06a740c2 [flang][driver] Copy test file into a temp dir when testing (nfc) adds d5047d762f3 [clangd] Update CC Ranking model with better sampling. adds bc84f89c71a [OpenCL][Docs] Fixed cross-section reference in OpenCLSupport adds 6227069bdce [DebugInfo][CodeView] Change in line tables only mode to em [...] adds a0770f9e4e9 [ARM] Constant tripcount tail predication loop tests. NFC adds f5abf0bd485 [ARM] Tail predication with constant loop bounds adds cc90d41945f [MIPatternMatch] Add m_OneNonDBGUse adds d0cb0d30a43 [mlir] Add Complex dialect. adds 86e604c4d68 [RISCV] Add implementation of targetShrinkDemandedConstant [...] adds 84de4faf4ca GetMacosAlignedVersion() fails if sysctl is not setup adds 4f24d0dd538 Fix libc++ clang-cl build, swap attribute order adds a9e939760c6 [CodeGen] Removes unwanted optimisation for TargetConstantFP adds 1f21de535d3 [SLP] remove unused reduction functions; NFC adds a1be47b4771 [CodeView][DebugInfo] Add test case to show that linkage na [...] adds 64db296e5a8 Revert "[BasicAA] Handle recursive queries more efficiently" adds 61ec2280308 [NFC][SimplifyCFG] Add testcase showing that we fail to pre [...] adds b81f75fa791 [Utils] splitBlockBefore() always operates on DomTreeUpdate [...] adds c845c724c23 [Utils][SimplifyCFG] Port SplitBlock() to DomTreeUpdater adds 286cf6cb029 [SimplifyCFG] Port SplitBlockAndInsertIfThen() to DomTreeUpdater adds c6654a4cdab [SimplifyCFG][BasicBlockUtils] Port SplitBlockPredecessors( [...] adds a14c36fe27f [SimplifyCFG] switchToSelect(): don't forget to insert DomT [...] adds 6a42cbf6d21 [GWP-ASan] Add inbuilt options parser. adds 98c89ccfbd7 [MSVC] Don't add -nostdinc++ -isystem to runtimes builds adds 4a47da2cf44 [Sema] turns -Wfree-nonheap-object on by default adds ed0fd567ebd BreakCriticalEdges: do not split the critical edge from a C [...] adds d7bc3b7ce23 [mlir][Linalg] Add missing check to canonicalization of Gen [...] adds 10ac9b29a4c Skip 'g' packet tests when running on darwin; debugserver d [...] adds ceb3cdccd0f [SLP] remove dead code in reduction matching; NFC adds ceaf0110ff5 Revert "Revert "ADT: Fix reference invalidation in SmallVec [...] adds aa8a2d8a3da [AArch64][GlobalISel] Select immediate fcmp if the zero is [...] adds 76f5c5a7b05 [ADT][Support] Fix C4146 error from MSVC adds a1500105ee6 [SimplifyCFG] Optimize CFG when null is passed to a functio [...] adds e65b9b04cde Revert "[WebAssembly] MC layer writes table symbols to obje [...] adds 187d771d27e Revert "[WebAssembly] Add support for table linking to wasm-ld" adds d302398ff05 hwasan: Update register-dump-read.c test to reserve x23 ins [...] adds aa3d4d99395 [NFC] Disallow unused prefixes under MC/RISCV adds 1bd083b5d6d [flang] Create names to allow access to inaccessible specifics adds 3afbfb4145b [mlir][NFC] Move helper substWithMin into Affine utils adds 2a27a9819a1 [mlir][AsmPrinter] Properly escape strings when printing locations adds fd2083d73c2 [mlir] Fixing potential build break in my previous commit adds 999f5da6b30 [debugserver] Fix inverted if block that resulted in us usi [...] adds e8049dc3c8a [NewPM][Inliner] Move the 'always inliner' case in the same [...] No new revisions were added by this update. Summary of changes: .github/lockdown.yml | 8 + .../abseil/UpgradeDurationConversionsCheck.cpp | 4 +- .../abseil/UpgradeDurationConversionsCheck.h | 5 +- clang-tools-extra/clangd/AST.cpp | 1 + clang-tools-extra/clangd/ASTSignals.cpp | 42 + clang-tools-extra/clangd/ASTSignals.h | 39 + clang-tools-extra/clangd/CMakeLists.txt | 1 + clang-tools-extra/clangd/ClangdServer.cpp | 14 +- clang-tools-extra/clangd/CodeComplete.cpp | 9 +- clang-tools-extra/clangd/CodeComplete.h | 21 - clang-tools-extra/clangd/CollectMacros.cpp | 8 +- clang-tools-extra/clangd/CollectMacros.h | 18 +- clang-tools-extra/clangd/FindSymbols.cpp | 4 + clang-tools-extra/clangd/FindTarget.cpp | 10 + clang-tools-extra/clangd/FindTarget.h | 3 + .../clangd/GlobalCompilationDatabase.cpp | 57 +- .../clangd/GlobalCompilationDatabase.h | 26 +- clang-tools-extra/clangd/JSONTransport.cpp | 56 +- clang-tools-extra/clangd/Quality.cpp | 24 +- clang-tools-extra/clangd/QueryDriverDatabase.cpp | 21 +- clang-tools-extra/clangd/SemanticHighlighting.cpp | 4 +- clang-tools-extra/clangd/TUScheduler.cpp | 73 +- clang-tools-extra/clangd/TUScheduler.h | 3 + clang-tools-extra/clangd/XRefs.cpp | 2 +- clang-tools-extra/clangd/index/Background.cpp | 7 +- clang-tools-extra/clangd/index/Background.h | 4 + clang-tools-extra/clangd/index/BackgroundQueue.cpp | 26 +- clang-tools-extra/clangd/index/SymbolCollector.cpp | 21 +- .../clangd/quality/model/features.json | 18 +- clang-tools-extra/clangd/quality/model/forest.json | 583744 ++++++++++-------- .../clangd/refactor/tweaks/ExpandAutoType.cpp | 12 +- clang-tools-extra/clangd/tool/Check.cpp | 1 + clang-tools-extra/clangd/tool/ClangdMain.cpp | 10 - .../clangd/unittests/ASTSignalsTests.cpp | 75 + .../clangd/unittests/BackgroundIndexTests.cpp | 76 +- clang-tools-extra/clangd/unittests/CMakeLists.txt | 1 + .../clangd/unittests/CodeCompleteTests.cpp | 13 +- .../clangd/unittests/CollectMacrosTests.cpp | 12 +- .../clangd/unittests/FindSymbolsTests.cpp | 16 +- .../clangd/unittests/FindTargetTests.cpp | 41 + .../unittests/GlobalCompilationDatabaseTests.cpp | 86 +- .../clangd/unittests/ParsedASTTests.cpp | 4 +- .../clangd/unittests/TUSchedulerTests.cpp | 47 +- .../unittests/tweaks/ExpandAutoTypeTests.cpp | 3 + .../readability-function-cognitive-complexity.cpp | 2 +- .../clang-tidy/TransformerClangTidyCheckTest.cpp | 38 +- clang/docs/ClangCommandLineReference.rst | 9 +- clang/docs/ClangOffloadBundler.rst | 4 +- clang/docs/OpenCLSupport.rst | 89 +- clang/docs/UsersManual.rst | 157 +- clang/include/clang/AST/DeclObjC.h | 30 +- clang/include/clang/AST/DependentDiagnostic.h | 6 +- clang/include/clang/AST/Expr.h | 39 +- clang/include/clang/AST/TemplateBase.h | 8 +- clang/include/clang/Basic/Attr.td | 23 + clang/include/clang/Basic/AttrDocs.td | 25 + clang/include/clang/Basic/BuiltinsAArch64.def | 6 + clang/include/clang/Basic/DiagnosticGroups.td | 1 + clang/include/clang/Basic/DiagnosticSemaKinds.td | 41 +- clang/include/clang/Basic/LangOptions.def | 2 + clang/include/clang/Basic/SourceManager.h | 33 +- clang/include/clang/Driver/Options.td | 1172 +- clang/include/clang/Frontend/CompilerInvocation.h | 21 +- clang/include/clang/Sema/DeclSpec.h | 83 +- clang/include/clang/Sema/Designator.h | 49 +- clang/include/clang/Sema/Initialization.h | 18 +- clang/include/clang/Sema/Sema.h | 121 +- clang/include/clang/Serialization/ASTReader.h | 10 +- clang/include/clang/Serialization/ASTWriter.h | 5 + .../clang/Tooling/Transformer/RewriteRule.h | 10 +- clang/lib/AST/DeclObjC.cpp | 4 +- clang/lib/AST/Expr.cpp | 14 +- clang/lib/AST/RecordLayoutBuilder.cpp | 21 +- clang/lib/AST/TemplateBase.cpp | 4 +- clang/lib/Basic/Targets/AArch64.cpp | 3 + clang/lib/Basic/Targets/PPC.cpp | 6 +- clang/lib/CodeGen/CGBuiltin.cpp | 120 + clang/lib/CodeGen/CGCXXABI.h | 7 + clang/lib/CodeGen/CGCall.cpp | 16 +- clang/lib/CodeGen/CGDebugInfo.cpp | 44 +- clang/lib/CodeGen/CGDebugInfo.h | 8 +- clang/lib/CodeGen/CGExprScalar.cpp | 37 +- clang/lib/CodeGen/CodeGenFunction.cpp | 3 +- clang/lib/CodeGen/CodeGenModule.cpp | 3 - clang/lib/CodeGen/MicrosoftCXXABI.cpp | 16 +- clang/lib/CodeGen/TargetInfo.cpp | 6 +- clang/lib/Driver/ToolChains/Clang.cpp | 30 +- clang/lib/Driver/ToolChains/Gnu.cpp | 2 + clang/lib/Frontend/CompilerInvocation.cpp | 152 +- .../Headers/__clang_cuda_math_forward_declares.h | 3 + clang/lib/Headers/arm_acle.h | 26 + clang/lib/Lex/PPMacroExpansion.cpp | 10 +- clang/lib/Parse/ParseDeclCXX.cpp | 4 +- clang/lib/Parse/ParsePragma.cpp | 29 +- clang/lib/Sema/DeclSpec.cpp | 20 +- clang/lib/Sema/Sema.cpp | 3 +- clang/lib/Sema/SemaAttr.cpp | 151 +- clang/lib/Sema/SemaChecking.cpp | 41 +- clang/lib/Sema/SemaDecl.cpp | 8 +- clang/lib/Sema/SemaDeclAttr.cpp | 77 + clang/lib/Sema/SemaDeclCXX.cpp | 13 +- clang/lib/Sema/SemaExpr.cpp | 13 +- clang/lib/Sema/SemaLookup.cpp | 7 + clang/lib/Sema/SemaTemplate.cpp | 5 + clang/lib/Sema/SemaType.cpp | 14 +- clang/lib/Serialization/ASTReader.cpp | 11 +- clang/lib/Serialization/ASTWriter.cpp | 10 +- clang/lib/Tooling/Transformer/RewriteRule.cpp | 7 +- clang/test/Analysis/NewDelete-intersections.mm | 9 +- clang/test/Analysis/free.c | 20 +- clang/test/CodeGen/aarch64-ls64.c | 163 + clang/test/CodeGen/attr-nomerge.cpp | 54 +- clang/test/CodeGen/fpconstrained.c | 4 +- clang/test/CodeGen/fpconstrained.cpp | 4 +- clang/test/CodeGen/incomplete-function-type.c | 1 + clang/test/CodeGen/math-builtins-long.c | 97 +- clang/test/CodeGen/noexceptionsfpmath.c | 2 +- clang/test/CodeGen/thinlto-distributed-newpm.ll | 9 - .../test/CodeGen/unique-internal-linkage-names.cpp | 20 +- clang/test/CodeGenCUDA/propagate-metadata.cu | 12 +- .../debug-info-codeview-display-name.cpp | 40 +- .../debug-info-gline-tables-only-codeview.cpp | 30 + .../test/CodeGenCXX/fdebug-info-for-profiling.cpp | 21 + clang/test/CodeGenCXX/homogeneous-aggregates.cpp | 69 + .../CodeGenCXX/microsoft-abi-member-pointers.cpp | 10 + clang/test/Driver/aix-pragma-pack.c | 4 + clang/test/Driver/fast-math.c | 4 - clang/test/Driver/fcs-profile-generate.c | 15 + clang/test/Driver/fp-model.c | 8 - clang/test/Driver/ppc-features.cpp | 30 +- clang/test/Driver/split-debug.c | 9 + clang/test/Frontend/fixed_point_compound.c | 110 + clang/test/Frontend/fixed_point_conversions.c | 299 + clang/test/Frontend/fixed_point_conversions_half.c | 309 + .../Frontend/optimization-remark-line-directive.c | 2 +- clang/test/Frontend/optimization-remark-new-pm.c | 4 +- .../optimization-remark-with-hotness-new-pm.c | 26 +- .../Frontend/optimization-remark-with-hotness.c | 2 +- clang/test/Frontend/optimization-remark.c | 26 +- clang/test/Layout/aix-double-struct-member.cpp | 9 +- .../test/Layout/aix-power-natural-interaction.cpp | 146 + ...pragma-attribute-supported-attributes-list.test | 2 + clang/test/PCH/aix-pragma-pack.c | 119 + clang/test/Parser/fp-floatcontrol-syntax.cpp | 4 +- clang/test/Preprocessor/aarch64-target-features.c | 6 + clang/test/Sema/aix-pragma-pack-and-align.c | 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compiler-rt/lib/scudo/standalone/combined.h | 21 +- compiler-rt/lib/scudo/standalone/flags.cpp | 15 - .../lib/scudo/standalone/tests/CMakeLists.txt | 2 +- .../lib/scudo/standalone/tests/flags_test.cpp | 15 - .../test/hwasan/TestCases/register-dump-read.c | 12 +- .../test/scudo/standalone/unit/lit.site.cfg.py.in | 2 +- compiler-rt/tools/gwp_asan/CMakeLists.txt | 15 +- .../tools/gwp_asan/options_parser_fuzzer.cpp | 12 + flang/CMakeLists.txt | 4 - flang/include/flang/Evaluate/characteristics.h | 23 +- flang/include/flang/Evaluate/fold.h | 24 +- flang/include/flang/Evaluate/shape.h | 86 +- flang/include/flang/Evaluate/tools.h | 27 +- flang/include/flang/Evaluate/type.h | 7 +- flang/include/flang/Parser/dump-parse-tree.h | 2 +- flang/include/flang/Parser/parse-tree.h | 4 +- flang/include/flang/Semantics/expression.h | 2 + flang/include/flang/Semantics/semantics.h | 4 +- flang/include/flang/Semantics/tools.h | 8 + flang/include/flang/Version.inc.in | 3 + flang/lib/Evaluate/characteristics.cpp | 58 +- flang/lib/Evaluate/check-expression.cpp | 90 +- flang/lib/Evaluate/fold.cpp | 7 + flang/lib/Evaluate/intrinsics.cpp | 7 +- flang/lib/Evaluate/shape.cpp | 254 +- flang/lib/Evaluate/tools.cpp | 153 +- flang/lib/Parser/unparse.cpp | 2 +- flang/lib/Semantics/check-acc-structure.h | 4 +- flang/lib/Semantics/check-call.cpp | 21 +- flang/lib/Semantics/check-declarations.cpp | 10 +- flang/lib/Semantics/check-directive-structure.h | 34 +- flang/lib/Semantics/check-do-forall.cpp | 45 +- flang/lib/Semantics/check-omp-structure.cpp | 53 +- flang/lib/Semantics/check-omp-structure.h | 6 + flang/lib/Semantics/expression.cpp | 44 +- flang/lib/Semantics/mod-file.cpp | 78 +- flang/lib/Semantics/resolve-names.cpp | 59 +- flang/lib/Semantics/semantics.cpp | 42 +- flang/lib/Semantics/tools.cpp | 115 +- flang/test/Frontend/input-output-file.f90 | 6 +- flang/test/Semantics/assign03.f90 | 2 +- flang/test/Semantics/call09.f90 | 27 +- flang/test/Semantics/data04.f90 | 1 - flang/test/Semantics/modfile03.f90 | 18 + flang/test/Semantics/modfile07.f90 | 26 + flang/test/Semantics/modfile35.f90 | 6 +- flang/test/Semantics/modfile37.f90 | 32 + flang/test/Semantics/modfile38.f90 | 35 + flang/test/Semantics/modfile39.f90 | 48 + flang/test/Semantics/omp-device-constructs.f90 | 2 +- flang/test/Semantics/omp-do01-positivecase.f90 | 19 + flang/test/Semantics/omp-do01.f90 | 12 +- flang/test/Semantics/omp-do05-positivecase.f90 | 36 + flang/test/Semantics/omp-do05.f90 | 38 +- flang/test/Semantics/omp-parallell01.f90 | 3 +- flang/test/Semantics/resolve44.f90 | 2 - flang/test/Semantics/resolve53.f90 | 4 +- flang/test/Semantics/separate-mp02.f90 | 12 +- flang/test/Semantics/shape.f90 | 8 + flang/tools/f18/CMakeLists.txt | 2 - flang/tools/f18/f18.cpp | 15 +- flang/tools/f18/f18_version.h.in | 9 - libc/benchmarks/LibcMemoryBenchmarkMain.cpp | 11 +- libc/config/linux/aarch64/entrypoints.txt | 3 + libc/config/linux/x86_64/entrypoints.txt | 3 + libc/spec/gnu_ext.td | 19 +- libc/spec/posix.td | 15 + libc/src/__support/CMakeLists.txt | 10 +- libc/src/__support/common.h | 55 + libc/src/__support/common.h.def | 32 - libc/src/ctype/CMakeLists.txt | 16 + libc/src/ctype/isascii.cpp | 17 + libc/src/ctype/isascii.h | 20 + libc/src/ctype/isblank.cpp | 2 +- libc/src/ctype/iscntrl.cpp | 2 +- libc/src/ctype/toascii.cpp | 17 + libc/src/ctype/toascii.h | 18 + libc/src/string/CMakeLists.txt | 12 + libc/src/string/memmove.cpp | 61 + libc/src/string/memmove.h | 20 + libc/src/string/memory_utils/memcpy_utils.h | 33 +- libc/src/string/memory_utils/utils.h | 4 + libc/src/string/x86/memcpy.cpp | 39 +- libc/test/src/ctype/CMakeLists.txt | 20 + libc/test/src/ctype/isascii_test.cpp | 23 + libc/test/src/ctype/toascii_test.cpp | 24 + libc/test/src/math/LdExpTest.h | 4 +- libc/test/src/string/CMakeLists.txt | 11 + libc/test/src/string/memmove_test.cpp | 70 + .../src/string/memory_utils/memcpy_utils_test.cpp | 39 +- libc/utils/UnitTest/CMakeLists.txt | 3 +- libc/utils/UnitTest/FuchsiaTest.h | 14 + libc/utils/UnitTest/LibcTest.cpp | 350 + libc/utils/UnitTest/LibcTest.h | 260 + libc/utils/UnitTest/Test.cpp | 350 - libc/utils/UnitTest/Test.h | 260 +- libcxx/docs/Cxx2bStatusPaperStatus.csv | 2 +- libcxx/docs/DesignDocs/VisibilityMacros.rst | 6 - libcxx/docs/FeatureTestMacroTable.rst | 2 +- libcxx/include/CMakeLists.txt | 1 + libcxx/include/__config | 17 +- libcxx/include/__locale | 10 +- libcxx/include/algorithm | 7 +- libcxx/include/support/openbsd/xlocale.h | 19 + libcxx/include/type_traits | 22 + libcxx/include/version | 2 +- libcxx/src/chrono.cpp | 5 +- libcxx/src/locale.cpp | 4 +- .../algorithm.version.pass.cpp | 2 + .../support.limits.general/any.version.pass.cpp | 2 + .../support.limits.general/array.version.pass.cpp | 2 + .../support.limits.general/atomic.version.pass.cpp | 2 + .../barrier.version.pass.cpp | 2 + .../support.limits.general/bit.version.pass.cpp | 2 + .../support.limits.general/chrono.version.pass.cpp | 2 + .../support.limits.general/cmath.version.pass.cpp | 2 + .../compare.version.pass.cpp | 2 + .../complex.version.pass.cpp | 2 + .../concepts.version.pass.cpp | 2 + .../cstddef.version.pass.cpp | 2 + .../support.limits.general/deque.version.pass.cpp | 2 + .../exception.version.pass.cpp | 2 + .../execution.version.pass.cpp | 2 + .../filesystem.version.pass.cpp | 2 + .../forward_list.version.pass.cpp | 2 + .../functional.version.pass.cpp | 2 + .../iomanip.version.pass.cpp | 2 + .../istream.version.pass.cpp | 2 + .../iterator.version.pass.cpp | 2 + .../support.limits.general/latch.version.pass.cpp | 2 + .../support.limits.general/limits.version.pass.cpp | 2 + .../support.limits.general/list.version.pass.cpp | 2 + .../support.limits.general/locale.version.pass.cpp | 2 + .../support.limits.general/map.version.pass.cpp | 2 + .../support.limits.general/memory.version.pass.cpp | 2 + .../support.limits.general/mutex.version.pass.cpp | 2 + .../support.limits.general/new.version.pass.cpp | 2 + .../numbers.version.pass.cpp | 2 + .../numeric.version.pass.cpp | 2 + .../optional.version.pass.cpp | 2 + .../ostream.version.pass.cpp | 2 + .../support.limits.general/regex.version.pass.cpp | 2 + .../scoped_allocator.version.pass.cpp | 2 + .../semaphore.version.pass.cpp | 2 + .../support.limits.general/set.version.pass.cpp | 2 + .../shared_mutex.version.pass.cpp | 2 + .../support.limits.general/span.version.pass.cpp | 2 + .../support.limits.general/string.version.pass.cpp | 2 + .../string_view.version.pass.cpp | 2 + .../support.limits.general/thread.version.pass.cpp | 2 + .../support.limits.general/tuple.version.pass.cpp | 2 + .../type_traits.version.pass.cpp | 18 +- .../unordered_map.version.pass.cpp | 2 + .../unordered_set.version.pass.cpp | 2 + .../utility.version.pass.cpp | 2 + .../variant.version.pass.cpp | 2 + .../support.limits.general/vector.version.pass.cpp | 2 + .../version.version.pass.cpp | 18 +- .../thread.lock.guard/adopt_lock.pass.cpp | 8 +- .../thread.lock/thread.lock.guard/mutex.pass.cpp | 8 +- .../meta.unary.prop/is_scoped_enum.pass.cpp | 120 + .../time/time.clock/time.clock.steady/now.pass.cpp | 2 + .../generate_feature_test_macro_components.py | 3 +- libunwind/include/__libunwind_config.h | 3 + libunwind/src/UnwindCursor.hpp | 110 +- libunwind/test/signal_unwind.pass.cpp | 9 +- libunwind/test/unwind_leaffunction.pass.cpp | 6 +- lld/COFF/Chunks.cpp | 113 +- lld/COFF/Chunks.h | 10 + lld/COFF/DebugTypes.cpp | 20 + lld/COFF/PDB.cpp | 643 +- lld/ELF/Driver.cpp | 11 +- lld/ELF/OutputSections.h | 6 - lld/ELF/SyntheticSections.cpp | 7 + lld/MachO/InputSection.cpp | 2 +- lld/README.md | 2 +- lld/include/lld/Common/LLVM.h | 6 + lld/test/ELF/debug-gnu-pubnames.s | 18 - lld/test/ELF/gdb-index.s | 15 +- lld/test/ELF/lto/devirt_vcall_vis_public.ll | 36 +- lld/test/ELF/lto/exclude-libs-libcall.ll | 28 + lld/test/wasm/debug-removed-fn.ll | 2 +- lld/test/wasm/tls-no-shared.s | 2 +- lld/test/wasm/tls.s | 33 +- lld/wasm/Driver.cpp | 2 +- lld/wasm/InputChunks.cpp | 4 + lld/wasm/InputFiles.cpp | 33 +- lld/wasm/InputFiles.h | 3 + lld/wasm/InputTable.h | 60 + lld/wasm/MarkLive.cpp | 4 + lld/wasm/SymbolTable.cpp | 65 + lld/wasm/SymbolTable.h | 7 + lld/wasm/Symbols.cpp | 45 + lld/wasm/Symbols.h | 68 +- lld/wasm/SyntheticSections.cpp | 63 +- lld/wasm/SyntheticSections.h | 26 +- lld/wasm/Writer.cpp | 19 +- lld/wasm/WriterUtils.cpp | 17 +- lld/wasm/WriterUtils.h | 1 + lldb/bindings/interface/SBAddress.i | 5 +- lldb/bindings/interface/SBBreakpoint.i | 8 +- lldb/bindings/interface/SBBreakpointLocation.i | 2 +- lldb/bindings/interface/SBBreakpointName.i | 4 +- lldb/bindings/interface/SBCommandInterpreter.i | 8 +- .../interface/SBCommandInterpreterRunOptions.i | 13 +- lldb/bindings/interface/SBCommandReturnObject.i | 4 +- lldb/bindings/interface/SBCompileUnit.i | 36 +- lldb/bindings/interface/SBEnvironment.i | 3 +- lldb/bindings/interface/SBError.i | 4 +- lldb/bindings/interface/SBEvent.i | 32 +- lldb/bindings/interface/SBFileSpec.i | 2 +- lldb/bindings/interface/SBFrame.i | 4 +- lldb/bindings/interface/SBFunction.i | 2 +- lldb/bindings/interface/SBInstructionList.i | 10 +- lldb/bindings/interface/SBLineEntry.i | 36 +- lldb/bindings/interface/SBListener.i | 2 +- lldb/bindings/interface/SBModule.i | 14 +- lldb/bindings/interface/SBPlatform.i | 2 +- lldb/bindings/interface/SBProcess.i | 32 +- lldb/bindings/interface/SBSection.i | 22 +- lldb/bindings/interface/SBSourceManager.i | 2 +- lldb/bindings/interface/SBStream.i | 2 +- lldb/bindings/interface/SBSymbol.i | 4 +- lldb/bindings/interface/SBSymbolContext.i | 2 +- lldb/bindings/interface/SBSymbolContextList.i | 2 +- lldb/bindings/interface/SBTarget.i | 32 +- lldb/bindings/interface/SBThread.i | 6 +- lldb/bindings/interface/SBType.i | 154 +- lldb/bindings/interface/SBTypeEnumMember.i | 6 +- lldb/bindings/interface/SBValue.i | 50 +- lldb/bindings/interface/SBValueList.i | 111 +- lldb/bindings/interface/SBWatchpoint.i | 2 +- lldb/bindings/python/python-extensions.swig | 18 +- lldb/bindings/python/python.swig | 34 +- .../Python/lldbsuite/test/lldbplatformutil.py | 14 +- lldb/packages/Python/lldbsuite/test/lldbtest.py | 29 +- .../Plugins/ObjectFile/wasm/ObjectFileWasm.cpp | 61 +- .../gdb-server/PlatformRemoteGDBServer.cpp | 2 +- .../Process/Utility/DynamicRegisterInfo.cpp | 91 +- .../Plugins/Process/Utility/DynamicRegisterInfo.h | 12 +- .../GDBRemoteCommunicationServerLLGS.cpp | 98 + .../gdb-remote/GDBRemoteCommunicationServerLLGS.h | 13 + .../GDBRemoteCommunicationServerPlatform.cpp | 2 +- .../gdb-remote/GDBRemoteRegisterContext.cpp | 28 +- .../Process/gdb-remote/GDBRemoteRegisterContext.h | 10 +- .../Process/gdb-remote/ProcessGDBRemote.cpp | 30 +- .../Plugins/Process/gdb-remote/ProcessGDBRemote.h | 2 +- .../Plugins/Process/gdb-remote/ThreadGDBRemote.cpp | 12 +- .../Plugins/Process/gdb-remote/ThreadGDBRemote.h | 4 + .../Plugins/Process/minidump/MinidumpParser.cpp | 26 +- lldb/test/API/macosx/builtin-debugtrap/main.cpp | 1 + .../tools/lldb-server/TestGdbRemoteAttachWait.py | 75 + .../TestPlatformProcessConnect.py | 52 +- .../register-reading/TestGdbRemoteGPacket.py | 2 + .../ObjectFile/wasm/embedded-debug-sections.yaml | 100 + .../Shell/SymbolFile/NativePDB/disassembly.cpp | 4 +- lldb/test/Shell/SymbolFile/NativePDB/load-pdb.cpp | 2 +- lldb/tools/debugserver/source/CMakeLists.txt | 4 +- .../tools/debugserver/source/MacOSX/MachProcess.mm | 139 +- lldb/tools/debugserver/source/MacOSX/MachTask.mm | 11 +- lldb/tools/debugserver/source/RNBRemote.cpp | 19 +- lldb/tools/debugserver/source/debugserver.cpp | 46 +- .../Process/minidump/MinidumpParserTest.cpp | 41 + llvm/CMakeLists.txt | 7 - llvm/CODE_OWNERS.TXT | 8 +- llvm/docs/AMDGPUUsage.rst | 48 +- llvm/docs/DebuggingJITedCode.rst | 201 +- llvm/docs/LangRef.rst | 36 +- .../LLJITDumpObjects/LLJITDumpObjects.cpp | 1 + llvm/include/llvm/ADT/DepthFirstIterator.h | 2 +- llvm/include/llvm/ADT/IntrusiveRefCntPtr.h | 6 + llvm/include/llvm/ADT/SmallVector.h | 235 +- llvm/include/llvm/ADT/StringExtras.h | 13 +- llvm/include/llvm/Analysis/DivergenceAnalysis.h | 2 +- llvm/include/llvm/Analysis/InlineAdvisor.h | 58 +- llvm/include/llvm/Analysis/LoopCacheAnalysis.h | 6 +- llvm/include/llvm/Analysis/MLInlineAdvisor.h | 10 +- llvm/include/llvm/Analysis/ReplayInlineAdvisor.h | 5 +- llvm/include/llvm/BinaryFormat/Dwarf.h | 9 +- llvm/include/llvm/BinaryFormat/Wasm.h | 4 +- llvm/include/llvm/CodeGen/FastISel.h | 25 +- .../GlobalISel/LegalizationArtifactCombiner.h | 4 +- .../llvm/CodeGen/GlobalISel/MIPatternMatch.h | 20 + .../llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 5 + llvm/include/llvm/CodeGen/ISDOpcodes.h | 9 +- llvm/include/llvm/CodeGen/LiveIntervals.h | 5 +- llvm/include/llvm/CodeGen/LiveRegUnits.h | 1 - llvm/include/llvm/CodeGen/MIRYamlMapping.h | 2 +- llvm/include/llvm/CodeGen/MachineLoopUtils.h | 4 - llvm/include/llvm/CodeGen/SelectionDAG.h | 6 +- llvm/include/llvm/CodeGen/SlotIndexes.h | 45 +- llvm/include/llvm/CodeGen/StackMaps.h | 9 + llvm/include/llvm/CodeGen/TargetFrameLowering.h | 2 +- llvm/include/llvm/CodeGen/TargetInstrInfo.h | 7 +- llvm/include/llvm/DWARFLinker/DWARFLinker.h | 6 +- .../llvm/DWARFLinker/DWARFLinkerCompileUnit.h | 2 +- llvm/include/llvm/DWARFLinker/DWARFStreamer.h | 2 +- .../PDB/Native/DbiModuleDescriptorBuilder.h | 63 +- .../include/llvm/ExecutionEngine/JITLink/JITLink.h | 20 +- llvm/include/llvm/ExecutionEngine/Orc/Core.h | 3 + llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h | 13 +- llvm/include/llvm/Frontend/OpenACC/ACC.td | 4 +- llvm/include/llvm/Frontend/OpenACC/CMakeLists.txt | 2 +- llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h | 5 +- llvm/include/llvm/IR/DebugInfoMetadata.h | 4 + llvm/include/llvm/IR/FixedPointBuilder.h | 59 + llvm/include/llvm/IR/Function.h | 4 + llvm/include/llvm/IR/IntrinsicsAArch64.td | 8 + llvm/include/llvm/IR/IntrinsicsRISCV.td | 32 +- llvm/include/llvm/IR/Value.h | 4 + llvm/include/llvm/LTO/Config.h | 6 +- llvm/include/llvm/LTO/LTOBackend.h | 6 + llvm/include/llvm/MC/MCObjectFileInfo.h | 4 +- llvm/include/llvm/Object/ELF.h | 60 +- llvm/include/llvm/Object/Wasm.h | 5 +- llvm/include/llvm/ObjectYAML/ELFYAML.h | 42 +- llvm/include/llvm/Option/OptParser.td | 41 +- llvm/include/llvm/Pass.h | 14 + llvm/include/llvm/Passes/PassBuilder.h | 21 +- .../include/llvm/Passes/StandardInstrumentations.h | 14 +- llvm/include/llvm/Support/Allocator.h | 25 +- llvm/include/llvm/Support/Compiler.h | 16 +- llvm/include/llvm/Support/KnownBits.h | 4 +- llvm/include/llvm/Support/MathExtras.h | 2 +- llvm/include/llvm/Support/Program.h | 12 +- .../llvm/Target/GlobalISel/SelectionDAGCompat.td | 2 +- llvm/include/llvm/Transforms/IPO/Inliner.h | 9 +- llvm/include/llvm/Transforms/IPO/SampleProfile.h | 9 +- .../llvm/Transforms/Utils/BasicBlockUtils.h | 97 +- .../Vectorize/LoopVectorizationLegality.h | 2 +- llvm/lib/Analysis/CallPrinter.cpp | 2 +- llvm/lib/Analysis/ConstraintSystem.cpp | 2 +- llvm/lib/Analysis/DevelopmentModeInlineAdvisor.cpp | 12 +- llvm/lib/Analysis/IRSimilarityIdentifier.cpp | 2 +- llvm/lib/Analysis/InlineAdvisor.cpp | 102 +- llvm/lib/Analysis/InstructionSimplify.cpp | 24 +- llvm/lib/Analysis/LazyCallGraph.cpp | 2 +- llvm/lib/Analysis/MLInlineAdvisor.cpp | 30 +- llvm/lib/Analysis/ModuleSummaryAnalysis.cpp | 2 +- llvm/lib/Analysis/ReplayInlineAdvisor.cpp | 43 +- llvm/lib/Analysis/VFABIDemangling.cpp | 6 +- llvm/lib/Analysis/ValueTracking.cpp | 13 +- llvm/lib/BinaryFormat/Dwarf.cpp | 3 + llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 4 +- .../AsmPrinter/DbgEntityHistoryCalculator.cpp | 2 +- llvm/lib/CodeGen/CodeGenPrepare.cpp | 4 +- llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp | 2 +- llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp | 3 +- llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp | 2 +- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 9 +- llvm/lib/CodeGen/InlineSpiller.cpp | 37 +- .../CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp | 8 +- .../CodeGen/LiveDebugValues/VarLocBasedImpl.cpp | 5 +- llvm/lib/CodeGen/MIRParser/MILexer.cpp | 1 + llvm/lib/CodeGen/MIRParser/MILexer.h | 1 + llvm/lib/CodeGen/MIRParser/MIParser.cpp | 8 +- llvm/lib/CodeGen/MachineBasicBlock.cpp | 2 +- llvm/lib/CodeGen/MachineLoopUtils.cpp | 11 - llvm/lib/CodeGen/MachineOperand.cpp | 6 +- llvm/lib/CodeGen/MachinePipeliner.cpp | 1 - llvm/lib/CodeGen/MachineVerifier.cpp | 23 + llvm/lib/CodeGen/RDFLiveness.cpp | 4 +- llvm/lib/CodeGen/RegAllocFast.cpp | 3 +- llvm/lib/CodeGen/SafeStackLayout.cpp | 8 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 227 +- llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 246 +- .../CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 6 +- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 30 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 25 +- .../CodeGen/SelectionDAG/StatepointLowering.cpp | 21 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 50 +- llvm/lib/CodeGen/StackMaps.cpp | 61 +- llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp | 2 +- llvm/lib/DWARFLinker/DWARFLinker.cpp | 45 +- llvm/lib/DWARFLinker/DWARFLinkerCompileUnit.cpp | 6 +- llvm/lib/DWARFLinker/DWARFStreamer.cpp | 50 +- .../PDB/Native/DbiModuleDescriptorBuilder.cpp | 81 +- llvm/lib/DebugInfo/PDB/Native/DbiStreamBuilder.cpp | 10 +- llvm/lib/Demangle/MicrosoftDemangleNodes.cpp | 1 - .../lib/ExecutionEngine/JITLink/JITLinkGeneric.cpp | 12 +- llvm/lib/ExecutionEngine/MCJIT/MCJIT.h | 10 +- llvm/lib/ExecutionEngine/Orc/Core.cpp | 30 +- llvm/lib/ExecutionEngine/Orc/LLJIT.cpp | 25 +- .../RuntimeDyld/RuntimeDyldChecker.cpp | 4 +- llvm/lib/FileCheck/FileCheck.cpp | 1 - llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 21 +- llvm/lib/IR/AutoUpgrade.cpp | 1 - llvm/lib/IR/DebugInfoMetadata.cpp | 1 + llvm/lib/IR/LegacyPassManager.cpp | 3 +- llvm/lib/IR/Value.cpp | 12 + llvm/lib/LTO/LTOBackend.cpp | 31 +- llvm/lib/MC/MCParser/AsmParser.cpp | 2 +- llvm/lib/MC/MCSectionMachO.cpp | 20 +- llvm/lib/Object/WasmObjectFile.cpp | 7 +- llvm/lib/ObjectYAML/ELFEmitter.cpp | 51 +- llvm/lib/ObjectYAML/ELFYAML.cpp | 8 +- llvm/lib/Option/OptTable.cpp | 2 +- llvm/lib/Passes/PassBuilder.cpp | 77 +- llvm/lib/Passes/PassRegistry.def | 9 +- llvm/lib/Passes/StandardInstrumentations.cpp | 53 +- llvm/lib/Support/KnownBits.cpp | 43 +- llvm/lib/Support/Program.cpp | 14 +- llvm/lib/Support/Unix/Path.inc | 2 - llvm/lib/Support/Unix/Program.inc | 6 +- llvm/lib/Support/Windows/Program.inc | 18 +- llvm/lib/Support/Windows/Threading.inc | 25 +- llvm/lib/TableGen/Record.cpp | 4 +- llvm/lib/TableGen/TGParser.cpp | 19 +- llvm/lib/Target/AArch64/AArch64.td | 9 +- llvm/lib/Target/AArch64/AArch64FrameLowering.cpp | 12 +- llvm/lib/Target/AArch64/AArch64FrameLowering.h | 4 +- llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 12 +- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 83 +- llvm/lib/Target/AArch64/AArch64ISelLowering.h | 12 + llvm/lib/Target/AArch64/AArch64InstrGISel.td | 14 + llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 32 +- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 10 +- llvm/lib/Target/AArch64/AArch64MCInstLower.cpp | 6 + llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 32 +- llvm/lib/Target/AArch64/AArch64SchedA64FX.td | 3890 + llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 8 +- .../AArch64/GISel/AArch64InstructionSelector.cpp | 47 +- .../Target/AArch64/GISel/AArch64LegalizerInfo.cpp | 4 +- .../AArch64/GISel/AArch64RegisterBankInfo.cpp | 14 +- llvm/lib/Target/AArch64/SVEIntrinsicOpts.cpp | 50 +- llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 6 +- llvm/lib/Target/AMDGPU/AMDGPUInline.cpp | 23 - .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 8 +- .../Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp | 2 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 60 +- llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp | 18 +- .../Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 18 +- llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp | 34 +- .../AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp | 1 - llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 2 +- llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 22 +- llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 2 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 8 +- llvm/lib/Target/AMDGPU/SIInsertSkips.cpp | 66 +- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 104 +- llvm/lib/Target/AMDGPU/SIInstrInfo.td | 195 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 130 +- llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp | 6 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 8 +- llvm/lib/Target/AMDGPU/SISchedule.td | 2 +- llvm/lib/Target/AMDGPU/VOP2Instructions.td | 6 +- llvm/lib/Target/AMDGPU/VOP3Instructions.td | 534 +- llvm/lib/Target/AMDGPU/VOP3PInstructions.td | 66 +- llvm/lib/Target/ARC/ARCTargetMachine.cpp | 4 +- llvm/lib/Target/ARM/ARM.h | 2 + llvm/lib/Target/ARM/ARMBlockPlacement.cpp | 231 + llvm/lib/Target/ARM/ARMCallLowering.cpp | 8 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 25 +- llvm/lib/Target/ARM/ARMTargetMachine.cpp | 7 +- llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 1 - llvm/lib/Target/ARM/CMakeLists.txt | 1 + llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp | 1 - llvm/lib/Target/ARM/MVETailPredication.cpp | 22 +- llvm/lib/Target/AVR/AVRTargetMachine.cpp | 2 +- llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp | 2 - llvm/lib/Target/BPF/BPFTargetMachine.cpp | 4 +- llvm/lib/Target/CSKY/CSKYTargetMachine.cpp | 2 +- llvm/lib/Target/Hexagon/HexagonISelLowering.h | 1 + llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp | 113 +- llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp | 4 +- .../Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp | 2 +- .../Hexagon/MCTargetDesc/HexagonShuffler.cpp | 5 +- llvm/lib/Target/Lanai/LanaiTargetMachine.cpp | 4 +- llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp | 11 +- llvm/lib/Target/Mips/MipsRegisterBankInfo.h | 2 +- .../Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp | 94 +- .../Target/PowerPC/MCTargetDesc/PPCInstPrinter.h | 85 +- .../PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp | 12 +- llvm/lib/Target/PowerPC/PPC.td | 15 + llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 2 +- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 78 + llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 5 +- llvm/lib/Target/PowerPC/PPCInstr64Bit.td | 7 +- llvm/lib/Target/PowerPC/PPCInstrInfo.td | 7 + llvm/lib/Target/PowerPC/PPCSubtarget.cpp | 3 + llvm/lib/Target/PowerPC/PPCSubtarget.h | 4 + llvm/lib/Target/PowerPC/PPCTargetMachine.cpp | 7 + llvm/lib/Target/RISCV/AsmParser/CMakeLists.txt | 1 - llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 4 +- llvm/lib/Target/RISCV/CMakeLists.txt | 2 - .../RISCV/Disassembler/RISCVDisassembler.cpp | 2 +- llvm/lib/Target/RISCV/MCTargetDesc/CMakeLists.txt | 3 +- .../Target/RISCV/MCTargetDesc/RISCVAsmBackend.h | 2 +- .../{Utils => MCTargetDesc}/RISCVBaseInfo.cpp | 0 llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 411 + .../Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp | 4 +- .../Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp | 5 +- .../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 2 +- .../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 2 +- .../RISCV/{Utils => MCTargetDesc}/RISCVMatInt.cpp | 0 .../RISCV/{Utils => MCTargetDesc}/RISCVMatInt.h | 0 llvm/lib/Target/RISCV/RISCV.h | 2 +- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 2 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 169 +- llvm/lib/Target/RISCV/RISCVISelLowering.h | 17 + llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 2 +- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 6 +- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 37 +- llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td | 161 + llvm/lib/Target/RISCV/RISCVMCInstLower.cpp | 9 + llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 4 - llvm/lib/Target/RISCV/RISCVSubtarget.h | 2 +- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 2 +- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 2 +- llvm/lib/Target/RISCV/Utils/CMakeLists.txt | 10 - llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h | 414 - llvm/lib/Target/Sparc/SparcISelLowering.cpp | 38 +- llvm/lib/Target/Sparc/SparcTargetMachine.cpp | 4 +- .../lib/Target/SystemZ/SystemZMachineScheduler.cpp | 1 + llvm/lib/Target/SystemZ/SystemZScheduleZ13.td | 2 +- llvm/lib/Target/SystemZ/SystemZScheduleZ14.td | 2 +- llvm/lib/Target/SystemZ/SystemZScheduleZ15.td | 2 +- llvm/lib/Target/SystemZ/SystemZScheduleZ196.td | 2 +- llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td | 2 +- llvm/lib/Target/VE/VETargetMachine.cpp | 4 +- .../Target/WebAssembly/WebAssemblyCFGStackify.cpp | 102 +- .../Target/WebAssembly/WebAssemblyISelLowering.cpp | 3 +- .../WebAssembly/WebAssemblyLateEHPrepare.cpp | 77 + .../Target/WebAssembly/WebAssemblyUtilities.cpp | 14 + llvm/lib/Target/WebAssembly/WebAssemblyUtilities.h | 5 + llvm/lib/Target/X86/X86.td | 3 +- llvm/lib/Target/X86/X86FlagsCopyLowering.cpp | 1 - llvm/lib/Target/X86/X86ISelLowering.cpp | 395 +- llvm/lib/Target/X86/X86ISelLowering.h | 1 + llvm/lib/Target/X86/X86IndirectThunks.cpp | 1 - llvm/lib/Target/X86/X86MCInstLower.cpp | 6 +- llvm/lib/Target/XCore/XCoreTargetMachine.cpp | 4 +- llvm/lib/TextAPI/MachO/InterfaceFile.cpp | 2 - llvm/lib/Transforms/Coroutines/CoroFrame.cpp | 29 +- llvm/lib/Transforms/IPO/Attributor.cpp | 2 +- llvm/lib/Transforms/IPO/AttributorAttributes.cpp | 1 - llvm/lib/Transforms/IPO/FunctionAttrs.cpp | 18 + llvm/lib/Transforms/IPO/IROutliner.cpp | 32 +- llvm/lib/Transforms/IPO/Inliner.cpp | 8 +- llvm/lib/Transforms/IPO/OpenMPOpt.cpp | 212 +- llvm/lib/Transforms/IPO/SampleProfile.cpp | 29 +- llvm/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp | 2 +- llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp | 4 +- .../Transforms/InstCombine/InstCombineAndOrXor.cpp | 8 + .../Transforms/InstCombine/InstCombineCalls.cpp | 4 +- .../Transforms/InstCombine/InstCombineCompares.cpp | 15 + .../InstCombine/InstCombineLoadStoreAlloca.cpp | 18 +- .../Transforms/InstCombine/InstCombineSelect.cpp | 6 +- .../Instrumentation/HWAddressSanitizer.cpp | 6 +- .../Instrumentation/SanitizerCoverage.cpp | 2 +- .../Transforms/Scalar/ConstraintElimination.cpp | 7 +- llvm/lib/Transforms/Scalar/LICM.cpp | 16 +- llvm/lib/Transforms/Scalar/LoopSink.cpp | 2 +- .../Transforms/Scalar/LowerMatrixIntrinsics.cpp | 16 +- llvm/lib/Transforms/Scalar/NewGVN.cpp | 7 +- .../Transforms/Scalar/RewriteStatepointsForGC.cpp | 8 +- llvm/lib/Transforms/Scalar/SROA.cpp | 2 +- llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp | 4 + llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp | 17 +- llvm/lib/Transforms/Utils/BasicBlockUtils.cpp | 233 +- llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp | 18 +- llvm/lib/Transforms/Utils/InlineFunction.cpp | 3 +- llvm/lib/Transforms/Utils/Local.cpp | 44 +- llvm/lib/Transforms/Utils/LoopUtils.cpp | 3 +- llvm/lib/Transforms/Utils/LoopVersioning.cpp | 2 +- llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 95 +- .../Utils/UniqueInternalLinkageNames.cpp | 21 +- .../Vectorize/LoopVectorizationLegality.cpp | 20 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 79 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 94 +- llvm/runtimes/CMakeLists.txt | 939 +- .../CodeGen/AArch64/GlobalISel/arm64-fallback.ll | 7 - .../CodeGen/AArch64/GlobalISel/inline-memcpy.mir | 4 +- .../GlobalISel/legalize-ext-csedebug-output.mir | 3 - .../GlobalISel/legalize-fp128-fconstant.mir | 22 + .../GlobalISel/legalize-non-pow2-load-store.mir | 4 +- .../AArch64/GlobalISel/regbank-fp-use-def.mir | 46 +- .../CodeGen/AArch64/GlobalISel/select-fcmp.mir | 27 + .../CodeGen/AArch64/GlobalISel/select-fp-casts.mir | 71 +- llvm/test/CodeGen/AArch64/arm64-abi_align.ll | 8 +- llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll | 15 +- llvm/test/CodeGen/AArch64/arm64-fast-isel-gv.ll | 6 +- .../CodeGen/AArch64/arm64-fast-isel-intrinsic.ll | 4 +- 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.../AMDGPU/promote-constOffset-to-imm-gfx10.mir | 8 +- .../CodeGen/AMDGPU/promote-constOffset-to-imm.mir | 8 +- llvm/test/CodeGen/AMDGPU/r600-legalize-umax-bug.ll | 23 +- llvm/test/CodeGen/AMDGPU/regbank-reassign.mir | 8 +- .../CodeGen/AMDGPU/regcoal-subrange-join-seg.mir | 4 +- llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir | 2 +- ...coalescing-remove-partial-redundancy-assert.mir | 6 +- .../CodeGen/AMDGPU/rename-independent-subregs.mir | 2 +- .../CodeGen/AMDGPU/s_add_co_pseudo_lowering.mir | 14 +- .../sched-assert-onlydbg-value-empty-region.mir | 6 +- llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir | 34 +- ...d-handleMoveUp-subreg-def-across-subreg-def.mir | 12 +- llvm/test/CodeGen/AMDGPU/sched-prefer-non-mfma.mir | 4 +- llvm/test/CodeGen/AMDGPU/schedule-barrier.mir | 8 +- .../CodeGen/AMDGPU/sdwa-peephole-instr-gfx10.mir | 24 +- llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir | 26 +- llvm/test/CodeGen/AMDGPU/sdwa-preserve.mir | 2 +- llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir | 8 +- llvm/test/CodeGen/AMDGPU/setcc.ll | 16 +- llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir | 12 +- .../CodeGen/AMDGPU/smem-no-clause-coalesced.mir | 4 +- .../CodeGen/AMDGPU/spill-agpr-partially-undef.mir | 12 +- llvm/test/CodeGen/AMDGPU/spill-agpr.mir | 316 +- .../AMDGPU/stale-livevar-in-twoaddr-pass.mir | 2 +- .../CodeGen/AMDGPU/subreg-split-live-in-error.mir | 18 +- llvm/test/CodeGen/AMDGPU/twoaddr-mad.mir | 2 +- llvm/test/CodeGen/AMDGPU/v_swap_b32.mir | 4 +- llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir | 24 +- llvm/test/CodeGen/AMDGPU/waitcnt.mir | 8 +- .../GlobalISel/irtranslator-varargs-lowering.ll | 21 + llvm/test/CodeGen/ARM/O3-pipeline.ll | 3 + llvm/test/CodeGen/ARM/fast-isel-call.ll | 72 +- llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll | 14 +- .../ARM/fast-isel-ldr-str-thumb-neg-index.ll | 18 +- llvm/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll | 38 +- llvm/test/CodeGen/ARM/fast-isel-select.ll | 46 +- llvm/test/CodeGen/ARM/fast-isel-vararg.ll | 6 +- llvm/test/CodeGen/ARM/fast-isel.ll | 19 +- llvm/test/CodeGen/ARM/speculation-hardening-sls.ll | 12 +- llvm/test/CodeGen/ARM/swifterror.ll | 6 +- llvm/test/CodeGen/Hexagon/autohvx/widen-setcc.ll | 21 + .../MIR/X86/expected-align-in-memory-operand.mir | 4 +- ...ted-alignment-after-align-in-memory-operand.mir | 4 +- .../expected-positive-alignment-after-align.mir | 4 +- llvm/test/CodeGen/MIR/X86/memory-operands.mir | 36 +- llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll | 74 +- llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll | 2 +- llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll | 100 +- llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll | 32 +- llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll | 18 +- llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll | 4 +- llvm/test/CodeGen/Mips/Fast-ISel/shftopm.ll | 12 +- llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll | 6 +- llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll | 10 +- .../store_split_because_of_memsize_or_align.mir | 28 +- .../CodeGen/Mips/GlobalISel/regbankselect/load.mir | 2 +- .../regbankselect/long_ambiguous_chain_s32.mir | 18 +- .../regbankselect/long_ambiguous_chain_s64.mir | 18 +- .../Mips/GlobalISel/regbankselect/store.mir | 2 +- .../CodeGen/Mips/emergency-spill-slot-near-fp.ll | 3 + llvm/test/CodeGen/NVPTX/f16-instructions.ll | 4 +- llvm/test/CodeGen/PowerPC/aix-cc-abi.ll | 52 +- llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll | 4 +- llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll | 4 +- llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll | 4 +- llvm/test/CodeGen/PowerPC/elf-common.ll | 6 +- llvm/test/CodeGen/PowerPC/fast-isel-load-store.ll | 54 +- llvm/test/CodeGen/PowerPC/fold_swtest_br.ll | 204 + llvm/test/CodeGen/PowerPC/lower-massv.ll | 2 +- llvm/test/CodeGen/PowerPC/mcm-1.ll | 8 +- llvm/test/CodeGen/PowerPC/mcm-13.ll | 4 +- llvm/test/CodeGen/PowerPC/mcm-2.ll | 8 +- llvm/test/CodeGen/PowerPC/mcm-3.ll | 8 +- llvm/test/CodeGen/PowerPC/mcm-6.ll | 4 +- llvm/test/CodeGen/PowerPC/mcm-9.ll | 4 +- llvm/test/CodeGen/PowerPC/mcm-default.ll | 4 +- llvm/test/CodeGen/PowerPC/popcnt-zext.ll | 4 +- llvm/test/CodeGen/PowerPC/ppc32-pic.ll | 6 +- llvm/test/CodeGen/PowerPC/spe.ll | 2043 +- llvm/test/CodeGen/PowerPC/srem-lkk.ll | 4 +- llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll | 8 +- llvm/test/CodeGen/PowerPC/testComparesigeuc.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesigeui.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesigeull.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesigeus.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesileuc.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesileui.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesileull.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesileus.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesiltsc.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesiltsi.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesiltsll.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesiltss.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesiltuc.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesiltui.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesiltus.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllgeui.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllgeull.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllgeus.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllleuc.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllleui.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllleull.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllleus.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllltsll.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllltuc.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllltus.ll | 6 +- llvm/test/CodeGen/PowerPC/urem-lkk.ll | 4 +- llvm/test/CodeGen/PowerPC/vec_splat.ll | 4 +- .../CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll | 10 +- llvm/test/CodeGen/PowerPC/vmladduhm.ll | 4 +- llvm/test/CodeGen/PowerPC/vsx.ll | 40 +- llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll | 12 +- llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll | 8 +- llvm/test/CodeGen/RISCV/callee-saved-gprs.ll | 8 +- .../RISCV/calling-conv-ilp32-ilp32f-common.ll | 12 +- .../calling-conv-ilp32-ilp32f-ilp32d-common.ll | 44 +- llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll | 12 +- llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll | 12 +- .../RISCV/calling-conv-ilp32f-ilp32d-common.ll | 10 +- .../RISCV/calling-conv-lp64-lp64f-common.ll | 4 +- .../RISCV/calling-conv-lp64-lp64f-lp64d-common.ll | 22 +- llvm/test/CodeGen/RISCV/calling-conv-lp64.ll | 12 +- .../test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll | 4 +- llvm/test/CodeGen/RISCV/copysign-casts.ll | 8 +- llvm/test/CodeGen/RISCV/double-br-fcmp.ll | 89 +- llvm/test/CodeGen/RISCV/double-fcmp.ll | 48 +- llvm/test/CodeGen/RISCV/double-select-fcmp.ll | 90 +- llvm/test/CodeGen/RISCV/float-br-fcmp.ll | 87 +- llvm/test/CodeGen/RISCV/float-fcmp.ll | 46 +- llvm/test/CodeGen/RISCV/float-select-fcmp.ll | 82 +- llvm/test/CodeGen/RISCV/frame-info.ll | 10 +- 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llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll | 312 +- llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll | 467 +- llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll | 419 +- llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll | 419 +- llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll | 419 +- llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll | 419 +- llvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll | 424 +- llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll | 972 +- llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll | 972 +- llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll | 972 +- llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll | 220 +- llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll | 224 +- llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll | 312 +- llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll | 797 +- llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv32.ll | 380 + llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv64.ll | 380 + llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll | 388 +- llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll | 388 +- llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll | 519 +- llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll | 388 +- llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll | 379 + llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll | 379 + llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll | 783 + llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll | 755 + llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll | 286 +- llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll | 286 +- llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll | 1008 +- llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll | 1008 +- llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll | 109 + llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll | 286 +- llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv64.ll | 286 +- llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll | 286 +- llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll | 286 +- llvm/test/CodeGen/RISCV/srem-lkk.ll | 22 +- llvm/test/CodeGen/RISCV/srem-vector-lkk.ll | 98 +- ...tack-realignment-with-variable-sized-objects.ll | 5 +- llvm/test/CodeGen/RISCV/stack-realignment.ll | 128 +- llvm/test/CodeGen/RISCV/vararg.ll | 40 +- llvm/test/CodeGen/SPARC/fp128-split.ll | 55 + llvm/test/CodeGen/SystemZ/misched-cutoff.ll | 51 + .../CodeGen/Thumb2/LowOverheadLoops/constbound.ll | 210 + .../Thumb2/LowOverheadLoops/tp-multiple-vpst.ll | 44 +- llvm/test/CodeGen/Thumb2/block-placement.mir | 443 + llvm/test/CodeGen/Thumb2/mve-shuffleext.ll | 267 + llvm/test/CodeGen/Thumb2/mve-vcvt.ll | 51 + llvm/test/CodeGen/Thumb2/mve-vmovnstore.ll | 52 + llvm/test/CodeGen/Thumb2/mve-vmull-loop.ll | 41 +- llvm/test/CodeGen/Thumb2/mve-vqdmulh.ll | 81 +- llvm/test/CodeGen/Thumb2/mve-vst2.ll | 23 +- llvm/test/CodeGen/VE/VELIntrinsics/vand.ll | 4 +- llvm/test/CodeGen/VE/VELIntrinsics/vld.ll | 130 +- llvm/test/CodeGen/WebAssembly/cfg-stackify-eh.ll | 95 +- llvm/test/CodeGen/WebAssembly/comparisons-f32.ll | 28 +- llvm/test/CodeGen/WebAssembly/comparisons-f64.ll | 28 +- llvm/test/CodeGen/WebAssembly/exception.ll | 68 + llvm/test/CodeGen/WebAssembly/simd-comparisons.ll | 68 +- llvm/test/CodeGen/X86/atomic-unordered.ll | 21 +- llvm/test/CodeGen/X86/atomic64.ll | 4 +- llvm/test/CodeGen/X86/avoid-sfb-offset.mir | 6 +- llvm/test/CodeGen/X86/avx512-mask-zext-bugfix.ll | 2 +- llvm/test/CodeGen/X86/avx512-trunc.ll | 20 +- llvm/test/CodeGen/X86/bmi-intrinsics-fast-isel.ll | 4 +- llvm/test/CodeGen/X86/bug47278.mir | 8 +- llvm/test/CodeGen/X86/call-rv-marker.ll | 175 + llvm/test/CodeGen/X86/combine-umin.ll | 36 +- llvm/test/CodeGen/X86/crash-O0.ll | 13 +- llvm/test/CodeGen/X86/fast-isel-call-cleanup.ll | 2 +- llvm/test/CodeGen/X86/fast-isel-constant.ll | 24 - llvm/test/CodeGen/X86/fast-isel-mem.ll | 16 +- llvm/test/CodeGen/X86/fast-isel-prolog-dbgloc.ll | 74 + llvm/test/CodeGen/X86/fast-isel-select.ll | 8 +- llvm/test/CodeGen/X86/fptosi-sat-scalar.ll | 495 +- llvm/test/CodeGen/X86/fptoui-sat-scalar.ll | 441 +- llvm/test/CodeGen/X86/haddsub-2.ll | 36 +- llvm/test/CodeGen/X86/haddsub-4.ll | 32 + llvm/test/CodeGen/X86/haddsub-shuf.ll | 46 +- llvm/test/CodeGen/X86/haddsub-undef.ll | 41 +- llvm/test/CodeGen/X86/horizontal-sum.ll | 459 +- llvm/test/CodeGen/X86/inreg.ll | 4 +- llvm/test/CodeGen/X86/known-bits-vector.ll | 12 +- llvm/test/CodeGen/X86/lit.local.cfg | 8 - llvm/test/CodeGen/X86/lvi-hardening-loads.ll | 2 +- llvm/test/CodeGen/X86/lzcnt-cmp.ll | 174 +- llvm/test/CodeGen/X86/membarrier.ll | 2 +- llvm/test/CodeGen/X86/memcpy-inline-fsrm.ll | 1 + llvm/test/CodeGen/X86/non-value-mem-operand.mir | 6 +- llvm/test/CodeGen/X86/pr32241.ll | 10 +- llvm/test/CodeGen/X86/pr32256.ll | 4 +- llvm/test/CodeGen/X86/pr32284.ll | 16 +- llvm/test/CodeGen/X86/pr32340.ll | 52 +- llvm/test/CodeGen/X86/pr32345.ll | 8 +- llvm/test/CodeGen/X86/pr32484.ll | 2 +- llvm/test/CodeGen/X86/pr44749.ll | 2 - llvm/test/CodeGen/X86/pr48727.ll | 51 + llvm/test/CodeGen/X86/psubus.ll | 510 +- llvm/test/CodeGen/X86/sdiv_fix_sat.ll | 20 +- llvm/test/CodeGen/X86/select-prof-codegen.ll | 6 +- llvm/test/CodeGen/X86/sink-local-value.ll | 2 +- llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll | 16 +- llvm/test/CodeGen/X86/statepoint-fixup-call.mir | 4 +- .../CodeGen/X86/statepoint-fixup-copy-prop-neg.mir | 6 +- llvm/test/CodeGen/X86/udiv_fix_sat.ll | 2 +- .../X86/vector-constrained-fp-intrinsics.ll | 766 +- llvm/test/CodeGen/X86/vector-pack-256.ll | 66 +- llvm/test/CodeGen/X86/vector-trunc.ll | 8 +- llvm/test/CodeGen/X86/volatile.ll | 38 +- llvm/test/CodeGen/lit.local.cfg | 7 + llvm/test/DebugInfo/COFF/lines-bb-start.ll | 1 - llvm/test/DebugInfo/Mips/delay-slot.ll | 3 +- llvm/test/DebugInfo/X86/LLVM_implicit_pointer.ll | 87 + llvm/test/DebugInfo/X86/fission-ranges.ll | 24 +- llvm/test/DebugInfo/X86/prologue-stack.ll | 2 +- llvm/test/LTO/X86/objc-arc-contract.ll | 13 + llvm/test/LTO/X86/tli-nobuiltin.ll | 31 + llvm/test/MC/AArch64/armv8.7a-ls64.s | 4 +- llvm/test/MC/AArch64/armv8.7a-xs.s | 6 +- llvm/test/MC/AArch64/lit.local.cfg | 8 + llvm/test/MC/AMDGPU/add-sub-no-carry.s | 6 +- llvm/test/MC/AMDGPU/buf-fmt-d16-packed.s | 6 +- llvm/test/MC/AMDGPU/buf-fmt-d16-unpacked.s | 6 +- llvm/test/MC/AMDGPU/ds-gfx9.s | 4 +- llvm/test/MC/AMDGPU/ds.s | 12 +- llvm/test/MC/AMDGPU/flat-gfx10.s | 4 +- llvm/test/MC/AMDGPU/flat-global.s | 10 +- llvm/test/MC/AMDGPU/flat-scratch-instructions.s | 10 +- llvm/test/MC/AMDGPU/gfx10_asm_dpp16.s | 4 +- llvm/test/MC/AMDGPU/gfx10_asm_dpp8.s | 4 +- llvm/test/MC/AMDGPU/gfx10_asm_ds.s | 4 +- llvm/test/MC/AMDGPU/gfx10_asm_flat.s | 4 +- llvm/test/MC/AMDGPU/gfx10_asm_mubuf.s | 4 +- llvm/test/MC/AMDGPU/gfx10_asm_smem.s | 4 +- llvm/test/MC/AMDGPU/gfx10_asm_sop.s | 4 +- llvm/test/MC/AMDGPU/gfx10_asm_vop1.s | 8 +- llvm/test/MC/AMDGPU/gfx10_asm_vop2.s | 4 +- llvm/test/MC/AMDGPU/gfx10_asm_vopc.s | 8 +- llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s | 8 +- llvm/test/MC/AMDGPU/gfx10_asm_vopc_sdwa.s | 8 +- llvm/test/MC/AMDGPU/gfx10_asm_vopcx.s | 4 +- llvm/test/MC/AMDGPU/hsa-metadata-kernel-args-v3.s | 6 +- llvm/test/MC/AMDGPU/hsa-metadata-kernel-args.s | 6 +- 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.../lib/Conversion/VectorToROCDL/VectorToROCDL.cpp | 16 +- mlir/lib/Dialect/Affine/Utils/Utils.cpp | 27 + mlir/lib/Dialect/CMakeLists.txt | 1 + .../PDL => lib/Dialect/Complex}/CMakeLists.txt | 0 mlir/lib/Dialect/Complex/IR/CMakeLists.txt | 14 + mlir/lib/Dialect/Complex/IR/ComplexDialect.cpp | 16 + mlir/lib/Dialect/Complex/IR/ComplexOps.cpp | 19 + mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp | 58 +- mlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp | 28 +- mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp | 154 +- mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp | 2 +- mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp | 4 +- mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp | 306 +- mlir/lib/Dialect/Linalg/IR/LinalgTypes.cpp | 3 - mlir/lib/Dialect/Linalg/Transforms/Bufferize.cpp | 13 +- mlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt | 1 + .../Linalg/Transforms/ElementwiseToLinalg.cpp | 17 +- mlir/lib/Dialect/Linalg/Transforms/Fusion.cpp | 161 +- .../Dialect/Linalg/Transforms/FusionOnTensors.cpp | 123 +- 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mlir/lib/Target/LLVMIR/ModuleTranslation.cpp | 8 +- mlir/lib/Target/LLVMIR/TypeTranslation.cpp | 27 +- mlir/lib/Target/SPIRV/CMakeLists.txt | 28 + mlir/lib/Target/SPIRV/Deserialization.cpp | 3033 - .../Target/SPIRV/Deserialization/CMakeLists.txt | 17 + .../SPIRV/Deserialization/Deserialization.cpp | 23 + .../SPIRV/Deserialization/DeserializeOps.cpp | 565 + .../Target/SPIRV/Deserialization/Deserializer.cpp | 1920 + .../Target/SPIRV/Deserialization/Deserializer.h | 613 + mlir/lib/Target/SPIRV/Serialization/CMakeLists.txt | 15 + .../SPIRV/{ => Serialization}/Serialization.cpp | 0 mlir/lib/Transforms/BufferDeallocation.cpp | 10 +- mlir/lib/Transforms/PipelineDataTransfer.cpp | 10 +- mlir/lib/Transforms/Utils/DialectConversion.cpp | 16 + .../Utils/GreedyPatternRewriteDriver.cpp | 2 +- mlir/test/Analysis/test-dominance.mlir | 4 +- mlir/test/Analysis/test-liveness.mlir | 2 +- mlir/test/Bindings/Python/CMakeLists.txt | 4 +- mlir/test/Bindings/Python/ir_affine_expr.py | 275 + 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100644 llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll create mode 100644 llvm/test/CodeGen/SPARC/fp128-split.ll create mode 100644 llvm/test/CodeGen/SystemZ/misched-cutoff.ll create mode 100644 llvm/test/CodeGen/Thumb2/LowOverheadLoops/constbound.ll create mode 100644 llvm/test/CodeGen/Thumb2/block-placement.mir create mode 100644 llvm/test/CodeGen/X86/call-rv-marker.ll delete mode 100644 llvm/test/CodeGen/X86/fast-isel-constant.ll create mode 100644 llvm/test/CodeGen/X86/fast-isel-prolog-dbgloc.ll create mode 100644 llvm/test/CodeGen/X86/pr48727.ll create mode 100644 llvm/test/CodeGen/lit.local.cfg create mode 100644 llvm/test/DebugInfo/X86/LLVM_implicit_pointer.ll create mode 100644 llvm/test/LTO/X86/objc-arc-contract.ll create mode 100644 llvm/test/LTO/X86/tli-nobuiltin.ll create mode 100644 llvm/test/MC/PowerPC/modern-aix-as.s create mode 100644 llvm/test/MachineVerifier/verifier-statepoint.mir delete mode 100644 llvm/test/Other/new-pm-module-inliner-wrapper.ll create mode 100644 llvm/test/TableGen/cast-string.td create mode 100644 llvm/test/TableGen/spurious-semi.td create mode 100644 llvm/test/Transforms/Coroutines/coro-spill-promise.ll create mode 100644 llvm/test/Transforms/DeadStoreElimination/MSSA/stores-of-existi [...] create mode 100644 llvm/test/Transforms/FunctionAttrs/willreturn.ll create mode 100644 llvm/test/Transforms/IROutliner/outlining-bitcasts.ll create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-amx-load-store.ll create mode 100644 llvm/test/Transforms/LoopIdiom/memcpy.ll create mode 100644 llvm/test/Transforms/LoopStrengthReduce/callbr-critical-edge-sp [...] create mode 100644 llvm/test/Transforms/LoopStrengthReduce/callbr-critical-edge-sp [...] create mode 100644 llvm/test/Transforms/SimpleLoopUnswitch/pipeline.ll create mode 100644 llvm/test/Transforms/SimplifyCFG/switchToSelect-domtree-preserv [...] create mode 100644 llvm/test/Transforms/UniqueInternalLinkageNames/unique-internal [...] delete mode 100644 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100644 mlir/include/mlir/Conversion/ComplexToLLVM/ComplexToLLVM.h create mode 100644 mlir/include/mlir/Conversion/TosaToLinalg/TosaToLinalg.h copy mlir/include/mlir/Dialect/{PDL => Complex}/CMakeLists.txt (100%) create mode 100644 mlir/include/mlir/Dialect/Complex/IR/CMakeLists.txt create mode 100644 mlir/include/mlir/Dialect/Complex/IR/Complex.h create mode 100644 mlir/include/mlir/Dialect/Complex/IR/ComplexBase.td create mode 100644 mlir/include/mlir/Dialect/Complex/IR/ComplexOps.td create mode 100644 mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBarrierOps.td create mode 100644 mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td create mode 100644 mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td create mode 100644 mlir/include/mlir/Dialect/StandardOps/Utils/Utils.h create mode 100644 mlir/include/mlir/TableGen/Builder.h create mode 100644 mlir/lib/Analysis/LinearTransform.cpp create mode 100644 mlir/lib/Bindings/Python/LinalgOps.td create mode 100644 mlir/lib/Bindings/Python/ShapeOps.td create mode 100644 mlir/lib/Bindings/Python/TensorOps.td create mode 100644 mlir/lib/CAPI/Dialect/CMakeLists.txt create mode 100644 mlir/lib/CAPI/Dialect/Linalg.cpp create mode 100644 mlir/lib/CAPI/Dialect/SCF.cpp create mode 100644 mlir/lib/CAPI/Dialect/Shape.cpp create mode 100644 mlir/lib/CAPI/Dialect/Standard.cpp create mode 100644 mlir/lib/CAPI/Dialect/Tensor.cpp delete mode 100644 mlir/lib/CAPI/Standard/CMakeLists.txt delete mode 100644 mlir/lib/CAPI/Standard/StandardDialect.cpp create mode 100644 mlir/lib/Conversion/ComplexToLLVM/CMakeLists.txt create mode 100644 mlir/lib/Conversion/ComplexToLLVM/ComplexToLLVM.cpp create mode 100644 mlir/lib/Conversion/TosaToLinalg/CMakeLists.txt create mode 100644 mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp create mode 100644 mlir/lib/Conversion/TosaToLinalg/TosaToLinalgPass.cpp copy mlir/{include/mlir/Dialect/PDL => lib/Dialect/Complex}/CMakeLists.txt (100%) create mode 100644 mlir/lib/Dialect/Complex/IR/CMakeLists.txt create mode 100644 mlir/lib/Dialect/Complex/IR/ComplexDialect.cpp create mode 100644 mlir/lib/Dialect/Complex/IR/ComplexOps.cpp create mode 100644 mlir/lib/Dialect/StandardOps/Utils/Utils.cpp create mode 100644 mlir/lib/TableGen/Builder.cpp create mode 100644 mlir/lib/Target/SPIRV/CMakeLists.txt delete mode 100644 mlir/lib/Target/SPIRV/Deserialization.cpp create mode 100644 mlir/lib/Target/SPIRV/Deserialization/CMakeLists.txt create mode 100644 mlir/lib/Target/SPIRV/Deserialization/Deserialization.cpp create mode 100644 mlir/lib/Target/SPIRV/Deserialization/DeserializeOps.cpp create mode 100644 mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp create mode 100644 mlir/lib/Target/SPIRV/Deserialization/Deserializer.h create mode 100644 mlir/lib/Target/SPIRV/Serialization/CMakeLists.txt rename mlir/lib/Target/SPIRV/{ => Serialization}/Serialization.cpp (100%) create mode 100644 mlir/test/Bindings/Python/ir_affine_expr.py create mode 100644 mlir/test/Conversion/ComplexToLLVM/convert-to-llvm.mlir create mode 100644 mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir create mode 100644 mlir/test/Dialect/Complex/ops.mlir create mode 100644 mlir/test/Dialect/Linalg/sparse_nd.mlir create mode 100644 mlir/test/Dialect/Linalg/sparse_vector.mlir create mode 100644 mlir/test/Dialect/SPIRV/IR/barrier-ops.mlir create mode 100644 mlir/test/Dialect/SPIRV/IR/cast-ops.mlir create mode 100644 mlir/test/Dialect/SPIRV/IR/memory-ops.mlir create mode 100644 mlir/test/Dialect/SPIRV/IR/misc-ops.mlir delete mode 100644 mlir/test/Dialect/SPIRV/IR/ops.mlir create mode 100644 mlir/test/Target/SPIRV/barrier-ops.mlir delete mode 100644 mlir/test/Target/SPIRV/barrier.mlir create mode 100644 mlir/test/Transforms/test-pattern-selective-replacement.mlir create mode 100644 mlir/test/mlir-tblgen/directive-common.td delete mode 100644 mlir/test/mlir-tblgen/openmp-common.td create mode 100644 mlir/tools/mlir-tblgen/DirectiveCommonGen.cpp delete mode 100644 mlir/tools/mlir-tblgen/OpenMPCommonGen.cpp create mode 100644 mlir/unittests/Analysis/LinearTransformTest.cpp create mode 100644 openmp/libomptarget/plugins/common/CMakeLists.txt create mode 100644 openmp/libomptarget/plugins/common/MemoryManager/CMakeLists.txt create mode 100644 openmp/libomptarget/plugins/common/MemoryManager/MemoryManager.h delete mode 100644 openmp/libomptarget/plugins/common/elf_common.c create mode 100644 openmp/libomptarget/plugins/common/elf_common/CMakeLists.txt create mode 100644 openmp/libomptarget/plugins/common/elf_common/elf_common.h delete mode 100644 openmp/libomptarget/src/MemoryManager.cpp delete mode 100644 openmp/libomptarget/src/MemoryManager.h create mode 100644 runtimes/CMakeLists.txt rename {llvm/runtimes => runtimes}/Components.cmake.in (100%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/glibc] branch linaro-local/ci/tcwg_bmk_tk1/llvm-master-arm-spec2k6-Os_LTO updated (1c426b1d59 -> 86f65dffc2)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/llvm-master-arm-spec2k6-Os_LTO in repository toolchain/ci/glibc. from 1c426b1d59 Update STATX_ATTR_DAX value from Linux 5.10. adds 7b9c3260bc support: Add xchmod wrapper adds 42dda89dcb posix: Fix return value of system if shell can not be execut [...] adds 4dddd7e9cb posix: Sync tempname with gnulib [BZ #26648] adds bf7db6d369 math: Add BZ#18980 fix back on dbl-64 cosh adds 87d583c6e8 install: Replace scripts/output-format.sed with objdump -f [ [...] adds 0400f92833 Makerules: Do not require startup files for format.lds probe object adds f430293d84 posix: consume less entropy on tempname adds 2ef23b5205 x86: Set header.feature_1 in TCB for always-on CET [BZ #27177] adds 86a4d3fa7d elf: work around a gcc bug in elf_get_dynamic_info adds efbbd9c33a ldconfig/x86: Store ISA level in cache and aux cache adds cf12900645 Use the right argument code in unnormal tests adds 7137d682eb ifuncmain6pie: Remove the circular IFUNC dependency [BZ #20019] adds d18f59bf92 Fix x86 build with --enable-tunable=no adds 2d651eb926 x86: Move x86 processor cache info to cpu_features adds cc528f9a7e math/test-tgmath2: Fix fabs failure when no long double adds 86f65dffc2 ld.so: Add --list-tunables to print tunable values No new revisions were added by this update. Summary of changes: Makerules | 16 +- NEWS | 4 + benchtests/strcoll-inputs/filelist#en_US.UTF-8 | 1 - config.make.in | 1 - configure | 19 - configure.ac | 11 - elf/Makefile | 13 + elf/cache.c | 39 +- elf/dl-cache.c | 4 + elf/dl-main.h | 2 +- elf/dl-tunables.c | 43 ++ elf/dl-tunables.h | 2 + elf/dl-usage.c | 7 +- elf/get-dynamic-info.h | 41 +- elf/ifuncmain6pie.c | 14 +- elf/ifuncmod6.c | 8 +- elf/ldconfig.c | 18 +- elf/readelflib.c | 81 +++- elf/readlib.c | 7 +- elf/rtld.c | 19 + elf/tst-glibc-hwcaps-2-cache.c | 45 ++ .../etc/ld.so.conf | 0 .../postclean.req | 0 elf/tst-glibc-hwcaps-2-cache.script | 8 + elf/tst-rtld-list-tunables.exp | 14 + elf/tst-rtld-list-tunables.sh | 34 ++ manual/tunables.texi | 38 ++ math/libm-test-driver.c | 12 +- math/libm-test-fpclassify.inc | 14 +- math/libm-test-isinf.inc | 14 +- math/libm-test-isnan.inc | 14 +- math/libm-test-issignaling.inc | 14 +- math/test-tgmath2.c | 4 +- scripts/output-format.sed | 35 -- stdlib/tst-system.c | 17 + support/Makefile | 1 + support/xchmod.c | 30 ++ support/xunistd.h | 1 + sysdeps/generic/dl-cache.h | 16 +- sysdeps/generic/dl-isa-level.h | 25 ++ sysdeps/generic/elf-read-prop.h | 34 ++ sysdeps/generic/ldconfig.h | 22 +- sysdeps/ieee754/dbl-64/e_cosh.c | 3 +- sysdeps/posix/system.c | 4 + sysdeps/posix/tempname.c | 291 +++++++------ sysdeps/unix/sysv/linux/arm/readelflib.c | 22 +- sysdeps/unix/sysv/linux/ia64/readelflib.c | 22 +- sysdeps/unix/sysv/linux/mips/readelflib.c | 22 +- sysdeps/unix/sysv/linux/powerpc/readelflib.c | 22 +- sysdeps/unix/sysv/linux/riscv/readelflib.c | 22 +- sysdeps/unix/sysv/linux/s390/readelflib.c | 22 +- sysdeps/unix/sysv/linux/sparc/readelflib.c | 22 +- sysdeps/unix/sysv/linux/x86/elf-read-prop.h | 60 +++ sysdeps/unix/sysv/linux/x86/readelflib.c | 23 +- sysdeps/unix/sysv/linux/x86_64/Makefile | 51 +++ .../unix/sysv/linux/x86_64/tst-glibc-hwcaps-2.c | 84 ++++ .../sysv/linux/x86_64/x86-64-isa-level-VALUE.c | 4 + sysdeps/x86/Makefile | 6 + sysdeps/x86/cacheinfo.c | 46 ++- sysdeps/x86/cacheinfo.h | 400 ++---------------- sysdeps/x86/cpu-features.c | 35 +- sysdeps/x86/dl-cacheinfo.h | 460 +++++++++++++++++++++ sysdeps/x86/dl-cet.c | 5 +- sysdeps/x86/dl-isa-level.h | 31 ++ sysdeps/x86/get-isa-level.h | 1 + sysdeps/x86/include/cpu-features.h | 22 + sysdeps/x86/tst-setjmp-cet.c | 1 + sysdeps/x86_64/dl-hwcaps-subdirs.c | 1 + 68 files changed, 1630 insertions(+), 794 deletions(-) create mode 100644 elf/tst-glibc-hwcaps-2-cache.c copy elf/{tst-glibc-hwcaps-cache.root => tst-glibc-hwcaps-2-cache.root}/etc/ld.so. [...] copy elf/{tst-glibc-hwcaps-cache.root => tst-glibc-hwcaps-2-cache.root}/postclean. [...] create mode 100644 elf/tst-glibc-hwcaps-2-cache.script create mode 100644 elf/tst-rtld-list-tunables.exp create mode 100755 elf/tst-rtld-list-tunables.sh delete mode 100644 scripts/output-format.sed create mode 100644 support/xchmod.c create mode 100644 sysdeps/generic/dl-isa-level.h create mode 100644 sysdeps/generic/elf-read-prop.h create mode 100644 sysdeps/unix/sysv/linux/x86/elf-read-prop.h create mode 100644 sysdeps/unix/sysv/linux/x86_64/tst-glibc-hwcaps-2.c create mode 100644 sysdeps/unix/sysv/linux/x86_64/x86-64-isa-level-VALUE.c create mode 100644 sysdeps/x86/dl-isa-level.h create mode 100644 sysdeps/x86/tst-setjmp-cet.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_bmk_tk1/llvm-master-arm-spec2k6-Os_LTO updated (8c09b788a96 -> 2c356f221bb)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/llvm-master-arm-spec2k6-Os_LTO in repository toolchain/ci/gcc. from 8c09b788a96 Make the serialized link target more verbose adds 3dd0d3ee1d2 c++, abi: Fix abi_tag attribute handling [PR98481] adds cbe9758ff49 Properly release symtab::m_clones. adds b81fbfe1eb5 aarch64: Add support for unpacked SVE shifts adds 48c7f5b8811 aarch64: Add support for unpacked SVE mult, max and min adds ab76e3db6b8 aarch64: Add general unpacked SVE conditional binary arithmetic adds 3f8b0bba035 aarch64: Add support for unpacked SVE ADR adds 907ea379559 aarch64: Add support for unpacked SVE ABD adds 7446de5a2af aarch64: Add support for unpacked SVE MULH adds 37426e0f060 aarch64: Add support for unpacked SVE conditional BIC adds a958b2fc6da aarch64: Add support for unpacked SVE ASRD adds 67fbb7f0fda Daily bump. adds ab88f360723 analyzer: fix ICE merging dereferencing unknown ptrs [PR98628] adds 640296c367f make FOR_EACH_IMM_USE_STMT safe for early exits adds 240f0a490da Delete dead code in ix86_expand_sse_comi. adds 814299a9d49 c++: -Wmissing-field-initializers in unevaluated ctx [PR98620] adds ab96073df00 MAINTAINERS: Add myself for write after approval adds ff99d05f40f configure, make: Fix up --enable-link-serialization adds 13d47c37a2c reassoc: Optimize in reassoc x < 0 && y < 0 to (x | y) < 0 [...] adds 24ea113f75c widening_mul: Fix up ICE caused by my signed multiplication [...] adds b2230210f17 gcov: add more debugging facility adds e91910d3576 options: properly compare string arguments adds 52a170b1a18 tree-optimization/98550 - fix BB vect unrolling check adds e0bec6ceac4 c++: Fix ICE with CTAD in concept [PR98611] adds cf2ac1c30af [PR97969] LRA: Transform pattern `plus (plus (hard reg, con [...] adds 25bef68902f arm: Add movmisalign patterns for MVE (PR target/97875) adds 1aff68d54c3 Fix typo in function-abi.h adds 248feb2fa2c gcov: fix printf format for 32-bit hosts adds e2aa8a5f982 libcody: Simplify configure [PR 98414, 98509] adds 728fee7a798 MAINTAINERS: Fix spacing adds 5a9cfad2de9 Avoid a couple more ICEs in print_mem_ref (PR c/98597). adds cfaaa6a1ca7 syscall: ensure openat uses variadic libc wrapper adds 6851dda2e79 Daily bump. adds abb3993e49c amdgcn: Fix subdf3 pattern adds c8812bac8ee amdgcn: Improve FP division accuracy adds 3df6fac0080 amdgcn: Fix exec register live-on-entry to BB in md-reorg adds 7993fe1877a amdgcn: Remove dead code for fixed v0 register adds b668a06e37f i386: Optimize _mm_unpacklo_epi8 of 0 vector as second argu [...] adds 3f325179b32 [PATCH v2] aarch64: Add cpu cost tables for A64FX adds 6b70fa678b1 ipa: remove a dead code adds 5d057bfeff7 i386: Add define_insn_and_split patterns for btrl [PR96938] adds ffd28c265e6 tree-optimization/98640 - fix bogus sign-extension with VN adds 4c598b038df doc: Fix typos in C++ Modules documentation adds 0db5f488486 libstdc++: Remove <debug/array> from Doxygen config adds 7875e8dc831 if-to-switch: fix also virtual phis adds b1d1e2b54c6 i386, expand: Optimize also 256-bit and 512-bit permutatati [...] adds 2b356e689c3 hurd: libgcc unwinding over signal trampolines with SIGINFO adds c23aea6edc9 gcc-changelog: Allow modifications to old ChangeLogs without entry adds f04e7e540e2 libstdc++: Fix typo in ChangeLog-2020 adds e9cb89b936f Hurd: Enable ifunc by default adds 40b371a7c2f sh: Remove match_scratch operand test adds 6d75168146f rtl-ssa: Fix reversed comparisons in accesses.h comment adds 5ab67cdee61 aarch64: Tighten condition on sve/sel* tests adds 3ddc18251a8 tree-optimization/92645 - improve SLP with existing vectors adds cf7a3353061 aarch64: Add support for unpacked SVE MLA and MAD adds 264a1269b44 aarch64: Add support for unpacked SVE MLS and MSB adds 11cbea852b0 c++: Fix cp_build_function_call_vec [PR 98626] adds a2d04f3d2c9 mklog: support define_insn_and_split format adds 285fa338b06 tree-optimization/92645 - avoid harmful early BIT_FIELD_REF [...] adds 7d7ef413ef1 gcc-changelog: Support multiline parentheses wrapping adds 8fc183ccd06 match.pd: Fold (~X | C) ^ D into (X | C) ^ (~D ^ C) if (~D [...] adds 796ead19f85 c++: Failure to lookup using-decl name [PR98231] adds 8cba7cb3202 or1k: Implement profile hook calling _mcount adds e1171c32502 or1k: Add builtin define to detect hard float adds b77f6d2fa84 or1k: Support for softfloat to emulate hw exceptions adds 6ed637c585b or1k: Add note to indicate execstack adds e40fdcc4f42 or1k: Fixup exception header data encodings adds be0851b8e93 Daily bump. adds c7f1ff01a23 aarch64: Reimplement vmovn_high_* intrinsics using builtins adds 52cd1cd1b67 aarch64: reimplement vqmovn_high* intrinsics using builtins adds 48f8d1d48f2 aarch64: Reimplememnt vmovn/vmovl intrinsics with builtins instead adds e45c41988bf vect: Account for unused IFN_LOAD_LANES results adds 8f8762a2e86 match.pd: Optimize ~(X >> Y) to ~X >> Y if ~X can be simpli [...] adds 0efdc7b31c2 i386: Fix the pmovzx SSE4.1 define_insn_and_split patterns [...] adds 08a4adcf2b6 i386: Remove reduntand assignment in i386-options.c [PR98671] adds d61d2a5f3ce c++: Fix erroneous parm comparison logic [PR 98372] adds 194a9d67be4 libstdc++: Update copyright dates on new files adds a802a2ef5f1 arm: Replace calls to __builtin_vcge* by <=,>= in arm_neon. [...] adds a512079ef40 i386: Update PR target/95021 tests adds 2182274f510 tree-optimization/98674 - improve dependence analysis adds 5ebdd53534d i386: Resolve variable shadowing in i386-options.c [PR98671] adds 77d372abec0 x86: Error on -fcf-protection with incompatible target adds 236d6a33ca6 mklog: skip unsupported files adds 7624c58c6b7 gcov: add one more pytest adds aa3d33dccb5 RTEMS: Fix Ada build for riscv adds 57a4f5e4eac libstdc++: Define function to throw filesystem_error [PR 98471] adds 6106dfb9f73 [nvptx libgomp plugin] Build only in supported configurations adds 9ac3e2feb3d libgo: update hurd support adds d0d2becf2df PR fortran/98661 - valgrind issues with error recovery adds c1a2cf88059 Revert "PR fortran/98661 - valgrind issues with error recovery" adds 9e1e6e63104 PR fortran/98661 - valgrind issues with error recovery adds 05a30af3f23 libstdc++: Implement N3644 for _GLIBCXX_DEBUG iterators adds 505caa7295b [gcn offloading] Only supported in 64-bit configurations adds 088e46b8d4d declare getpass in analyzer/sensitive-1.c test adds 6541fcadc86 use sigjmp_buf for analyzer sigsetjmp tests adds 3651c1b5c9c calibrate intervals to avoid zero in futures poll test adds bdd1b1f5552 PR fortran/93340 - fix missed substring simplifications adds f6ffd449e0c c++: Tweak g++.dg/template/pr98372.C. adds 8a18261afd9 analyzer: const fixes [PR98679] adds dea4a32b24f analyzer: fixes to -fdump-analyzer-json adds fe701195313 slp: elide intermediate nodes for complex add and avoid truncate adds 500600c7840 slp: Support optimizing load distribution adds e09173d84da slp: support complex multiply and complex multiply conjugate adds 31fac31800b slp: support complex FMA and complex FMA conjugate adds 478e571a3ee slp: support complex FMS and complex FMS conjugate adds b50df1e749b slp: Add complex operations class to share first match amon [...] adds 59832db9a71 slp: Add Tests for complex mul, mls and mla" adds f1096055854 Add GCC_EXTRA_DIAGNOSTIC_OUTPUT environment variable for fi [...] adds 02e7af1122c libstdc++: Implement N3644 for _GLIBCXX_DEBUG iterators adds 387f6c15d30 Handle fancy_abort before diagnostic initialization [PR98586] adds f1fc27b6c51 c++: Minor refactoring in process_init_constructor_record adds b95d97f1a5f jit: remove "Alpha" warning from docs adds 5fff80fd79c Daily bump. adds b0ccd3922f5 compiler: add support for reading embedcfg files adds c4eec1efae0 testsuite: Fix sed script errors in complex tests adds 2ea6f4a377e tree-optimization/98685 - fix placement of extern converts adds 7432f255b70 arm: Auto-vectorization for MVE: vshl adds bfab355012c arm: Auto-vectorization for MVE: vshr adds 0411ae7f08e libatomic, libgomp, libitc: Fix bootstrap [PR70454] adds cb60334b716 testsuite/96098 - remove redundant testcase adds 1a630642009 arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics adds d03f14c354a testsuite/96147 - remove scanning for ! vect_hw_misalign adds e1bd80fb706 testsuite/96147 - key scanning on vect_hw_misalign adds aa4ee5798fe testsuite/96147 - scan for vectorized load adds b36c9cd0947 testsuite/96147 - align vector access adds dc8475e3348 Pytest in tests: improve adds 446703ccc2c tree-optimization/96376 - do not check alignment for invari [...] adds f1d054017ef Revert "arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 [...] adds 63999d751df arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics adds f9a577927eb IBM Z: Fix linking to libatomic in target test cases adds 7f6cdaa9a8d rtl-ssa: Fix a silly typo adds f2cc526f47a recog: Fix insn_change_watermark destructor adds 5a783f42d77 aarch64: Add a minipass for fusing CC insns [PR88836] adds 492b90f33df c++: Fix langspecs with -fsyntax-only [PR98591] adds 1ba71fabb78 preprocessor: Make quoting : [PR 95253] adds 7d0df0aeb67 i386: Use cpp_define_formatted for __SIZEOF_FLOAT80__ definition adds d3959070aa4 [PATCH] aarch64: Implement vmlsl[_high]* intrinsics using builtins adds 50dbced2f37 openmp: Change the way of building of reduction array type adds adb520606ce c-family: Improve MEM_REF printing for diagnostics [PR98597] adds a3128bf0128 bootstrap: fix failing diagnostic selftest on Windows [PR98696] adds aaec739250b testsuite: Add testcase coverage for already fixed [PR96671] adds c0194736b47 gcc.dg/analyzer tests: use __builtin_alloca, not alloca.h adds cd09079cfd5 c++: Fix list-init of array of no-copy type [PR63707] adds ad260343385 AArch64: Add NEON, SVE and SVE2 RTL patterns for Multiply, [...] adds 424deca72b6 c++: Fix copy elision for base initialization adds d75199f7823 c++: Avoid redundant copy in {} init [PR98642] adds e63c2161d09 drop -dumpbase-ext from producer string adds 5c046034e3e match.pd: Optimize (x < 0) ^ (y < 0) to (x ^ y) < 0 etc. [PR96681] adds 0425f4c1b63 match.pd: Generalize the PR64309 simplifications [PR96669] adds e1efa6af61a preprocessor: Make quoting : [PR 95253] adds 9beb6d88eff c++: Fix qualified array-type construction [PR 98538] adds b90e4a97419 fortran: Fixes a bug in ISO_Fortran_binding.c. adds c029fcb5680 Reset force_source_line in final.c adds f1ad419ebfd rs6000, vector integer multiply/divide/modulo instructions adds 2f7f0d32e74 Daily bump. adds 2c356f221bb libstdc++-v3: Add -fcf-protection=none to -march=i486 No new revisions were added by this update. Summary of changes: ChangeLog | 8 + MAINTAINERS | 7 +- contrib/ChangeLog | 30 + contrib/gcc-changelog/git_commit.py | 44 +- contrib/gcc-changelog/test_email.py | 12 + contrib/gcc-changelog/test_patches.txt | 82 + contrib/mklog.py | 15 +- contrib/test_mklog.py | 42 + gcc/ChangeLog | 832 +++++++ gcc/DATESTAMP | 2 +- gcc/Makefile.in | 7 + gcc/ada/ChangeLog | 6 + gcc/ada/Makefile.rtl | 5 + gcc/analyzer/ChangeLog | 28 + gcc/analyzer/analyzer.h | 2 +- gcc/analyzer/engine.cc | 29 +- gcc/analyzer/exploded-graph.h | 4 + gcc/analyzer/pending-diagnostic.h | 2 +- gcc/analyzer/store.cc | 9 +- gcc/analyzer/store.h | 4 +- gcc/analyzer/supergraph.cc | 29 +- gcc/c-family/ChangeLog | 20 + gcc/c-family/c-pretty-print.c | 259 +- gcc/c/ChangeLog | 6 + gcc/c/c-typeck.c | 4 +- gcc/cgraphunit.c | 2 - gcc/common/config/i386/i386-common.c | 2 +- gcc/config.gcc | 6 +- gcc/config/aarch64/aarch64-cc-fusion.cc | 296 +++ gcc/config/aarch64/aarch64-cost-tables.h | 103 + gcc/config/aarch64/aarch64-passes.def | 1 + gcc/config/aarch64/aarch64-protos.h | 1 + gcc/config/aarch64/aarch64-simd-builtins.def | 23 + gcc/config/aarch64/aarch64-simd.md | 145 +- gcc/config/aarch64/aarch64-sve.md | 645 +++-- gcc/config/aarch64/aarch64-sve2.md | 42 + gcc/config/aarch64/aarch64.c | 79 +- gcc/config/aarch64/arm_neon.h | 195 +- gcc/config/aarch64/iterators.md | 119 +- gcc/config/aarch64/t-aarch64 | 6 + gcc/config/arm/arm.c | 9 + gcc/config/arm/arm.h | 40 + gcc/config/arm/arm_neon.h | 87 +- gcc/config/arm/arm_neon_builtins.def | 2 - gcc/config/arm/mve.md | 70 +- gcc/config/arm/neon.md | 78 - gcc/config/arm/vec-common.md | 81 + gcc/config/gcn/gcn-valu.md | 62 +- gcc/config/gcn/gcn.c | 28 +- gcc/config/gcn/gcn.md | 3 +- gcc/config/gcn/mkoffload.c | 260 +- gcc/config/i386/i386-builtins.c | 2 +- gcc/config/i386/i386-builtins.h | 4 - gcc/config/i386/i386-c.c | 9 +- gcc/config/i386/i386-expand.c | 31 +- gcc/config/i386/i386-options.c | 25 +- gcc/config/i386/i386-options.h | 2 +- gcc/config/i386/i386.c | 2 +- gcc/config/i386/i386.h | 6 +- gcc/config/i386/i386.md | 65 + gcc/config/i386/predicates.md | 32 + gcc/config/i386/sse.md | 189 ++ gcc/config/ia64/ia64.c | 9 + gcc/config/mips/mips.c | 9 + gcc/config/or1k/linux.h | 2 + gcc/config/or1k/or1k.h | 21 +- gcc/config/rs6000/altivec.h | 4 + gcc/config/rs6000/altivec.md | 2 - gcc/config/rs6000/rs6000-builtin.def | 21 + gcc/config/rs6000/rs6000-call.c | 53 + gcc/config/rs6000/rs6000.c | 10 + gcc/config/rs6000/rs6000.md | 5 +- gcc/config/rs6000/vsx.md | 211 +- gcc/config/sh/sh.md | 3 +- gcc/config/sparc/sparc.c | 6 + gcc/configure | 7 +- gcc/configure.ac | 7 +- gcc/cp/ChangeLog | 80 + gcc/cp/call.c | 145 +- gcc/cp/class.c | 8 + gcc/cp/cp-tree.h | 3 +- gcc/cp/decl2.c | 7 +- gcc/cp/lang-specs.h | 40 +- gcc/cp/module.cc | 4 +- gcc/cp/name-lookup.c | 10 + gcc/cp/name-lookup.h | 1 + gcc/cp/pt.c | 3 + gcc/cp/tree.c | 49 +- gcc/cp/typeck2.c | 46 +- gcc/d/ChangeLog | 10 + gcc/diagnostic.c | 189 +- gcc/diagnostic.h | 23 +- gcc/doc/extend.texi | 120 + gcc/doc/install.texi | 2 +- gcc/doc/invoke.texi | 23 +- gcc/doc/md.texi | 134 ++ gcc/doc/sourcebuild.texi | 4 + gcc/doc/tree-ssa.texi | 16 +- gcc/final.c | 1 + gcc/fortran/ChangeLog | 29 + gcc/fortran/gfortran.h | 1 + gcc/fortran/primary.c | 55 + gcc/fortran/resolve.c | 10 +- gcc/function-abi.h | 2 +- gcc/gcov.c | 43 +- gcc/gimple-if-to-switch.cc | 11 +- gcc/gimple-ssa-strength-reduction.c | 2 +- gcc/go/ChangeLog | 4 + gcc/go/Make-lang.in | 1 + gcc/go/gofrontend/MERGE | 2 +- gcc/go/gofrontend/embed.cc | 628 +++++ gcc/go/gofrontend/gogo.h | 4 + gcc/graphite-scop-detection.c | 4 +- gcc/internal-fn.def | 6 + gcc/ipa-modref.c | 4 +- gcc/ipa-pure-const.c | 8 +- gcc/ipa-sra.c | 22 +- gcc/jit/ChangeLog | 6 + gcc/jit/docs/_build/texinfo/libgccjit.texi | 10 +- gcc/jit/docs/cp/index.rst | 4 - gcc/jit/docs/index.rst | 4 - gcc/lra-eliminations.c | 28 +- gcc/match.pd | 65 +- gcc/optabs.c | 8 +- gcc/optabs.def | 6 + gcc/optc-save-gen.awk | 6 +- gcc/opts.c | 5 +- gcc/profile.c | 5 + gcc/recog.h | 8 +- gcc/rtl-ssa/accesses.h | 8 +- gcc/rtl-ssa/functions.h | 2 +- gcc/rtl-ssa/member-fns.inl | 2 +- gcc/ssa-iterators.h | 39 +- gcc/symtab-clones.h | 2 +- gcc/testsuite/ChangeLog | 510 ++++ gcc/testsuite/g++.dg/abi/abi-tag24.C | 17 + gcc/testsuite/g++.dg/cpp0x/constexpr-52830.C | 1 + gcc/testsuite/g++.dg/cpp0x/initlist-array13.C | 16 + gcc/testsuite/g++.dg/cpp1z/elide4.C | 24 + gcc/testsuite/g++.dg/cpp1z/elide5.C | 15 + gcc/testsuite/g++.dg/cpp2a/concepts-ctad1.C | 16 + gcc/testsuite/g++.dg/cpp2a/concepts-ctad2.C | 13 + gcc/testsuite/g++.dg/gcov/gcov-17.C | 40 + gcc/testsuite/g++.dg/gcov/test-gcov-17.py | 37 + gcc/testsuite/g++.dg/lookup/using63.C | 17 + gcc/testsuite/g++.dg/modules/dep-1_a.C | 4 +- gcc/testsuite/g++.dg/modules/dep-1_b.C | 4 +- gcc/testsuite/g++.dg/modules/dep-2.C | 6 +- gcc/testsuite/g++.dg/modules/pr98591.H | 3 + gcc/testsuite/g++.dg/opt/pr98550.C | 96 + gcc/testsuite/g++.dg/template/pr98372.C | 28 + gcc/testsuite/g++.dg/template/pr98538.C | 18 + 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gcc/testsuite/gcc.dg/analyzer/malloc-paths-8.c | 7 +- gcc/testsuite/gcc.dg/analyzer/pr98628.c | 19 + gcc/testsuite/gcc.dg/analyzer/sensitive-1.c | 5 + gcc/testsuite/gcc.dg/analyzer/sigsetjmp-5.c | 2 +- gcc/testsuite/gcc.dg/analyzer/sigsetjmp-6.c | 2 +- ...w-locus-GCC_EXTRA_DIAGNOSTIC_OUTPUT-fixits-v1.c | 71 + ...w-locus-GCC_EXTRA_DIAGNOSTIC_OUTPUT-fixits-v2.c | 71 + gcc/testsuite/gcc.dg/plugin/plugin.exp | 2 + gcc/testsuite/gcc.dg/pr69047.c | 4 +- gcc/testsuite/gcc.dg/torture/pr98640.c | 22 + gcc/testsuite/gcc.dg/tree-ssa/pr95731.c | 22 + gcc/testsuite/gcc.dg/tree-ssa/pr96669-1.c | 59 + gcc/testsuite/gcc.dg/tree-ssa/pr96671-1.c | 51 + gcc/testsuite/gcc.dg/tree-ssa/pr96671-2.c | 51 + gcc/testsuite/gcc.dg/tree-ssa/pr96681.c | 35 + gcc/testsuite/gcc.dg/tree-ssa/pr96688.c | 24 + gcc/testsuite/gcc.dg/tree-ssa/pr96691.c | 21 + gcc/testsuite/gcc.dg/tree-ssa/pr98455.c | 19 + gcc/testsuite/gcc.dg/tree-ssa/reassoc-37.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-54.c | 6 +- gcc/testsuite/gcc.dg/uninit-38.c | 80 +- gcc/testsuite/gcc.dg/uninit-39.c | 47 + gcc/testsuite/gcc.dg/uninit-40.c | 50 + gcc/testsuite/gcc.dg/vect/bb-slp-32.c | 1 + gcc/testsuite/gcc.dg/vect/bb-slp-9.c | 2 +- gcc/testsuite/gcc.dg/vect/bb-slp-pr68892.c | 20 - gcc/testsuite/gcc.dg/vect/bb-slp-pr98685.c | 15 + .../gcc.dg/vect/complex/complex-mla-template.c | 101 + .../gcc.dg/vect/complex/complex-mls-template.c | 101 + .../gcc.dg/vect/complex/complex-mul-template.c | 71 + .../complex/fast-math-bb-slp-complex-mla-double.c | 9 + .../complex/fast-math-bb-slp-complex-mla-float.c | 8 + .../fast-math-bb-slp-complex-mla-half-float.c | 9 + .../complex/fast-math-bb-slp-complex-mls-double.c | 9 + .../complex/fast-math-bb-slp-complex-mls-float.c | 8 + .../fast-math-bb-slp-complex-mls-half-float.c | 9 + .../complex/fast-math-bb-slp-complex-mul-double.c | 9 + .../complex/fast-math-bb-slp-complex-mul-float.c | 8 + .../fast-math-bb-slp-complex-mul-half-float.c | 9 + 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libcody/configure | 209 +- libcody/configure.ac | 15 +- libcody/dox.cfg.in | 2478 -------------------- libcody/fatal.cc | 22 - libcody/gdbinit.in | 11 - libcody/internal.hh | 3 - libcpp/ChangeLog | 5 + libcpp/mkdeps.c | 1 - libgcc/ChangeLog | 17 + libgcc/config/i386/gnu-unwind.h | 60 +- libgcc/config/or1k/sfp-machine.h | 41 +- libgfortran/ChangeLog | 6 + libgfortran/runtime/ISO_Fortran_binding.c | 3 +- libgo/Makefile.am | 2 +- libgo/Makefile.in | 2 +- libgo/go/crypto/x509/root_hurd.go | 6 + libgo/go/runtime/export_pipe2_test.go | 2 +- libgo/go/runtime/nbpipe_test.go | 2 +- libgo/go/runtime/os_hurd.go | 18 +- libgo/go/syscall/exec_linux.go | 2 +- libgo/misc/cgo/test/cthread_unix.c | 2 +- libgomp/ChangeLog | 16 + libgomp/configure | 86 +- libgomp/configure.tgt | 35 +- libgomp/plugin/configfrag.ac | 92 +- libgomp/plugin/plugin-nvptx.c | 9 - libitm/ChangeLog | 7 + libitm/configure.tgt | 37 +- libstdc++-v3/ChangeLog | 55 + libstdc++-v3/ChangeLog-2020 | 2 +- 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libcody/gdbinit.in copy libstdc++-v3/testsuite/{30_threads/barrier/2.cc => 23_containers/deque/debug/ [...] copy libstdc++-v3/testsuite/{30_threads/barrier/1.cc => 23_containers/unordered_ma [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_bmk_tk1/llvm-master-arm-spec2k6-Os_LTO updated (de6a7ee4bd -> 68b007788a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/llvm-master-arm-spec2k6-Os_LTO in repository toolchain/ci/binutils-gdb. from de6a7ee4bd asan: heap buffer overflow in _bfd_vms_slurp_egsd adds 40b119304e Re: elf: Allow mixed ordered/unordered inputs for non-reloca [...] adds 5f8c2a1507 Update config.sub and config.guess adds d750c713c9 Update libiberty with latest sources from gcc mainline adds c8bad65eee is_relocatable_executable --exclude-libs failure adds b281a04ff0 ld sysroot-prefix test fails adds b5ff370e96 Fix TUI source window drawing adds 1b6d4bb223 Redraw both spaces between line numbers and source code adds 5519536196 Prevent flickering when redrawing the TUI source window adds b09ad6eae9 libctf: do not print array declarators backwards adds 57f97d0e6d libctf, ld: CTF dumper changes for consistency adds 91e7ce2fd7 libctf, ld: more dumper improvements adds ffeece6ac2 libctf, ld: prohibit getting the size or alignment of forwards adds 37002871ac libctf, ld: dump enums: generally improve dump formatting adds 1038406a8f libctf: rip out BFD_DEPENDENCIES / BFD_LIBADD adds c59e30ed17 libctf: new testsuite adds 9bc769718d libctf: new test of enum lookups with the _next iterator adds abed0b0718 libctf: warn about information loss because of unreleased fo [...] adds 6c3a38777b libctf, include: support unnamed structure members better adds 8769046e5a libctf: remove outdated comment about parent dict importing adds abe4ca69a1 libctf: fix lookups of pointers by name in parent dicts adds 608a333d7d libctf: fix old ChangeLog typo adds b4b6ea4680 libctf, ld: fix formatting of forwards to unions and enums adds 70d3120f32 libctf, testsuite: don't run without a suitable compiler adds 0814dbfbfc libctf, testsuite: adjust for real return type of ctf_member_count adds 85dd67bd6d Automatic date update in version.in adds 0c7f5bd08c sim: h8300: simplify testsuite runner adds a2f8e947a8 sim: h8300: fix test mach markers adds c004e77f7d sim: testsuite: delete unused Make-common.in file adds 865288236d sim: fr30: delete unused testsuite adds fbc09e7af7 RISC-V: Implement support for big endian targets. adds f36ce378b4 RISC-V: Fix riscv gas/ld testsuites failures for big endian. adds 286d2f2cd7 RISC-V: Mention -mbig-endian and -mlittle-endian in doc adds 22206e847d gas APP macro tests adds 73624512cf ld rgn-at10 and rgn-at11 test adds 3677b72961 sparc-sun-solaris2 and sparc64-sun-solaris2 config adds 85f55c2b75 sparc-elf ld test fails adds 599c86c4a5 score-elf binutils-all/strip-13 fail adds 4b186f88b8 gdbsupport: common-utils.h: fix typo in header adds 3c55062cc1 gdb/testsuite: fix race in gdb.threads/signal-while-stepping [...] adds b49180acf2 Fix fixed-point binary operation type handling adds 1606216201 config.sub update broke powerpc-eabivle adds 4018f4e0fc ld pr22471 test fails adds f526791a6f Regen ld/po/BLD-POTFILES.in adds e2ede46cb2 Automatic date update in version.in adds 6987d5a1bb binutils/readelf.c: Correct grammar in comment adds d4e57b87a3 bfin: Check bfd_link_hash_indirect adds 2652cfad8d RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructio [...] adds 1861f7cfbf sim: cris: fix C tests with newer toolchains adds 9446bcf6be fix paths in ChangeLog adds 4d4490b8d7 ld: xfail riscv64*-*-* for ld-scripts/empty-address-2 tests. adds aa881ecde4 RISC-V: Add pause hint instruction. adds 78e4948694 [gdb/build] Fix gdbserver build with -fsanitize=address adds 17d60030ae Fix another path length problem opening files on Win32 systems. adds d4813f1046 Fix regression in Ada aggregate assignment adds 8e604ff077 xfail more cases of complaints about relocs in read-only sections adds dc20061339 sh-pe ld XPASSes adds 959d6a673e Fix regression in Ada do_full_match adds 3b288c8e2e m68k: Require m68020up rather than m68000up for CHK.L instruction. adds d1bcae833b ELF: Don't generate unused section symbols adds 1b0927db3c Updated French translation for the opcodes/ subdirectory. adds f478212851 libtool.m4: update GNU/Hurd test from upstream. In upstream [...] adds e904f56d02 gdb/sim: add support for exporting memory map adds bfc7d04afb sim: h8300: delete opcode caching adds a39487c668 sim: cris: use -sim with C tests for cris-elf targets adds e6c1dbbfe8 sim: cris: disable test that crashes the linker adds 0f8e278da2 sim: ChangeLog: move arch-specific entries into the arch dir adds 9a50f40e82 Automatic date update in version.in adds f4cfa91741 sim: ppc: stub out sim_memory_map adds e343681375 gdb/fortran: Correct the lval type for array elements of int [...] adds 1940319c0e [gdb] Fix internal-error in process_event_stop_test adds fb932b57cb Treat the AArch64 register id_aa64mmfr2_el1 as a core system [...] adds e84c871648 Fix places in the AArch64 opcodes library code where a call [...] adds 3c8c6de21d gdb: user variables with components of dynamic type adds ed20522215 Updated Swedish translation for the opcodes/ subdirectory adds d00f086803 gdb: add missing test for completion of invalid /FMT strings adds 6abd4cf281 gdb: check for empty strings in get_standard_cache_dir/get_s [...] adds 8fc48b7961 Pass void_context_p to parse_expression adds 46f900c065 sim: require a C11 compiler adds a7e906e8f5 Automatic date update in version.in adds 6430704567 configure regen adds aae7fcb8d7 POWER10: Add Return-Oriented Programming instructions adds b1b29aa51a elf: Verify section size for mixed ordered/unordered inputs adds ba9e922fa0 ld/x86-64: Also set LAM_U57 when setting LAM_U48 adds ce0be4070f sim: common: add missing stdlib.h for abort() adds 055bc77a80 Add Changelog entries and NEWS entries for 2.36 branch adds 573fe3fbc1 Change version number to 2.36.50 and regenerate files adds be2c78856d Update release howto with 2.37 numbers adds b5a4a01af4 sim: hw: rework code to avoid gcc warnings adds f41464416a sim: pru: fix include ordering with sim-main.h adds 0a94990bf6 ld/x86-64: Properly Handle -z lam-u48/lam-u57 adds bf470982f9 sim: enable -Werror by default for some arches adds 50df264dae sim: clean up stale AC_PREREQ refs adds f8cab0b995 sim: sh64: delete port adds f074c07d8d sim: common: clean up asprintf includes a bit adds 7eb99e5e27 sim: cr16/d10v: move storage out of header adds a9fd212a24 sim: replace rindex with strrchr adds 50ad1254d5 GCC: Pass --plugin to AR and RANLIB adds a4966cd965 Binutils: Pass --plugin to AR and RANLIB adds af019bfde9 Support the PGO build for binutils+gdb adds 66beed0227 Fix erroneous agent expression test adds bc167b6b3e Remove a use of print_expression adds 54585eee2e Avoid crash in compile_to_object adds 5834526f4b Automatic date update in version.in adds 46b1518d4c Automatic date update in version.in adds a8aa72b913 Updated translations for multiple subdirectories adds 68ed285428 sim: clean up C11 header includes adds 933306703a sim: rl78: move storage out of header adds 90e123dd60 sim: common: fix printf formats adds a0c38f0d70 sim: or1k: fix include ordering with sim-main.h adds 5c1008a41f sim: call SIM_AC_OPTION_WARNINGS(no) in remaining ports adds 9c70334dee sim: always call SIM_AC_OPTION_WARNINGS adds c0f6e439cc Add support for more MIPS variants to the linker command line. adds 82c70b08df aarch64: Remove support for CSRE adds 10dadadc5b [gdb/testsuite] Fix gdb.arch/amd64-stap-three-arg-disp.S adds 062eaacbac gdb: change jit_debug to a bool adds eef401dce1 gdb: convert solib-aix to new-style debug macros adds c6185dce03 gdb: convert aarch64 to new-style debug macros adds 254c3783fe sim: tests: get common tests working again adds eabdd87b2e Automatic date update in version.in adds 03c02f3116 GCC: Check if AR works with --plugin and rc adds 83b33c6cb9 Binutils: Check if AR works with --plugin and rc adds 44124a4683 binuitils: Check if AR is usable for LTO build adds f631b79abe sim: or1k: delete redundant SIM_AC_OPTION_INLINE call adds f220ef633c sim: common: use #error properly adds 68895f7d7e sim: README-HACKING: clean up stale run references adds 5e9e2f41eb sim: or1k: clean up stale build entries adds e998918e98 sim: or1k: fix mixing of code & decl warning adds 7c654b719d gdb/fortran: add symbol base comparison operators adds ce38f5edf1 gdb: fix debug dump of OP_BOOL expressions adds 6d104cac0a Updated translations for some subdirectories adds c2e9a4a3ed elf/x86-64: Adjust R_AMD64_DIR64/R_AMD64_DIR32 for PE/x86-64 inputs adds 18bfb5057f [gdb/testsuite] Require is_amd64_regs_target in gdb.base/dis [...] adds d546b61084 Implement a workaround for GNU mak jobserver adds 5291fe3cd1 aarch64: Add support for bfloat16 in gdb. adds b2f2ae0d6f gdb: remove pre_init_ui_hook from top.c adds 3f94e58859 [gdb/testsuite] Add have_mpx in lib/gdb.exp adds 16e9019ef7 gdb: move baud_rate and serial_parity declarations to serial.h adds fe7a351a8e gdb: move read{now,never}_symbol_files declarations to symfile.h adds 24a7f1b548 gdb: fix indentation in infrun.c adds 3034143dc6 src-release: fix indentation adds 4180301e81 Automatic date update in version.in adds 62fe7512a7 sim: watch: fix pc watchpoints on little endian host systems adds c54f3efdc2 sim: watch: fix range expression processing adds 2ce40d1a51 Add SEH support to code generated by dlltool. adds 8c4645b488 Remove sflag_info param from wild callback functions adds b209b5a6b8 SHF_LINK_ORDER fixup_link_order in ld adds 5347ed60c5 Regen Makefile.in for jobserver.m4 aclocal.m4 dependency adds 844bf810cf x86: Don't generate GOT_symbol for PLT relocations adds b634d11d61 ld: Check for ELF input before accessing ELF section data adds 54ca900277 gdb: convert jit to new-style debug macros adds 5e12f48ffb gdb: bool-ify file_is_auto_load_safe adds db972fce46 gdb: bool-ify ext_lang_auto_load_enabled and friends adds 5bf7e91b2b gdb: bool-ify users of file_is_auto_load_safe adds 506195754c gdb: bool-ify maybe_add_script_{text,file} adds fb0f5031bb gdb: turn arc_debug into a bool adds d8d1feb424 gdb: convert arc to new-style debug macros adds 4120e4885b Re: SHF_LINK_ORDER fixup_link_order in ld adds 3eeabe12c3 Automatic date update in version.in adds c9d220893e gdb: make the remote target track its own thread resume state adds bd497355ea gdb: remove target_ops::commit_resume implementation in reco [...] adds 8f66807b98 gdb: better handling of 'S' packets adds d9b1deff13 sim: watch: add basic default handler that traps adds 54780889e9 sim: h8300: drop separate eightbit memory buffer adds adb0bd8fda gas: bfin: fix build time warnings adds abad28152e gas: bfin: build lexer with -Werror adds 271bea6acd ld: tests: add -msim when testing bfin targets adds 7e0d77ef5f Fix an illegal memory access parsing a win32pstatus note wit [...] adds 116d0cf103 [gdb/testsuite] Fix gdb.base/style.exp with -m32 adds 5fae2a2c66 [gdb/breakpoint] Handle .plt.sec in in_plt_section adds 5a10699ff3 Updated translations for some subdirectories adds 8ca9c7eb67 bfin: Skip non SEC_ALLOC section for R_BFIN_FUNCDESC adds 58eadc4b69 Fix building gdb with gcc-4.x adds c14dee84dd Update my email address (long overdue!) adds 17e8913732 Add myself to gdb/MAINTAINERS adds 5aa06b1b14 Automatic date update in version.in adds 5fda40b28f gas: make [248]byte directives available everywhere adds 3624a6c15c PR26539, memory leak in inflate.c adds 37a9c3a53e sim: testsuite: allow tests to declare expected exit status adds 7cf91a2481 sim: m32r: clean up redundant test coverage adds 89bfc2a429 sim: frv: clean up redundant test coverage adds 137d6efd8a sim: mips: delete empty stub test dir adds 29fd199ed8 sim: d10v: relocate tests & clean up test harness adds bb3eddb5bd sim: testsuite: delete configure script adds dcd709e056 RISC-V: Comments tidy and improvement. adds b800637e76 RISC-V: Error and warning messages tidy. adds 1942a04836 RISC-V: Indent and GNU coding standards tidy, also aligned t [...] adds 4bb5732e27 RISC-V: Fixed the indent that caused by the previous commits [...] adds 10f92414d6 [gdb/testsuite] Fix gdb.fortran/array-slices.exp with -m32 adds 5a11fff005 gdb/tui: compare pointer to nullptr, not 0 adds e403a898b5 Automatic date update in version.in adds 1368b914e9 sim: testsuite: flatten tree adds eb6e6af8c1 PR26002 undefined symbol VER_NDX_GLOBAL vs. VER_NDX_LOCAL adds ad92f33d38 Tidy inflateEnd calls adds 68b007788a ld/x86: Add -z report-relative-reloc No new revisions were added by this update. Summary of changes: ChangeLog | 159 + Makefile.def | 4 +- Makefile.in | 81 +- Makefile.tpl | 63 +- bfd/ChangeLog | 280 + bfd/Makefile.in | 1 + bfd/aclocal.m4 | 1 + bfd/aix386-core.c | 1 + bfd/aout-target.h | 1 + bfd/bfd-in2.h | 24 +- bfd/bfdio.c | 23 +- bfd/binary.c | 1 + bfd/cisco-core.c | 2 + bfd/coff-alpha.c | 1 + bfd/coff-i386.c | 4 +- bfd/coff-ia64.c | 1 + bfd/coff-mips.c | 3 + bfd/coff-rs6000.c | 2 + bfd/coff-sh.c | 2 + bfd/coff-tic30.c | 1 + bfd/coff-tic54x.c | 26 + bfd/coff-x86_64.c | 2 + bfd/coff64-rs6000.c | 2 + bfd/coffcode.h | 3 + bfd/compress.c | 3 +- bfd/config.bfd | 17 +- bfd/configure | 87 +- bfd/configure.ac | 4 + bfd/doc/Makefile.in | 1 + bfd/elf-linker-x86.h | 3 + bfd/elf.c | 20 +- bfd/elf32-bfin.c | 245 +- bfd/elf32-i386.c | 36 + bfd/elf32-score.c | 10 +- bfd/elf32-score7.c | 10 +- bfd/elf64-x86-64.c | 33 + bfd/elfcode.h | 8 +- bfd/elflink.c | 256 +- bfd/elfnn-riscv.c | 416 +- bfd/elfxx-riscv.c | 56 +- bfd/elfxx-riscv.h | 4 +- bfd/elfxx-target.h | 6 + bfd/elfxx-x86.c | 69 +- bfd/elfxx-x86.h | 7 + bfd/hppabsd-core.c | 1 + bfd/hpux-core.c | 1 + bfd/i386msdos.c | 1 + bfd/ihex.c | 1 + bfd/irix-core.c | 1 + bfd/mach-o-target.c | 1 + bfd/mmo.c | 1 + bfd/netbsd-core.c | 1 + bfd/osf-core.c | 1 + bfd/pdp11.c | 1 + bfd/pef.c | 2 + bfd/plugin.c | 1 + bfd/po/bfd.pot | 2574 +-- bfd/po/fr.po | 2666 +-- bfd/po/pt.po | 2681 ++-- bfd/po/sr.po | 2687 ++-- bfd/po/uk.po | 2666 +-- bfd/ppcboot.c | 1 + bfd/ptrace-core.c | 1 + bfd/reloc.c | 7 + bfd/sco5-core.c | 1 + bfd/section.c | 7 +- bfd/som.c | 1 + bfd/srec.c | 2 + bfd/syms.c | 3 + bfd/targets.c | 18 + bfd/tekhex.c | 1 + bfd/trad-core.c | 1 + bfd/verilog.c | 1 + bfd/version.h | 2 +- bfd/version.m4 | 2 +- bfd/vms-alpha.c | 1 + bfd/vms-lib.c | 1 + bfd/wasm-module.c | 1 + bfd/xsym.c | 1 + binutils/BRANCHES | 1 + binutils/ChangeLog | 97 + binutils/MAINTAINERS | 6 +- binutils/Makefile.in | 1 + binutils/NEWS | 2 + binutils/README-how-to-make-a-release | 40 +- binutils/aclocal.m4 | 1 + binutils/configure | 85 +- binutils/configure.ac | 2 + binutils/dlltool.c | 50 +- binutils/doc/Makefile.in | 1 + binutils/objcopy.c | 24 + binutils/po/binutils.pot | 3317 ++-- binutils/po/fr.po | 3826 +++-- binutils/po/pt.po | 3943 ++--- binutils/po/sr.po | 3845 +++-- binutils/po/sv.po | 3804 +++-- binutils/po/uk.po | 3840 +++-- binutils/readelf.c | 10 +- binutils/testsuite/binutils-all/readelf.exp | 6 +- binutils/testsuite/binutils-all/readelf.s-64 | 2 +- .../{readelf.s-64 => readelf.s-64-unused} | 0 binutils/testsuite/binutils-all/readelf.ss | 5 +- binutils/testsuite/binutils-all/readelf.ss-64 | 5 +- .../{readelf.ss-64 => readelf.ss-64-unused} | 0 .../binutils-all/{readelf.ss => readelf.ss-unused} | 0 binutils/testsuite/lib/binutils-common.exp | 31 + config.guess | 272 +- config.sub | 638 +- config/ChangeLog | 19 + config/gcc-plugin.m4 | 40 + config/jobserver.m4 | 24 + configure | 246 +- configure.ac | 84 + cpu/ChangeLog | 4 + elfcpp/ChangeLog | 4 + gas/ChangeLog | 223 + gas/Makefile.am | 4 +- gas/Makefile.in | 5 +- gas/NEWS | 10 +- gas/aclocal.m4 | 1 + gas/config/bfin-lex.l | 5 +- gas/config/obj-elf.c | 7 +- gas/config/tc-aarch64.c | 31 - gas/config/tc-i386.c | 39 +- gas/config/tc-riscv.c | 569 +- gas/config/tc-riscv.h | 8 +- gas/configure | 85 +- gas/configure.ac | 2 + gas/configure.tgt | 4 +- gas/doc/Makefile.in | 1 + gas/doc/as.texi | 8 +- gas/doc/c-aarch64.texi | 2 - gas/doc/c-riscv.texi | 8 + gas/po/fr.po | 7239 ++++----- gas/po/gas.pot | 2131 +-- gas/po/uk.po | 7237 ++++----- gas/read.c | 6 + gas/subsegs.c | 4 + gas/testsuite/gas/aarch64/csre-invalid.d | 3 - gas/testsuite/gas/aarch64/csre-invalid.s | 6 - gas/testsuite/gas/aarch64/csre.d | 29 - gas/testsuite/gas/aarch64/csre_csr-invalid.d | 3 - gas/testsuite/gas/aarch64/csre_csr-invalid.l | 2 - gas/testsuite/gas/aarch64/csre_csr-invalid.s | 4 - gas/testsuite/gas/aarch64/csre_csr.d | 10 - gas/testsuite/gas/aarch64/csre_csr.s | 4 - gas/testsuite/gas/cfi/cfi-label.d | 4 +- gas/testsuite/gas/elf/elf.exp | 6 +- gas/testsuite/gas/elf/section2.e | 7 - .../gas/elf/{section2.e => section2.e-unused} | 0 gas/testsuite/gas/elf/symver.d | 4 - gas/testsuite/gas/i386/i386.exp | 4 + gas/testsuite/gas/i386/ilp32/elf/symver.d | 4 - gas/testsuite/gas/i386/ilp32/x86-64-size-1.d | 24 +- gas/testsuite/gas/i386/ilp32/x86-64-size-3.d | 16 +- gas/testsuite/gas/i386/ilp32/x86-64-size-5.d | 12 +- gas/testsuite/gas/i386/ilp32/x86-64-unwind.d | 6 +- gas/testsuite/gas/i386/no-got.d | 17 + gas/testsuite/gas/i386/no-got.s | 5 + gas/testsuite/gas/i386/size-1.d | 24 +- gas/testsuite/gas/i386/size-3.d | 16 +- gas/testsuite/gas/i386/svr4.d | 3 - gas/testsuite/gas/i386/x86-64-no-got.d | 17 + gas/testsuite/gas/i386/x86-64-no-got.s | 5 + gas/testsuite/gas/i386/x86-64-size-1.d | 24 +- gas/testsuite/gas/i386/x86-64-size-3.d | 16 +- gas/testsuite/gas/i386/x86-64-size-5.d | 12 +- gas/testsuite/gas/i386/x86-64-unwind.d | 10 +- gas/testsuite/gas/macros/app1.d | 1 + gas/testsuite/gas/macros/app2.d | 1 + gas/testsuite/gas/macros/app3.d | 1 + gas/testsuite/gas/macros/app4.d | 1 + gas/testsuite/gas/ppc/ppc.exp | 2 + gas/testsuite/gas/ppc/rop-checks.d | 3 + gas/testsuite/gas/ppc/rop-checks.l | 17 + gas/testsuite/gas/ppc/rop-checks.s | 18 + gas/testsuite/gas/ppc/rop.d | 27 + gas/testsuite/gas/ppc/rop.s | 21 + gas/testsuite/gas/riscv/bitmanip-insns-32.d | 37 + gas/testsuite/gas/riscv/bitmanip-insns-64.d | 55 + gas/testsuite/gas/riscv/bitmanip-insns.s | 58 + gas/testsuite/gas/riscv/li32.d | 2 +- gas/testsuite/gas/riscv/li64.d | 2 +- gas/testsuite/gas/riscv/lla32.d | 2 +- gas/testsuite/gas/riscv/lla64.d | 2 +- gas/testsuite/gas/riscv/march-ok-g2.d | 2 +- gas/testsuite/gas/riscv/march-ok-g2_p1.d | 2 +- gas/testsuite/gas/riscv/march-ok-g2p0.d | 2 +- gas/testsuite/gas/riscv/march-ok-i2p0.d | 2 +- gas/testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d | 2 +- .../gas/riscv/march-ok-nse-with-version.d | 2 +- gas/testsuite/gas/riscv/march-ok-two-nse.d | 2 +- gas/testsuite/gas/riscv/pause.d | 10 + gas/testsuite/gas/riscv/pause.s | 2 + gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 6 +- .../gas/riscv/priv-reg-fail-read-only-01.l | 136 +- .../gas/riscv/priv-reg-fail-read-only-02.l | 48 +- gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 130 +- .../gas/riscv/priv-reg-fail-version-1p10.l | 48 +- .../gas/riscv/priv-reg-fail-version-1p11.l | 46 +- .../gas/riscv/priv-reg-fail-version-1p9p1.l | 54 +- gas/testsuite/gas/sparc/sparc.exp | 34 +- gas/write.c | 43 +- gdb/ChangeLog | 246 + gdb/MAINTAINERS | 1 + gdb/aarch64-tdep.c | 94 +- gdb/ada-lang.c | 70 +- gdb/arc-linux-nat.c | 16 +- gdb/arc-linux-tdep.c | 43 +- gdb/arc-newlib-tdep.c | 11 +- gdb/arc-tdep.c | 151 +- gdb/arc-tdep.h | 7 +- gdb/arch/aarch64-insn.c | 9 +- gdb/arch/aarch64-insn.h | 5 + gdb/auto-load.c | 82 +- gdb/auto-load.h | 16 +- gdb/breakpoint.c | 164 +- gdb/compile/compile.c | 4 +- gdb/expprint.c | 9 +- gdb/expression.h | 3 +- gdb/extension-priv.h | 2 +- gdb/extension.c | 7 +- gdb/extension.h | 5 +- gdb/f-exp.y | 36 +- gdb/f-lang.c | 6 +- gdb/features/aarch64-fpu.c | 5 + gdb/features/aarch64-fpu.xml | 2 + gdb/guile/guile-internal.h | 5 +- gdb/guile/scm-auto-load.c | 5 +- gdb/infrun.c | 2 +- gdb/jit.c | 80 +- gdb/main.c | 1 + gdb/objfiles.h | 3 +- gdb/parse.c | 15 +- gdb/printcmd.c | 10 +- gdb/python/py-auto-load.c | 5 +- gdb/python/python-internal.h | 5 +- gdb/record-btrace.c | 11 - gdb/record-full.c | 10 - gdb/remote-sim.c | 18 + gdb/remote.c | 330 +- gdb/serial.c | 7 +- gdb/serial.h | 8 + gdb/solib-aix.c | 23 +- gdb/symfile.c | 10 +- gdb/symfile.h | 8 + gdb/target.h | 6 - gdb/testsuite/ChangeLog | 106 + gdb/testsuite/gdb.ada/assign_arr.exp | 3 + gdb/testsuite/gdb.ada/fixed_points.exp | 17 + .../gdb.ada/fixed_points/fixed_points.adb | 1 + gdb/testsuite/gdb.ada/fixed_points/pck.ads | 5 + gdb/testsuite/gdb.ada/voidctx.exp | 40 + gdb/testsuite/gdb.ada/voidctx/pck.adb | 27 + gdb/testsuite/gdb.ada/voidctx/pck.ads | 23 + gdb/testsuite/gdb.ada/voidctx/voidctx.adb | 31 + gdb/testsuite/gdb.arch/aarch64-fp.exp | 25 + gdb/testsuite/gdb.arch/amd64-stap-three-arg-disp.S | 5 +- gdb/testsuite/gdb.arch/i386-mpx-call.c | 78 +- gdb/testsuite/gdb.arch/i386-mpx-call.exp | 17 +- gdb/testsuite/gdb.arch/i386-mpx-map.c | 45 +- gdb/testsuite/gdb.arch/i386-mpx-map.exp | 23 +- gdb/testsuite/gdb.arch/i386-mpx-sigsegv.c | 80 +- gdb/testsuite/gdb.arch/i386-mpx-sigsegv.exp | 15 +- gdb/testsuite/gdb.arch/i386-mpx-simple_segv.c | 40 +- gdb/testsuite/gdb.arch/i386-mpx-simple_segv.exp | 15 +- gdb/testsuite/gdb.arch/i386-mpx.c | 98 +- gdb/testsuite/gdb.arch/i386-mpx.exp | 22 +- gdb/testsuite/gdb.base/completion.exp | 5 + gdb/testsuite/gdb.base/disasm-optim.exp | 2 +- gdb/testsuite/gdb.base/empty-host-env-vars.exp | 72 + gdb/testsuite/gdb.base/style.exp | 49 +- gdb/testsuite/gdb.fortran/array-slices.exp | 2 +- gdb/testsuite/gdb.fortran/debug-expr.exp | 8 + gdb/testsuite/gdb.fortran/dot-ops.exp | 30 + gdb/testsuite/gdb.fortran/intvar-array.exp | 59 + gdb/testsuite/gdb.fortran/intvar-array.f90 | 28 + gdb/testsuite/gdb.fortran/intvar-dynamic-types.exp | 97 + gdb/testsuite/gdb.fortran/intvar-dynamic-types.f90 | 32 + .../gdb.server/stop-reply-no-thread-multi.c | 77 + .../gdb.server/stop-reply-no-thread-multi.exp | 136 + .../signal-while-stepping-over-bp-other-thread.exp | 2 +- gdb/testsuite/gdb.trace/ax.exp | 2 +- gdb/testsuite/lib/gdb.exp | 75 +- gdb/top.c | 5 - gdb/top.h | 4 - gdb/tracepoint.c | 17 +- gdb/tracepoint.h | 2 +- gdb/trad-frame.c | 5 +- gdb/tui/tui-source.c | 4 +- gdb/tui/tui-winsource.c | 9 +- gdb/tui/tui.c | 4 +- gdb/valarith.c | 46 +- gdb/valops.c | 63 +- gdb/value.c | 37 +- gdb/value.h | 5 + gdbserver/ChangeLog | 7 + gdbserver/Makefile.in | 13 +- gdbsupport/ChangeLog | 10 + gdbsupport/common-utils.h | 2 +- gdbsupport/pathstuff.cc | 14 +- gold/ChangeLog | 13 + gold/po/fr.po | 730 +- gold/po/sr.po | 729 +- gold/po/uk.po | 730 +- gprof/ChangeLog | 37 + gprof/Makefile.in | 1 + gprof/aclocal.m4 | 1 + gprof/configure | 85 +- gprof/configure.ac | 2 + gprof/po/gprof.pot | 4 +- include/ChangeLog | 48 + include/ctf-api.h | 12 +- include/elf/riscv.h | 3 +- include/gdb/ChangeLog | 4 + include/gdb/remote-sim.h | 9 + include/opcode/aarch64.h | 2 - include/opcode/riscv-opc.h | 127 +- include/opcode/riscv.h | 125 +- ld/ChangeLog | 460 + ld/Makefile.am | 12 + ld/Makefile.in | 19 + ld/NEWS | 5 + ld/aclocal.m4 | 1 + ld/configure | 97 +- ld/configure.ac | 2 + ld/configure.tgt | 25 +- ld/emulparams/elf32_x86_64.sh | 1 + ld/emulparams/elf32briscv.sh | 2 + ld/emulparams/elf32briscv_ilp32.sh | 2 + ld/emulparams/elf32briscv_ilp32f.sh | 2 + ld/emulparams/elf64briscv.sh | 2 + ld/emulparams/elf64briscv_lp64.sh | 2 + ld/emulparams/elf64briscv_lp64f.sh | 2 + ld/emulparams/elf_i386.sh | 1 + ld/emulparams/elf_x86_64.sh | 1 + ld/emulparams/x86-report-relative.sh | 11 + ld/emultempl/aarch64elf.em | 2 +- ld/emultempl/armelf.em | 2 +- ld/emultempl/beos.em | 2 +- ld/emultempl/cskyelf.em | 2 +- ld/emultempl/hppaelf.em | 2 +- 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+ libctf/ctf-lookup.c | 197 +- libctf/ctf-open.c | 13 +- libctf/ctf-types.c | 280 +- libctf/ctf-util.c | 5 +- libctf/testsuite/config/default.exp | 59 + libctf/testsuite/lib/ctf-lib.exp | 414 + .../testsuite/libctf-lookup/ambiguous-struct-A.c | 8 + .../testsuite/libctf-lookup/ambiguous-struct-B.c | 5 + libctf/testsuite/libctf-lookup/ambiguous-struct.c | 51 + libctf/testsuite/libctf-lookup/ambiguous-struct.lk | 4 + libctf/testsuite/libctf-lookup/enum-ctf.c | 8 + libctf/testsuite/libctf-lookup/enum-symbol-ctf.c | 1 + libctf/testsuite/libctf-lookup/enum-symbol.c | 153 + libctf/testsuite/libctf-lookup/enum-symbol.lk | 6 + libctf/testsuite/libctf-lookup/enum.c | 78 + libctf/testsuite/libctf-lookup/enum.lk | 10 + libctf/testsuite/libctf-lookup/lookup.exp | 48 + .../testsuite/libctf-lookup/struct-iteration-ctf.c | 28 + libctf/testsuite/libctf-lookup/struct-iteration.c | 92 + libctf/testsuite/libctf-lookup/struct-iteration.lk | 24 + libctf/testsuite/libctf-lookup/struct-lookup.c | 60 + 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- sim/common/sim-options.c | 8 - sim/common/sim-profile.c | 9 - sim/common/sim-profile.h | 2 +- sim/common/sim-trace.c | 8 - sim/common/sim-utils.c | 13 - sim/common/sim-watch.c | 28 +- sim/common/syscall.c | 6 - sim/configure | 24 +- sim/configure.ac | 16 +- sim/configure.tgt | 3 - sim/cr16/ChangeLog | 23 + sim/cr16/config.in | 6 - sim/cr16/configure | 121 +- sim/cr16/configure.ac | 2 +- sim/cr16/cr16_sim.h | 4 +- sim/cr16/interp.c | 2 + sim/cr16/simops.c | 4 - sim/cris/ChangeLog | 375 + sim/cris/config.in | 9 - sim/cris/configure | 123 +- sim/cris/configure.ac | 4 +- sim/cris/dv-rv.c | 14 - sim/cris/rvdummy.c | 7 - sim/cris/sim-if.c | 2 - sim/cris/traps.c | 2 - sim/d10v/ChangeLog | 24 + sim/d10v/config.in | 6 - sim/d10v/configure | 121 +- sim/d10v/configure.ac | 2 +- sim/d10v/d10v_sim.h | 4 +- sim/d10v/interp.c | 11 +- sim/d10v/simops.c | 2 - sim/erc32/ChangeLog | 18 + sim/erc32/config.in | 6 - sim/erc32/configure | 221 +- sim/erc32/configure.ac | 1 + sim/erc32/sis.c | 2 - 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sim/m32r/config.in | 6 - sim/m32r/configure | 221 +- sim/m32r/configure.ac | 1 + sim/m32r/sim-if.c | 8 - sim/m68hc11/ChangeLog | 17 + sim/m68hc11/config.in | 6 - sim/m68hc11/configure | 121 +- sim/m68hc11/configure.ac | 2 +- sim/mcore/ChangeLog | 17 + sim/mcore/config.in | 6 - sim/mcore/configure | 121 +- sim/mcore/configure.ac | 2 +- sim/microblaze/ChangeLog | 12 + sim/microblaze/config.in | 6 - sim/microblaze/configure | 124 +- sim/mips/ChangeLog | 19 + sim/mips/config.in | 6 - sim/mips/configure | 123 +- sim/mips/configure.ac | 2 +- sim/mips/interp.c | 8 - sim/mn10300/ChangeLog | 19 + sim/mn10300/config.in | 6 - sim/mn10300/configure | 121 +- sim/mn10300/configure.ac | 2 +- sim/mn10300/interp.c | 10 - sim/mn10300/op_utils.c | 11 - sim/moxie/ChangeLog | 17 + sim/moxie/config.in | 6 - sim/moxie/configure | 121 +- sim/moxie/configure.ac | 2 +- sim/msp430/ChangeLog | 12 + sim/msp430/config.in | 6 - sim/msp430/configure | 124 +- sim/or1k/ChangeLog | 92 + sim/or1k/Makefile.in | 12 +- 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sim/ppc/tree.c | 11 - sim/pru/ChangeLog | 21 + sim/pru/config.in | 6 - sim/pru/configure | 124 +- sim/pru/configure.ac | 1 - sim/pru/sim-main.h | 2 + sim/rl78/ChangeLog | 22 + sim/rl78/config.in | 6 - sim/rl78/configure | 221 +- sim/rl78/configure.ac | 1 + sim/rl78/cpu.c | 2 + sim/rl78/cpu.h | 2 +- sim/rx/ChangeLog | 18 + sim/rx/config.in | 6 - sim/rx/configure | 221 +- sim/rx/configure.ac | 1 + sim/rx/main.c | 2 - sim/sh/ChangeLog | 19 + sim/sh/config.in | 6 - sim/sh/configure | 121 +- sim/sh/configure.ac | 2 +- sim/sh/interp.c | 12 - sim/sh64/ChangeLog | 856 - sim/sh64/Makefile.in | 150 - sim/sh64/aclocal.m4 | 119 - sim/sh64/arch.c | 67 - sim/sh64/arch.h | 216 - sim/sh64/config.in | 254 - sim/sh64/configure | 16053 ------------------- sim/sh64/configure.ac | 15 - sim/sh64/cpu.c | 564 - sim/sh64/cpu.h | 341 - sim/sh64/cpuall.h | 75 - sim/sh64/decode-compact.c | 6134 ------- sim/sh64/decode-compact.h | 279 - sim/sh64/decode-media.c | 4100 ----- sim/sh64/decode-media.h | 269 - sim/sh64/decode.h | 16 - sim/sh64/defs-compact.h | 509 - sim/sh64/defs-media.h | 920 -- sim/sh64/eng-compact.h | 34 - sim/sh64/eng-media.h | 34 - sim/sh64/eng.h | 23 - sim/sh64/mloop-compact.c | 635 - sim/sh64/mloop-media.c | 624 - sim/sh64/sem-compact-switch.c | 5210 ------ sim/sh64/sem-compact.c | 5589 ------- sim/sh64/sem-media-switch.c | 5656 ------- sim/sh64/sem-media.c | 6063 ------- sim/sh64/sh-desc.c | 3562 ---- sim/sh64/sh-desc.h | 315 - sim/sh64/sh-opc.h | 214 - sim/sh64/sh64-sim.h | 84 - sim/sh64/sh64.c | 1138 -- sim/sh64/sim-if.c | 204 - sim/sh64/sim-main.h | 72 - sim/testsuite/ChangeLog | 88 +- sim/testsuite/Makefile.in | 9 +- sim/testsuite/{sim => }/aarch64/ChangeLog | 0 sim/testsuite/{sim => }/aarch64/adds.s | 0 sim/testsuite/{sim => }/aarch64/addv.s | 0 sim/testsuite/{sim => }/aarch64/allinsn.exp | 0 sim/testsuite/{sim => }/aarch64/bit.s | 0 sim/testsuite/{sim => }/aarch64/cmtst.s | 0 sim/testsuite/{sim => }/aarch64/cnt.s | 0 sim/testsuite/{sim => }/aarch64/fcmXX.s | 0 sim/testsuite/{sim => }/aarch64/fcmp.s | 0 sim/testsuite/{sim => }/aarch64/fcsel.s | 0 sim/testsuite/{sim => }/aarch64/fcvtl.s | 0 sim/testsuite/{sim => }/aarch64/fcvtz.s | 0 sim/testsuite/{sim => }/aarch64/fminnm.s | 0 sim/testsuite/{sim => }/aarch64/fstur.s | 0 sim/testsuite/{sim => }/aarch64/ldn_multiple.s | 0 sim/testsuite/{sim => }/aarch64/ldn_single.s | 0 sim/testsuite/{sim => }/aarch64/ldnr.s | 0 sim/testsuite/{sim => }/aarch64/mla.s | 0 sim/testsuite/{sim => }/aarch64/mls.s | 0 sim/testsuite/{sim => }/aarch64/mul.s | 0 sim/testsuite/{sim => }/aarch64/pass.s | 0 sim/testsuite/{sim => }/aarch64/stn_multiple.s | 0 sim/testsuite/{sim => }/aarch64/stn_single.s | 0 sim/testsuite/{sim => }/aarch64/sumov.s | 0 sim/testsuite/{sim => }/aarch64/sumulh.s | 0 sim/testsuite/{sim => }/aarch64/tbnz.s | 0 sim/testsuite/{sim => }/aarch64/testutils.inc | 0 sim/testsuite/{sim => }/aarch64/uzp.s | 0 sim/testsuite/{sim => }/aarch64/xtl.s | 0 sim/testsuite/{sim => }/aarch64/xtn.s | 0 sim/testsuite/{sim => }/arm/ChangeLog | 0 sim/testsuite/{sim => }/arm/adc.cgs | 0 sim/testsuite/{sim => }/arm/add.cgs | 0 sim/testsuite/{sim => }/arm/allinsn.exp | 0 sim/testsuite/{sim => }/arm/and.cgs | 0 sim/testsuite/{sim => }/arm/b.cgs | 0 sim/testsuite/{sim => }/arm/bic.cgs | 0 sim/testsuite/{sim => }/arm/bl.cgs | 0 sim/testsuite/{sim => }/arm/bx.cgs | 0 sim/testsuite/{sim => }/arm/cmn.cgs | 0 sim/testsuite/{sim => }/arm/cmp.cgs | 0 sim/testsuite/{sim => }/arm/eor.cgs | 0 sim/testsuite/{sim => }/arm/hello.ms | 0 sim/testsuite/{sim => }/arm/iwmmxt/iwmmxt.exp | 0 sim/testsuite/{sim => }/arm/iwmmxt/tbcst.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/testutils.inc | 0 sim/testsuite/{sim => }/arm/iwmmxt/textrm.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tinsr.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmia.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmiaph.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmiaxy.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmovmsk.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wacc.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wadd.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/waligni.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/walignr.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wand.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wandn.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wavg2.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wcmpeq.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wcmpgt.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmac.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmadd.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmax.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmin.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmov.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmul.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wor.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wpack.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wror.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsad.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wshufh.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsll.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsra.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsrl.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsub.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckeh.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckel.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckih.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckil.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wxor.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wzero.cgs | 0 sim/testsuite/{sim => }/arm/ldm.cgs | 0 sim/testsuite/{sim => }/arm/ldr.cgs | 0 sim/testsuite/{sim => }/arm/ldrb.cgs | 0 sim/testsuite/{sim => }/arm/ldrh.cgs | 0 sim/testsuite/{sim => }/arm/ldrsb.cgs | 0 sim/testsuite/{sim => }/arm/ldrsh.cgs | 0 sim/testsuite/{sim => }/arm/misaligned1.ms | 0 sim/testsuite/{sim => }/arm/misaligned2.ms | 0 sim/testsuite/{sim => }/arm/misaligned3.ms | 0 sim/testsuite/{sim => }/arm/misc.exp | 0 sim/testsuite/{sim => }/arm/mla.cgs | 0 sim/testsuite/{sim => }/arm/mov.cgs | 0 sim/testsuite/{sim => }/arm/movw-movt.ms | 0 sim/testsuite/{sim => }/arm/mrs.cgs | 0 sim/testsuite/{sim => }/arm/msr.cgs | 0 sim/testsuite/{sim => }/arm/mul.cgs | 0 sim/testsuite/{sim => }/arm/mvn.cgs | 0 sim/testsuite/{sim => }/arm/orr.cgs | 0 sim/testsuite/{sim => }/arm/rsb.cgs | 0 sim/testsuite/{sim => }/arm/rsc.cgs | 0 sim/testsuite/{sim => }/arm/sbc.cgs | 0 sim/testsuite/{sim => }/arm/smlal.cgs | 0 sim/testsuite/{sim => }/arm/smull.cgs | 0 sim/testsuite/{sim => }/arm/stm.cgs | 0 sim/testsuite/{sim => }/arm/str.cgs | 0 sim/testsuite/{sim => }/arm/strb.cgs | 0 sim/testsuite/{sim => }/arm/strh.cgs | 0 sim/testsuite/{sim => }/arm/sub.cgs | 0 sim/testsuite/{sim => }/arm/swi.cgs | 0 sim/testsuite/{sim => }/arm/swp.cgs | 0 sim/testsuite/{sim => }/arm/swpb.cgs | 0 sim/testsuite/{sim => }/arm/teq.cgs | 0 sim/testsuite/{sim => }/arm/testutils.inc | 0 sim/testsuite/{sim => }/arm/thumb/adc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add-hd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add-hd-rs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add-rd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add-sp.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add.cgs | 0 sim/testsuite/{sim => }/arm/thumb/addi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/addi8.cgs | 0 sim/testsuite/{sim => }/arm/thumb/allthumb.exp | 0 sim/testsuite/{sim => }/arm/thumb/and.cgs | 0 sim/testsuite/{sim => }/arm/thumb/asr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/b.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bcc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bcs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/beq.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bge.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bgt.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bhi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bic.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bl-hi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bl-lo.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ble.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bls.cgs | 0 sim/testsuite/{sim => }/arm/thumb/blt.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bmi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bne.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bpl.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bvc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bvs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bx-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bx-rs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmn.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmp-hd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmp-hd-rs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmp-rd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmp.cgs | 0 sim/testsuite/{sim => }/arm/thumb/eor.cgs | 0 sim/testsuite/{sim => }/arm/thumb/lda-pc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/lda-sp.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldmia.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldr-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldr-pc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldr-sprel.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldrb-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldrb.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldrh-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldrh.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldsb.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldsh.cgs | 0 sim/testsuite/{sim => }/arm/thumb/lsl.cgs | 0 sim/testsuite/{sim => }/arm/thumb/lsr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mov-hd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mov-hd-rs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mov-rd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mov.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mul.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mvn.cgs | 0 sim/testsuite/{sim => }/arm/thumb/neg.cgs | 0 sim/testsuite/{sim => }/arm/thumb/orr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/pop-pc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/pop.cgs | 0 sim/testsuite/{sim => }/arm/thumb/push-lr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/push.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ror.cgs | 0 sim/testsuite/{sim => }/arm/thumb/sbc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/stmia.cgs | 0 sim/testsuite/{sim => }/arm/thumb/str-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/str-sprel.cgs | 0 sim/testsuite/{sim => }/arm/thumb/str.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strb-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strb.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strh-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strh.cgs | 0 sim/testsuite/{sim => }/arm/thumb/sub-sp.cgs | 0 sim/testsuite/{sim => }/arm/thumb/sub.cgs | 0 sim/testsuite/{sim => }/arm/thumb/subi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/subi8.cgs | 0 sim/testsuite/{sim => }/arm/thumb/swi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/testutils.inc | 0 sim/testsuite/{sim => }/arm/thumb/tst.cgs | 0 sim/testsuite/{sim => }/arm/tst.cgs | 0 sim/testsuite/{sim => }/arm/umlal.cgs | 0 sim/testsuite/{sim => }/arm/umull.cgs | 0 sim/testsuite/{sim => }/arm/xscale/blx.cgs | 0 sim/testsuite/{sim => }/arm/xscale/mia.cgs | 0 sim/testsuite/{sim => }/arm/xscale/miaph.cgs | 0 sim/testsuite/{sim => }/arm/xscale/miaxy.cgs | 0 sim/testsuite/{sim => }/arm/xscale/mra.cgs | 0 sim/testsuite/{sim => }/arm/xscale/testutils.inc | 0 sim/testsuite/{sim => }/arm/xscale/xscale.exp | 0 sim/testsuite/{sim => }/avr/ChangeLog | 0 sim/testsuite/{sim => }/avr/allinsn.exp | 0 sim/testsuite/{sim => }/avr/pass.s | 0 sim/testsuite/{sim => }/avr/testutils.inc | 0 sim/testsuite/{sim => }/bfin/.gitignore | 0 sim/testsuite/{sim => }/bfin/10272_small.s | 0 sim/testsuite/{sim => }/bfin/10436.s | 0 sim/testsuite/{sim => }/bfin/10622.s | 0 sim/testsuite/{sim => }/bfin/10742.s | 0 sim/testsuite/{sim => }/bfin/10799.s | 0 sim/testsuite/{sim => }/bfin/11080.s | 0 sim/testsuite/{sim => }/bfin/7641.s | 0 sim/testsuite/{sim => }/bfin/ChangeLog | 0 sim/testsuite/{sim => }/bfin/PN_generator.s | 0 sim/testsuite/{sim => }/bfin/a0.s | 0 sim/testsuite/{sim => }/bfin/a0shift.S | 0 sim/testsuite/{sim => }/bfin/a1.s | 0 sim/testsuite/{sim => }/bfin/a10.s | 0 sim/testsuite/{sim => }/bfin/a11.S | 0 sim/testsuite/{sim => }/bfin/a12.s | 0 sim/testsuite/{sim => }/bfin/a2.s | 0 sim/testsuite/{sim => }/bfin/a20.S | 0 sim/testsuite/{sim => }/bfin/a21.s | 0 sim/testsuite/{sim => }/bfin/a22.s | 0 sim/testsuite/{sim => }/bfin/a23.s | 0 sim/testsuite/{sim => }/bfin/a24.s | 0 sim/testsuite/{sim => }/bfin/a25.s | 0 sim/testsuite/{sim => }/bfin/a26.s | 0 sim/testsuite/{sim => }/bfin/a3.s | 0 sim/testsuite/{sim => }/bfin/a30.s | 0 sim/testsuite/{sim => }/bfin/a4.s | 0 sim/testsuite/{sim => }/bfin/a5.s | 0 sim/testsuite/{sim => }/bfin/a6.s | 0 sim/testsuite/{sim => }/bfin/a7.s | 0 sim/testsuite/{sim => }/bfin/a8.s | 0 sim/testsuite/{sim => }/bfin/a9.s | 0 sim/testsuite/{sim => }/bfin/abs-2.S | 0 sim/testsuite/{sim => }/bfin/abs-3.S | 0 sim/testsuite/{sim => }/bfin/abs-4.S | 0 sim/testsuite/{sim => }/bfin/abs.S | 0 sim/testsuite/{sim => }/bfin/abs_acc.s | 0 sim/testsuite/{sim => }/bfin/acc-rot.s | 0 sim/testsuite/{sim => }/bfin/acp5_19.s | 0 sim/testsuite/{sim => }/bfin/acp5_4.s | 0 sim/testsuite/{sim => }/bfin/add_imm7.s | 0 sim/testsuite/{sim => }/bfin/add_shift.S | 0 sim/testsuite/{sim => }/bfin/add_sub_acc.s | 0 sim/testsuite/{sim => }/bfin/addsub_flags.S | 0 sim/testsuite/{sim => }/bfin/algnbug1.s | 0 sim/testsuite/{sim => }/bfin/algnbug2.s | 0 sim/testsuite/{sim => }/bfin/allinsn.exp | 0 sim/testsuite/{sim => }/bfin/argc.c | 0 sim/testsuite/{sim => }/bfin/ashift.s | 0 sim/testsuite/{sim => }/bfin/ashift_flags.s | 0 sim/testsuite/{sim => }/bfin/ashift_left.s | 0 sim/testsuite/{sim => }/bfin/b0.S | 0 sim/testsuite/{sim => }/bfin/b1.s | 0 sim/testsuite/{sim => }/bfin/b2.S | 0 sim/testsuite/{sim => }/bfin/brcc.s | 0 sim/testsuite/{sim => }/bfin/brevadd.s | 0 sim/testsuite/{sim => }/bfin/byteop16m.s | 0 sim/testsuite/{sim => }/bfin/byteop16p.s | 0 sim/testsuite/{sim => }/bfin/byteop1p.s | 0 sim/testsuite/{sim => }/bfin/byteop2p.s | 0 sim/testsuite/{sim => }/bfin/byteop3p.s | 0 sim/testsuite/{sim => }/bfin/byteunpack.s | 0 .../{sim => }/bfin/c_alu2op_arith_r_sft.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_b.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_h.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_mix.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_neg.s | 0 .../{sim => }/bfin/c_alu2op_conv_toggle.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_xb.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_xh.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_divq.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_divs.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_log_l_sft.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_log_r_sft.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_shadd_1.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_shadd_2.s | 0 sim/testsuite/{sim => }/bfin/c_br_preg_killed_ac.s | 0 .../{sim => }/bfin/c_br_preg_killed_ex1.s | 0 sim/testsuite/{sim => }/bfin/c_br_preg_stall_ac.s | 0 sim/testsuite/{sim => }/bfin/c_br_preg_stall_ex1.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_bp1.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_bp2.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_bp3.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_bp4.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_bp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_bp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_nbp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_fbkwd.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_nbp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brt_bp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brt_nbp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_kills_dhits.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_kills_dmiss.s | 0 sim/testsuite/{sim => }/bfin/c_cactrl_iflush_pr.s | 0 .../{sim => }/bfin/c_cactrl_iflush_pr_pp.s | 0 sim/testsuite/{sim => }/bfin/c_calla_ljump.s | 0 sim/testsuite/{sim => }/bfin/c_calla_subr.s | 0 sim/testsuite/{sim => }/bfin/c_cc2dreg.s | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_ac.S | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_an.s | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_aq.s | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av0.S | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av1.S | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_az.s | 0 .../{sim => }/bfin/c_cc_flag_ccmv_depend.S | 0 .../{sim => }/bfin/c_cc_flagdreg_mvbrsft.s | 0 .../{sim => }/bfin/c_cc_flagdreg_mvbrsft_s1.s | 0 .../{sim => }/bfin/c_cc_flagdreg_mvbrsft_sn.s | 0 .../{sim => }/bfin/c_cc_regmvlogi_mvbrsft.s | 0 .../{sim => }/bfin/c_cc_regmvlogi_mvbrsft_s1.s | 0 .../{sim => }/bfin/c_cc_regmvlogi_mvbrsft_sn.S | 0 sim/testsuite/{sim => }/bfin/c_ccflag_a0a1.S | 0 sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr_uu.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3_uu.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3_uu.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr_uu.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_cc_pr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_ncc_pr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_comp3op_dr_and_dr.s | 0 .../{sim => }/bfin/c_comp3op_dr_minus_dr.s | 0 sim/testsuite/{sim => }/bfin/c_comp3op_dr_mix.s | 0 sim/testsuite/{sim => }/bfin/c_comp3op_dr_or_dr.s | 0 .../{sim => }/bfin/c_comp3op_dr_plus_dr.s | 0 sim/testsuite/{sim => }/bfin/c_comp3op_dr_xor_dr.s | 0 .../{sim => }/bfin/c_comp3op_pr_plus_pr_sh1.s | 0 .../{sim => }/bfin/c_comp3op_pr_plus_pr_sh2.s | 0 .../{sim => }/bfin/c_compi2opd_dr_add_i7_n.s | 0 .../{sim => }/bfin/c_compi2opd_dr_add_i7_p.s | 0 .../{sim => }/bfin/c_compi2opd_dr_eq_i7_n.s | 0 .../{sim => }/bfin/c_compi2opd_dr_eq_i7_p.s | 0 sim/testsuite/{sim => }/bfin/c_compi2opd_flags.S | 0 sim/testsuite/{sim => }/bfin/c_compi2opd_flags_2.S | 0 .../{sim => }/bfin/c_compi2opp_pr_add_i7_n.s | 0 .../{sim => }/bfin/c_compi2opp_pr_add_i7_p.s | 0 .../{sim => }/bfin/c_compi2opp_pr_eq_i7_n.s | 0 .../{sim => }/bfin/c_compi2opp_pr_eq_i7_p.s | 0 .../{sim => }/bfin/c_dagmodik_lnz_imgebl.s | 0 .../{sim => }/bfin/c_dagmodik_lnz_imltbl.s | 0 .../{sim => }/bfin/c_dagmodik_lz_inc_dec.s | 0 .../{sim => }/bfin/c_dagmodim_lnz_imgebl.s | 0 .../{sim => }/bfin/c_dagmodim_lnz_imltbl.s | 0 .../{sim => }/bfin/c_dagmodim_lz_inc_dec.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_a0_pm_a1.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_a0a1s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_a_abs_a.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_a_neg_a.s | 0 .../{sim => }/bfin/c_dsp32alu_aa_absabs.s | 0 .../{sim => }/bfin/c_dsp32alu_aa_negneg.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_abs.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_absabs.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_alhwx.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_awx.s | 0 .../{sim => }/bfin/c_dsp32alu_byteop1ew.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop2.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop3.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_bytepack.s | 0 .../{sim => }/bfin/c_dsp32alu_byteunpack.s | 0 .../{sim => }/bfin/c_dsp32alu_disalnexcpt.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_max.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_maxmax.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_min.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_minmin.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_mix.s | 0 .../{sim => }/bfin/c_dsp32alu_r_lh_a0pa1.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_r_negneg.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_p.s | 0 .../{sim => }/bfin/c_dsp32alu_rh_rnd12_m.s | 0 .../{sim => }/bfin/c_dsp32alu_rh_rnd12_p.s | 0 .../{sim => }/bfin/c_dsp32alu_rh_rnd20_m.s | 0 .../{sim => }/bfin/c_dsp32alu_rh_rnd20_p.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_p.s | 0 .../{sim => }/bfin/c_dsp32alu_rl_rnd12_m.s | 0 .../{sim => }/bfin/c_dsp32alu_rl_rnd12_p.s | 0 .../{sim => }/bfin/c_dsp32alu_rl_rnd20_m.s | 0 .../{sim => }/bfin/c_dsp32alu_rl_rnd20_p.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rlh_rnd.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rm.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rmm.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rmp.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rp.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rpm.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rpp.s | 0 .../{sim => }/bfin/c_dsp32alu_rr_lph_a1a0.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm_aa.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp.s | 0 .../{sim => }/bfin/c_dsp32alu_rrpmmp_sft.s | 0 .../{sim => }/bfin/c_dsp32alu_rrpmmp_sft_x.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm.s | 0 .../{sim => }/bfin/c_dsp32alu_rrppmm_sft.s | 0 .../{sim => }/bfin/c_dsp32alu_rrppmm_sft_x.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_saa.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_sat_aa.S | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_search.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_sgn.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0.s | 0 .../{sim => }/bfin/c_dsp32mac_a1a0_iuw32.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_i.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_ih.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_is.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_iu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_t.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_tu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_i.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_ih.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_is.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_iu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_t.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_tu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0.s | 0 .../{sim => }/bfin/c_dsp32mac_dr_a1a0_iutsh.s | 0 .../{sim => }/bfin/c_dsp32mac_dr_a1a0_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_mix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a0_i.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a0_is.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a0_m.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a0_s.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a0_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1_i.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1_is.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1_m.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1_s.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1_u.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0_i.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0_is.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0_m.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0_s.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_mix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_i.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_ih.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_is.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_iu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_i.s | 0 .../{sim => }/bfin/c_dsp32mult_dr_m_iutsh.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_t.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_mix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_t.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_tu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_i.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_is.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m.s | 0 .../{sim => }/bfin/c_dsp32mult_pair_m_i.s | 0 .../{sim => }/bfin/c_dsp32mult_pair_m_is.s | 0 .../{sim => }/bfin/c_dsp32mult_pair_m_s.s | 0 .../{sim => }/bfin/c_dsp32mult_pair_m_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_a0alr.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_af.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_af_s.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_ln.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_ln_s.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_lp.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_lp_s.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_rn.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_rn_s.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_rp.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_rp_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh_s.s | 0 .../{sim => }/bfin/c_dsp32shift_align16.s | 0 .../{sim => }/bfin/c_dsp32shift_align24.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_align8.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_amix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_bitmux.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_bxor.s | 0 .../{sim => }/bfin/c_dsp32shift_expadj_h.s | 0 .../{sim => }/bfin/c_dsp32shift_expadj_l.s | 0 .../{sim => }/bfin/c_dsp32shift_expadj_r.s | 0 .../{sim => }/bfin/c_dsp32shift_expexp_r.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_fdepx.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_fextx.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_lf.s | 0 .../{sim => }/bfin/c_dsp32shift_lhalf_ln.s | 0 .../{sim => }/bfin/c_dsp32shift_lhalf_lp.s | 0 .../{sim => }/bfin/c_dsp32shift_lhalf_rn.s | 0 .../{sim => }/bfin/c_dsp32shift_lhalf_rp.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_lhh.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_lmix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_ones.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_pack.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_rot.s | 0 .../{sim => }/bfin/c_dsp32shift_rot_mix.s | 0 .../{sim => }/bfin/c_dsp32shift_signbits_r.s | 0 .../{sim => }/bfin/c_dsp32shift_signbits_rh.s | 0 .../{sim => }/bfin/c_dsp32shift_signbits_rl.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_vmax.s | 0 .../{sim => }/bfin/c_dsp32shift_vmaxvmax.s | 0 .../{sim => }/bfin/c_dsp32shiftim_a0alr.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af_s.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_ln.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_ln_s.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_lp.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_lp_s.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_rn.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_rn_s.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_rp.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_rp_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahh_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_amix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lf.s | 0 .../{sim => }/bfin/c_dsp32shiftim_lhalf_ln.s | 0 .../{sim => }/bfin/c_dsp32shiftim_lhalf_lp.s | 0 .../{sim => }/bfin/c_dsp32shiftim_lhalf_rn.s | 0 .../{sim => }/bfin/c_dsp32shiftim_lhalf_rp.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhh.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lmix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_rot.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_i.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ipp.s | 0 .../{sim => }/bfin/c_dspldst_ld_dr_ippm.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_i.s | 0 .../{sim => }/bfin/c_dspldst_ld_drhi_ipp.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_i.s | 0 .../{sim => }/bfin/c_dspldst_ld_drlo_ipp.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_i.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ipp.s | 0 .../{sim => }/bfin/c_dspldst_st_dr_ippm.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_i.s | 0 .../{sim => }/bfin/c_dspldst_st_drhi_ipp.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_i.s | 0 .../{sim => }/bfin/c_dspldst_st_drlo_ipp.s | 0 sim/testsuite/{sim => }/bfin/c_except_illopcode.S | 0 sim/testsuite/{sim => }/bfin/c_except_sys_sstep.S | 0 sim/testsuite/{sim => }/bfin/c_except_user_mode.S | 0 sim/testsuite/{sim => }/bfin/c_interr_disable.S | 0 .../{sim => }/bfin/c_interr_disable_enable.S | 0 sim/testsuite/{sim => }/bfin/c_interr_excpt.S | 0 .../{sim => }/bfin/c_interr_loopsetup_stld.S | 0 sim/testsuite/{sim => }/bfin/c_interr_nested.S | 0 sim/testsuite/{sim => }/bfin/c_interr_nmi.S | 0 sim/testsuite/{sim => }/bfin/c_interr_pending.S | 0 sim/testsuite/{sim => }/bfin/c_interr_pending_2.S | 0 sim/testsuite/{sim => }/bfin/c_interr_timer.S | 0 .../{sim => }/bfin/c_interr_timer_reload.S | 0 .../{sim => }/bfin/c_interr_timer_tcount.S | 0 .../{sim => }/bfin/c_interr_timer_tscale.S | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_drhi.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_drlo.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_ibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_ibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_ibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_dr.s | 0 .../{sim => }/bfin/c_ldimmhalf_lzhi_ibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_pibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xb.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xb.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xh.s | 0 .../{sim => }/bfin/c_ldst_ld_d_p_ppmm_hbx.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xb.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_mm.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_pp.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_p.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_mm.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_pp.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xb.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_st_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_ld_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_ld_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_st_dr_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_st_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_st_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstiifp_st_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstiifp_st_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_hi.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_lo.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_h_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_lohi.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_hi.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_lo.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_st_lohi.s | 0 sim/testsuite/{sim => }/bfin/c_linkage.s | 0 .../{sim => }/bfin/c_logi2op_alshft_mix.s | 0 .../{sim => }/bfin/c_logi2op_arith_shft.s | 0 sim/testsuite/{sim => }/bfin/c_logi2op_bitclr.s | 0 sim/testsuite/{sim => }/bfin/c_logi2op_bitset.s | 0 sim/testsuite/{sim => }/bfin/c_logi2op_bittgl.s | 0 sim/testsuite/{sim => }/bfin/c_logi2op_bittst.s | 0 .../{sim => }/bfin/c_logi2op_log_l_shft.s | 0 .../{sim => }/bfin/c_logi2op_log_l_shft_astat.S | 0 .../{sim => }/bfin/c_logi2op_log_r_shft.s | 0 .../{sim => }/bfin/c_logi2op_log_r_shft_astat.S | 0 sim/testsuite/{sim => }/bfin/c_logi2op_nbittst.s | 0 sim/testsuite/{sim => }/bfin/c_loopsetup_nested.s | 0 .../{sim => }/bfin/c_loopsetup_nested_bot.s | 0 .../{sim => }/bfin/c_loopsetup_nested_prelc.s | 0 .../{sim => }/bfin/c_loopsetup_nested_top.s | 0 sim/testsuite/{sim => }/bfin/c_loopsetup_overlap.s | 0 .../{sim => }/bfin/c_loopsetup_preg_div2_lc0.s | 0 .../{sim => }/bfin/c_loopsetup_preg_div2_lc1.s | 0 .../{sim => }/bfin/c_loopsetup_preg_lc0.s | 0 .../{sim => }/bfin/c_loopsetup_preg_lc1.s | 0 .../{sim => }/bfin/c_loopsetup_preg_stld.s | 0 sim/testsuite/{sim => }/bfin/c_loopsetup_prelc.s | 0 .../{sim => }/bfin/c_loopsetup_topbotcntr.s | 0 sim/testsuite/{sim => }/bfin/c_mmr_interr_ctl.s | 0 sim/testsuite/{sim => }/bfin/c_mmr_loop.S | 0 .../{sim => }/bfin/c_mmr_loop_user_except.S | 0 .../{sim => }/bfin/c_mmr_ppop_illegal_adr.S | 0 .../{sim => }/bfin/c_mmr_ppopm_illegal_adr.S | 0 sim/testsuite/{sim => }/bfin/c_mmr_timer.S | 0 sim/testsuite/{sim => }/bfin/c_mode_supervisor.S | 0 sim/testsuite/{sim => }/bfin/c_mode_user.S | 0 .../{sim => }/bfin/c_mode_user_superivsor.S | 0 .../{sim => }/bfin/c_multi_issue_dsp_ld_ld.s | 0 .../{sim => }/bfin/c_multi_issue_dsp_ldst_1.s | 0 .../{sim => }/bfin/c_multi_issue_dsp_ldst_2.s | 0 .../{sim => }/bfin/c_progctrl_call_pcpr.s | 0 sim/testsuite/{sim => }/bfin/c_progctrl_call_pr.s | 0 .../{sim => }/bfin/c_progctrl_clisti_interr.S | 0 .../{sim => }/bfin/c_progctrl_csync_mmr.S | 0 .../{sim => }/bfin/c_progctrl_except_rtx.S | 0 sim/testsuite/{sim => }/bfin/c_progctrl_excpt.S | 0 .../{sim => }/bfin/c_progctrl_jump_pcpr.s | 0 sim/testsuite/{sim => }/bfin/c_progctrl_jump_pr.s | 0 sim/testsuite/{sim => }/bfin/c_progctrl_nop.s | 0 .../{sim => }/bfin/c_progctrl_raise_rt_i_n.S | 0 sim/testsuite/{sim => }/bfin/c_progctrl_rts.s | 0 sim/testsuite/{sim => }/bfin/c_ptr2op_pr_neg_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ptr2op_pr_sft_2_1.s | 0 .../{sim => }/bfin/c_ptr2op_pr_shadd_1_2.s | 0 .../{sim => }/bfin/c_pushpopmultiple_dp.s | 0 .../{sim => }/bfin/c_pushpopmultiple_dp_pair.s | 0 .../{sim => }/bfin/c_pushpopmultiple_dreg.s | 0 .../{sim => }/bfin/c_pushpopmultiple_preg.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_acc_acc.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_dag_lz_dep.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_dr_acc_acc.s | 0 .../{sim => }/bfin/c_regmv_dr_dep_nostall.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_dr_dr.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_dr_imlb.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_dr_pr.s | 0 .../{sim => }/bfin/c_regmv_imlb_dep_nostall.s | 0 .../{sim => }/bfin/c_regmv_imlb_dep_stall.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_imlb_dr.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_imlb_imlb.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_imlb_pr.s | 0 .../{sim => }/bfin/c_regmv_pr_dep_nostall.s | 0 .../{sim => }/bfin/c_regmv_pr_dep_stall.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_pr_dr.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_pr_imlb.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_pr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_seq_ac_raise_mv.S | 0 .../{sim => }/bfin/c_seq_ac_raise_mv_ppop.S | 0 .../{sim => }/bfin/c_seq_ac_regmv_pushpop.S | 0 .../{sim => }/bfin/c_seq_dec_raise_pushpop.S | 0 .../{sim => }/bfin/c_seq_ex1_brcc_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex1_call_mv_pop.S | 0 sim/testsuite/{sim => }/bfin/c_seq_ex1_j_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex1_raise_brcc_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex1_raise_call_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex1_raise_j_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex2_brcc_mp_mv_pop.S | 0 sim/testsuite/{sim => }/bfin/c_seq_ex2_mmr_mvpop.S | 0 .../{sim => }/bfin/c_seq_ex2_mmrj_mvpop.S | 0 .../{sim => }/bfin/c_seq_ex2_raise_mmr_mvpop.S | 0 .../{sim => }/bfin/c_seq_ex2_raise_mmrj_mvpop.S | 0 .../{sim => }/bfin/c_seq_ex3_ls_brcc_mvp.S | 0 .../{sim => }/bfin/c_seq_ex3_ls_mmr_mvp.S | 0 .../{sim => }/bfin/c_seq_ex3_ls_mmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_cs_lsmmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_rti_lsmmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_rtn_lsmmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_rtx_lsmmrj_mvp.S | 0 sim/testsuite/{sim => }/bfin/c_ujump.s | 0 sim/testsuite/{sim => }/bfin/cc-alu.S | 0 sim/testsuite/{sim => }/bfin/cc-astat-bits.s | 0 sim/testsuite/{sim => }/bfin/cc0.s | 0 sim/testsuite/{sim => }/bfin/cc1.s | 0 sim/testsuite/{sim => }/bfin/cc5.S | 0 sim/testsuite/{sim => }/bfin/cec-exact-exception.S | 0 sim/testsuite/{sim => }/bfin/cec-ifetch.S | 0 sim/testsuite/{sim => }/bfin/cec-multi-pending.S | 0 sim/testsuite/{sim => }/bfin/cec-no-snen-reti.S | 0 .../{sim => }/bfin/cec-non-operating-env.s | 0 sim/testsuite/{sim => }/bfin/cec-raise-reti.S | 0 sim/testsuite/{sim => }/bfin/cec-snen-reti.S | 0 sim/testsuite/{sim => }/bfin/cec-syscfg-ssstep.S | 0 sim/testsuite/{sim => }/bfin/cec-system-call.S | 0 sim/testsuite/{sim => }/bfin/cir.s | 0 sim/testsuite/{sim => }/bfin/cir1.s | 0 sim/testsuite/{sim => }/bfin/cli-sti.s | 0 sim/testsuite/{sim => }/bfin/cmpacc.s | 0 sim/testsuite/{sim => }/bfin/cmpdreg.S | 0 sim/testsuite/{sim => }/bfin/compare.s | 0 sim/testsuite/{sim => }/bfin/conv_enc_gen.s | 0 sim/testsuite/{sim => }/bfin/cycles.s | 0 sim/testsuite/{sim => }/bfin/d0.s | 0 sim/testsuite/{sim => }/bfin/d1.s | 0 sim/testsuite/{sim => }/bfin/d2.s | 0 .../{sim => }/bfin/dbg_brprd_ntkn_src_kill.S | 0 .../{sim => }/bfin/dbg_brtkn_nprd_src_kill.S | 0 sim/testsuite/{sim => }/bfin/dbg_jmp_src_kill.S | 0 sim/testsuite/{sim => }/bfin/dbg_tr_basic.S | 0 sim/testsuite/{sim => }/bfin/dbg_tr_simplejp.S | 0 sim/testsuite/{sim => }/bfin/dbg_tr_tbuf0.S | 0 sim/testsuite/{sim => }/bfin/dbg_tr_umode.S | 0 .../{sim => }/bfin/disalnexcpt_implicit.S | 0 sim/testsuite/{sim => }/bfin/div0.s | 0 sim/testsuite/{sim => }/bfin/divq.s | 0 sim/testsuite/{sim => }/bfin/dotproduct.s | 0 sim/testsuite/{sim => }/bfin/dotproduct2.s | 0 sim/testsuite/{sim => }/bfin/double_prec_mult.s | 0 sim/testsuite/{sim => }/bfin/dsp_a4.s | 0 sim/testsuite/{sim => }/bfin/dsp_a7.s | 0 sim/testsuite/{sim => }/bfin/dsp_a8.s | 0 sim/testsuite/{sim => }/bfin/dsp_d0.s | 0 sim/testsuite/{sim => }/bfin/dsp_d1.s | 0 sim/testsuite/{sim => }/bfin/dsp_neg.S | 0 sim/testsuite/{sim => }/bfin/dsp_s1.s | 0 sim/testsuite/{sim => }/bfin/e0.s | 0 sim/testsuite/{sim => }/bfin/edn_snafu.s | 0 sim/testsuite/{sim => }/bfin/eu_dsp32mac_s.s | 0 sim/testsuite/{sim => }/bfin/events.s | 0 sim/testsuite/{sim => }/bfin/f221.s | 0 sim/testsuite/{sim => }/bfin/fact.s | 0 sim/testsuite/{sim => }/bfin/fir.s | 0 sim/testsuite/{sim => }/bfin/fsm.s | 0 sim/testsuite/{sim => }/bfin/greg2.s | 0 sim/testsuite/{sim => }/bfin/hwloop-bits.S | 0 sim/testsuite/{sim => }/bfin/hwloop-branch-in.s | 0 sim/testsuite/{sim => }/bfin/hwloop-branch-out.s | 0 sim/testsuite/{sim => }/bfin/hwloop-lt-bits.s | 0 sim/testsuite/{sim => }/bfin/hwloop-nested.s | 0 sim/testsuite/{sim => }/bfin/i0.s | 0 sim/testsuite/{sim => }/bfin/iir.s | 0 sim/testsuite/{sim => }/bfin/issue103.s | 0 sim/testsuite/{sim => }/bfin/issue109.s | 0 sim/testsuite/{sim => }/bfin/issue112.s | 0 sim/testsuite/{sim => }/bfin/issue113.s | 0 sim/testsuite/{sim => }/bfin/issue117.s | 0 sim/testsuite/{sim => }/bfin/issue118.s | 0 sim/testsuite/{sim => }/bfin/issue119.s | 0 sim/testsuite/{sim => }/bfin/issue121.s | 0 sim/testsuite/{sim => }/bfin/issue123.s | 0 sim/testsuite/{sim => }/bfin/issue124.s | 0 sim/testsuite/{sim => }/bfin/issue125.s | 0 sim/testsuite/{sim => }/bfin/issue126.s | 0 sim/testsuite/{sim => }/bfin/issue127.s | 0 sim/testsuite/{sim => }/bfin/issue129.s | 0 sim/testsuite/{sim => }/bfin/issue139.S | 0 sim/testsuite/{sim => }/bfin/issue140.S | 0 sim/testsuite/{sim => }/bfin/issue142.s | 0 sim/testsuite/{sim => }/bfin/issue144.s | 0 sim/testsuite/{sim => }/bfin/issue146.S | 0 sim/testsuite/{sim => }/bfin/issue175.s | 0 sim/testsuite/{sim => }/bfin/issue205.s | 0 sim/testsuite/{sim => }/bfin/issue257.s | 0 sim/testsuite/{sim => }/bfin/issue272.S | 0 sim/testsuite/{sim => }/bfin/issue83.s | 0 sim/testsuite/{sim => }/bfin/issue89.s | 0 sim/testsuite/{sim => }/bfin/l0.s | 0 sim/testsuite/{sim => }/bfin/l0shift.s | 0 sim/testsuite/{sim => }/bfin/l2_loop.s | 0 sim/testsuite/{sim => }/bfin/link-2.s | 0 sim/testsuite/{sim => }/bfin/link.s | 0 sim/testsuite/{sim => }/bfin/lmu_cplb_multiple0.S | 0 sim/testsuite/{sim => }/bfin/lmu_cplb_multiple1.S | 0 sim/testsuite/{sim => }/bfin/lmu_excpt_align.S | 0 sim/testsuite/{sim => }/bfin/lmu_excpt_default.S | 0 sim/testsuite/{sim => }/bfin/lmu_excpt_illaddr.S | 0 sim/testsuite/{sim => }/bfin/lmu_excpt_prot0.S | 0 sim/testsuite/{sim => }/bfin/lmu_excpt_prot1.S | 0 sim/testsuite/{sim => }/bfin/load.s | 0 sim/testsuite/{sim => }/bfin/logic.s | 0 sim/testsuite/{sim => }/bfin/loop_snafu.s | 0 sim/testsuite/{sim => }/bfin/loop_strncpy.s | 0 sim/testsuite/{sim => }/bfin/lp0.s | 0 sim/testsuite/{sim => }/bfin/lp1.s | 0 sim/testsuite/{sim => }/bfin/lsetup.s | 0 sim/testsuite/{sim => }/bfin/m0boundary.s | 0 sim/testsuite/{sim => }/bfin/m1.S | 0 sim/testsuite/{sim => }/bfin/m10.s | 0 sim/testsuite/{sim => }/bfin/m11.s | 0 sim/testsuite/{sim => }/bfin/m12.s | 0 sim/testsuite/{sim => }/bfin/m13.s | 0 sim/testsuite/{sim => }/bfin/m14.s | 0 sim/testsuite/{sim => }/bfin/m15.s | 0 sim/testsuite/{sim => }/bfin/m16.s | 0 sim/testsuite/{sim => }/bfin/m17.s | 0 sim/testsuite/{sim => }/bfin/m2.s | 0 sim/testsuite/{sim => }/bfin/m3.s | 0 sim/testsuite/{sim => }/bfin/m4.s | 0 sim/testsuite/{sim => }/bfin/m5.s | 0 sim/testsuite/{sim => }/bfin/m6.s | 0 sim/testsuite/{sim => }/bfin/m7.s | 0 sim/testsuite/{sim => }/bfin/m8.s | 0 sim/testsuite/{sim => }/bfin/m9.s | 0 sim/testsuite/{sim => }/bfin/mac2halfreg.S | 0 sim/testsuite/{sim => }/bfin/math.s | 0 sim/testsuite/{sim => }/bfin/max_min_flags.s | 0 sim/testsuite/{sim => }/bfin/mc_s2.s | 0 .../{sim => }/bfin/mdma-32bit-1d-neg-count.c | 0 sim/testsuite/{sim => }/bfin/mdma-32bit-1d.c | 0 .../{sim => }/bfin/mdma-8bit-1d-neg-count.c | 0 sim/testsuite/{sim => }/bfin/mdma-8bit-1d.c | 0 sim/testsuite/{sim => }/bfin/mdma-skel.h | 0 sim/testsuite/{sim => }/bfin/mem3.s | 0 sim/testsuite/{sim => }/bfin/mmr-exception.s | 0 sim/testsuite/{sim => }/bfin/move.s | 0 sim/testsuite/{sim => }/bfin/msa_acp_5.10.S | 0 sim/testsuite/{sim => }/bfin/msa_acp_5.12_1.S | 0 sim/testsuite/{sim => }/bfin/msa_acp_5.12_2.S | 0 sim/testsuite/{sim => }/bfin/msa_acp_5_10.s | 0 sim/testsuite/{sim => }/bfin/mult.s | 0 sim/testsuite/{sim => }/bfin/neg-2.S | 0 sim/testsuite/{sim => }/bfin/neg-3.S | 0 sim/testsuite/{sim => }/bfin/neg.S | 0 sim/testsuite/{sim => }/bfin/nshift.s | 0 sim/testsuite/{sim => }/bfin/pr.s | 0 sim/testsuite/{sim => }/bfin/push-pop-multiple.s | 0 sim/testsuite/{sim => }/bfin/push-pop.s | 0 sim/testsuite/{sim => }/bfin/pushpopreg_1.s | 0 sim/testsuite/{sim => }/bfin/quadaddsub.s | 0 sim/testsuite/{sim => }/bfin/random_0001.s | 0 sim/testsuite/{sim => }/bfin/random_0002.S | 0 sim/testsuite/{sim => }/bfin/random_0003.S | 0 sim/testsuite/{sim => }/bfin/random_0004.S | 0 sim/testsuite/{sim => }/bfin/random_0005.S | 0 sim/testsuite/{sim => }/bfin/random_0006.S | 0 sim/testsuite/{sim => }/bfin/random_0007.S | 0 sim/testsuite/{sim => }/bfin/random_0008.S | 0 sim/testsuite/{sim => }/bfin/random_0009.S | 0 sim/testsuite/{sim => }/bfin/random_0010.S | 0 sim/testsuite/{sim => }/bfin/random_0011.S | 0 sim/testsuite/{sim => }/bfin/random_0012.S | 0 sim/testsuite/{sim => }/bfin/random_0013.S | 0 sim/testsuite/{sim => }/bfin/random_0014.S | 0 sim/testsuite/{sim => }/bfin/random_0015.S | 0 sim/testsuite/{sim => }/bfin/random_0016.S | 0 sim/testsuite/{sim => }/bfin/random_0017.S | 0 sim/testsuite/{sim => }/bfin/random_0018.S | 0 sim/testsuite/{sim => }/bfin/random_0019.S | 0 sim/testsuite/{sim => }/bfin/random_0020.S | 0 sim/testsuite/{sim => }/bfin/random_0021.S | 0 sim/testsuite/{sim => }/bfin/random_0022.S | 0 sim/testsuite/{sim => }/bfin/random_0023.S | 0 sim/testsuite/{sim => }/bfin/random_0024.S | 0 sim/testsuite/{sim => }/bfin/random_0025.S | 0 sim/testsuite/{sim => }/bfin/random_0026.S | 0 sim/testsuite/{sim => }/bfin/random_0027.S | 0 sim/testsuite/{sim => }/bfin/random_0028.S | 0 sim/testsuite/{sim => }/bfin/random_0029.S | 0 sim/testsuite/{sim => }/bfin/random_0030.S | 0 sim/testsuite/{sim => }/bfin/random_0031.S | 0 sim/testsuite/{sim => }/bfin/random_0032.S | 0 sim/testsuite/{sim => }/bfin/random_0033.S | 0 sim/testsuite/{sim => }/bfin/random_0034.S | 0 sim/testsuite/{sim => }/bfin/random_0035.S | 0 sim/testsuite/{sim => }/bfin/random_0036.S | 0 sim/testsuite/{sim => }/bfin/random_0037.S | 0 sim/testsuite/{sim => }/bfin/run-tests.sh | 0 sim/testsuite/{sim => }/bfin/s0.s | 0 sim/testsuite/{sim => }/bfin/s1.s | 0 sim/testsuite/{sim => }/bfin/s10.s | 0 sim/testsuite/{sim => }/bfin/s11.s | 0 sim/testsuite/{sim => }/bfin/s12.s | 0 sim/testsuite/{sim => }/bfin/s13.s | 0 sim/testsuite/{sim => }/bfin/s14.s | 0 sim/testsuite/{sim => }/bfin/s15.s | 0 sim/testsuite/{sim => }/bfin/s16.s | 0 sim/testsuite/{sim => }/bfin/s17.s | 0 sim/testsuite/{sim => }/bfin/s18.s | 0 sim/testsuite/{sim => }/bfin/s19.s | 0 sim/testsuite/{sim => }/bfin/s2.s | 0 sim/testsuite/{sim => }/bfin/s20.s | 0 sim/testsuite/{sim => }/bfin/s21.s | 0 sim/testsuite/{sim => }/bfin/s3.s | 0 sim/testsuite/{sim => }/bfin/s30.s | 0 sim/testsuite/{sim => }/bfin/s4.s | 0 sim/testsuite/{sim => }/bfin/s5.s | 0 sim/testsuite/{sim => }/bfin/s6.s | 0 sim/testsuite/{sim => }/bfin/s7.s | 0 sim/testsuite/{sim => }/bfin/s8.s | 0 sim/testsuite/{sim => }/bfin/s9.s | 0 sim/testsuite/{sim => }/bfin/saatest.s | 0 sim/testsuite/{sim => }/bfin/se_all16bitopcodes.S | 0 sim/testsuite/{sim => }/bfin/se_all32bitopcodes.S | 0 .../{sim => }/bfin/se_all32bitopcodes.lds | 0 .../{sim => }/bfin/se_all64bitg0opcodes.S | 0 .../{sim => }/bfin/se_all64bitg1opcodes.S | 0 .../{sim => }/bfin/se_all64bitg2opcodes.S | 0 sim/testsuite/{sim => }/bfin/se_allopcodes.h | 0 sim/testsuite/{sim => }/bfin/se_brtarget_stall.S | 0 sim/testsuite/{sim => }/bfin/se_bug_ui.S | 0 sim/testsuite/{sim => }/bfin/se_bug_ui2.S | 0 sim/testsuite/{sim => }/bfin/se_bug_ui3.S | 0 sim/testsuite/{sim => }/bfin/se_cc2stat_haz.S | 0 sim/testsuite/{sim => }/bfin/se_cc_kill.S | 0 sim/testsuite/{sim => }/bfin/se_cof.S | 0 sim/testsuite/{sim => }/bfin/se_event_quad.S | 0 .../{sim => }/bfin/se_excpt_dagprotviol.S | 0 sim/testsuite/{sim => }/bfin/se_excpt_ifprotviol.S | 0 sim/testsuite/{sim => }/bfin/se_excpt_ssstep.S | 0 .../{sim => }/bfin/se_illegalcombination.S | 0 sim/testsuite/{sim => }/bfin/se_kill_wbbr.S | 0 sim/testsuite/{sim => }/bfin/se_kills2.S | 0 sim/testsuite/{sim => }/bfin/se_loop_disable.S | 0 sim/testsuite/{sim => }/bfin/se_loop_kill.S | 0 sim/testsuite/{sim => }/bfin/se_loop_kill_01.S | 0 sim/testsuite/{sim => }/bfin/se_loop_kill_dcr.S | 0 sim/testsuite/{sim => }/bfin/se_loop_kill_dcr_01.S | 0 sim/testsuite/{sim => }/bfin/se_loop_lr.S | 0 sim/testsuite/{sim => }/bfin/se_loop_mv2lb_stall.S | 0 sim/testsuite/{sim => }/bfin/se_loop_mv2lc.S | 0 sim/testsuite/{sim => }/bfin/se_loop_mv2lc_stall.S | 0 sim/testsuite/{sim => }/bfin/se_loop_mv2lt_stall.S | 0 sim/testsuite/{sim => }/bfin/se_loop_nest_ppm.S | 0 sim/testsuite/{sim => }/bfin/se_loop_nest_ppm_1.S | 0 sim/testsuite/{sim => }/bfin/se_loop_nest_ppm_2.S | 0 sim/testsuite/{sim => }/bfin/se_loop_ppm.S | 0 sim/testsuite/{sim => }/bfin/se_loop_ppm_1.S | 0 sim/testsuite/{sim => }/bfin/se_loop_ppm_int.S | 0 sim/testsuite/{sim => }/bfin/se_lsetup_kill.S | 0 sim/testsuite/{sim => }/bfin/se_misaligned_fetch.S | 0 sim/testsuite/{sim => }/bfin/se_more_ret_haz.S | 0 sim/testsuite/{sim => }/bfin/se_mv2lp.S | 0 sim/testsuite/{sim => }/bfin/se_oneins_zoff.S | 0 sim/testsuite/{sim => }/bfin/se_popkill.S | 0 sim/testsuite/{sim => }/bfin/se_regmv_usp_sysreg.S | 0 sim/testsuite/{sim => }/bfin/se_rets_hazard.s | 0 sim/testsuite/{sim => }/bfin/se_rts_rti.S | 0 .../{sim => }/bfin/se_ssstep_dagprotviol.S | 0 sim/testsuite/{sim => }/bfin/se_ssync.S | 0 sim/testsuite/{sim => }/bfin/se_stall_if2.S | 0 .../{sim => }/bfin/se_undefinedinstruction1.S | 0 .../{sim => }/bfin/se_undefinedinstruction2.S | 0 .../{sim => }/bfin/se_undefinedinstruction3.S | 0 .../{sim => }/bfin/se_undefinedinstruction4.S | 0 .../{sim => }/bfin/se_usermode_protviol.S | 0 sim/testsuite/{sim => }/bfin/seqstat.s | 0 sim/testsuite/{sim => }/bfin/sign.s | 0 sim/testsuite/{sim => }/bfin/simple0.s | 0 sim/testsuite/{sim => }/bfin/sri.s | 0 sim/testsuite/{sim => }/bfin/stk.s | 0 sim/testsuite/{sim => }/bfin/stk2.s | 0 sim/testsuite/{sim => }/bfin/stk3.s | 0 sim/testsuite/{sim => }/bfin/stk4.s | 0 sim/testsuite/{sim => }/bfin/stk5.s | 0 sim/testsuite/{sim => }/bfin/stk6.s | 0 sim/testsuite/{sim => }/bfin/syscfg.s | 0 sim/testsuite/{sim => }/bfin/tar10622.s | 0 sim/testsuite/{sim => }/bfin/test-dma.h | 0 sim/testsuite/{sim => }/bfin/test.h | 0 sim/testsuite/{sim => }/bfin/testset.s | 0 sim/testsuite/{sim => }/bfin/testset2.s | 0 sim/testsuite/{sim => }/bfin/testutils.inc | 0 sim/testsuite/{sim => }/bfin/unlink.S | 0 sim/testsuite/{sim => }/bfin/up0.s | 0 sim/testsuite/{sim => }/bfin/usp.S | 0 sim/testsuite/{sim => }/bfin/vec-abs-2.S | 0 sim/testsuite/{sim => }/bfin/vec-abs-3.S | 0 sim/testsuite/{sim => }/bfin/vec-abs.S | 0 sim/testsuite/{sim => }/bfin/vec-neg-2.S | 0 sim/testsuite/{sim => }/bfin/vec-neg-3.S | 0 sim/testsuite/{sim => }/bfin/vec-neg.S | 0 sim/testsuite/{sim => }/bfin/vecadd.s | 0 sim/testsuite/{sim => }/bfin/vit_max.s | 0 sim/testsuite/{sim => }/bfin/vit_max2.s | 0 sim/testsuite/{sim => }/bfin/viterbi2.s | 0 sim/testsuite/{sim => }/bfin/wtf.s | 0 sim/testsuite/{sim => }/bfin/x1.s | 0 sim/testsuite/{sim => }/bfin/zcall.s | 0 sim/testsuite/{sim => }/bfin/zeroflagrnd.s | 0 sim/testsuite/bpf/ChangeLog | 20 + sim/testsuite/{sim => }/bpf/allinsn.exp | 0 sim/testsuite/{sim => }/bpf/alu.s | 0 sim/testsuite/{sim => }/bpf/alu32.s | 0 sim/testsuite/{sim => }/bpf/endbe.s | 0 sim/testsuite/{sim => }/bpf/endle.s | 0 sim/testsuite/{sim => }/bpf/jmp.s | 0 sim/testsuite/{sim => }/bpf/jmp32.s | 0 sim/testsuite/{sim => }/bpf/ldabs.s | 0 sim/testsuite/{sim => }/bpf/mem.s | 0 sim/testsuite/{sim => }/bpf/mov.s | 0 sim/testsuite/{sim => }/bpf/testutils.inc | 0 sim/testsuite/{sim => }/bpf/xadd.s | 0 sim/testsuite/common/Make-common.in | 90 - sim/testsuite/common/alu-tst.c | 7 +- sim/testsuite/common/bits-gen.c | 25 +- sim/testsuite/common/bits-tst.c | 39 +- sim/testsuite/configure | 3267 ---- sim/testsuite/configure.ac | 32 - sim/testsuite/{sim => }/cr16/ChangeLog | 0 sim/testsuite/{sim => }/cr16/addb.cgs | 0 sim/testsuite/{sim => }/cr16/addd.cgs | 0 sim/testsuite/{sim => }/cr16/addi.cgs | 0 sim/testsuite/{sim => }/cr16/addw.cgs | 0 sim/testsuite/{sim => }/cr16/allinsn.exp | 0 sim/testsuite/{sim => }/cr16/andb.cgs | 0 sim/testsuite/{sim => }/cr16/andd.cgs | 0 sim/testsuite/{sim => }/cr16/andw.cgs | 0 sim/testsuite/{sim => }/cr16/ashub.cgs | 0 sim/testsuite/{sim => }/cr16/ashub_i.cgs | 0 sim/testsuite/{sim => }/cr16/ashud.cgs | 0 sim/testsuite/{sim => }/cr16/ashud_i.cgs | 0 sim/testsuite/{sim => }/cr16/ashuw.cgs | 0 sim/testsuite/{sim => }/cr16/ashuw_i.cgs | 0 sim/testsuite/{sim => }/cr16/bal1_24.cgs | 0 sim/testsuite/{sim => }/cr16/bal2_24.cgs | 0 sim/testsuite/{sim => }/cr16/bcc.cgs | 0 sim/testsuite/{sim => }/cr16/bcs.cgs | 0 sim/testsuite/{sim => }/cr16/beq.cgs | 0 sim/testsuite/{sim => }/cr16/beq0b.cgs | 0 sim/testsuite/{sim => }/cr16/beq0w.cgs | 0 sim/testsuite/{sim => }/cr16/bge.cgs | 0 sim/testsuite/{sim => }/cr16/bgt.cgs | 0 sim/testsuite/{sim => }/cr16/bhi.cgs | 0 sim/testsuite/{sim => }/cr16/bhs.cgs | 0 sim/testsuite/{sim => }/cr16/bht.cgs | 0 sim/testsuite/{sim => }/cr16/blo.cgs | 0 sim/testsuite/{sim => }/cr16/bls.cgs | 0 sim/testsuite/{sim => }/cr16/blt.cgs | 0 sim/testsuite/{sim => }/cr16/bne.cgs | 0 sim/testsuite/{sim => }/cr16/bne0b.cgs | 0 sim/testsuite/{sim => }/cr16/bne0w.cgs | 0 sim/testsuite/{sim => }/cr16/br.cgs | 0 sim/testsuite/{sim => }/cr16/cbitb.cgs | 0 sim/testsuite/{sim => }/cr16/cbitw.cgs | 0 sim/testsuite/{sim => }/cr16/cmpb.cgs | 0 sim/testsuite/{sim => }/cr16/cmpb_i.cgs | 0 sim/testsuite/{sim => }/cr16/cmpd.cgs | 0 sim/testsuite/{sim => }/cr16/cmpd_i.cgs | 0 sim/testsuite/{sim => }/cr16/cmpi.cgs | 0 sim/testsuite/{sim => }/cr16/cmpw.cgs | 0 sim/testsuite/{sim => }/cr16/cmpw_i.cgs | 0 sim/testsuite/{sim => }/cr16/excp.cgs | 0 sim/testsuite/{sim => }/cr16/hello.ms | 0 sim/testsuite/{sim => }/cr16/hw-trap.ms | 0 sim/testsuite/{sim => }/cr16/jal.cgs | 0 sim/testsuite/{sim => }/cr16/jcc.cgs | 0 sim/testsuite/{sim => }/cr16/jcs.cgs | 0 sim/testsuite/{sim => }/cr16/jeq.cgs | 0 sim/testsuite/{sim => }/cr16/jfc.cgs | 0 sim/testsuite/{sim => }/cr16/jfs.cgs | 0 sim/testsuite/{sim => }/cr16/jge.cgs | 0 sim/testsuite/{sim => }/cr16/jgt.cgs | 0 sim/testsuite/{sim => }/cr16/jhi.cgs | 0 sim/testsuite/{sim => }/cr16/jhs.cgs | 0 sim/testsuite/{sim => }/cr16/jlo.cgs | 0 sim/testsuite/{sim => }/cr16/jls.cgs | 0 sim/testsuite/{sim => }/cr16/jlt.cgs | 0 sim/testsuite/{sim => }/cr16/jne.cgs | 0 sim/testsuite/{sim => }/cr16/jump.cgs | 0 sim/testsuite/{sim => }/cr16/loadb.cgs | 0 sim/testsuite/{sim => }/cr16/loadd.cgs | 0 sim/testsuite/{sim => }/cr16/loadm.cgs | 0 sim/testsuite/{sim => }/cr16/loadmp.cgs | 0 sim/testsuite/{sim => }/cr16/loadw.cgs | 0 sim/testsuite/{sim => }/cr16/lpr-spr.cgs | 0 sim/testsuite/{sim => }/cr16/lprd-sprd.cgs | 0 sim/testsuite/{sim => }/cr16/lshb.cgs | 0 sim/testsuite/{sim => }/cr16/lshb_i.cgs | 0 sim/testsuite/{sim => }/cr16/lshd.cgs | 0 sim/testsuite/{sim => }/cr16/lshd_i.cgs | 0 sim/testsuite/{sim => }/cr16/lshw.cgs | 0 sim/testsuite/{sim => }/cr16/lshw_i.cgs | 0 sim/testsuite/{sim => }/cr16/macqw.cgs | 0 sim/testsuite/{sim => }/cr16/macsw.cgs | 0 sim/testsuite/{sim => }/cr16/macuw.cgs | 0 sim/testsuite/{sim => }/cr16/misc.exp | 0 sim/testsuite/{sim => }/cr16/movb.cgs | 0 sim/testsuite/{sim => }/cr16/movd.cgs | 0 sim/testsuite/{sim => }/cr16/movw.cgs | 0 sim/testsuite/{sim => }/cr16/movxb.cgs | 0 sim/testsuite/{sim => }/cr16/movxw.cgs | 0 sim/testsuite/{sim => }/cr16/movzb.cgs | 0 sim/testsuite/{sim => }/cr16/movzw.cgs | 0 sim/testsuite/{sim => }/cr16/mulb.cgs | 0 sim/testsuite/{sim => }/cr16/mulsb.cgs | 0 sim/testsuite/{sim => }/cr16/mulsw.cgs | 0 sim/testsuite/{sim => }/cr16/muluw.cgs | 0 sim/testsuite/{sim => }/cr16/mulw.cgs | 0 sim/testsuite/{sim => }/cr16/nop.cgs | 0 sim/testsuite/{sim => }/cr16/orb.cgs | 0 sim/testsuite/{sim => }/cr16/ord.cgs | 0 sim/testsuite/{sim => }/cr16/orw.cgs | 0 sim/testsuite/{sim => }/cr16/pop1.cgs | 0 sim/testsuite/{sim => }/cr16/pop2.cgs | 0 sim/testsuite/{sim => }/cr16/pop3.cgs | 0 sim/testsuite/{sim => }/cr16/popret1.cgs | 0 sim/testsuite/{sim => }/cr16/popret2.cgs | 0 sim/testsuite/{sim => }/cr16/popret3.cgs | 0 sim/testsuite/{sim => }/cr16/push1.cgs | 0 sim/testsuite/{sim => }/cr16/push2.cgs | 0 sim/testsuite/{sim => }/cr16/push3.cgs | 0 sim/testsuite/{sim => }/cr16/sbitb.cgs | 0 sim/testsuite/{sim => }/cr16/sbitw.cgs | 0 sim/testsuite/{sim => }/cr16/scc.cgs | 0 sim/testsuite/{sim => }/cr16/scs.cgs | 0 sim/testsuite/{sim => }/cr16/seq.cgs | 0 sim/testsuite/{sim => }/cr16/sfc.cgs | 0 sim/testsuite/{sim => }/cr16/sfs.cgs | 0 sim/testsuite/{sim => }/cr16/sge.cgs | 0 sim/testsuite/{sim => }/cr16/sgt.cgs | 0 sim/testsuite/{sim => }/cr16/shi.cgs | 0 sim/testsuite/{sim => }/cr16/shs.cgs | 0 sim/testsuite/{sim => }/cr16/slo.cgs | 0 sim/testsuite/{sim => }/cr16/sls.cgs | 0 sim/testsuite/{sim => }/cr16/slt.cgs | 0 sim/testsuite/{sim => }/cr16/sne.cgs | 0 sim/testsuite/{sim => }/cr16/storb.cgs | 0 sim/testsuite/{sim => }/cr16/stord.cgs | 0 sim/testsuite/{sim => }/cr16/storw.cgs | 0 sim/testsuite/{sim => }/cr16/subb.cgs | 0 sim/testsuite/{sim => }/cr16/subd.cgs | 0 sim/testsuite/{sim => }/cr16/subi.cgs | 0 sim/testsuite/{sim => }/cr16/subw.cgs | 0 sim/testsuite/{sim => }/cr16/tbit.cgs | 0 sim/testsuite/{sim => }/cr16/tbitb.cgs | 0 sim/testsuite/{sim => }/cr16/tbitw.cgs | 0 sim/testsuite/{sim => }/cr16/testutils.inc | 0 sim/testsuite/{sim => }/cr16/uread16.ms | 0 sim/testsuite/{sim => }/cr16/uread32.ms | 0 sim/testsuite/{sim => }/cr16/xorb.cgs | 0 sim/testsuite/{sim => }/cr16/xord.cgs | 0 sim/testsuite/{sim => }/cr16/xorw.cgs | 0 sim/testsuite/cris/ChangeLog | 204 + sim/testsuite/{sim => }/cris/asm/abs.ms | 0 sim/testsuite/{sim => }/cris/asm/addc.ms | 0 sim/testsuite/{sim => }/cris/asm/addcpc.ms | 0 sim/testsuite/{sim => }/cris/asm/addcv32c.ms | 0 sim/testsuite/{sim => }/cris/asm/addcv32m.ms | 0 sim/testsuite/{sim => }/cris/asm/addcv32r.ms | 0 sim/testsuite/{sim => }/cris/asm/addi.ms | 0 sim/testsuite/{sim => }/cris/asm/addiv32.ms | 0 sim/testsuite/{sim => }/cris/asm/addm.ms | 0 sim/testsuite/{sim => }/cris/asm/addoc.ms | 0 sim/testsuite/{sim => }/cris/asm/addom.ms | 0 sim/testsuite/{sim => }/cris/asm/addoq.ms | 0 sim/testsuite/{sim => }/cris/asm/addq.ms | 0 sim/testsuite/{sim => }/cris/asm/addqpc.ms | 0 sim/testsuite/{sim => }/cris/asm/addr.ms | 0 sim/testsuite/{sim => }/cris/asm/addswpc.ms | 0 sim/testsuite/{sim => }/cris/asm/addxc.ms | 0 sim/testsuite/{sim => }/cris/asm/addxm.ms | 0 sim/testsuite/{sim => }/cris/asm/addxr.ms | 0 sim/testsuite/{sim => }/cris/asm/andc.ms | 0 sim/testsuite/{sim => }/cris/asm/andm.ms | 0 sim/testsuite/{sim => }/cris/asm/andq.ms | 0 sim/testsuite/{sim => }/cris/asm/andr.ms | 0 sim/testsuite/{sim => }/cris/asm/asm.exp | 0 sim/testsuite/{sim => }/cris/asm/asr.ms | 0 sim/testsuite/{sim => }/cris/asm/ba.ms | 0 sim/testsuite/{sim => }/cris/asm/badarch1.ms | 0 sim/testsuite/{sim => }/cris/asm/bare1.ms | 0 sim/testsuite/{sim => }/cris/asm/bare2.ms | 0 sim/testsuite/{sim => }/cris/asm/bare3.ms | 0 sim/testsuite/{sim => }/cris/asm/bas.ms | 0 sim/testsuite/{sim => }/cris/asm/bccb.ms | 0 sim/testsuite/{sim => }/cris/asm/bdapc.ms | 0 sim/testsuite/{sim => }/cris/asm/bdapm.ms | 0 sim/testsuite/{sim => }/cris/asm/bdapq.ms | 0 sim/testsuite/{sim => }/cris/asm/bdapqpc.ms | 0 sim/testsuite/{sim => }/cris/asm/biap.ms | 0 sim/testsuite/{sim => }/cris/asm/boundc.ms | 0 sim/testsuite/{sim => }/cris/asm/boundm.ms | 0 sim/testsuite/{sim => }/cris/asm/boundmv32.ms | 0 sim/testsuite/{sim => }/cris/asm/boundr.ms | 0 sim/testsuite/{sim => }/cris/asm/break.ms | 0 sim/testsuite/{sim => }/cris/asm/btst.ms | 0 sim/testsuite/{sim => }/cris/asm/ccr-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/ccs-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/clearfv10.ms | 0 sim/testsuite/{sim => }/cris/asm/clearfv32.ms | 0 sim/testsuite/{sim => }/cris/asm/clrjmp1.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpc.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpm.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpq.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpr.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpxc.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpxm.ms | 0 sim/testsuite/{sim => }/cris/asm/dflags.ms | 0 sim/testsuite/{sim => }/cris/asm/dip.ms | 0 sim/testsuite/{sim => }/cris/asm/dstep.ms | 0 sim/testsuite/{sim => }/cris/asm/fidxd.ms | 0 sim/testsuite/{sim => }/cris/asm/fidxi.ms | 0 sim/testsuite/{sim => }/cris/asm/ftagd.ms | 0 sim/testsuite/{sim => }/cris/asm/ftagi.ms | 0 sim/testsuite/{sim => }/cris/asm/halt.ms | 0 sim/testsuite/{sim => }/cris/asm/io1.ms | 0 sim/testsuite/{sim => }/cris/asm/io2.ms | 0 sim/testsuite/{sim => }/cris/asm/io3.ms | 0 sim/testsuite/{sim => }/cris/asm/io4.ms | 0 sim/testsuite/{sim => }/cris/asm/io5.ms | 0 sim/testsuite/{sim => }/cris/asm/io6.ms | 0 sim/testsuite/{sim => }/cris/asm/io7.ms | 0 sim/testsuite/{sim => }/cris/asm/io8.ms | 0 sim/testsuite/{sim => }/cris/asm/io9.ms | 0 sim/testsuite/{sim => }/cris/asm/jsr.ms | 0 sim/testsuite/{sim => }/cris/asm/jsrmv10.ms | 0 sim/testsuite/{sim => }/cris/asm/jumpmp.ms | 0 sim/testsuite/{sim => }/cris/asm/jumppv32.ms | 0 sim/testsuite/{sim => }/cris/asm/lapc.ms | 0 sim/testsuite/{sim => }/cris/asm/lsl.ms | 0 sim/testsuite/{sim => }/cris/asm/lsr.ms | 0 sim/testsuite/{sim => }/cris/asm/lz.ms | 0 sim/testsuite/{sim => }/cris/asm/mcp.ms | 0 sim/testsuite/{sim => }/cris/asm/movdelsr1.ms | 0 sim/testsuite/{sim => }/cris/asm/movecpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movecr.ms | 0 sim/testsuite/{sim => }/cris/asm/movecrt10.ms | 0 sim/testsuite/{sim => }/cris/asm/movecrt32.ms | 0 sim/testsuite/{sim => }/cris/asm/movect10.ms | 0 sim/testsuite/{sim => }/cris/asm/movei.ms | 0 sim/testsuite/{sim => }/cris/asm/movempc.ms | 0 sim/testsuite/{sim => }/cris/asm/movemr.ms | 0 sim/testsuite/{sim => }/cris/asm/movemrv10.ms | 0 sim/testsuite/{sim => }/cris/asm/movemrv32.ms | 0 sim/testsuite/{sim => }/cris/asm/movepcb.ms | 0 sim/testsuite/{sim => }/cris/asm/movepcd.ms | 0 sim/testsuite/{sim => }/cris/asm/movepcw.ms | 0 sim/testsuite/{sim => }/cris/asm/moveq.ms | 0 sim/testsuite/{sim => }/cris/asm/moveqpc.ms | 0 sim/testsuite/{sim => }/cris/asm/mover.ms | 0 sim/testsuite/{sim => }/cris/asm/moverbpc.ms | 0 sim/testsuite/{sim => }/cris/asm/moverdpc.ms | 0 sim/testsuite/{sim => }/cris/asm/moverm.ms | 0 sim/testsuite/{sim => }/cris/asm/moverpcb.ms | 0 sim/testsuite/{sim => }/cris/asm/moverpcd.ms | 0 sim/testsuite/{sim => }/cris/asm/moverpcw.ms | 0 sim/testsuite/{sim => }/cris/asm/moverwpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movesmp.ms | 0 sim/testsuite/{sim => }/cris/asm/movmp.ms | 0 sim/testsuite/{sim => }/cris/asm/movmp8.ms | 0 sim/testsuite/{sim => }/cris/asm/movpmv10.ms | 0 sim/testsuite/{sim => }/cris/asm/movpmv32.ms | 0 sim/testsuite/{sim => }/cris/asm/movppc.ms | 0 sim/testsuite/{sim => }/cris/asm/movpr.ms | 0 sim/testsuite/{sim => }/cris/asm/movprv10.ms | 0 sim/testsuite/{sim => }/cris/asm/movprv32.ms | 0 sim/testsuite/{sim => }/cris/asm/movrss.ms | 0 sim/testsuite/{sim => }/cris/asm/movscpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movscr.ms | 0 sim/testsuite/{sim => }/cris/asm/movsm.ms | 0 sim/testsuite/{sim => }/cris/asm/movsmpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movsr.ms | 0 sim/testsuite/{sim => }/cris/asm/movsrpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movssr.ms | 0 sim/testsuite/{sim => }/cris/asm/movucpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movucr.ms | 0 sim/testsuite/{sim => }/cris/asm/movum.ms | 0 sim/testsuite/{sim => }/cris/asm/movumpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movur.ms | 0 sim/testsuite/{sim => }/cris/asm/movurpc.ms | 0 sim/testsuite/{sim => }/cris/asm/mstep.ms | 0 sim/testsuite/{sim => }/cris/asm/msteppc1.ms | 0 sim/testsuite/{sim => }/cris/asm/msteppc2.ms | 0 sim/testsuite/{sim => }/cris/asm/msteppc3.ms | 0 sim/testsuite/{sim => }/cris/asm/mulv10.ms | 0 sim/testsuite/{sim => }/cris/asm/mulv32.ms | 0 sim/testsuite/{sim => }/cris/asm/mulx.ms | 0 sim/testsuite/{sim => }/cris/asm/neg.ms | 0 sim/testsuite/{sim => }/cris/asm/nonvcv32.ms | 0 sim/testsuite/{sim => }/cris/asm/nopv10t.ms | 0 sim/testsuite/{sim => }/cris/asm/nopv32t.ms | 0 sim/testsuite/{sim => }/cris/asm/nopv32t2.ms | 0 sim/testsuite/{sim => }/cris/asm/nopv32t3.ms | 0 sim/testsuite/{sim => }/cris/asm/nopv32t4.ms | 0 sim/testsuite/{sim => }/cris/asm/not.ms | 0 sim/testsuite/{sim => }/cris/asm/op3.ms | 0 sim/testsuite/{sim => }/cris/asm/opterr1.ms | 0 sim/testsuite/{sim => }/cris/asm/opterr2.ms | 0 sim/testsuite/{sim => }/cris/asm/opterr3.ms | 0 sim/testsuite/{sim => }/cris/asm/opterr4.ms | 0 sim/testsuite/{sim => }/cris/asm/opterr5.ms | 0 sim/testsuite/{sim => }/cris/asm/option1.ms | 0 sim/testsuite/{sim => }/cris/asm/option2.ms | 0 sim/testsuite/{sim => }/cris/asm/option3.ms | 0 sim/testsuite/{sim => }/cris/asm/option4.ms | 0 sim/testsuite/{sim => }/cris/asm/orc.ms | 0 sim/testsuite/{sim => }/cris/asm/orm.ms | 0 sim/testsuite/{sim => }/cris/asm/orq.ms | 0 sim/testsuite/{sim => }/cris/asm/orr.ms | 0 sim/testsuite/{sim => }/cris/asm/pcplus.ms | 0 sim/testsuite/{sim => }/cris/asm/pid1.ms | 0 sim/testsuite/{sim => }/cris/asm/raw1.ms | 0 sim/testsuite/{sim => }/cris/asm/raw10.ms | 0 sim/testsuite/{sim => }/cris/asm/raw11.ms | 0 sim/testsuite/{sim => }/cris/asm/raw12.ms | 0 sim/testsuite/{sim => }/cris/asm/raw13.ms | 0 sim/testsuite/{sim => }/cris/asm/raw14.ms | 0 sim/testsuite/{sim => }/cris/asm/raw15.ms | 0 sim/testsuite/{sim => }/cris/asm/raw16.ms | 0 sim/testsuite/{sim => }/cris/asm/raw17.ms | 0 sim/testsuite/{sim => }/cris/asm/raw2.ms | 0 sim/testsuite/{sim => }/cris/asm/raw3.ms | 0 sim/testsuite/{sim => }/cris/asm/raw4.ms | 0 sim/testsuite/{sim => }/cris/asm/raw5.ms | 0 sim/testsuite/{sim => }/cris/asm/raw6.ms | 0 sim/testsuite/{sim => }/cris/asm/raw7.ms | 0 sim/testsuite/{sim => }/cris/asm/raw8.ms | 0 sim/testsuite/{sim => }/cris/asm/raw9.ms | 0 sim/testsuite/{sim => }/cris/asm/ret.ms | 0 sim/testsuite/{sim => }/cris/asm/rfe.ms | 0 sim/testsuite/{sim => }/cris/asm/rfg.ms | 0 sim/testsuite/{sim => }/cris/asm/rfn.ms | 0 sim/testsuite/{sim => }/cris/asm/sbfs.ms | 0 sim/testsuite/{sim => }/cris/asm/scc.ms | 0 sim/testsuite/{sim => }/cris/asm/sfe.ms | 0 sim/testsuite/{sim => }/cris/asm/subc.ms | 0 sim/testsuite/{sim => }/cris/asm/subm.ms | 0 sim/testsuite/{sim => }/cris/asm/subq.ms | 0 sim/testsuite/{sim => }/cris/asm/subqpc.ms | 0 sim/testsuite/{sim => }/cris/asm/subr.ms | 0 sim/testsuite/{sim => }/cris/asm/subxc.ms | 0 sim/testsuite/{sim => }/cris/asm/subxm.ms | 0 sim/testsuite/{sim => }/cris/asm/subxr.ms | 0 sim/testsuite/{sim => }/cris/asm/swap.ms | 0 sim/testsuite/{sim => }/cris/asm/tb.ms | 0 sim/testsuite/{sim => }/cris/asm/test.ms | 0 sim/testsuite/{sim => }/cris/asm/testutils.inc | 0 sim/testsuite/{sim => }/cris/asm/tjmpsrv32-2.ms | 0 sim/testsuite/{sim => }/cris/asm/tjmpsrv32.ms | 0 sim/testsuite/{sim => }/cris/asm/tjsrcv10.ms | 0 sim/testsuite/{sim => }/cris/asm/tjsrcv32.ms | 0 sim/testsuite/{sim => }/cris/asm/tmemv10.ms | 0 sim/testsuite/{sim => }/cris/asm/tmemv32.ms | 0 sim/testsuite/{sim => }/cris/asm/tmulv10.ms | 0 sim/testsuite/{sim => }/cris/asm/tmulv32.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvm1.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvm2.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvmrv10.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvmrv32.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvrmv10.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvrmv32.ms | 0 sim/testsuite/{sim => }/cris/asm/user.ms | 0 sim/testsuite/{sim => }/cris/asm/x0-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x0-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x1-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x1-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x10-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x2-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x2-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x3-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x3-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x4-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x5-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x5-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x6-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x6-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x7-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x7-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x8-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x9-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/xor.ms | 0 sim/testsuite/{sim => }/cris/c/access1.c | 0 sim/testsuite/{sim => }/cris/c/append1.c | 0 sim/testsuite/{sim => }/cris/c/badldso1.c | 0 sim/testsuite/{sim => }/cris/c/badldso2.c | 0 sim/testsuite/{sim => }/cris/c/badldso3.c | 0 sim/testsuite/cris/c/c.exp | 253 + sim/testsuite/{sim => }/cris/c/clone1.c | 0 sim/testsuite/{sim => }/cris/c/clone2.c | 0 sim/testsuite/{sim => }/cris/c/clone3.c | 0 sim/testsuite/{sim => }/cris/c/clone4.c | 0 sim/testsuite/{sim => }/cris/c/clone5.c | 0 sim/testsuite/{sim => }/cris/c/clone6.c | 0 sim/testsuite/{sim => }/cris/c/ex1.c | 0 sim/testsuite/{sim => }/cris/c/exitg1.c | 0 sim/testsuite/{sim => }/cris/c/exitg2.c | 0 sim/testsuite/{sim => }/cris/c/fcntl1.c | 0 sim/testsuite/{sim => }/cris/c/fcntl2.c | 0 sim/testsuite/{sim => }/cris/c/fdopen1.c | 0 sim/testsuite/{sim => }/cris/c/fdopen2.c | 0 sim/testsuite/{sim => }/cris/c/freopen1.c | 0 sim/testsuite/{sim => }/cris/c/freopen2.c | 0 sim/testsuite/{sim => }/cris/c/ftruncate1.c | 0 sim/testsuite/{sim => }/cris/c/ftruncate2.c | 0 sim/testsuite/{sim => }/cris/c/getcwd1.c | 0 sim/testsuite/{sim => }/cris/c/gettod.c | 0 sim/testsuite/{sim => }/cris/c/hello.c | 0 sim/testsuite/cris/c/helloaout.c | 14 + sim/testsuite/{sim => }/cris/c/hellodyn.c | 0 sim/testsuite/{sim => }/cris/c/hellodyn2.c | 0 sim/testsuite/{sim => }/cris/c/hellodyn3.c | 0 sim/testsuite/{sim => }/cris/c/kill1.c | 0 sim/testsuite/cris/c/kill2.c | 18 + sim/testsuite/{sim => }/cris/c/kill3.c | 0 sim/testsuite/{sim => }/cris/c/mapbrk.c | 0 sim/testsuite/{sim => }/cris/c/mmap1.c | 0 sim/testsuite/{sim => }/cris/c/mmap2.c | 0 sim/testsuite/{sim => }/cris/c/mmap3.c | 0 sim/testsuite/{sim => }/cris/c/mmap4.c | 0 sim/testsuite/{sim => }/cris/c/mmap5.c | 0 sim/testsuite/{sim => }/cris/c/mmap6.c | 0 sim/testsuite/{sim => }/cris/c/mmap7.c | 0 sim/testsuite/{sim => }/cris/c/mmap8.c | 0 sim/testsuite/{sim => }/cris/c/mprotect1.c | 0 sim/testsuite/{sim => }/cris/c/mprotect2.c | 0 sim/testsuite/{sim => }/cris/c/mremap.c | 0 sim/testsuite/cris/c/openpf1.c | 38 + sim/testsuite/cris/c/openpf2.c | 16 + sim/testsuite/{sim => }/cris/c/openpf3.c | 0 sim/testsuite/{sim => }/cris/c/openpf4.c | 0 sim/testsuite/{sim => }/cris/c/openpf5.c | 0 sim/testsuite/cris/c/pipe1.c | 48 + sim/testsuite/{sim => }/cris/c/pipe2.c | 0 sim/testsuite/{sim => }/cris/c/pipe3.c | 0 sim/testsuite/{sim => }/cris/c/pipe4.c | 0 sim/testsuite/{sim => }/cris/c/pipe5.c | 0 sim/testsuite/{sim => }/cris/c/pipe6.c | 0 sim/testsuite/{sim => }/cris/c/pipe7.c | 0 sim/testsuite/{sim => }/cris/c/readlink1.c | 0 sim/testsuite/{sim => }/cris/c/readlink10.c | 0 sim/testsuite/{sim => }/cris/c/readlink11.c | 0 sim/testsuite/{sim => }/cris/c/readlink2.c | 0 sim/testsuite/{sim => }/cris/c/readlink3.c | 0 sim/testsuite/cris/c/readlink4.c | 62 + sim/testsuite/{sim => }/cris/c/readlink5.c | 0 sim/testsuite/{sim => }/cris/c/readlink6.c | 0 sim/testsuite/{sim => }/cris/c/readlink7.c | 0 sim/testsuite/{sim => }/cris/c/readlink8.c | 0 sim/testsuite/{sim => }/cris/c/readlink9.c | 0 sim/testsuite/{sim => }/cris/c/rename2.c | 0 sim/testsuite/{sim => }/cris/c/rtsigprocmask1.c | 0 sim/testsuite/{sim => }/cris/c/rtsigprocmask2.c | 0 sim/testsuite/{sim => }/cris/c/rtsigsuspend1.c | 0 sim/testsuite/{sim => }/cris/c/rtsigsuspend2.c | 0 sim/testsuite/cris/c/sched1.c | 16 + sim/testsuite/cris/c/sched2.c | 20 + sim/testsuite/cris/c/sched3.c | 25 + sim/testsuite/cris/c/sched4.c | 25 + sim/testsuite/{sim => }/cris/c/sched5.c | 0 sim/testsuite/{sim => }/cris/c/sched6.c | 0 sim/testsuite/{sim => }/cris/c/sched7.c | 0 sim/testsuite/{sim => }/cris/c/sched8.c | 0 sim/testsuite/{sim => }/cris/c/sched9.c | 0 sim/testsuite/{sim => }/cris/c/seek1.c | 0 sim/testsuite/{sim => }/cris/c/seek2.c | 0 sim/testsuite/{sim => }/cris/c/seek3.c | 0 sim/testsuite/{sim => }/cris/c/seek4.c | 0 sim/testsuite/{sim => }/cris/c/setrlimit1.c | 0 sim/testsuite/{sim => }/cris/c/settls1.c | 0 sim/testsuite/{sim => }/cris/c/sig1.c | 0 sim/testsuite/{sim => }/cris/c/sig10.c | 0 sim/testsuite/{sim => }/cris/c/sig11.c | 0 sim/testsuite/{sim => }/cris/c/sig12.c | 0 sim/testsuite/{sim => }/cris/c/sig13.c | 0 sim/testsuite/{sim => }/cris/c/sig2.c | 0 sim/testsuite/{sim => }/cris/c/sig3.c | 0 sim/testsuite/{sim => }/cris/c/sig4.c | 0 sim/testsuite/cris/c/sig5.c | 18 + sim/testsuite/{sim => }/cris/c/sig6.c | 0 sim/testsuite/{sim => }/cris/c/sig7.c | 0 sim/testsuite/cris/c/sig8.c | 21 + sim/testsuite/{sim => }/cris/c/sig9.c | 0 sim/testsuite/{sim => }/cris/c/sigreturn1.c | 0 sim/testsuite/{sim => }/cris/c/sigreturn2.c | 0 sim/testsuite/{sim => }/cris/c/sigreturn3.c | 0 sim/testsuite/{sim => }/cris/c/sigreturn4.c | 0 sim/testsuite/{sim => }/cris/c/sjlj.c | 0 sim/testsuite/{sim => }/cris/c/sock1.c | 0 sim/testsuite/{sim => }/cris/c/stat1.c | 0 sim/testsuite/{sim => }/cris/c/stat2.c | 0 sim/testsuite/{sim => }/cris/c/stat3.c | 0 sim/testsuite/{sim => }/cris/c/stat4.c | 0 sim/testsuite/{sim => }/cris/c/stat5.c | 0 sim/testsuite/{sim => }/cris/c/stat7.c | 0 sim/testsuite/{sim => }/cris/c/stat8.c | 0 sim/testsuite/{sim => }/cris/c/syscall1.c | 0 sim/testsuite/{sim => }/cris/c/syscall2.c | 0 sim/testsuite/{sim => }/cris/c/syscall3.c | 0 sim/testsuite/{sim => }/cris/c/syscall4.c | 0 sim/testsuite/{sim => }/cris/c/syscall5.c | 0 sim/testsuite/{sim => }/cris/c/syscall6.c | 0 sim/testsuite/{sim => }/cris/c/syscall7.c | 0 sim/testsuite/{sim => }/cris/c/syscall8.c | 0 sim/testsuite/{sim => }/cris/c/sysctl1.c | 0 sim/testsuite/{sim => }/cris/c/sysctl2.c | 0 sim/testsuite/{sim => }/cris/c/sysctl3.c | 0 sim/testsuite/{sim => }/cris/c/thread2.c | 0 sim/testsuite/{sim => }/cris/c/thread3.c | 0 sim/testsuite/{sim => }/cris/c/thread4.c | 0 sim/testsuite/{sim => }/cris/c/thread5.c | 0 sim/testsuite/{sim => }/cris/c/time1.c | 0 sim/testsuite/{sim => }/cris/c/time2.c | 0 sim/testsuite/{sim => }/cris/c/truncate1.c | 0 sim/testsuite/{sim => }/cris/c/truncate2.c | 0 sim/testsuite/{sim => }/cris/c/ugetrlimit1.c | 0 sim/testsuite/{sim => }/cris/c/uname1.c | 0 sim/testsuite/{sim => }/cris/c/writev1.c | 0 sim/testsuite/{sim => }/cris/c/writev2.c | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/host1.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq1.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq2.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq3.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq4.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq5.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq6.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/mbox1.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/mem1.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/mem2.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/poll1.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/quit.s | 0 sim/testsuite/cris/hw/rv-n-cris/rvc.exp | 249 + sim/testsuite/{sim => }/cris/hw/rv-n-cris/std.dev | 0 .../{sim => }/cris/hw/rv-n-cris/testutils.inc | 0 .../{sim => }/cris/hw/rv-n-cris/trivial1.ms | 0 .../{sim => }/cris/hw/rv-n-cris/trivial2.ms | 0 .../{sim => }/cris/hw/rv-n-cris/trivial3.ms | 0 .../{sim => }/cris/hw/rv-n-cris/trivial4.ms | 0 .../{sim => }/cris/hw/rv-n-cris/trivial4.r | 0 .../{sim => }/cris/hw/rv-n-cris/trivial5.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/wd1.ms | 0 sim/testsuite/d10v-elf/ChangeLog | 139 - sim/testsuite/d10v-elf/Makefile.in | 180 - sim/testsuite/d10v-elf/configure | 2984 ---- sim/testsuite/d10v-elf/configure.ac | 18 - sim/testsuite/d10v-elf/exit47.s | 4 - sim/testsuite/d10v-elf/hello.s | 5 - sim/testsuite/d10v-elf/loop.s | 6 - sim/testsuite/d10v-elf/t-ae-ld-d.s | 13 - sim/testsuite/d10v-elf/t-ae-ld-i.s | 16 - sim/testsuite/d10v-elf/t-ae-ld-id.s | 15 - sim/testsuite/d10v-elf/t-ae-ld-im.s | 16 - sim/testsuite/d10v-elf/t-ae-ld-ip.s | 16 - sim/testsuite/d10v-elf/t-ae-ld2w-d.s | 13 - sim/testsuite/d10v-elf/t-ae-ld2w-i.s | 16 - sim/testsuite/d10v-elf/t-ae-ld2w-id.s | 14 - sim/testsuite/d10v-elf/t-ae-ld2w-im.s | 16 - sim/testsuite/d10v-elf/t-ae-ld2w-ip.s | 16 - sim/testsuite/d10v-elf/t-ae-st-d.s | 13 - sim/testsuite/d10v-elf/t-ae-st-i.s | 16 - sim/testsuite/d10v-elf/t-ae-st-id.s | 14 - sim/testsuite/d10v-elf/t-ae-st-im.s | 16 - sim/testsuite/d10v-elf/t-ae-st-ip.s | 16 - sim/testsuite/d10v-elf/t-ae-st-is.s | 16 - sim/testsuite/d10v-elf/t-ae-st2w-d.s | 13 - sim/testsuite/d10v-elf/t-ae-st2w-i.s | 16 - sim/testsuite/d10v-elf/t-ae-st2w-id.s | 14 - sim/testsuite/d10v-elf/t-ae-st2w-im.s | 16 - sim/testsuite/d10v-elf/t-ae-st2w-ip.s | 16 - sim/testsuite/d10v-elf/t-ae-st2w-is.s | 16 - sim/testsuite/d10v-elf/t-dbt.s | 33 - sim/testsuite/d10v-elf/t-ld-st.s | 32 - sim/testsuite/d10v-elf/t-mac.s | 71 - sim/testsuite/d10v-elf/t-macros.i | 233 - sim/testsuite/d10v-elf/t-mod-ld-pre.s | 126 - sim/testsuite/d10v-elf/t-msbu.s | 28 - sim/testsuite/d10v-elf/t-mulxu.s | 28 - sim/testsuite/d10v-elf/t-mvtac.s | 19 - sim/testsuite/d10v-elf/t-mvtc.s | 129 - sim/testsuite/d10v-elf/t-rac.s | 16 - sim/testsuite/d10v-elf/t-rachi.s | 28 - sim/testsuite/d10v-elf/t-rdt.s | 18 - sim/testsuite/d10v-elf/t-rep.s | 45 - sim/testsuite/d10v-elf/t-rie-xx.s | 12 - sim/testsuite/d10v-elf/t-rte.s | 18 - sim/testsuite/d10v-elf/t-sac.s | 23 - sim/testsuite/d10v-elf/t-sachi.s | 22 - sim/testsuite/d10v-elf/t-sadd.s | 38 - sim/testsuite/d10v-elf/t-slae.s | 39 - sim/testsuite/d10v-elf/t-sp.s | 17 - sim/testsuite/d10v-elf/t-sub.s | 42 - sim/testsuite/d10v-elf/t-sub2w.s | 57 - sim/testsuite/d10v-elf/t-subi.s | 39 - sim/testsuite/d10v-elf/t-trap.s | 5 - sim/testsuite/d10v/ChangeLog | 144 + sim/testsuite/d10v/allinsn.exp | 17 + sim/testsuite/d10v/exit47.s | 8 + sim/testsuite/d10v/hello.s | 8 + sim/testsuite/d10v/t-ae-ld-d.s | 17 + sim/testsuite/d10v/t-ae-ld-i.s | 20 + sim/testsuite/d10v/t-ae-ld-id.s | 19 + sim/testsuite/d10v/t-ae-ld-im.s | 20 + sim/testsuite/d10v/t-ae-ld-ip.s | 20 + sim/testsuite/d10v/t-ae-ld2w-d.s | 17 + sim/testsuite/d10v/t-ae-ld2w-i.s | 20 + sim/testsuite/d10v/t-ae-ld2w-id.s | 18 + sim/testsuite/d10v/t-ae-ld2w-im.s | 20 + sim/testsuite/d10v/t-ae-ld2w-ip.s | 20 + sim/testsuite/d10v/t-ae-st-d.s | 17 + sim/testsuite/d10v/t-ae-st-i.s | 20 + sim/testsuite/d10v/t-ae-st-id.s | 18 + sim/testsuite/d10v/t-ae-st-im.s | 20 + sim/testsuite/d10v/t-ae-st-ip.s | 20 + sim/testsuite/d10v/t-ae-st-is.s | 20 + sim/testsuite/d10v/t-ae-st2w-d.s | 17 + sim/testsuite/d10v/t-ae-st2w-i.s | 20 + sim/testsuite/d10v/t-ae-st2w-id.s | 18 + sim/testsuite/d10v/t-ae-st2w-im.s | 20 + sim/testsuite/d10v/t-ae-st2w-ip.s | 20 + sim/testsuite/d10v/t-ae-st2w-is.s | 20 + sim/testsuite/d10v/t-dbt.s | 38 + sim/testsuite/d10v/t-ld-st.s | 36 + sim/testsuite/d10v/t-mac.s | 75 + sim/testsuite/d10v/t-macros.i | 235 + sim/testsuite/d10v/t-mod-ld-pre.s | 126 + sim/testsuite/d10v/t-msbu.s | 32 + sim/testsuite/d10v/t-mulxu.s | 32 + sim/testsuite/d10v/t-mvtac.s | 23 + sim/testsuite/d10v/t-mvtc.s | 134 + sim/testsuite/d10v/t-rac.s | 20 + sim/testsuite/d10v/t-rachi.s | 32 + sim/testsuite/d10v/t-rdt.s | 23 + sim/testsuite/d10v/t-rep.s | 49 + sim/testsuite/d10v/t-rie-xx.s | 16 + sim/testsuite/d10v/t-rte.s | 22 + sim/testsuite/d10v/t-sac.s | 27 + sim/testsuite/d10v/t-sachi.s | 26 + sim/testsuite/d10v/t-sadd.s | 42 + sim/testsuite/d10v/t-slae.s | 43 + sim/testsuite/d10v/t-sp.s | 21 + sim/testsuite/d10v/t-sub.s | 46 + sim/testsuite/d10v/t-sub2w.s | 61 + sim/testsuite/d10v/t-subi.s | 43 + sim/testsuite/d10v/t-trap.s | 10 + sim/testsuite/frv-elf/ChangeLog | 48 - sim/testsuite/frv-elf/Makefile.in | 158 - sim/testsuite/frv-elf/cache.s | 164 - sim/testsuite/frv-elf/configure | 2984 ---- sim/testsuite/frv-elf/configure.ac | 18 - sim/testsuite/frv-elf/exit47.s | 5 - sim/testsuite/frv-elf/grloop.s | 10 - sim/testsuite/frv-elf/hello.s | 16 - sim/testsuite/frv-elf/loop.s | 2 - sim/testsuite/frv/ChangeLog | 82 + sim/testsuite/{sim => }/frv/add.cgs | 0 sim/testsuite/{sim => }/frv/add.pcgs | 0 sim/testsuite/{sim => }/frv/addcc.cgs | 0 sim/testsuite/{sim => }/frv/addi.cgs | 0 sim/testsuite/{sim => }/frv/addicc.cgs | 0 sim/testsuite/{sim => }/frv/addx.cgs | 0 sim/testsuite/{sim => }/frv/addxcc.cgs | 0 sim/testsuite/{sim => }/frv/addxi.cgs | 0 sim/testsuite/{sim => }/frv/addxicc.cgs | 0 sim/testsuite/{sim => }/frv/allinsn.exp | 0 sim/testsuite/{sim => }/frv/and.cgs | 0 sim/testsuite/{sim => }/frv/andcc.cgs | 0 sim/testsuite/{sim => }/frv/andcr.cgs | 0 sim/testsuite/{sim => }/frv/andi.cgs | 0 sim/testsuite/{sim => }/frv/andicc.cgs | 0 sim/testsuite/{sim => }/frv/andncr.cgs | 0 sim/testsuite/{sim => }/frv/bar.cgs | 0 sim/testsuite/{sim => }/frv/bc.cgs | 0 sim/testsuite/{sim => }/frv/bcclr.cgs | 0 sim/testsuite/{sim => }/frv/bceqlr.cgs | 0 sim/testsuite/{sim => }/frv/bcgelr.cgs | 0 sim/testsuite/{sim => }/frv/bcgtlr.cgs | 0 sim/testsuite/{sim => }/frv/bchilr.cgs | 0 sim/testsuite/{sim => }/frv/bclelr.cgs | 0 sim/testsuite/{sim => }/frv/bclr.cgs | 0 sim/testsuite/{sim => }/frv/bclslr.cgs | 0 sim/testsuite/{sim => }/frv/bcltlr.cgs | 0 sim/testsuite/{sim => }/frv/bcnclr.cgs | 0 sim/testsuite/{sim => }/frv/bcnelr.cgs | 0 sim/testsuite/{sim => }/frv/bcnlr.cgs | 0 sim/testsuite/{sim => }/frv/bcnolr.cgs | 0 sim/testsuite/{sim => }/frv/bcnvlr.cgs | 0 sim/testsuite/{sim => }/frv/bcplr.cgs | 0 sim/testsuite/{sim => }/frv/bcralr.cgs | 0 sim/testsuite/{sim => }/frv/bctrlr.cgs | 0 sim/testsuite/{sim => }/frv/bcvlr.cgs | 0 sim/testsuite/{sim => }/frv/beq.cgs | 0 sim/testsuite/{sim => }/frv/beqlr.cgs | 0 sim/testsuite/{sim => }/frv/bge.cgs | 0 sim/testsuite/{sim => }/frv/bgelr.cgs | 0 sim/testsuite/{sim => }/frv/bgt.cgs | 0 sim/testsuite/{sim => }/frv/bgtlr.cgs | 0 sim/testsuite/{sim => }/frv/bhi.cgs | 0 sim/testsuite/{sim => }/frv/bhilr.cgs | 0 sim/testsuite/{sim => }/frv/ble.cgs | 0 sim/testsuite/{sim => }/frv/blelr.cgs | 0 sim/testsuite/{sim => }/frv/bls.cgs | 0 sim/testsuite/{sim => }/frv/blslr.cgs | 0 sim/testsuite/{sim => }/frv/blt.cgs | 0 sim/testsuite/{sim => }/frv/bltlr.cgs | 0 sim/testsuite/{sim => }/frv/bn.cgs | 0 sim/testsuite/{sim => }/frv/bnc.cgs | 0 sim/testsuite/{sim => }/frv/bnclr.cgs | 0 sim/testsuite/{sim => }/frv/bne.cgs | 0 sim/testsuite/{sim => }/frv/bnelr.cgs | 0 sim/testsuite/{sim => }/frv/bnlr.cgs | 0 sim/testsuite/{sim => }/frv/bno.cgs | 0 sim/testsuite/{sim => }/frv/bnolr.cgs | 0 sim/testsuite/{sim => }/frv/bnv.cgs | 0 sim/testsuite/{sim => }/frv/bnvlr.cgs | 0 sim/testsuite/{sim => }/frv/bp.cgs | 0 sim/testsuite/{sim => }/frv/bplr.cgs | 0 sim/testsuite/{sim => }/frv/bra.cgs | 0 sim/testsuite/{sim => }/frv/bralr.cgs | 0 sim/testsuite/{sim => }/frv/branch.pcgs | 0 sim/testsuite/{sim => }/frv/break.cgs | 0 sim/testsuite/{sim => }/frv/bv.cgs | 0 sim/testsuite/{sim => }/frv/bvlr.cgs | 0 sim/testsuite/frv/cache.ms | 168 + sim/testsuite/{sim => }/frv/cadd.cgs | 0 sim/testsuite/{sim => }/frv/caddcc.cgs | 0 sim/testsuite/{sim => }/frv/call.cgs | 0 sim/testsuite/{sim => }/frv/call.pcgs | 0 sim/testsuite/{sim => }/frv/callil.cgs | 0 sim/testsuite/{sim => }/frv/calll.cgs | 0 sim/testsuite/{sim => }/frv/cand.cgs | 0 sim/testsuite/{sim => }/frv/candcc.cgs | 0 sim/testsuite/{sim => }/frv/ccalll.cgs | 0 sim/testsuite/{sim => }/frv/cckc.cgs | 0 sim/testsuite/{sim => }/frv/cckeq.cgs | 0 sim/testsuite/{sim => }/frv/cckge.cgs | 0 sim/testsuite/{sim => }/frv/cckgt.cgs | 0 sim/testsuite/{sim => }/frv/cckhi.cgs | 0 sim/testsuite/{sim => }/frv/cckle.cgs | 0 sim/testsuite/{sim => }/frv/cckls.cgs | 0 sim/testsuite/{sim => }/frv/ccklt.cgs | 0 sim/testsuite/{sim => }/frv/cckn.cgs | 0 sim/testsuite/{sim => }/frv/ccknc.cgs | 0 sim/testsuite/{sim => }/frv/cckne.cgs | 0 sim/testsuite/{sim => }/frv/cckno.cgs | 0 sim/testsuite/{sim => }/frv/ccknv.cgs | 0 sim/testsuite/{sim => }/frv/cckp.cgs | 0 sim/testsuite/{sim => }/frv/cckra.cgs | 0 sim/testsuite/{sim => }/frv/cckv.cgs | 0 sim/testsuite/{sim => }/frv/ccmp.cgs | 0 sim/testsuite/{sim => }/frv/cfabss.cgs | 0 sim/testsuite/{sim => }/frv/cfadds.cgs | 0 sim/testsuite/{sim => }/frv/cfckeq.cgs | 0 sim/testsuite/{sim => }/frv/cfckge.cgs | 0 sim/testsuite/{sim => }/frv/cfckgt.cgs | 0 sim/testsuite/{sim => }/frv/cfckle.cgs | 0 sim/testsuite/{sim => }/frv/cfcklg.cgs | 0 sim/testsuite/{sim => }/frv/cfcklt.cgs | 0 sim/testsuite/{sim => }/frv/cfckne.cgs | 0 sim/testsuite/{sim => }/frv/cfckno.cgs | 0 sim/testsuite/{sim => }/frv/cfcko.cgs | 0 sim/testsuite/{sim => }/frv/cfckra.cgs | 0 sim/testsuite/{sim => }/frv/cfcku.cgs | 0 sim/testsuite/{sim => }/frv/cfckue.cgs | 0 sim/testsuite/{sim => }/frv/cfckug.cgs | 0 sim/testsuite/{sim => }/frv/cfckuge.cgs | 0 sim/testsuite/{sim => }/frv/cfckul.cgs | 0 sim/testsuite/{sim => }/frv/cfckule.cgs | 0 sim/testsuite/{sim => }/frv/cfcmps.cgs | 0 sim/testsuite/{sim => }/frv/cfdivs.cgs | 0 sim/testsuite/{sim => }/frv/cfitos.cgs | 0 sim/testsuite/{sim => }/frv/cfmadds.cgs | 0 sim/testsuite/{sim => }/frv/cfmas.cgs | 0 sim/testsuite/{sim => }/frv/cfmovs.cgs | 0 sim/testsuite/{sim => }/frv/cfmss.cgs | 0 sim/testsuite/{sim => }/frv/cfmsubs.cgs | 0 sim/testsuite/{sim => }/frv/cfmuls.cgs | 0 sim/testsuite/{sim => }/frv/cfnegs.cgs | 0 sim/testsuite/{sim => }/frv/cfsqrts.cgs | 0 sim/testsuite/{sim => }/frv/cfstoi.cgs | 0 sim/testsuite/{sim => }/frv/cfsubs.cgs | 0 sim/testsuite/{sim => }/frv/cjmpl.cgs | 0 sim/testsuite/{sim => }/frv/ckc.cgs | 0 sim/testsuite/{sim => }/frv/ckeq.cgs | 0 sim/testsuite/{sim => }/frv/ckge.cgs | 0 sim/testsuite/{sim => }/frv/ckgt.cgs | 0 sim/testsuite/{sim => }/frv/ckhi.cgs | 0 sim/testsuite/{sim => }/frv/ckle.cgs | 0 sim/testsuite/{sim => }/frv/ckls.cgs | 0 sim/testsuite/{sim => }/frv/cklt.cgs | 0 sim/testsuite/{sim => }/frv/ckn.cgs | 0 sim/testsuite/{sim => }/frv/cknc.cgs | 0 sim/testsuite/{sim => }/frv/ckne.cgs | 0 sim/testsuite/{sim => }/frv/ckno.cgs | 0 sim/testsuite/{sim => }/frv/cknv.cgs | 0 sim/testsuite/{sim => }/frv/ckp.cgs | 0 sim/testsuite/{sim => }/frv/ckra.cgs | 0 sim/testsuite/{sim => }/frv/ckv.cgs | 0 sim/testsuite/{sim => }/frv/cld.cgs | 0 sim/testsuite/{sim => }/frv/cldbf.cgs | 0 sim/testsuite/{sim => }/frv/cldbfu.cgs | 0 sim/testsuite/{sim => }/frv/cldd.cgs | 0 sim/testsuite/{sim => }/frv/clddf.cgs | 0 sim/testsuite/{sim => }/frv/clddfu.cgs | 0 sim/testsuite/{sim => }/frv/clddu.cgs | 0 sim/testsuite/{sim => }/frv/cldf.cgs | 0 sim/testsuite/{sim => }/frv/cldfu.cgs | 0 sim/testsuite/{sim => }/frv/cldhf.cgs | 0 sim/testsuite/{sim => }/frv/cldhfu.cgs | 0 sim/testsuite/{sim => }/frv/cldq.cgs | 0 sim/testsuite/{sim => }/frv/cldqu.cgs | 0 sim/testsuite/{sim => }/frv/cldsb.cgs | 0 sim/testsuite/{sim => }/frv/cldsbu.cgs | 0 sim/testsuite/{sim => }/frv/cldsh.cgs | 0 sim/testsuite/{sim => }/frv/cldshu.cgs | 0 sim/testsuite/{sim => }/frv/cldu.cgs | 0 sim/testsuite/{sim => }/frv/cldub.cgs | 0 sim/testsuite/{sim => }/frv/cldubu.cgs | 0 sim/testsuite/{sim => }/frv/clduh.cgs | 0 sim/testsuite/{sim => }/frv/clduhu.cgs | 0 sim/testsuite/{sim => }/frv/clrfa.cgs | 0 sim/testsuite/{sim => }/frv/clrfr.cgs | 0 sim/testsuite/{sim => }/frv/clrga.cgs | 0 sim/testsuite/{sim => }/frv/clrgr.cgs | 0 sim/testsuite/{sim => }/frv/cmaddhss.cgs | 0 sim/testsuite/{sim => }/frv/cmaddhus.cgs | 0 sim/testsuite/{sim => }/frv/cmand.cgs | 0 sim/testsuite/{sim => }/frv/cmbtoh.cgs | 0 sim/testsuite/{sim => }/frv/cmbtohe.cgs | 0 sim/testsuite/{sim => }/frv/cmcpxis.cgs | 0 sim/testsuite/{sim => }/frv/cmcpxiu.cgs | 0 sim/testsuite/{sim => }/frv/cmcpxrs.cgs | 0 sim/testsuite/{sim => }/frv/cmcpxru.cgs | 0 sim/testsuite/{sim => }/frv/cmexpdhd.cgs | 0 sim/testsuite/{sim => }/frv/cmexpdhw.cgs | 0 sim/testsuite/{sim => }/frv/cmhtob.cgs | 0 sim/testsuite/{sim => }/frv/cmmachs.cgs | 0 sim/testsuite/{sim => }/frv/cmmachu.cgs | 0 sim/testsuite/{sim => }/frv/cmmulhs.cgs | 0 sim/testsuite/{sim => }/frv/cmmulhu.cgs | 0 sim/testsuite/{sim => }/frv/cmnot.cgs | 0 sim/testsuite/{sim => }/frv/cmor.cgs | 0 sim/testsuite/{sim => }/frv/cmov.cgs | 0 sim/testsuite/{sim => }/frv/cmovfg.cgs | 0 sim/testsuite/{sim => }/frv/cmovfgd.cgs | 0 sim/testsuite/{sim => }/frv/cmovgf.cgs | 0 sim/testsuite/{sim => }/frv/cmovgfd.cgs | 0 sim/testsuite/{sim => }/frv/cmp.cgs | 0 sim/testsuite/{sim => }/frv/cmpb.cgs | 0 sim/testsuite/{sim => }/frv/cmpba.cgs | 0 sim/testsuite/{sim => }/frv/cmpi.cgs | 0 sim/testsuite/{sim => }/frv/cmqmachs.cgs | 0 sim/testsuite/{sim => }/frv/cmqmachu.cgs | 0 sim/testsuite/{sim => }/frv/cmqmulhs.cgs | 0 sim/testsuite/{sim => }/frv/cmqmulhu.cgs | 0 sim/testsuite/{sim => }/frv/cmsubhss.cgs | 0 sim/testsuite/{sim => }/frv/cmsubhus.cgs | 0 sim/testsuite/{sim => }/frv/cmxor.cgs | 0 sim/testsuite/{sim => }/frv/cnot.cgs | 0 sim/testsuite/{sim => }/frv/commitfa.cgs | 0 sim/testsuite/{sim => }/frv/commitfr.cgs | 0 sim/testsuite/{sim => }/frv/commitga.cgs | 0 sim/testsuite/{sim => }/frv/commitgr.cgs | 0 sim/testsuite/{sim => }/frv/cop1.cgs | 0 sim/testsuite/{sim => }/frv/cop2.cgs | 0 sim/testsuite/{sim => }/frv/cor.cgs | 0 sim/testsuite/{sim => }/frv/corcc.cgs | 0 sim/testsuite/{sim => }/frv/cscan.cgs | 0 sim/testsuite/{sim => }/frv/csdiv.cgs | 0 sim/testsuite/{sim => }/frv/csll.cgs | 0 sim/testsuite/{sim => }/frv/csllcc.cgs | 0 sim/testsuite/{sim => }/frv/csmul.cgs | 0 sim/testsuite/{sim => }/frv/csmulcc.cgs | 0 sim/testsuite/{sim => }/frv/csra.cgs | 0 sim/testsuite/{sim => }/frv/csracc.cgs | 0 sim/testsuite/{sim => }/frv/csrl.cgs | 0 sim/testsuite/{sim => }/frv/csrlcc.cgs | 0 sim/testsuite/{sim => }/frv/cst.cgs | 0 sim/testsuite/{sim => }/frv/cstb.cgs | 0 sim/testsuite/{sim => }/frv/cstbf.cgs | 0 sim/testsuite/{sim => }/frv/cstbfu.cgs | 0 sim/testsuite/{sim => }/frv/cstbu.cgs | 0 sim/testsuite/{sim => }/frv/cstd.cgs | 0 sim/testsuite/{sim => }/frv/cstdf.cgs | 0 sim/testsuite/{sim => }/frv/cstdfu.cgs | 0 sim/testsuite/{sim => }/frv/cstdu.cgs | 0 sim/testsuite/{sim => }/frv/cstf.cgs | 0 sim/testsuite/{sim => }/frv/cstfu.cgs | 0 sim/testsuite/{sim => }/frv/csth.cgs | 0 sim/testsuite/{sim => }/frv/csthf.cgs | 0 sim/testsuite/{sim => }/frv/csthfu.cgs | 0 sim/testsuite/{sim => }/frv/csthu.cgs | 0 sim/testsuite/{sim => }/frv/cstq.cgs | 0 sim/testsuite/{sim => }/frv/cstu.cgs | 0 sim/testsuite/{sim => }/frv/csub.cgs | 0 sim/testsuite/{sim => }/frv/csubcc.cgs | 0 sim/testsuite/{sim => }/frv/cswap.cgs | 0 sim/testsuite/{sim => }/frv/cudiv.cgs | 0 sim/testsuite/{sim => }/frv/cxor.cgs | 0 sim/testsuite/{sim => }/frv/cxorcc.cgs | 0 sim/testsuite/{sim => }/frv/dcef.cgs | 0 sim/testsuite/{sim => }/frv/dcei.cgs | 0 sim/testsuite/{sim => }/frv/dcf.cgs | 0 sim/testsuite/{sim => }/frv/dci.cgs | 0 sim/testsuite/frv/exit47.ms | 11 + sim/testsuite/{sim => }/frv/fabsd.cgs | 0 sim/testsuite/{sim => }/frv/fabss.cgs | 0 sim/testsuite/{sim => }/frv/faddd.cgs | 0 sim/testsuite/{sim => }/frv/fadds.cgs | 0 sim/testsuite/{sim => }/frv/fbeq.cgs | 0 sim/testsuite/{sim => }/frv/fbeqlr.cgs | 0 sim/testsuite/{sim => }/frv/fbge.cgs | 0 sim/testsuite/{sim => }/frv/fbgelr.cgs | 0 sim/testsuite/{sim => }/frv/fbgt.cgs | 0 sim/testsuite/{sim => }/frv/fbgtlr.cgs | 0 sim/testsuite/{sim => }/frv/fble.cgs | 0 sim/testsuite/{sim => }/frv/fblelr.cgs | 0 sim/testsuite/{sim => }/frv/fblg.cgs | 0 sim/testsuite/{sim => }/frv/fblglr.cgs | 0 sim/testsuite/{sim => }/frv/fblt.cgs | 0 sim/testsuite/{sim => }/frv/fbltlr.cgs | 0 sim/testsuite/{sim => }/frv/fbne.cgs | 0 sim/testsuite/{sim => }/frv/fbnelr.cgs | 0 sim/testsuite/{sim => }/frv/fbno.cgs | 0 sim/testsuite/{sim => }/frv/fbnolr.cgs | 0 sim/testsuite/{sim => }/frv/fbo.cgs | 0 sim/testsuite/{sim => }/frv/fbolr.cgs | 0 sim/testsuite/{sim => }/frv/fbra.cgs | 0 sim/testsuite/{sim => }/frv/fbralr.cgs | 0 sim/testsuite/{sim => }/frv/fbu.cgs | 0 sim/testsuite/{sim => }/frv/fbue.cgs | 0 sim/testsuite/{sim => }/frv/fbuelr.cgs | 0 sim/testsuite/{sim => }/frv/fbug.cgs | 0 sim/testsuite/{sim => }/frv/fbuge.cgs | 0 sim/testsuite/{sim => }/frv/fbugelr.cgs | 0 sim/testsuite/{sim => }/frv/fbuglr.cgs | 0 sim/testsuite/{sim => }/frv/fbul.cgs | 0 sim/testsuite/{sim => }/frv/fbule.cgs | 0 sim/testsuite/{sim => }/frv/fbulelr.cgs | 0 sim/testsuite/{sim => }/frv/fbullr.cgs | 0 sim/testsuite/{sim => }/frv/fbulr.cgs | 0 sim/testsuite/{sim => }/frv/fcbeqlr.cgs | 0 sim/testsuite/{sim => }/frv/fcbgelr.cgs | 0 sim/testsuite/{sim => }/frv/fcbgtlr.cgs | 0 sim/testsuite/{sim => }/frv/fcblelr.cgs | 0 sim/testsuite/{sim => }/frv/fcblglr.cgs | 0 sim/testsuite/{sim => }/frv/fcbltlr.cgs | 0 sim/testsuite/{sim => }/frv/fcbnelr.cgs | 0 sim/testsuite/{sim => }/frv/fcbnolr.cgs | 0 sim/testsuite/{sim => }/frv/fcbolr.cgs | 0 sim/testsuite/{sim => }/frv/fcbralr.cgs | 0 sim/testsuite/{sim => }/frv/fcbuelr.cgs | 0 sim/testsuite/{sim => }/frv/fcbugelr.cgs | 0 sim/testsuite/{sim => }/frv/fcbuglr.cgs | 0 sim/testsuite/{sim => }/frv/fcbulelr.cgs | 0 sim/testsuite/{sim => }/frv/fcbullr.cgs | 0 sim/testsuite/{sim => }/frv/fcbulr.cgs | 0 sim/testsuite/{sim => }/frv/fckeq.cgs | 0 sim/testsuite/{sim => }/frv/fckge.cgs | 0 sim/testsuite/{sim => }/frv/fckgt.cgs | 0 sim/testsuite/{sim => }/frv/fckle.cgs | 0 sim/testsuite/{sim => }/frv/fcklg.cgs | 0 sim/testsuite/{sim => }/frv/fcklt.cgs | 0 sim/testsuite/{sim => }/frv/fckne.cgs | 0 sim/testsuite/{sim => }/frv/fckno.cgs | 0 sim/testsuite/{sim => }/frv/fcko.cgs | 0 sim/testsuite/{sim => }/frv/fckra.cgs | 0 sim/testsuite/{sim => }/frv/fcku.cgs | 0 sim/testsuite/{sim => }/frv/fckue.cgs | 0 sim/testsuite/{sim => }/frv/fckug.cgs | 0 sim/testsuite/{sim => }/frv/fckuge.cgs | 0 sim/testsuite/{sim => }/frv/fckul.cgs | 0 sim/testsuite/{sim => }/frv/fckule.cgs | 0 sim/testsuite/{sim => }/frv/fcmpd.cgs | 0 sim/testsuite/{sim => }/frv/fcmps.cgs | 0 sim/testsuite/{sim => }/frv/fdabss.cgs | 0 sim/testsuite/{sim => }/frv/fdadds.cgs | 0 sim/testsuite/{sim => }/frv/fdcmps.cgs | 0 sim/testsuite/{sim => }/frv/fddivs.cgs | 0 sim/testsuite/{sim => }/frv/fditos.cgs | 0 sim/testsuite/{sim => }/frv/fdivd.cgs | 0 sim/testsuite/{sim => }/frv/fdivs.cgs | 0 sim/testsuite/{sim => }/frv/fdmadds.cgs | 0 sim/testsuite/{sim => }/frv/fdmas.cgs | 0 sim/testsuite/{sim => }/frv/fdmovs.cgs | 0 sim/testsuite/{sim => }/frv/fdmss.cgs | 0 sim/testsuite/{sim => }/frv/fdmulcs.cgs | 0 sim/testsuite/{sim => }/frv/fdmuls.cgs | 0 sim/testsuite/{sim => }/frv/fdnegs.cgs | 0 sim/testsuite/{sim => }/frv/fdsads.cgs | 0 sim/testsuite/{sim => }/frv/fdsqrts.cgs | 0 sim/testsuite/{sim => }/frv/fdstoi.cgs | 0 sim/testsuite/{sim => }/frv/fdsubs.cgs | 0 sim/testsuite/{sim => }/frv/fdtoi.cgs | 0 sim/testsuite/{sim => }/frv/fitod.cgs | 0 sim/testsuite/{sim => }/frv/fitos.cgs | 0 sim/testsuite/{sim => }/frv/fmad.cgs | 0 sim/testsuite/{sim => }/frv/fmaddd.cgs | 0 sim/testsuite/{sim => }/frv/fmadds.cgs | 0 sim/testsuite/{sim => }/frv/fmas.cgs | 0 sim/testsuite/{sim => }/frv/fmovd.cgs | 0 sim/testsuite/{sim => }/frv/fmovs.cgs | 0 sim/testsuite/{sim => }/frv/fmsd.cgs | 0 sim/testsuite/{sim => }/frv/fmss.cgs | 0 sim/testsuite/{sim => }/frv/fmsubd.cgs | 0 sim/testsuite/{sim => }/frv/fmsubs.cgs | 0 sim/testsuite/{sim => }/frv/fmuld.cgs | 0 sim/testsuite/{sim => }/frv/fmuls.cgs | 0 sim/testsuite/{sim => }/frv/fnegd.cgs | 0 sim/testsuite/{sim => }/frv/fnegs.cgs | 0 sim/testsuite/{sim => }/frv/fnop.cgs | 0 sim/testsuite/{sim => }/frv/fr400/addss.cgs | 0 sim/testsuite/{sim => }/frv/fr400/allinsn.exp | 0 sim/testsuite/{sim => }/frv/fr400/csdiv.cgs | 0 sim/testsuite/{sim => }/frv/fr400/maddaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr400/masaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr400/maveh.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mclracc.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhdseth.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhdsets.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhsethih.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhsethis.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhsetloh.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhsetlos.cgs | 0 sim/testsuite/{sim => }/frv/fr400/movgs.cgs | 0 sim/testsuite/{sim => }/frv/fr400/movsg.cgs | 0 sim/testsuite/{sim => }/frv/fr400/msubaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr400/scutss.cgs | 0 sim/testsuite/{sim => }/frv/fr400/sdiv.cgs | 0 sim/testsuite/{sim => }/frv/fr400/sdivi.cgs | 0 sim/testsuite/{sim => }/frv/fr400/slass.cgs | 0 sim/testsuite/{sim => }/frv/fr400/smass.cgs | 0 sim/testsuite/{sim => }/frv/fr400/smsss.cgs | 0 sim/testsuite/{sim => }/frv/fr400/smu.cgs | 0 sim/testsuite/{sim => }/frv/fr400/subss.cgs | 0 sim/testsuite/{sim => }/frv/fr400/udiv.cgs | 0 sim/testsuite/{sim => }/frv/fr400/udivi.cgs | 0 sim/testsuite/{sim => }/frv/fr500/allinsn.exp | 0 sim/testsuite/{sim => }/frv/fr500/cmqaddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr500/cmqaddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr500/cmqsubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr500/cmqsubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr500/dcpl.cgs | 0 sim/testsuite/{sim => }/frv/fr500/dcul.cgs | 0 sim/testsuite/{sim => }/frv/fr500/mclracc.cgs | 0 sim/testsuite/{sim => }/frv/fr500/mqaddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr500/mqaddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr500/mqsubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr500/mqsubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/allinsn.exp | 0 sim/testsuite/{sim => }/frv/fr550/cmaddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmaddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmcpxiu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmcpxru.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmmachs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmmachu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqaddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqaddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqmachs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqmachu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqsubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqsubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmsubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmsubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/dcpl.cgs | 0 sim/testsuite/{sim => }/frv/fr550/dcul.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mabshs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/maddaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/maddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/maddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/masaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mdaddaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mdasaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mdsubaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mmachs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mmachu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mmrdhs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mmrdhu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqaddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqaddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqmachs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqmachu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqmacxhs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqsubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqsubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqxmachs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqxmacxhs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/msubaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/msubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/msubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mtrap.cgs | 0 sim/testsuite/{sim => }/frv/fr550/udiv.cgs | 0 sim/testsuite/{sim => }/frv/fr550/udivi.cgs | 0 sim/testsuite/{sim => }/frv/fsqrtd.cgs | 0 sim/testsuite/{sim => }/frv/fsqrts.cgs | 0 sim/testsuite/{sim => }/frv/fstoi.cgs | 0 sim/testsuite/{sim => }/frv/fsubd.cgs | 0 sim/testsuite/{sim => }/frv/fsubs.cgs | 0 sim/testsuite/{sim => }/frv/fteq.cgs | 0 sim/testsuite/{sim => }/frv/ftge.cgs | 0 sim/testsuite/{sim => }/frv/ftgt.cgs | 0 sim/testsuite/{sim => }/frv/ftieq.cgs | 0 sim/testsuite/{sim => }/frv/ftige.cgs | 0 sim/testsuite/{sim => }/frv/ftigt.cgs | 0 sim/testsuite/{sim => }/frv/ftile.cgs | 0 sim/testsuite/{sim => }/frv/ftilg.cgs | 0 sim/testsuite/{sim => }/frv/ftilt.cgs | 0 sim/testsuite/{sim => }/frv/ftine.cgs | 0 sim/testsuite/{sim => }/frv/ftino.cgs | 0 sim/testsuite/{sim => }/frv/ftio.cgs | 0 sim/testsuite/{sim => }/frv/ftira.cgs | 0 sim/testsuite/{sim => }/frv/ftiu.cgs | 0 sim/testsuite/{sim => }/frv/ftiue.cgs | 0 sim/testsuite/{sim => }/frv/ftiug.cgs | 0 sim/testsuite/{sim => }/frv/ftiuge.cgs | 0 sim/testsuite/{sim => }/frv/ftiul.cgs | 0 sim/testsuite/{sim => }/frv/ftle.cgs | 0 sim/testsuite/{sim => }/frv/ftlg.cgs | 0 sim/testsuite/{sim => }/frv/ftlt.cgs | 0 sim/testsuite/{sim => }/frv/ftne.cgs | 0 sim/testsuite/{sim => }/frv/ftno.cgs | 0 sim/testsuite/{sim => }/frv/fto.cgs | 0 sim/testsuite/{sim => }/frv/ftra.cgs | 0 sim/testsuite/{sim => }/frv/ftu.cgs | 0 sim/testsuite/{sim => }/frv/ftue.cgs | 0 sim/testsuite/{sim => }/frv/ftug.cgs | 0 sim/testsuite/{sim => }/frv/ftuge.cgs | 0 sim/testsuite/{sim => }/frv/ftul.cgs | 0 sim/testsuite/{sim => }/frv/ftule.cgs | 0 sim/testsuite/frv/grloop.ms | 13 + sim/testsuite/frv/hello.ms | 19 + sim/testsuite/{sim => }/frv/icei.cgs | 0 sim/testsuite/{sim => }/frv/ici.cgs | 0 sim/testsuite/{sim => }/frv/icpl.cgs | 0 sim/testsuite/{sim => }/frv/icul.cgs | 0 sim/testsuite/{sim => }/frv/interrupts.exp | 0 .../{sim => }/frv/interrupts/Ipipe-fr400.cgs | 0 .../{sim => }/frv/interrupts/Ipipe-fr500.cgs | 0 .../{sim => }/frv/interrupts/badalign-fr550.cgs | 0 .../{sim => }/frv/interrupts/badalign.cgs | 0 .../{sim => }/frv/interrupts/compound-fr550.cgs | 0 .../{sim => }/frv/interrupts/compound.cgs | 0 .../frv/interrupts/data_store_error-fr550.cgs | 0 .../{sim => }/frv/interrupts/data_store_error.cgs | 0 .../frv/interrupts/fp_exception-fr550.cgs | 0 .../{sim => }/frv/interrupts/fp_exception.cgs | 0 sim/testsuite/{sim => }/frv/interrupts/illinsn.cgs | 0 .../frv/interrupts/insn_access_error-fr550.cgs | 0 .../{sim => }/frv/interrupts/insn_access_error.cgs | 0 .../{sim => }/frv/interrupts/mp_exception.cgs | 0 .../frv/interrupts/privileged_instruction.cgs | 0 .../{sim => }/frv/interrupts/regalign.cgs | 0 sim/testsuite/{sim => }/frv/interrupts/reset.cgs | 0 .../{sim => }/frv/interrupts/shadow_regs.cgs | 0 sim/testsuite/{sim => }/frv/interrupts/timer.cgs | 0 sim/testsuite/{sim => }/frv/jmpil.cgs | 0 sim/testsuite/{sim => }/frv/jmpl.cgs | 0 sim/testsuite/{sim => }/frv/jmpl.pcgs | 0 sim/testsuite/{sim => }/frv/ld.cgs | 0 sim/testsuite/{sim => }/frv/ldbf.cgs | 0 sim/testsuite/{sim => }/frv/ldbfi.cgs | 0 sim/testsuite/{sim => }/frv/ldbfu.cgs | 0 sim/testsuite/{sim => }/frv/ldc.cgs | 0 sim/testsuite/{sim => }/frv/ldcu.cgs | 0 sim/testsuite/{sim => }/frv/ldd.cgs | 0 sim/testsuite/{sim => }/frv/lddc.cgs | 0 sim/testsuite/{sim => }/frv/lddcu.cgs | 0 sim/testsuite/{sim => }/frv/lddf.cgs | 0 sim/testsuite/{sim => }/frv/lddfi.cgs | 0 sim/testsuite/{sim => }/frv/lddfu.cgs | 0 sim/testsuite/{sim => }/frv/lddi.cgs | 0 sim/testsuite/{sim => }/frv/lddu.cgs | 0 sim/testsuite/{sim => }/frv/ldf.cgs | 0 sim/testsuite/{sim => }/frv/ldfi.cgs | 0 sim/testsuite/{sim => }/frv/ldfu.cgs | 0 sim/testsuite/{sim => }/frv/ldhf.cgs | 0 sim/testsuite/{sim => }/frv/ldhfi.cgs | 0 sim/testsuite/{sim => }/frv/ldhfu.cgs | 0 sim/testsuite/{sim => }/frv/ldi.cgs | 0 sim/testsuite/{sim => }/frv/ldq.cgs | 0 sim/testsuite/{sim => }/frv/ldqc.cgs | 0 sim/testsuite/{sim => }/frv/ldqcu.cgs | 0 sim/testsuite/{sim => }/frv/ldqf.cgs | 0 sim/testsuite/{sim => }/frv/ldqfi.cgs | 0 sim/testsuite/{sim => }/frv/ldqfu.cgs | 0 sim/testsuite/{sim => }/frv/ldqi.cgs | 0 sim/testsuite/{sim => }/frv/ldqu.cgs | 0 sim/testsuite/{sim => }/frv/ldsb.cgs | 0 sim/testsuite/{sim => }/frv/ldsbi.cgs | 0 sim/testsuite/{sim => }/frv/ldsbu.cgs | 0 sim/testsuite/{sim => }/frv/ldsh.cgs | 0 sim/testsuite/{sim => }/frv/ldshi.cgs | 0 sim/testsuite/{sim => }/frv/ldshu.cgs | 0 sim/testsuite/{sim => }/frv/ldu.cgs | 0 sim/testsuite/{sim => }/frv/ldub.cgs | 0 sim/testsuite/{sim => }/frv/ldubi.cgs | 0 sim/testsuite/{sim => }/frv/ldubu.cgs | 0 sim/testsuite/{sim => }/frv/lduh.cgs | 0 sim/testsuite/{sim => }/frv/lduhi.cgs | 0 sim/testsuite/{sim => }/frv/lduhu.cgs | 0 sim/testsuite/{sim => }/frv/lrbranch.pcgs | 0 sim/testsuite/{sim => }/frv/mabshs.cgs | 0 sim/testsuite/{sim => }/frv/maddhss.cgs | 0 sim/testsuite/{sim => }/frv/maddhus.cgs | 0 sim/testsuite/{sim => }/frv/mand.cgs | 0 sim/testsuite/{sim => }/frv/maveh.cgs | 0 sim/testsuite/{sim => }/frv/mbtoh.cgs | 0 sim/testsuite/{sim => }/frv/mbtohe.cgs | 0 sim/testsuite/{sim => }/frv/mclracc.cgs | 0 sim/testsuite/{sim => }/frv/mcmpsh.cgs | 0 sim/testsuite/{sim => }/frv/mcmpuh.cgs | 0 sim/testsuite/{sim => }/frv/mcop1.cgs | 0 sim/testsuite/{sim => }/frv/mcop2.cgs | 0 sim/testsuite/{sim => }/frv/mcplhi.cgs | 0 sim/testsuite/{sim => }/frv/mcpli.cgs | 0 sim/testsuite/{sim => }/frv/mcpxis.cgs | 0 sim/testsuite/{sim => }/frv/mcpxiu.cgs | 0 sim/testsuite/{sim => }/frv/mcpxrs.cgs | 0 sim/testsuite/{sim => }/frv/mcpxru.cgs | 0 sim/testsuite/{sim => }/frv/mcut.cgs | 0 sim/testsuite/{sim => }/frv/mcuti.cgs | 0 sim/testsuite/{sim => }/frv/mcutss.cgs | 0 sim/testsuite/{sim => }/frv/mcutssi.cgs | 0 sim/testsuite/{sim => }/frv/mdaddaccs.cgs | 0 sim/testsuite/{sim => }/frv/mdasaccs.cgs | 0 sim/testsuite/{sim => }/frv/mdcutssi.cgs | 0 sim/testsuite/{sim => }/frv/mdpackh.cgs | 0 sim/testsuite/{sim => }/frv/mdrotli.cgs | 0 sim/testsuite/{sim => }/frv/mdsubaccs.cgs | 0 sim/testsuite/{sim => }/frv/mdunpackh.cgs | 0 sim/testsuite/{sim => }/frv/membar.cgs | 0 sim/testsuite/{sim => }/frv/mexpdhd.cgs | 0 sim/testsuite/{sim => }/frv/mexpdhw.cgs | 0 sim/testsuite/{sim => }/frv/mhdseth.cgs | 0 sim/testsuite/{sim => }/frv/mhdsets.cgs | 0 sim/testsuite/{sim => }/frv/mhsethih.cgs | 0 sim/testsuite/{sim => }/frv/mhsethis.cgs | 0 sim/testsuite/{sim => }/frv/mhsetloh.cgs | 0 sim/testsuite/{sim => }/frv/mhsetlos.cgs | 0 sim/testsuite/{sim => }/frv/mhtob.cgs | 0 sim/testsuite/frv/misc.exp | 19 + sim/testsuite/{sim => }/frv/mmachs.cgs | 0 sim/testsuite/{sim => }/frv/mmachu.cgs | 0 sim/testsuite/{sim => }/frv/mmrdhs.cgs | 0 sim/testsuite/{sim => }/frv/mmrdhu.cgs | 0 sim/testsuite/{sim => }/frv/mmulhs.cgs | 0 sim/testsuite/{sim => }/frv/mmulhu.cgs | 0 sim/testsuite/{sim => }/frv/mmulxhs.cgs | 0 sim/testsuite/{sim => }/frv/mmulxhu.cgs | 0 sim/testsuite/{sim => }/frv/mnop.cgs | 0 sim/testsuite/{sim => }/frv/mnot.cgs | 0 sim/testsuite/{sim => }/frv/mor.cgs | 0 sim/testsuite/{sim => }/frv/mov.cgs | 0 sim/testsuite/{sim => }/frv/movfg.cgs | 0 sim/testsuite/{sim => }/frv/movfgd.cgs | 0 sim/testsuite/{sim => }/frv/movfgq.cgs | 0 sim/testsuite/{sim => }/frv/movgf.cgs | 0 sim/testsuite/{sim => }/frv/movgfd.cgs | 0 sim/testsuite/{sim => }/frv/movgfq.cgs | 0 sim/testsuite/{sim => }/frv/movgs.cgs | 0 sim/testsuite/{sim => }/frv/movsg.cgs | 0 sim/testsuite/{sim => }/frv/mpackh.cgs | 0 sim/testsuite/{sim => }/frv/mqcpxis.cgs | 0 sim/testsuite/{sim => }/frv/mqcpxiu.cgs | 0 sim/testsuite/{sim => }/frv/mqcpxrs.cgs | 0 sim/testsuite/{sim => }/frv/mqcpxru.cgs | 0 sim/testsuite/{sim => }/frv/mqlclrhs.cgs | 0 sim/testsuite/{sim => }/frv/mqlmths.cgs | 0 sim/testsuite/{sim => }/frv/mqmachs.cgs | 0 sim/testsuite/{sim => }/frv/mqmachu.cgs | 0 sim/testsuite/{sim => }/frv/mqmacxhs.cgs | 0 sim/testsuite/{sim => }/frv/mqmulhs.cgs | 0 sim/testsuite/{sim => }/frv/mqmulhu.cgs | 0 sim/testsuite/{sim => }/frv/mqmulxhs.cgs | 0 sim/testsuite/{sim => }/frv/mqmulxhu.cgs | 0 sim/testsuite/{sim => }/frv/mqsaths.cgs | 0 sim/testsuite/{sim => }/frv/mqsllhi.cgs | 0 sim/testsuite/{sim => }/frv/mqsrahi.cgs | 0 sim/testsuite/{sim => }/frv/mqxmachs.cgs | 0 sim/testsuite/{sim => }/frv/mqxmacxhs.cgs | 0 sim/testsuite/{sim => }/frv/mrdacc.cgs | 0 sim/testsuite/{sim => }/frv/mrdaccg.cgs | 0 sim/testsuite/{sim => }/frv/mrotli.cgs | 0 sim/testsuite/{sim => }/frv/mrotri.cgs | 0 sim/testsuite/{sim => }/frv/msaths.cgs | 0 sim/testsuite/{sim => }/frv/msathu.cgs | 0 sim/testsuite/{sim => }/frv/msllhi.cgs | 0 sim/testsuite/{sim => }/frv/msrahi.cgs | 0 sim/testsuite/{sim => }/frv/msrlhi.cgs | 0 sim/testsuite/{sim => }/frv/msubhss.cgs | 0 sim/testsuite/{sim => }/frv/msubhus.cgs | 0 sim/testsuite/{sim => }/frv/mtrap.cgs | 0 sim/testsuite/{sim => }/frv/munpackh.cgs | 0 sim/testsuite/{sim => }/frv/mwcut.cgs | 0 sim/testsuite/{sim => }/frv/mwcuti.cgs | 0 sim/testsuite/{sim => }/frv/mwtacc.cgs | 0 sim/testsuite/{sim => }/frv/mwtaccg.cgs | 0 sim/testsuite/{sim => }/frv/mxor.cgs | 0 sim/testsuite/{sim => }/frv/nandcr.cgs | 0 sim/testsuite/{sim => }/frv/nandncr.cgs | 0 sim/testsuite/{sim => }/frv/nfadds.cgs | 0 sim/testsuite/{sim => }/frv/nfdadds.cgs | 0 sim/testsuite/{sim => }/frv/nfdcmps.cgs | 0 sim/testsuite/{sim => }/frv/nfddivs.cgs | 0 sim/testsuite/{sim => }/frv/nfditos.cgs | 0 sim/testsuite/{sim => }/frv/nfdivs.cgs | 0 sim/testsuite/{sim => }/frv/nfdmadds.cgs | 0 sim/testsuite/{sim => }/frv/nfdmas.cgs | 0 sim/testsuite/{sim => }/frv/nfdmss.cgs | 0 sim/testsuite/{sim => }/frv/nfdmulcs.cgs | 0 sim/testsuite/{sim => }/frv/nfdmuls.cgs | 0 sim/testsuite/{sim => }/frv/nfdsads.cgs | 0 sim/testsuite/{sim => }/frv/nfdsqrts.cgs | 0 sim/testsuite/{sim => }/frv/nfdstoi.cgs | 0 sim/testsuite/{sim => }/frv/nfdsubs.cgs | 0 sim/testsuite/{sim => }/frv/nfitos.cgs | 0 sim/testsuite/{sim => }/frv/nfmadds.cgs | 0 sim/testsuite/{sim => }/frv/nfmas.cgs | 0 sim/testsuite/{sim => }/frv/nfmss.cgs | 0 sim/testsuite/{sim => }/frv/nfmsubs.cgs | 0 sim/testsuite/{sim => }/frv/nfmuls.cgs | 0 sim/testsuite/{sim => }/frv/nfsqrts.cgs | 0 sim/testsuite/{sim => }/frv/nfstoi.cgs | 0 sim/testsuite/{sim => }/frv/nfsubs.cgs | 0 sim/testsuite/{sim => }/frv/nld.cgs | 0 sim/testsuite/{sim => }/frv/nldbf.cgs | 0 sim/testsuite/{sim => }/frv/nldbfi.cgs | 0 sim/testsuite/{sim => }/frv/nldbfu.cgs | 0 sim/testsuite/{sim => }/frv/nldd.cgs | 0 sim/testsuite/{sim => }/frv/nlddf.cgs | 0 sim/testsuite/{sim => }/frv/nlddfi.cgs | 0 sim/testsuite/{sim => }/frv/nlddfu.cgs | 0 sim/testsuite/{sim => }/frv/nlddi.cgs | 0 sim/testsuite/{sim => }/frv/nlddu.cgs | 0 sim/testsuite/{sim => }/frv/nldf.cgs | 0 sim/testsuite/{sim => }/frv/nldfi.cgs | 0 sim/testsuite/{sim => }/frv/nldfu.cgs | 0 sim/testsuite/{sim => }/frv/nldhf.cgs | 0 sim/testsuite/{sim => }/frv/nldhfi.cgs | 0 sim/testsuite/{sim => }/frv/nldhfu.cgs | 0 sim/testsuite/{sim => }/frv/nldi.cgs | 0 sim/testsuite/{sim => }/frv/nldq.cgs | 0 sim/testsuite/{sim => }/frv/nldqf.cgs | 0 sim/testsuite/{sim => }/frv/nldqfi.cgs | 0 sim/testsuite/{sim => }/frv/nldqfu.cgs | 0 sim/testsuite/{sim => }/frv/nldqu.cgs | 0 sim/testsuite/{sim => }/frv/nldsb.cgs | 0 sim/testsuite/{sim => }/frv/nldsbi.cgs | 0 sim/testsuite/{sim => }/frv/nldsbu.cgs | 0 sim/testsuite/{sim => }/frv/nldsh.cgs | 0 sim/testsuite/{sim => }/frv/nldshi.cgs | 0 sim/testsuite/{sim => }/frv/nldshu.cgs | 0 sim/testsuite/{sim => }/frv/nldu.cgs | 0 sim/testsuite/{sim => }/frv/nldub.cgs | 0 sim/testsuite/{sim => }/frv/nldubi.cgs | 0 sim/testsuite/{sim => }/frv/nldubu.cgs | 0 sim/testsuite/{sim => }/frv/nlduh.cgs | 0 sim/testsuite/{sim => }/frv/nlduhi.cgs | 0 sim/testsuite/{sim => }/frv/nlduhu.cgs | 0 sim/testsuite/{sim => }/frv/nop.cgs | 0 sim/testsuite/{sim => }/frv/norcr.cgs | 0 sim/testsuite/{sim => }/frv/norncr.cgs | 0 sim/testsuite/{sim => }/frv/not.cgs | 0 sim/testsuite/{sim => }/frv/notcr.cgs | 0 sim/testsuite/{sim => }/frv/nsdiv.cgs | 0 sim/testsuite/{sim => }/frv/nsdivi.cgs | 0 sim/testsuite/{sim => }/frv/nudiv.cgs | 0 sim/testsuite/{sim => }/frv/nudivi.cgs | 0 sim/testsuite/{sim => }/frv/or.cgs | 0 sim/testsuite/{sim => }/frv/orcc.cgs | 0 sim/testsuite/{sim => }/frv/orcr.cgs | 0 sim/testsuite/{sim => }/frv/ori.cgs | 0 sim/testsuite/{sim => }/frv/oricc.cgs | 0 sim/testsuite/{sim => }/frv/orncr.cgs | 0 sim/testsuite/{sim => }/frv/parallel.exp | 0 sim/testsuite/{sim => }/frv/ret.cgs | 0 sim/testsuite/{sim => }/frv/rett.cgs | 0 sim/testsuite/{sim => }/frv/scan.cgs | 0 sim/testsuite/{sim => }/frv/scani.cgs | 0 sim/testsuite/{sim => }/frv/sdiv.cgs | 0 sim/testsuite/{sim => }/frv/sdivi.cgs | 0 sim/testsuite/{sim => }/frv/sethi.cgs | 0 sim/testsuite/{sim => }/frv/sethilo.pcgs | 0 sim/testsuite/{sim => }/frv/setlo.cgs | 0 sim/testsuite/{sim => }/frv/setlos.cgs | 0 sim/testsuite/{sim => }/frv/sll.cgs | 0 sim/testsuite/{sim => }/frv/sllcc.cgs | 0 sim/testsuite/{sim => }/frv/slli.cgs | 0 sim/testsuite/{sim => }/frv/sllicc.cgs | 0 sim/testsuite/{sim => }/frv/smul.cgs | 0 sim/testsuite/{sim => }/frv/smulcc.cgs | 0 sim/testsuite/{sim => }/frv/smuli.cgs | 0 sim/testsuite/{sim => }/frv/smulicc.cgs | 0 sim/testsuite/{sim => }/frv/sra.cgs | 0 sim/testsuite/{sim => }/frv/sracc.cgs | 0 sim/testsuite/{sim => }/frv/srai.cgs | 0 sim/testsuite/{sim => }/frv/sraicc.cgs | 0 sim/testsuite/{sim => }/frv/srl.cgs | 0 sim/testsuite/{sim => }/frv/srlcc.cgs | 0 sim/testsuite/{sim => }/frv/srli.cgs | 0 sim/testsuite/{sim => }/frv/srlicc.cgs | 0 sim/testsuite/{sim => }/frv/st.cgs | 0 sim/testsuite/{sim => }/frv/stb.cgs | 0 sim/testsuite/{sim => }/frv/stbf.cgs | 0 sim/testsuite/{sim => }/frv/stbfi.cgs | 0 sim/testsuite/{sim => }/frv/stbfu.cgs | 0 sim/testsuite/{sim => }/frv/stbi.cgs | 0 sim/testsuite/{sim => }/frv/stbu.cgs | 0 sim/testsuite/{sim => }/frv/stc.cgs | 0 sim/testsuite/{sim => }/frv/stcu.cgs | 0 sim/testsuite/{sim => }/frv/std.cgs | 0 sim/testsuite/{sim => }/frv/std.pcgs | 0 sim/testsuite/{sim => }/frv/stdc.cgs | 0 sim/testsuite/{sim => }/frv/stdc.pcgs | 0 sim/testsuite/{sim => }/frv/stdcu.cgs | 0 sim/testsuite/{sim => }/frv/stdf.cgs | 0 sim/testsuite/{sim => }/frv/stdf.pcgs | 0 sim/testsuite/{sim => }/frv/stdfi.cgs | 0 sim/testsuite/{sim => }/frv/stdfu.cgs | 0 sim/testsuite/{sim => }/frv/stdi.cgs | 0 sim/testsuite/{sim => }/frv/stdu.cgs | 0 sim/testsuite/{sim => }/frv/stf.cgs | 0 sim/testsuite/{sim => }/frv/stfi.cgs | 0 sim/testsuite/{sim => }/frv/stfu.cgs | 0 sim/testsuite/{sim => }/frv/sth.cgs | 0 sim/testsuite/{sim => }/frv/sthf.cgs | 0 sim/testsuite/{sim => }/frv/sthfi.cgs | 0 sim/testsuite/{sim => }/frv/sthfu.cgs | 0 sim/testsuite/{sim => }/frv/sthi.cgs | 0 sim/testsuite/{sim => }/frv/sthu.cgs | 0 sim/testsuite/{sim => }/frv/sti.cgs | 0 sim/testsuite/{sim => }/frv/stq.cgs | 0 sim/testsuite/{sim => }/frv/stq.pcgs | 0 sim/testsuite/{sim => }/frv/stqc.cgs | 0 sim/testsuite/{sim => }/frv/stqc.pcgs | 0 sim/testsuite/{sim => }/frv/stqcu.cgs | 0 sim/testsuite/{sim => }/frv/stqf.cgs | 0 sim/testsuite/{sim => }/frv/stqf.pcgs | 0 sim/testsuite/{sim => }/frv/stqfi.cgs | 0 sim/testsuite/{sim => }/frv/stqfu.cgs | 0 sim/testsuite/{sim => }/frv/stqi.cgs | 0 sim/testsuite/{sim => }/frv/stqu.cgs | 0 sim/testsuite/{sim => }/frv/stu.cgs | 0 sim/testsuite/{sim => }/frv/sub.cgs | 0 sim/testsuite/{sim => }/frv/subcc.cgs | 0 sim/testsuite/{sim => }/frv/subi.cgs | 0 sim/testsuite/{sim => }/frv/subicc.cgs | 0 sim/testsuite/{sim => }/frv/subx.cgs | 0 sim/testsuite/{sim => }/frv/subxcc.cgs | 0 sim/testsuite/{sim => }/frv/subxi.cgs | 0 sim/testsuite/{sim => }/frv/subxicc.cgs | 0 sim/testsuite/{sim => }/frv/swap.cgs | 0 sim/testsuite/{sim => }/frv/swapi.cgs | 0 sim/testsuite/{sim => }/frv/tc.cgs | 0 sim/testsuite/{sim => }/frv/teq.cgs | 0 sim/testsuite/{sim => }/frv/testutils.inc | 0 sim/testsuite/{sim => }/frv/tge.cgs | 0 sim/testsuite/{sim => }/frv/tgt.cgs | 0 sim/testsuite/{sim => }/frv/thi.cgs | 0 sim/testsuite/{sim => }/frv/tic.cgs | 0 sim/testsuite/{sim => }/frv/tieq.cgs | 0 sim/testsuite/{sim => }/frv/tige.cgs | 0 sim/testsuite/{sim => }/frv/tigt.cgs | 0 sim/testsuite/{sim => }/frv/tihi.cgs | 0 sim/testsuite/{sim => }/frv/tile.cgs | 0 sim/testsuite/{sim => }/frv/tils.cgs | 0 sim/testsuite/{sim => }/frv/tilt.cgs | 0 sim/testsuite/{sim => }/frv/tin.cgs | 0 sim/testsuite/{sim => }/frv/tinc.cgs | 0 sim/testsuite/{sim => }/frv/tine.cgs | 0 sim/testsuite/{sim => }/frv/tino.cgs | 0 sim/testsuite/{sim => }/frv/tinv.cgs | 0 sim/testsuite/{sim => }/frv/tip.cgs | 0 sim/testsuite/{sim => }/frv/tira.cgs | 0 sim/testsuite/{sim => }/frv/tiv.cgs | 0 sim/testsuite/{sim => }/frv/tle.cgs | 0 sim/testsuite/{sim => }/frv/tls.cgs | 0 sim/testsuite/{sim => }/frv/tlt.cgs | 0 sim/testsuite/{sim => }/frv/tn.cgs | 0 sim/testsuite/{sim => }/frv/tnc.cgs | 0 sim/testsuite/{sim => }/frv/tne.cgs | 0 sim/testsuite/{sim => }/frv/tno.cgs | 0 sim/testsuite/{sim => }/frv/tnv.cgs | 0 sim/testsuite/{sim => }/frv/tp.cgs | 0 sim/testsuite/{sim => }/frv/tra.cgs | 0 sim/testsuite/{sim => }/frv/tv.cgs | 0 sim/testsuite/{sim => }/frv/udiv.cgs | 0 sim/testsuite/{sim => }/frv/udivi.cgs | 0 sim/testsuite/{sim => }/frv/umul.cgs | 0 sim/testsuite/{sim => }/frv/umulcc.cgs | 0 sim/testsuite/{sim => }/frv/umuli.cgs | 0 sim/testsuite/{sim => }/frv/umulicc.cgs | 0 sim/testsuite/{sim => }/frv/xor.cgs | 0 sim/testsuite/{sim => }/frv/xorcc.cgs | 0 sim/testsuite/{sim => }/frv/xorcr.cgs | 0 sim/testsuite/{sim => }/frv/xori.cgs | 0 sim/testsuite/{sim => }/frv/xoricc.cgs | 0 sim/testsuite/{sim => }/ft32/ChangeLog | 0 sim/testsuite/{sim => }/ft32/allinsn.exp | 0 sim/testsuite/{sim => }/ft32/basic.s | 0 sim/testsuite/{sim => }/ft32/testutils.inc | 0 sim/testsuite/h8300/ChangeLog | 107 + sim/testsuite/{sim => }/h8300/addb.s | 0 sim/testsuite/{sim => }/h8300/addl.s | 0 sim/testsuite/{sim => }/h8300/adds.s | 0 sim/testsuite/{sim => }/h8300/addw.s | 0 sim/testsuite/{sim => }/h8300/addx.s | 0 sim/testsuite/h8300/allinsn.exp | 15 + sim/testsuite/{sim => }/h8300/andb.s | 0 sim/testsuite/{sim => }/h8300/andl.s | 0 sim/testsuite/{sim => }/h8300/andw.s | 0 sim/testsuite/{sim => }/h8300/band.s | 0 sim/testsuite/{sim => }/h8300/bfld.s | 0 sim/testsuite/{sim => }/h8300/biand.s | 0 sim/testsuite/{sim => }/h8300/bra.s | 0 sim/testsuite/{sim => }/h8300/brabc.s | 0 sim/testsuite/{sim => }/h8300/bset.s | 0 sim/testsuite/{sim => }/h8300/cmpb.s | 0 sim/testsuite/{sim => }/h8300/cmpl.s | 0 sim/testsuite/{sim => }/h8300/cmpw.s | 0 sim/testsuite/{sim => }/h8300/daa.s | 0 sim/testsuite/{sim => }/h8300/das.s | 0 sim/testsuite/{sim => }/h8300/dec.s | 0 sim/testsuite/{sim => }/h8300/div.s | 0 sim/testsuite/{sim => }/h8300/extl.s | 0 sim/testsuite/{sim => }/h8300/extw.s | 0 sim/testsuite/{sim => }/h8300/inc.s | 0 sim/testsuite/{sim => }/h8300/jmp.s | 0 sim/testsuite/{sim => }/h8300/ldc.s | 0 sim/testsuite/{sim => }/h8300/ldm.s | 0 sim/testsuite/{sim => }/h8300/mac.s | 0 sim/testsuite/{sim => }/h8300/mova.s | 0 sim/testsuite/{sim => }/h8300/movb.s | 0 sim/testsuite/{sim => }/h8300/movl.s | 0 sim/testsuite/{sim => }/h8300/movmd.s | 0 sim/testsuite/{sim => }/h8300/movsd.s | 0 sim/testsuite/{sim => }/h8300/movw.s | 0 sim/testsuite/{sim => }/h8300/mul.s | 0 sim/testsuite/{sim => }/h8300/neg.s | 0 sim/testsuite/{sim => }/h8300/nop.s | 0 sim/testsuite/{sim => }/h8300/not.s | 0 sim/testsuite/{sim => }/h8300/orb.s | 0 sim/testsuite/{sim => }/h8300/orl.s | 0 sim/testsuite/{sim => }/h8300/orw.s | 0 sim/testsuite/h8300/rotl.s | 1212 ++ sim/testsuite/h8300/rotr.s | 1802 +++ sim/testsuite/h8300/rotxl.s | 167 + sim/testsuite/h8300/rotxr.s | 2002 +++ sim/testsuite/h8300/shal.s | 167 + sim/testsuite/h8300/shar.s | 2000 +++ sim/testsuite/h8300/shll.s | 375 + sim/testsuite/h8300/shlr.s | 4085 +++++ sim/testsuite/{sim => }/h8300/stack.s | 0 sim/testsuite/{sim => }/h8300/stc.s | 0 sim/testsuite/{sim => }/h8300/subb.s | 0 sim/testsuite/{sim => }/h8300/subl.s | 0 sim/testsuite/{sim => }/h8300/subs.s | 0 sim/testsuite/{sim => }/h8300/subw.s | 0 sim/testsuite/{sim => }/h8300/subx.s | 0 sim/testsuite/h8300/tas.s | 80 + sim/testsuite/{sim => }/h8300/testutils.inc | 0 sim/testsuite/{sim => }/h8300/xorb.s | 0 sim/testsuite/{sim => }/h8300/xorl.s | 0 sim/testsuite/{sim => }/h8300/xorw.s | 0 sim/testsuite/{sim => }/iq2000/ChangeLog | 0 sim/testsuite/{sim => }/iq2000/allinsn.exp | 0 sim/testsuite/{sim => }/iq2000/pass.s | 0 sim/testsuite/{sim => }/iq2000/testutils.inc | 0 sim/testsuite/lib/sim-defs.exp | 23 +- sim/testsuite/{sim => }/lm32/ChangeLog | 0 sim/testsuite/{sim => }/lm32/allinsn.exp | 0 sim/testsuite/{sim => }/lm32/pass.s | 0 sim/testsuite/{sim => }/lm32/testutils.inc | 0 sim/testsuite/{sim => }/m32c/ChangeLog | 0 sim/testsuite/{sim => }/m32c/allinsn.exp | 0 sim/testsuite/{sim => }/m32c/blinky.s | 0 sim/testsuite/{sim => }/m32c/fail.s | 0 sim/testsuite/{sim => }/m32c/gloss.s | 0 sim/testsuite/{sim => }/m32c/pass.s | 0 sim/testsuite/{sim => }/m32c/sample.ld | 0 sim/testsuite/{sim => }/m32c/sample.s | 0 sim/testsuite/{sim => }/m32c/sample2.c | 0 sim/testsuite/{sim => }/m32c/testutils.inc | 0 sim/testsuite/m32r-elf/ChangeLog | 18 - sim/testsuite/m32r-elf/Makefile.in | 156 - sim/testsuite/m32r-elf/configure | 2984 ---- sim/testsuite/m32r-elf/configure.ac | 18 - sim/testsuite/m32r-elf/exit47.s | 7 - sim/testsuite/m32r-elf/hello.s | 17 - sim/testsuite/m32r-elf/loop.s | 2 - sim/testsuite/m32r/ChangeLog | 126 + sim/testsuite/{sim => }/m32r/add.cgs | 0 sim/testsuite/{sim => }/m32r/add3.cgs | 0 sim/testsuite/{sim => }/m32r/addi.cgs | 0 sim/testsuite/{sim => }/m32r/addv.cgs | 0 sim/testsuite/{sim => }/m32r/addv3.cgs | 0 sim/testsuite/{sim => }/m32r/addx.cgs | 0 sim/testsuite/{sim => }/m32r/allinsn.exp | 0 sim/testsuite/{sim => }/m32r/and.cgs | 0 sim/testsuite/{sim => }/m32r/and3.cgs | 0 sim/testsuite/{sim => }/m32r/bc24.cgs | 0 sim/testsuite/{sim => }/m32r/bc8.cgs | 0 sim/testsuite/{sim => }/m32r/beq.cgs | 0 sim/testsuite/{sim => }/m32r/beqz.cgs | 0 sim/testsuite/{sim => }/m32r/bgez.cgs | 0 sim/testsuite/{sim => }/m32r/bgtz.cgs | 0 sim/testsuite/{sim => }/m32r/bl24.cgs | 0 sim/testsuite/{sim => }/m32r/bl8.cgs | 0 sim/testsuite/{sim => }/m32r/blez.cgs | 0 sim/testsuite/{sim => }/m32r/bltz.cgs | 0 sim/testsuite/{sim => }/m32r/bnc24.cgs | 0 sim/testsuite/{sim => }/m32r/bnc8.cgs | 0 sim/testsuite/{sim => }/m32r/bne.cgs | 0 sim/testsuite/{sim => }/m32r/bnez.cgs | 0 sim/testsuite/{sim => }/m32r/bra24.cgs | 0 sim/testsuite/{sim => }/m32r/bra8.cgs | 0 sim/testsuite/{sim => }/m32r/cmp.cgs | 0 sim/testsuite/{sim => }/m32r/cmpi.cgs | 0 sim/testsuite/{sim => }/m32r/cmpu.cgs | 0 sim/testsuite/{sim => }/m32r/cmpui.cgs | 0 sim/testsuite/{sim => }/m32r/div.cgs | 0 sim/testsuite/{sim => }/m32r/divu.cgs | 0 sim/testsuite/m32r/exit47.ms | 11 + sim/testsuite/{sim => }/m32r/hello.ms | 0 sim/testsuite/{sim => }/m32r/hw-trap.ms | 0 sim/testsuite/{sim => }/m32r/jl.cgs | 0 sim/testsuite/{sim => }/m32r/jmp.cgs | 0 sim/testsuite/{sim => }/m32r/ld-d.cgs | 0 sim/testsuite/{sim => }/m32r/ld-plus.cgs | 0 sim/testsuite/{sim => }/m32r/ld.cgs | 0 sim/testsuite/{sim => }/m32r/ld24.cgs | 0 sim/testsuite/{sim => }/m32r/ldb-d.cgs | 0 sim/testsuite/{sim => }/m32r/ldb.cgs | 0 sim/testsuite/{sim => }/m32r/ldh-d.cgs | 0 sim/testsuite/{sim => }/m32r/ldh.cgs | 0 sim/testsuite/{sim => }/m32r/ldi16.cgs | 0 sim/testsuite/{sim => }/m32r/ldi8.cgs | 0 sim/testsuite/{sim => }/m32r/ldub-d.cgs | 0 sim/testsuite/{sim => }/m32r/ldub.cgs | 0 sim/testsuite/{sim => }/m32r/lduh-d.cgs | 0 sim/testsuite/{sim => }/m32r/lduh.cgs | 0 sim/testsuite/{sim => }/m32r/lock.cgs | 0 sim/testsuite/{sim => }/m32r/machi.cgs | 0 sim/testsuite/{sim => }/m32r/maclo.cgs | 0 sim/testsuite/{sim => }/m32r/macwhi.cgs | 0 sim/testsuite/{sim => }/m32r/macwlo.cgs | 0 sim/testsuite/{sim => }/m32r/misc.exp | 0 sim/testsuite/{sim => }/m32r/mul.cgs | 0 sim/testsuite/{sim => }/m32r/mulhi.cgs | 0 sim/testsuite/{sim => }/m32r/mullo.cgs | 0 sim/testsuite/{sim => }/m32r/mulwhi.cgs | 0 sim/testsuite/{sim => }/m32r/mulwlo.cgs | 0 sim/testsuite/{sim => }/m32r/mv.cgs | 0 sim/testsuite/{sim => }/m32r/mvfachi.cgs | 0 sim/testsuite/{sim => }/m32r/mvfaclo.cgs | 0 sim/testsuite/{sim => }/m32r/mvfacmi.cgs | 0 sim/testsuite/{sim => }/m32r/mvfc.cgs | 0 sim/testsuite/{sim => }/m32r/mvtachi.cgs | 0 sim/testsuite/{sim => }/m32r/mvtaclo.cgs | 0 sim/testsuite/{sim => }/m32r/mvtc.cgs | 0 sim/testsuite/{sim => }/m32r/neg.cgs | 0 sim/testsuite/{sim => }/m32r/nop.cgs | 0 sim/testsuite/{sim => }/m32r/not.cgs | 0 sim/testsuite/{sim => }/m32r/or.cgs | 0 sim/testsuite/{sim => }/m32r/or3.cgs | 0 sim/testsuite/{sim => }/m32r/rac.cgs | 0 sim/testsuite/{sim => }/m32r/rach.cgs | 0 sim/testsuite/{sim => }/m32r/rem.cgs | 0 sim/testsuite/{sim => }/m32r/remu.cgs | 0 sim/testsuite/{sim => }/m32r/rte.cgs | 0 sim/testsuite/{sim => }/m32r/seth.cgs | 0 sim/testsuite/{sim => }/m32r/sll.cgs | 0 sim/testsuite/{sim => }/m32r/sll3.cgs | 0 sim/testsuite/{sim => }/m32r/slli.cgs | 0 sim/testsuite/{sim => }/m32r/sra.cgs | 0 sim/testsuite/{sim => }/m32r/sra3.cgs | 0 sim/testsuite/{sim => }/m32r/srai.cgs | 0 sim/testsuite/{sim => }/m32r/srl.cgs | 0 sim/testsuite/{sim => }/m32r/srl3.cgs | 0 sim/testsuite/{sim => }/m32r/srli.cgs | 0 sim/testsuite/{sim => }/m32r/st-d.cgs | 0 sim/testsuite/{sim => }/m32r/st-minus.cgs | 0 sim/testsuite/{sim => }/m32r/st-plus.cgs | 0 sim/testsuite/{sim => }/m32r/st.cgs | 0 sim/testsuite/{sim => }/m32r/stb-d.cgs | 0 sim/testsuite/{sim => }/m32r/stb.cgs | 0 sim/testsuite/{sim => }/m32r/sth-d.cgs | 0 sim/testsuite/{sim => }/m32r/sth.cgs | 0 sim/testsuite/{sim => }/m32r/sub.cgs | 0 sim/testsuite/{sim => }/m32r/subv.cgs | 0 sim/testsuite/{sim => }/m32r/subx.cgs | 0 sim/testsuite/{sim => }/m32r/testutils.inc | 0 sim/testsuite/{sim => }/m32r/trap.cgs | 0 sim/testsuite/{sim => }/m32r/unlock.cgs | 0 sim/testsuite/{sim => }/m32r/uread16.ms | 0 sim/testsuite/{sim => }/m32r/uread32.ms | 0 sim/testsuite/{sim => }/m32r/uwrite16.ms | 0 sim/testsuite/{sim => }/m32r/uwrite32.ms | 0 sim/testsuite/{sim => }/m32r/xor.cgs | 0 sim/testsuite/{sim => }/m32r/xor3.cgs | 0 sim/testsuite/{sim => }/m68hc11/ChangeLog | 0 sim/testsuite/{sim => }/m68hc11/allinsn.exp | 0 sim/testsuite/{sim => }/m68hc11/pass.s | 0 sim/testsuite/{sim => }/m68hc11/testutils.inc | 0 sim/testsuite/{sim => }/mcore/ChangeLog | 0 sim/testsuite/{sim => }/mcore/allinsn.exp | 0 sim/testsuite/{sim => }/mcore/fail.s | 0 sim/testsuite/{sim => }/mcore/pass.s | 0 sim/testsuite/{sim => }/mcore/testutils.inc | 0 sim/testsuite/{sim => }/microblaze/ChangeLog | 0 sim/testsuite/{sim => }/microblaze/allinsn.exp | 0 sim/testsuite/{sim => }/microblaze/pass.s | 0 sim/testsuite/{sim => }/microblaze/testutils.inc | 0 sim/testsuite/{sim => }/mips/ChangeLog | 0 sim/testsuite/{sim => }/mips/basic.exp | 0 sim/testsuite/{sim => }/mips/fpu64-ps-sb1.s | 0 sim/testsuite/{sim => }/mips/fpu64-ps.s | 0 sim/testsuite/{sim => }/mips/hilo-hazard-1.s | 0 sim/testsuite/{sim => }/mips/hilo-hazard-2.s | 0 sim/testsuite/{sim => }/mips/hilo-hazard-3.s | 0 sim/testsuite/{sim => }/mips/hilo-hazard-4.s | 0 sim/testsuite/{sim => }/mips/mdmx-ob-sb1.s | 0 sim/testsuite/{sim => }/mips/mdmx-ob.s | 0 sim/testsuite/{sim => }/mips/mips32-dsp.s | 0 sim/testsuite/{sim => }/mips/mips32-dsp2.s | 0 sim/testsuite/{sim => }/mips/sanity.s | 0 sim/testsuite/{sim => }/mips/testutils.inc | 0 sim/testsuite/{sim => }/mips/utils-dsp.inc | 0 sim/testsuite/{sim => }/mips/utils-fpu.inc | 0 sim/testsuite/{sim => }/mips/utils-mdmx.inc | 0 sim/testsuite/mips64el-elf/ChangeLog | 19 - sim/testsuite/mips64el-elf/Makefile.in | 170 - sim/testsuite/mips64el-elf/configure | 2984 ---- sim/testsuite/mips64el-elf/configure.ac | 18 - sim/testsuite/{sim => }/mn10300/ChangeLog | 0 sim/testsuite/{sim => }/mn10300/allinsn.exp | 0 sim/testsuite/{sim => }/mn10300/pass.s | 0 sim/testsuite/{sim => }/mn10300/testutils.inc | 0 sim/testsuite/{sim => }/moxie/ChangeLog | 0 sim/testsuite/{sim => }/moxie/allinsn.exp | 0 sim/testsuite/{sim => }/moxie/pass.s | 0 sim/testsuite/{sim => }/moxie/testutils.inc | 0 sim/testsuite/{sim => }/msp430/ChangeLog | 0 sim/testsuite/{sim => }/msp430/add.s | 0 sim/testsuite/{sim => }/msp430/allinsn.exp | 0 sim/testsuite/{sim => }/msp430/mpyull_hwmult.s | 0 sim/testsuite/{sim => }/msp430/rrux.s | 0 sim/testsuite/{sim => }/msp430/testutils.inc | 0 sim/testsuite/{sim => }/or1k/ChangeLog | 0 sim/testsuite/{sim => }/or1k/add.S | 0 sim/testsuite/{sim => }/or1k/adrp.S | 0 sim/testsuite/{sim => }/or1k/alltests.exp | 0 sim/testsuite/{sim => }/or1k/and.S | 0 sim/testsuite/{sim => }/or1k/basic.S | 0 sim/testsuite/{sim => }/or1k/div.S | 0 sim/testsuite/{sim => }/or1k/ext.S | 0 sim/testsuite/{sim => }/or1k/find.S | 0 sim/testsuite/{sim => }/or1k/flag.S | 0 sim/testsuite/{sim => }/or1k/fpu-unordered.S | 0 sim/testsuite/{sim => }/or1k/fpu.S | 0 sim/testsuite/{sim => }/or1k/fpu64a32-unordered.S | 0 sim/testsuite/{sim => }/or1k/fpu64a32.S | 0 sim/testsuite/{sim => }/or1k/jump.S | 0 sim/testsuite/{sim => }/or1k/load.S | 0 sim/testsuite/{sim => }/or1k/mac.S | 0 sim/testsuite/{sim => }/or1k/mfspr.S | 0 sim/testsuite/{sim => }/or1k/mul.S | 0 sim/testsuite/{sim => }/or1k/or.S | 0 sim/testsuite/{sim => }/or1k/or1k-asm-test-env.h | 0 .../{sim => }/or1k/or1k-asm-test-helpers.h | 0 sim/testsuite/{sim => }/or1k/or1k-asm-test.h | 0 sim/testsuite/{sim => }/or1k/or1k-asm.h | 0 sim/testsuite/{sim => }/or1k/or1k-test.ld | 0 sim/testsuite/{sim => }/or1k/ror.S | 0 sim/testsuite/{sim => }/or1k/shift.S | 0 sim/testsuite/{sim => }/or1k/spr-defs.h | 0 sim/testsuite/{sim => }/or1k/sub.S | 0 sim/testsuite/{sim => }/or1k/xor.S | 0 sim/testsuite/{sim => }/pru/ChangeLog | 0 sim/testsuite/{sim => }/pru/add.s | 0 sim/testsuite/{sim => }/pru/allinsn.exp | 0 sim/testsuite/{sim => }/pru/dmem-zero-pass.s | 0 sim/testsuite/{sim => }/pru/dmem-zero-trap.s | 0 sim/testsuite/{sim => }/pru/dram.s | 0 sim/testsuite/{sim => }/pru/jmp.s | 0 sim/testsuite/{sim => }/pru/lmbd.s | 0 sim/testsuite/{sim => }/pru/loop-imm.s | 0 sim/testsuite/{sim => }/pru/loop-reg.s | 0 sim/testsuite/{sim => }/pru/mul.s | 0 sim/testsuite/{sim => }/pru/subreg.s | 0 sim/testsuite/{sim => }/pru/testutils.inc | 0 sim/testsuite/{sim => }/sh/ChangeLog | 0 sim/testsuite/{sim => }/sh/add.s | 0 sim/testsuite/{sim => }/sh/allinsn.exp | 0 sim/testsuite/{sim => }/sh/and.s | 0 sim/testsuite/{sim => }/sh/bandor.s | 0 sim/testsuite/{sim => }/sh/bandornot.s | 0 sim/testsuite/{sim => }/sh/bclr.s | 0 sim/testsuite/{sim => }/sh/bld.s | 0 sim/testsuite/{sim => }/sh/bldnot.s | 0 sim/testsuite/{sim => }/sh/bset.s | 0 sim/testsuite/{sim => }/sh/bst.s | 0 sim/testsuite/{sim => }/sh/bxor.s | 0 sim/testsuite/{sim => }/sh/clip.s | 0 sim/testsuite/{sim => }/sh/div.s | 0 sim/testsuite/{sim => }/sh/dmxy.s | 0 sim/testsuite/{sim => }/sh/fabs.s | 0 sim/testsuite/{sim => }/sh/fadd.s | 0 sim/testsuite/{sim => }/sh/fail.s | 0 sim/testsuite/{sim => }/sh/fcmpeq.s | 0 sim/testsuite/{sim => }/sh/fcmpgt.s | 0 sim/testsuite/{sim => }/sh/fcnvds.s | 0 sim/testsuite/{sim => }/sh/fcnvsd.s | 0 sim/testsuite/{sim => }/sh/fdiv.s | 0 sim/testsuite/{sim => }/sh/fipr.s | 0 sim/testsuite/{sim => }/sh/fldi0.s | 0 sim/testsuite/{sim => }/sh/fldi1.s | 0 sim/testsuite/{sim => }/sh/flds.s | 0 sim/testsuite/{sim => }/sh/float.s | 0 sim/testsuite/{sim => }/sh/fmac.s | 0 sim/testsuite/{sim => }/sh/fmov.s | 0 sim/testsuite/{sim => }/sh/fmul.s | 0 sim/testsuite/{sim => }/sh/fneg.s | 0 sim/testsuite/{sim => }/sh/fpchg.s | 0 sim/testsuite/{sim => }/sh/frchg.s | 0 sim/testsuite/{sim => }/sh/fsca.s | 0 sim/testsuite/{sim => }/sh/fschg.s | 0 sim/testsuite/{sim => }/sh/fsqrt.s | 0 sim/testsuite/{sim => }/sh/fsrra.s | 0 sim/testsuite/{sim => }/sh/fsub.s | 0 sim/testsuite/{sim => }/sh/ftrc.s | 0 sim/testsuite/{sim => }/sh/ldrc.s | 0 sim/testsuite/{sim => }/sh/loop.s | 0 sim/testsuite/{sim => }/sh/macl.s | 0 sim/testsuite/{sim => }/sh/macw.s | 0 sim/testsuite/{sim => }/sh/mov.s | 0 sim/testsuite/{sim => }/sh/movi.s | 0 sim/testsuite/{sim => }/sh/movli.s | 0 sim/testsuite/{sim => }/sh/movua.s | 0 sim/testsuite/{sim => }/sh/movxy.s | 0 sim/testsuite/{sim => }/sh/mulr.s | 0 sim/testsuite/{sim => }/sh/pabs.s | 0 sim/testsuite/{sim => }/sh/padd.s | 0 sim/testsuite/{sim => }/sh/paddc.s | 0 sim/testsuite/{sim => }/sh/pand.s | 0 sim/testsuite/{sim => }/sh/pass.s | 0 sim/testsuite/{sim => }/sh/pclr.s | 0 sim/testsuite/{sim => }/sh/pdec.s | 0 sim/testsuite/{sim => }/sh/pdmsb.s | 0 sim/testsuite/{sim => }/sh/pinc.s | 0 sim/testsuite/{sim => }/sh/pmuls.s | 0 sim/testsuite/{sim => }/sh/prnd.s | 0 sim/testsuite/{sim => }/sh/pshai.s | 0 sim/testsuite/{sim => }/sh/pshar.s | 0 sim/testsuite/{sim => }/sh/pshli.s | 0 sim/testsuite/{sim => }/sh/pshlr.s | 0 sim/testsuite/{sim => }/sh/psub.s | 0 sim/testsuite/{sim => }/sh/pswap.s | 0 sim/testsuite/{sim => }/sh/pushpop.s | 0 sim/testsuite/{sim => }/sh/resbank.s | 0 sim/testsuite/{sim => }/sh/sett.s | 0 sim/testsuite/{sim => }/sh/shll.s | 0 sim/testsuite/{sim => }/sh/shll16.s | 0 sim/testsuite/{sim => }/sh/shll2.s | 0 sim/testsuite/{sim => }/sh/shll8.s | 0 sim/testsuite/{sim => }/sh/shlr.s | 0 sim/testsuite/{sim => }/sh/shlr16.s | 0 sim/testsuite/{sim => }/sh/shlr2.s | 0 sim/testsuite/{sim => }/sh/shlr8.s | 0 sim/testsuite/{sim => }/sh/swap.s | 0 sim/testsuite/{sim => }/sh/testutils.inc | 0 sim/testsuite/sim/cris/ChangeLog | 176 - sim/testsuite/sim/cris/c/c.exp | 244 - sim/testsuite/sim/cris/c/helloaout.c | 10 - sim/testsuite/sim/cris/c/kill2.c | 16 - sim/testsuite/sim/cris/c/openpf1.c | 38 - sim/testsuite/sim/cris/c/openpf2.c | 16 - sim/testsuite/sim/cris/c/pipe1.c | 47 - sim/testsuite/sim/cris/c/readlink4.c | 62 - sim/testsuite/sim/cris/c/sched1.c | 15 - sim/testsuite/sim/cris/c/sched2.c | 19 - sim/testsuite/sim/cris/c/sched3.c | 24 - sim/testsuite/sim/cris/c/sched4.c | 24 - sim/testsuite/sim/cris/c/sig5.c | 16 - sim/testsuite/sim/cris/c/sig8.c | 19 - sim/testsuite/sim/cris/hw/rv-n-cris/rvc.exp | 249 - sim/testsuite/sim/fr30/ChangeLog | 112 - sim/testsuite/sim/fr30/add.cgs | 55 - sim/testsuite/sim/fr30/add.ms | 13 - sim/testsuite/sim/fr30/add2.cgs | 43 - sim/testsuite/sim/fr30/addc.cgs | 50 - sim/testsuite/sim/fr30/addn.cgs | 55 - sim/testsuite/sim/fr30/addn2.cgs | 43 - sim/testsuite/sim/fr30/addsp.cgs | 31 - sim/testsuite/sim/fr30/allinsn.exp | 19 - sim/testsuite/sim/fr30/and.cgs | 57 - sim/testsuite/sim/fr30/andb.cgs | 31 - sim/testsuite/sim/fr30/andccr.cgs | 51 - sim/testsuite/sim/fr30/andh.cgs | 31 - sim/testsuite/sim/fr30/asr.cgs | 65 - sim/testsuite/sim/fr30/asr2.cgs | 36 - sim/testsuite/sim/fr30/bandh.cgs | 30 - sim/testsuite/sim/fr30/bandl.cgs | 30 - sim/testsuite/sim/fr30/bc.cgs | 109 - sim/testsuite/sim/fr30/beorh.cgs | 36 - sim/testsuite/sim/fr30/beorl.cgs | 36 - sim/testsuite/sim/fr30/beq.cgs | 109 - sim/testsuite/sim/fr30/bge.cgs | 109 - sim/testsuite/sim/fr30/bgt.cgs | 109 - sim/testsuite/sim/fr30/bhi.cgs | 109 - sim/testsuite/sim/fr30/ble.cgs | 109 - sim/testsuite/sim/fr30/bls.cgs | 109 - sim/testsuite/sim/fr30/blt.cgs | 109 - sim/testsuite/sim/fr30/bn.cgs | 109 - sim/testsuite/sim/fr30/bnc.cgs | 109 - sim/testsuite/sim/fr30/bne.cgs | 109 - sim/testsuite/sim/fr30/bno.cgs | 109 - sim/testsuite/sim/fr30/bnv.cgs | 109 - sim/testsuite/sim/fr30/borh.cgs | 30 - sim/testsuite/sim/fr30/borl.cgs | 30 - sim/testsuite/sim/fr30/bp.cgs | 109 - sim/testsuite/sim/fr30/bra.cgs | 109 - sim/testsuite/sim/fr30/btsth.cgs | 30 - sim/testsuite/sim/fr30/btstl.cgs | 30 - sim/testsuite/sim/fr30/bv.cgs | 109 - sim/testsuite/sim/fr30/call.cgs | 69 - sim/testsuite/sim/fr30/cmp.cgs | 53 - sim/testsuite/sim/fr30/cmp2.cgs | 27 - sim/testsuite/sim/fr30/copld.cgs | 21 - sim/testsuite/sim/fr30/copop.cgs | 21 - sim/testsuite/sim/fr30/copst.cgs | 21 - sim/testsuite/sim/fr30/copsv.cgs | 21 - sim/testsuite/sim/fr30/div.ms | 176 - sim/testsuite/sim/fr30/div0s.cgs | 64 - sim/testsuite/sim/fr30/div0u.cgs | 25 - sim/testsuite/sim/fr30/div1.cgs | 113 - sim/testsuite/sim/fr30/div2.cgs | 120 - sim/testsuite/sim/fr30/div3.cgs | 34 - sim/testsuite/sim/fr30/div4s.cgs | 34 - sim/testsuite/sim/fr30/dmov.cgs | 73 - sim/testsuite/sim/fr30/dmovb.cgs | 46 - sim/testsuite/sim/fr30/dmovh.cgs | 46 - sim/testsuite/sim/fr30/enter.cgs | 34 - sim/testsuite/sim/fr30/eor.cgs | 69 - sim/testsuite/sim/fr30/eorb.cgs | 40 - sim/testsuite/sim/fr30/eorh.cgs | 40 - sim/testsuite/sim/fr30/extsb.cgs | 36 - sim/testsuite/sim/fr30/extsh.cgs | 48 - sim/testsuite/sim/fr30/extub.cgs | 42 - sim/testsuite/sim/fr30/extuh.cgs | 54 - sim/testsuite/sim/fr30/hello.ms | 19 - sim/testsuite/sim/fr30/int.cgs | 35 - sim/testsuite/sim/fr30/inte.cgs | 36 - sim/testsuite/sim/fr30/jmp.cgs | 29 - sim/testsuite/sim/fr30/ld.cgs | 219 - sim/testsuite/sim/fr30/ldi20.cgs | 37 - sim/testsuite/sim/fr30/ldi32.cgs | 37 - sim/testsuite/sim/fr30/ldi8.cgs | 37 - sim/testsuite/sim/fr30/ldm0.cgs | 60 - sim/testsuite/sim/fr30/ldm1.cgs | 59 - sim/testsuite/sim/fr30/ldres.cgs | 25 - sim/testsuite/sim/fr30/ldub.cgs | 115 - sim/testsuite/sim/fr30/lduh.cgs | 115 - sim/testsuite/sim/fr30/leave.cgs | 23 - sim/testsuite/sim/fr30/lsl.cgs | 65 - sim/testsuite/sim/fr30/lsl2.cgs | 36 - sim/testsuite/sim/fr30/lsr.cgs | 65 - sim/testsuite/sim/fr30/lsr2.cgs | 36 - sim/testsuite/sim/fr30/misc.exp | 20 - sim/testsuite/sim/fr30/mov.cgs | 108 - sim/testsuite/sim/fr30/mul.cgs | 240 - sim/testsuite/sim/fr30/mulh.cgs | 211 - sim/testsuite/sim/fr30/mulu.cgs | 101 - sim/testsuite/sim/fr30/muluh.cgs | 90 - sim/testsuite/sim/fr30/nop.cgs | 16 - sim/testsuite/sim/fr30/or.cgs | 55 - sim/testsuite/sim/fr30/orb.cgs | 33 - sim/testsuite/sim/fr30/orccr.cgs | 38 - sim/testsuite/sim/fr30/orh.cgs | 33 - sim/testsuite/sim/fr30/ret.cgs | 75 - sim/testsuite/sim/fr30/reti.cgs | 57 - sim/testsuite/sim/fr30/st.cgs | 194 - sim/testsuite/sim/fr30/stb.cgs | 84 - sim/testsuite/sim/fr30/sth.cgs | 84 - sim/testsuite/sim/fr30/stilm.cgs | 41 - sim/testsuite/sim/fr30/stm0.cgs | 101 - sim/testsuite/sim/fr30/stm1.cgs | 97 - sim/testsuite/sim/fr30/stres.cgs | 25 - sim/testsuite/sim/fr30/sub.cgs | 36 - sim/testsuite/sim/fr30/subc.cgs | 62 - sim/testsuite/sim/fr30/subn.cgs | 36 - sim/testsuite/sim/fr30/testutils.inc | 306 - sim/testsuite/sim/fr30/xchb.cgs | 20 - sim/testsuite/sim/frv/ChangeLog | 76 - sim/testsuite/sim/h8300/ChangeLog | 97 - sim/testsuite/sim/h8300/allinsn.exp | 65 - sim/testsuite/sim/h8300/rotl.s | 1212 -- sim/testsuite/sim/h8300/rotr.s | 1802 --- sim/testsuite/sim/h8300/rotxl.s | 167 - sim/testsuite/sim/h8300/rotxr.s | 2002 --- sim/testsuite/sim/h8300/shal.s | 167 - sim/testsuite/sim/h8300/shar.s | 2000 --- sim/testsuite/sim/h8300/shll.s | 375 - sim/testsuite/sim/h8300/shlr.s | 4085 ----- sim/testsuite/sim/h8300/tas.s | 80 - sim/testsuite/sim/m32r/ChangeLog | 122 - sim/testsuite/sim/sh64/ChangeLog | 21 - sim/testsuite/sim/sh64/compact.exp | 19 - sim/testsuite/sim/sh64/compact/ChangeLog | 26 - sim/testsuite/sim/sh64/compact/add.cgs | 55 - sim/testsuite/sim/sh64/compact/addc.cgs | 90 - sim/testsuite/sim/sh64/compact/addi.cgs | 46 - sim/testsuite/sim/sh64/compact/addv.cgs | 48 - sim/testsuite/sim/sh64/compact/and.cgs | 33 - sim/testsuite/sim/sh64/compact/andb.cgs | 24 - sim/testsuite/sim/sh64/compact/andi.cgs | 43 - sim/testsuite/sim/sh64/compact/bf.cgs | 24 - sim/testsuite/sim/sh64/compact/bfs.cgs | 28 - sim/testsuite/sim/sh64/compact/bra.cgs | 23 - sim/testsuite/sim/sh64/compact/braf.cgs | 24 - sim/testsuite/sim/sh64/compact/brk.cgs | 18 - sim/testsuite/sim/sh64/compact/bsr.cgs | 21 - sim/testsuite/sim/sh64/compact/bsrf.cgs | 22 - sim/testsuite/sim/sh64/compact/bt.cgs | 24 - sim/testsuite/sim/sh64/compact/bts.cgs | 28 - sim/testsuite/sim/sh64/compact/clrmac.cgs | 13 - sim/testsuite/sim/sh64/compact/clrs.cgs | 14 - sim/testsuite/sim/sh64/compact/clrt.cgs | 16 - sim/testsuite/sim/sh64/compact/cmpeq.cgs | 52 - sim/testsuite/sim/sh64/compact/cmpeqi.cgs | 39 - sim/testsuite/sim/sh64/compact/cmpge.cgs | 69 - sim/testsuite/sim/sh64/compact/cmpgt.cgs | 69 - sim/testsuite/sim/sh64/compact/cmphi.cgs | 68 - sim/testsuite/sim/sh64/compact/cmphs.cgs | 59 - sim/testsuite/sim/sh64/compact/cmppl.cgs | 37 - sim/testsuite/sim/sh64/compact/cmppz.cgs | 37 - sim/testsuite/sim/sh64/compact/cmpstr.cgs | 148 - sim/testsuite/sim/sh64/compact/div0s.cgs | 52 - sim/testsuite/sim/sh64/compact/div0u.cgs | 21 - sim/testsuite/sim/sh64/compact/div1.cgs | 52 - sim/testsuite/sim/sh64/compact/dmulsl.cgs | 115 - sim/testsuite/sim/sh64/compact/dmulul.cgs | 53 - sim/testsuite/sim/sh64/compact/dt.cgs | 42 - sim/testsuite/sim/sh64/compact/extsb.cgs | 29 - sim/testsuite/sim/sh64/compact/extsw.cgs | 32 - sim/testsuite/sim/sh64/compact/extub.cgs | 31 - sim/testsuite/sim/sh64/compact/extuw.cgs | 31 - sim/testsuite/sim/sh64/compact/fabs.cgs | 88 - sim/testsuite/sim/sh64/compact/fadd.cgs | 31 - sim/testsuite/sim/sh64/compact/fcmpeq.cgs | 88 - sim/testsuite/sim/sh64/compact/fcmpgt.cgs | 95 - sim/testsuite/sim/sh64/compact/fcnvds.cgs | 13 - sim/testsuite/sim/sh64/compact/fcnvsd.cgs | 27 - sim/testsuite/sim/sh64/compact/fdiv.cgs | 83 - sim/testsuite/sim/sh64/compact/fipr.cgs | 44 - sim/testsuite/sim/sh64/compact/fldi0.cgs | 17 - sim/testsuite/sim/sh64/compact/fldi1.cgs | 17 - sim/testsuite/sim/sh64/compact/flds.cgs | 26 - sim/testsuite/sim/sh64/compact/float.cgs | 80 - sim/testsuite/sim/sh64/compact/fmac.cgs | 78 - sim/testsuite/sim/sh64/compact/fmov.cgs | 273 - sim/testsuite/sim/sh64/compact/fmul.cgs | 121 - sim/testsuite/sim/sh64/compact/fneg.cgs | 83 - sim/testsuite/sim/sh64/compact/frchg.cgs | 13 - sim/testsuite/sim/sh64/compact/fschg.cgs | 13 - sim/testsuite/sim/sh64/compact/fsqrt.cgs | 93 - sim/testsuite/sim/sh64/compact/fsts.cgs | 11 - sim/testsuite/sim/sh64/compact/fsub.cgs | 120 - sim/testsuite/sim/sh64/compact/ftrc.cgs | 132 - sim/testsuite/sim/sh64/compact/ftrv.cgs | 74 - sim/testsuite/sim/sh64/compact/jmp.cgs | 29 - sim/testsuite/sim/sh64/compact/jsr.cgs | 29 - sim/testsuite/sim/sh64/compact/ldc-gbr.cgs | 22 - sim/testsuite/sim/sh64/compact/ldcl-gbr.cgs | 28 - sim/testsuite/sim/sh64/compact/lds-fpscr.cgs | 22 - sim/testsuite/sim/sh64/compact/lds-fpul.cgs | 17 - sim/testsuite/sim/sh64/compact/lds-mach.cgs | 23 - sim/testsuite/sim/sh64/compact/lds-macl.cgs | 23 - sim/testsuite/sim/sh64/compact/lds-pr.cgs | 23 - sim/testsuite/sim/sh64/compact/ldsl-fpscr.cgs | 43 - sim/testsuite/sim/sh64/compact/ldsl-fpul.cgs | 27 - sim/testsuite/sim/sh64/compact/ldsl-mach.cgs | 26 - sim/testsuite/sim/sh64/compact/ldsl-macl.cgs | 26 - sim/testsuite/sim/sh64/compact/ldsl-pr.cgs | 28 - sim/testsuite/sim/sh64/compact/macl.cgs | 76 - sim/testsuite/sim/sh64/compact/macw.cgs | 70 - sim/testsuite/sim/sh64/compact/mov.cgs | 40 - sim/testsuite/sim/sh64/compact/mova.cgs | 29 - sim/testsuite/sim/sh64/compact/movb1.cgs | 27 - sim/testsuite/sim/sh64/compact/movb10.cgs | 25 - sim/testsuite/sim/sh64/compact/movb2.cgs | 34 - sim/testsuite/sim/sh64/compact/movb3.cgs | 30 - sim/testsuite/sim/sh64/compact/movb4.cgs | 28 - sim/testsuite/sim/sh64/compact/movb5.cgs | 25 - sim/testsuite/sim/sh64/compact/movb6.cgs | 26 - sim/testsuite/sim/sh64/compact/movb7.cgs | 35 - sim/testsuite/sim/sh64/compact/movb8.cgs | 27 - sim/testsuite/sim/sh64/compact/movb9.cgs | 27 - sim/testsuite/sim/sh64/compact/movcal.cgs | 28 - sim/testsuite/sim/sh64/compact/movi.cgs | 39 - sim/testsuite/sim/sh64/compact/movl1.cgs | 31 - sim/testsuite/sim/sh64/compact/movl10.cgs | 34 - sim/testsuite/sim/sh64/compact/movl11.cgs | 32 - sim/testsuite/sim/sh64/compact/movl2.cgs | 43 - sim/testsuite/sim/sh64/compact/movl3.cgs | 36 - sim/testsuite/sim/sh64/compact/movl4.cgs | 38 - sim/testsuite/sim/sh64/compact/movl5.cgs | 37 - sim/testsuite/sim/sh64/compact/movl6.cgs | 25 - sim/testsuite/sim/sh64/compact/movl7.cgs | 37 - sim/testsuite/sim/sh64/compact/movl8.cgs | 24 - sim/testsuite/sim/sh64/compact/movl9.cgs | 24 - sim/testsuite/sim/sh64/compact/movt.cgs | 28 - sim/testsuite/sim/sh64/compact/movw1.cgs | 29 - sim/testsuite/sim/sh64/compact/movw10.cgs | 32 - sim/testsuite/sim/sh64/compact/movw11.cgs | 35 - sim/testsuite/sim/sh64/compact/movw2.cgs | 36 - sim/testsuite/sim/sh64/compact/movw3.cgs | 31 - sim/testsuite/sim/sh64/compact/movw4.cgs | 31 - sim/testsuite/sim/sh64/compact/movw5.cgs | 32 - sim/testsuite/sim/sh64/compact/movw6.cgs | 30 - sim/testsuite/sim/sh64/compact/movw7.cgs | 36 - sim/testsuite/sim/sh64/compact/movw8.cgs | 31 - sim/testsuite/sim/sh64/compact/movw9.cgs | 33 - sim/testsuite/sim/sh64/compact/mull.cgs | 64 - sim/testsuite/sim/sh64/compact/mulsw.cgs | 91 - sim/testsuite/sim/sh64/compact/muluw.cgs | 96 - sim/testsuite/sim/sh64/compact/neg.cgs | 55 - sim/testsuite/sim/sh64/compact/negc.cgs | 66 - sim/testsuite/sim/sh64/compact/nop.cgs | 13 - sim/testsuite/sim/sh64/compact/not.cgs | 47 - sim/testsuite/sim/sh64/compact/ocbi.cgs | 14 - sim/testsuite/sim/sh64/compact/ocbp.cgs | 15 - sim/testsuite/sim/sh64/compact/ocbwb.cgs | 15 - sim/testsuite/sim/sh64/compact/or.cgs | 43 - sim/testsuite/sim/sh64/compact/orb.cgs | 24 - sim/testsuite/sim/sh64/compact/ori.cgs | 40 - sim/testsuite/sim/sh64/compact/pref.cgs | 15 - sim/testsuite/sim/sh64/compact/rotcl.cgs | 121 - sim/testsuite/sim/sh64/compact/rotcr.cgs | 103 - sim/testsuite/sim/sh64/compact/rotl.cgs | 62 - sim/testsuite/sim/sh64/compact/rotr.cgs | 55 - sim/testsuite/sim/sh64/compact/rts.cgs | 24 - sim/testsuite/sim/sh64/compact/sets.cgs | 13 - sim/testsuite/sim/sh64/compact/sett.cgs | 16 - sim/testsuite/sim/sh64/compact/shad.cgs | 58 - sim/testsuite/sim/sh64/compact/shal.cgs | 57 - sim/testsuite/sim/sh64/compact/shar.cgs | 40 - sim/testsuite/sim/sh64/compact/shld.cgs | 48 - sim/testsuite/sim/sh64/compact/shll.cgs | 57 - sim/testsuite/sim/sh64/compact/shll16.cgs | 44 - sim/testsuite/sim/sh64/compact/shll2.cgs | 40 - sim/testsuite/sim/sh64/compact/shll8.cgs | 38 - sim/testsuite/sim/sh64/compact/shlr.cgs | 33 - sim/testsuite/sim/sh64/compact/shlr16.cgs | 14 - sim/testsuite/sim/sh64/compact/shlr2.cgs | 14 - sim/testsuite/sim/sh64/compact/shlr8.cgs | 14 - sim/testsuite/sim/sh64/compact/stc-gbr.cgs | 21 - sim/testsuite/sim/sh64/compact/stcl-gbr.cgs | 27 - sim/testsuite/sim/sh64/compact/sts-fpscr.cgs | 23 - sim/testsuite/sim/sh64/compact/sts-fpul.cgs | 14 - sim/testsuite/sim/sh64/compact/sts-mach.cgs | 22 - sim/testsuite/sim/sh64/compact/sts-macl.cgs | 21 - sim/testsuite/sim/sh64/compact/sts-pr.cgs | 22 - sim/testsuite/sim/sh64/compact/stsl-fpscr.cgs | 28 - sim/testsuite/sim/sh64/compact/stsl-fpul.cgs | 27 - sim/testsuite/sim/sh64/compact/stsl-mach.cgs | 42 - sim/testsuite/sim/sh64/compact/stsl-macl.cgs | 42 - sim/testsuite/sim/sh64/compact/stsl-pr.cgs | 42 - sim/testsuite/sim/sh64/compact/sub.cgs | 68 - sim/testsuite/sim/sh64/compact/subc.cgs | 109 - sim/testsuite/sim/sh64/compact/subv.cgs | 55 - sim/testsuite/sim/sh64/compact/swapb.cgs | 44 - sim/testsuite/sim/sh64/compact/swapw.cgs | 43 - sim/testsuite/sim/sh64/compact/tasb.cgs | 26 - sim/testsuite/sim/sh64/compact/testutils.inc | 49 - sim/testsuite/sim/sh64/compact/trapa.cgs | 13 - sim/testsuite/sim/sh64/compact/tst.cgs | 62 - sim/testsuite/sim/sh64/compact/tstb.cgs | 30 - sim/testsuite/sim/sh64/compact/tsti.cgs | 32 - sim/testsuite/sim/sh64/compact/xor.cgs | 70 - sim/testsuite/sim/sh64/compact/xorb.cgs | 24 - sim/testsuite/sim/sh64/compact/xori.cgs | 50 - sim/testsuite/sim/sh64/compact/xtrct.cgs | 46 - sim/testsuite/sim/sh64/interwork.exp | 20 - sim/testsuite/sim/sh64/media.exp | 19 - sim/testsuite/sim/sh64/media/ChangeLog | 102 - sim/testsuite/sim/sh64/media/add.cgs | 47 - sim/testsuite/sim/sh64/media/addi.cgs | 37 - sim/testsuite/sim/sh64/media/addil.cgs | 49 - sim/testsuite/sim/sh64/media/addl.cgs | 61 - sim/testsuite/sim/sh64/media/addzl.cgs | 39 - sim/testsuite/sim/sh64/media/alloco.cgs | 10 - sim/testsuite/sim/sh64/media/and.cgs | 68 - sim/testsuite/sim/sh64/media/andc.cgs | 50 - sim/testsuite/sim/sh64/media/andi.cgs | 46 - sim/testsuite/sim/sh64/media/beq.cgs | 52 - sim/testsuite/sim/sh64/media/beqi.cgs | 40 - sim/testsuite/sim/sh64/media/bge.cgs | 40 - sim/testsuite/sim/sh64/media/bgeu.cgs | 47 - sim/testsuite/sim/sh64/media/bgt.cgs | 32 - sim/testsuite/sim/sh64/media/bgtu.cgs | 36 - sim/testsuite/sim/sh64/media/blink.cgs | 17 - sim/testsuite/sim/sh64/media/bne.cgs | 23 - sim/testsuite/sim/sh64/media/bnei.cgs | 23 - sim/testsuite/sim/sh64/media/brk.cgs | 11 - sim/testsuite/sim/sh64/media/byterev.cgs | 67 - sim/testsuite/sim/sh64/media/cmpeq.cgs | 42 - sim/testsuite/sim/sh64/media/cmpgt.cgs | 43 - sim/testsuite/sim/sh64/media/cmpgtu.cgs | 43 - sim/testsuite/sim/sh64/media/cmveq.cgs | 32 - sim/testsuite/sim/sh64/media/cmvne.cgs | 32 - sim/testsuite/sim/sh64/media/fabsd.cgs | 39 - sim/testsuite/sim/sh64/media/fabss.cgs | 39 - sim/testsuite/sim/sh64/media/faddd.cgs | 33 - sim/testsuite/sim/sh64/media/fadds.cgs | 34 - sim/testsuite/sim/sh64/media/fcmpeqd.cgs | 36 - sim/testsuite/sim/sh64/media/fcmpeqs.cgs | 36 - sim/testsuite/sim/sh64/media/fcmpged.cgs | 46 - sim/testsuite/sim/sh64/media/fcmpges.cgs | 46 - sim/testsuite/sim/sh64/media/fcmpgtd.cgs | 36 - sim/testsuite/sim/sh64/media/fcmpgts.cgs | 36 - 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rename sim/testsuite/{sim => }/bfin/c_dsp32alu_aa_absabs.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_aa_negneg.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_abs.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_absabs.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_alhwx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_awx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop1ew.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop2.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop3.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_bytepack.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteunpack.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_disalnexcpt.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_max.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_maxmax.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_min.s (100%) rename sim/testsuite/{sim => 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(100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rlh_rnd.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rmm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rmp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rpm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rpp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rr_lph_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm_aa.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp_sft_x.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm_sft_x.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_saa.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_sat_aa.S (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_search.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_sgn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_iuw32.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_ih.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_iu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_tu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_ih.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_iu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_tu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0_iutsh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_ih.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_iu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_iutsh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_tu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_a0alr.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_af.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_af_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align16.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align24.s (100%) rename sim/testsuite/{sim => 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rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lmix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_rot.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ippm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ippm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_except_illopcode.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_sys_sstep.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_user_mode.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable_enable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_excpt.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_loopsetup_stld.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nested.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nmi.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending_2.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_reload.S (100%) rename sim/testsuite/{sim => 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=> }/frv/cmcpxrs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/cmexpdhd.cgs (100%) rename sim/testsuite/{sim => }/frv/cmexpdhw.cgs (100%) rename sim/testsuite/{sim => }/frv/cmhtob.cgs (100%) rename sim/testsuite/{sim => }/frv/cmmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmnot.cgs (100%) rename sim/testsuite/{sim => }/frv/cmor.cgs (100%) rename sim/testsuite/{sim => }/frv/cmov.cgs (100%) rename sim/testsuite/{sim => }/frv/cmovfg.cgs (100%) rename sim/testsuite/{sim => }/frv/cmovfgd.cgs (100%) rename sim/testsuite/{sim => }/frv/cmovgf.cgs (100%) rename sim/testsuite/{sim => }/frv/cmovgfd.cgs (100%) rename sim/testsuite/{sim => }/frv/cmp.cgs (100%) rename sim/testsuite/{sim => }/frv/cmpb.cgs (100%) rename sim/testsuite/{sim => }/frv/cmpba.cgs (100%) rename sim/testsuite/{sim => }/frv/cmpi.cgs (100%) rename sim/testsuite/{sim => }/frv/cmqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmqmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmqmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/cmsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/cmxor.cgs (100%) rename sim/testsuite/{sim => }/frv/cnot.cgs (100%) rename sim/testsuite/{sim => }/frv/commitfa.cgs (100%) rename sim/testsuite/{sim => }/frv/commitfr.cgs (100%) rename sim/testsuite/{sim => }/frv/commitga.cgs (100%) rename sim/testsuite/{sim => }/frv/commitgr.cgs (100%) rename sim/testsuite/{sim => }/frv/cop1.cgs (100%) rename sim/testsuite/{sim => }/frv/cop2.cgs (100%) rename sim/testsuite/{sim => }/frv/cor.cgs (100%) rename sim/testsuite/{sim => }/frv/corcc.cgs (100%) rename sim/testsuite/{sim => }/frv/cscan.cgs (100%) rename sim/testsuite/{sim => }/frv/csdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/csll.cgs (100%) rename sim/testsuite/{sim => }/frv/csllcc.cgs (100%) rename sim/testsuite/{sim => }/frv/csmul.cgs (100%) rename sim/testsuite/{sim => }/frv/csmulcc.cgs (100%) rename sim/testsuite/{sim => }/frv/csra.cgs (100%) rename sim/testsuite/{sim => }/frv/csracc.cgs (100%) rename sim/testsuite/{sim => }/frv/csrl.cgs (100%) rename sim/testsuite/{sim => }/frv/csrlcc.cgs (100%) rename sim/testsuite/{sim => }/frv/cst.cgs (100%) rename sim/testsuite/{sim => }/frv/cstb.cgs (100%) rename sim/testsuite/{sim => }/frv/cstbf.cgs (100%) rename sim/testsuite/{sim => }/frv/cstbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstbu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstd.cgs (100%) rename sim/testsuite/{sim => }/frv/cstdf.cgs (100%) rename sim/testsuite/{sim => }/frv/cstdfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstdu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstf.cgs (100%) rename sim/testsuite/{sim => }/frv/cstfu.cgs (100%) rename sim/testsuite/{sim => }/frv/csth.cgs (100%) rename sim/testsuite/{sim => }/frv/csthf.cgs (100%) rename sim/testsuite/{sim => }/frv/csthfu.cgs (100%) rename sim/testsuite/{sim => }/frv/csthu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstq.cgs (100%) rename sim/testsuite/{sim => }/frv/cstu.cgs (100%) rename sim/testsuite/{sim => }/frv/csub.cgs (100%) rename sim/testsuite/{sim => }/frv/csubcc.cgs (100%) rename sim/testsuite/{sim => }/frv/cswap.cgs (100%) rename sim/testsuite/{sim => }/frv/cudiv.cgs (100%) rename sim/testsuite/{sim => }/frv/cxor.cgs (100%) rename sim/testsuite/{sim => }/frv/cxorcc.cgs (100%) rename sim/testsuite/{sim => }/frv/dcef.cgs (100%) rename sim/testsuite/{sim => }/frv/dcei.cgs (100%) rename sim/testsuite/{sim => }/frv/dcf.cgs (100%) rename sim/testsuite/{sim => }/frv/dci.cgs (100%) create mode 100644 sim/testsuite/frv/exit47.ms rename sim/testsuite/{sim => }/frv/fabsd.cgs (100%) rename sim/testsuite/{sim => }/frv/fabss.cgs (100%) rename sim/testsuite/{sim => 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sim/testsuite/{sim => }/frv/fckno.cgs (100%) rename sim/testsuite/{sim => }/frv/fcko.cgs (100%) rename sim/testsuite/{sim => }/frv/fckra.cgs (100%) rename sim/testsuite/{sim => }/frv/fcku.cgs (100%) rename sim/testsuite/{sim => }/frv/fckue.cgs (100%) rename sim/testsuite/{sim => }/frv/fckug.cgs (100%) rename sim/testsuite/{sim => }/frv/fckuge.cgs (100%) rename sim/testsuite/{sim => }/frv/fckul.cgs (100%) rename sim/testsuite/{sim => }/frv/fckule.cgs (100%) rename sim/testsuite/{sim => }/frv/fcmpd.cgs (100%) rename sim/testsuite/{sim => }/frv/fcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/fdabss.cgs (100%) rename sim/testsuite/{sim => }/frv/fdadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fdcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/fddivs.cgs (100%) rename sim/testsuite/{sim => }/frv/fditos.cgs (100%) rename sim/testsuite/{sim => }/frv/fdivd.cgs (100%) rename sim/testsuite/{sim => }/frv/fdivs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmas.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmovs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmss.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmulcs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/fdnegs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdsads.cgs (100%) rename sim/testsuite/{sim => }/frv/fdsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/fdstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/fdsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdtoi.cgs (100%) rename sim/testsuite/{sim => }/frv/fitod.cgs (100%) rename sim/testsuite/{sim => }/frv/fitos.cgs (100%) rename sim/testsuite/{sim => }/frv/fmad.cgs (100%) rename sim/testsuite/{sim => }/frv/fmaddd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fmas.cgs (100%) rename sim/testsuite/{sim => }/frv/fmovd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmovs.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmss.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsubd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fmuld.cgs (100%) rename sim/testsuite/{sim => }/frv/fmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/fnegd.cgs (100%) rename sim/testsuite/{sim => }/frv/fnegs.cgs (100%) rename sim/testsuite/{sim => }/frv/fnop.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/addss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr400/csdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/maddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/masaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/maveh.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhdseth.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhdsets.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsethih.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsethis.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsetloh.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsetlos.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/movgs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/movsg.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/msubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/scutss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/sdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/sdivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/slass.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smass.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smsss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/subss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/udiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/udivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/dcpl.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/dcul.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr550/cmaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmcpxiu.cgs (100%) rename sim/testsuite/{sim => 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rename sim/testsuite/{sim => }/frv/fr550/masaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdaddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdasaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdsubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmrdhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmrdhu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqxmachs.cgs (100%) rename sim/testsuite/{sim => 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rename sim/testsuite/{sim => }/frv/ftue.cgs (100%) rename sim/testsuite/{sim => }/frv/ftug.cgs (100%) rename sim/testsuite/{sim => }/frv/ftuge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftul.cgs (100%) rename sim/testsuite/{sim => }/frv/ftule.cgs (100%) create mode 100644 sim/testsuite/frv/grloop.ms create mode 100644 sim/testsuite/frv/hello.ms rename sim/testsuite/{sim => }/frv/icei.cgs (100%) rename sim/testsuite/{sim => }/frv/ici.cgs (100%) rename sim/testsuite/{sim => }/frv/icpl.cgs (100%) rename sim/testsuite/{sim => }/frv/icul.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts.exp (100%) rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr400.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr500.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/badalign-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/badalign.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/compound-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/compound.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/data_store_error-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/data_store_error.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/fp_exception-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/fp_exception.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/illinsn.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/mp_exception.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/privileged_instruction.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/regalign.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/reset.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/shadow_regs.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/timer.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpil.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.pcgs (100%) rename sim/testsuite/{sim => }/frv/ld.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldc.cgs (100%) rename sim/testsuite/{sim => }/frv/ldcu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldd.cgs (100%) rename sim/testsuite/{sim => }/frv/lddc.cgs (100%) rename sim/testsuite/{sim => }/frv/lddcu.cgs (100%) rename sim/testsuite/{sim => }/frv/lddf.cgs (100%) rename sim/testsuite/{sim => }/frv/lddfi.cgs (100%) rename sim/testsuite/{sim => }/frv/lddfu.cgs (100%) rename sim/testsuite/{sim => }/frv/lddi.cgs (100%) rename sim/testsuite/{sim => }/frv/lddu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldfu.cgs (100%) rename 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}/frv/ldub.cgs (100%) rename sim/testsuite/{sim => }/frv/ldubi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldubu.cgs (100%) rename sim/testsuite/{sim => }/frv/lduh.cgs (100%) rename sim/testsuite/{sim => }/frv/lduhi.cgs (100%) rename sim/testsuite/{sim => }/frv/lduhu.cgs (100%) rename sim/testsuite/{sim => }/frv/lrbranch.pcgs (100%) rename sim/testsuite/{sim => }/frv/mabshs.cgs (100%) rename sim/testsuite/{sim => }/frv/maddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/maddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/mand.cgs (100%) rename sim/testsuite/{sim => }/frv/maveh.cgs (100%) rename sim/testsuite/{sim => }/frv/mbtoh.cgs (100%) rename sim/testsuite/{sim => }/frv/mbtohe.cgs (100%) rename sim/testsuite/{sim => }/frv/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/mcmpsh.cgs (100%) rename sim/testsuite/{sim => }/frv/mcmpuh.cgs (100%) rename sim/testsuite/{sim => }/frv/mcop1.cgs (100%) rename sim/testsuite/{sim => }/frv/mcop2.cgs (100%) rename sim/testsuite/{sim => }/frv/mcplhi.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpli.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxis.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxrs.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/mcut.cgs (100%) rename sim/testsuite/{sim => }/frv/mcuti.cgs (100%) rename sim/testsuite/{sim => }/frv/mcutss.cgs (100%) rename sim/testsuite/{sim => }/frv/mcutssi.cgs (100%) rename sim/testsuite/{sim => }/frv/mdaddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdasaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdcutssi.cgs (100%) rename sim/testsuite/{sim => }/frv/mdpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mdrotli.cgs (100%) rename sim/testsuite/{sim => }/frv/mdsubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdunpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/membar.cgs (100%) rename sim/testsuite/{sim => }/frv/mexpdhd.cgs (100%) rename sim/testsuite/{sim => }/frv/mexpdhw.cgs (100%) rename sim/testsuite/{sim => }/frv/mhdseth.cgs (100%) rename sim/testsuite/{sim => }/frv/mhdsets.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsethih.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsethis.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsetloh.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsetlos.cgs (100%) rename sim/testsuite/{sim => }/frv/mhtob.cgs (100%) create mode 100644 sim/testsuite/frv/misc.exp rename sim/testsuite/{sim => }/frv/mmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmrdhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmrdhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulxhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mnop.cgs (100%) rename sim/testsuite/{sim => }/frv/mnot.cgs (100%) rename sim/testsuite/{sim => }/frv/mor.cgs (100%) rename sim/testsuite/{sim => }/frv/mov.cgs (100%) rename sim/testsuite/{sim => }/frv/movfg.cgs (100%) rename sim/testsuite/{sim => }/frv/movfgd.cgs (100%) rename sim/testsuite/{sim => }/frv/movfgq.cgs (100%) rename sim/testsuite/{sim => }/frv/movgf.cgs (100%) rename sim/testsuite/{sim => }/frv/movgfd.cgs (100%) rename sim/testsuite/{sim => }/frv/movgfq.cgs (100%) rename sim/testsuite/{sim => }/frv/movgs.cgs (100%) rename sim/testsuite/{sim => }/frv/movsg.cgs (100%) rename sim/testsuite/{sim => }/frv/mpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxis.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxrs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/mqlclrhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqlmths.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmachu.cgs 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sim/testsuite/{sim => }/frv/msrlhi.cgs (100%) rename sim/testsuite/{sim => }/frv/msubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/msubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/mtrap.cgs (100%) rename sim/testsuite/{sim => }/frv/munpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mwcut.cgs (100%) rename sim/testsuite/{sim => }/frv/mwcuti.cgs (100%) rename sim/testsuite/{sim => }/frv/mwtacc.cgs (100%) rename sim/testsuite/{sim => }/frv/mwtaccg.cgs (100%) rename sim/testsuite/{sim => }/frv/mxor.cgs (100%) rename sim/testsuite/{sim => }/frv/nandcr.cgs (100%) rename sim/testsuite/{sim => }/frv/nandncr.cgs (100%) rename sim/testsuite/{sim => }/frv/nfadds.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdadds.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/nfddivs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfditos.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdivs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmadds.cgs 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}/frv/nldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldbfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldd.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddf.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddi.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldhf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldhfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldhfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldq.cgs (100%) rename sim/testsuite/{sim => }/frv/nldqf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldqfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldqfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldqu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldsb.cgs (100%) rename sim/testsuite/{sim => }/frv/nldsbi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldsbu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldsh.cgs (100%) rename sim/testsuite/{sim => }/frv/nldshi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldshu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldub.cgs (100%) rename sim/testsuite/{sim => }/frv/nldubi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldubu.cgs (100%) rename sim/testsuite/{sim => }/frv/nlduh.cgs (100%) rename sim/testsuite/{sim => }/frv/nlduhi.cgs (100%) rename sim/testsuite/{sim => }/frv/nlduhu.cgs (100%) rename sim/testsuite/{sim => }/frv/nop.cgs (100%) rename sim/testsuite/{sim => }/frv/norcr.cgs (100%) rename sim/testsuite/{sim => }/frv/norncr.cgs (100%) rename sim/testsuite/{sim => }/frv/not.cgs (100%) rename sim/testsuite/{sim => }/frv/notcr.cgs (100%) rename sim/testsuite/{sim => }/frv/nsdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/nsdivi.cgs (100%) rename sim/testsuite/{sim => }/frv/nudiv.cgs (100%) rename sim/testsuite/{sim => }/frv/nudivi.cgs (100%) rename sim/testsuite/{sim => }/frv/or.cgs (100%) rename sim/testsuite/{sim => }/frv/orcc.cgs (100%) rename sim/testsuite/{sim => }/frv/orcr.cgs (100%) rename sim/testsuite/{sim => }/frv/ori.cgs (100%) rename sim/testsuite/{sim => }/frv/oricc.cgs (100%) rename sim/testsuite/{sim => }/frv/orncr.cgs (100%) rename sim/testsuite/{sim => }/frv/parallel.exp (100%) rename sim/testsuite/{sim => }/frv/ret.cgs (100%) rename sim/testsuite/{sim => }/frv/rett.cgs (100%) rename sim/testsuite/{sim => }/frv/scan.cgs (100%) rename sim/testsuite/{sim => }/frv/scani.cgs (100%) rename sim/testsuite/{sim => }/frv/sdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/sdivi.cgs (100%) rename sim/testsuite/{sim => }/frv/sethi.cgs (100%) rename sim/testsuite/{sim => }/frv/sethilo.pcgs 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3 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk_tk1/llvm-master-arm-spec2k6-Os_LTO updated (dbead9d5 -> 339be002)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/llvm-master-arm-spec2k6-Os_LTO in repository toolchain/ci/base-artifacts. discards dbead9d5 10: update: glibc-1c426b1d59cc7a5f9133f4799f2640234a3077e3: 1 new 339be002 10: update: binutils-gcc-glibc-llvm: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (dbead9d5) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_bmk_tk1/llvm-master-arm- [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 183 +- 02-prepare_abe/console.log | 440 +- 03-build_abe-binutils/console.log | 11481 +- 04-build_abe-stage1/console.log | 20661 ++-- 05-build_abe-linux/console.log | 2000 +- 06-build_abe-glibc/console.log | 40188 +++---- 07-build_abe-stage2/console.log | 40665 +++---- 08-build_llvm-true/console.log | 13692 +-- 10-benchmark--Os_LTO_mthumb/benchmark-start.log | 2 +- 10-benchmark--Os_LTO_mthumb/benchmark.log | 14 +- 10-benchmark--Os_LTO_mthumb/console.log | 299 +- 11-check_regression/console.log | 760 +- 11-check_regression/results-0.csv | 126 +- 11-check_regression/results-1.csv | 123 +- 11-check_regression/results-brief.csv | 38 +- 11-check_regression/results-full.csv | 131 +- 11-check_regression/results.csv | 46 +- 11-check_regression/results.log | 2812 +- 12-update_baseline/console.log | 922 +- 12-update_baseline/results-1.csv | 123 +- 12-update_baseline/results-brief.csv | 36 +- 12-update_baseline/results-full.csv | 123 +- 12-update_baseline/results.csv | 44 +- 12-update_baseline/results.log | 2008 +- console.log | 131473 +++++++++++---------- jenkins/manifest.sh | 26 +- results | 2 +- results_id | 2 +- 28 files changed, 135303 insertions(+), 133117 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-next-allmodconfig updated (ed0aa6151e7 -> 5d201f32885)

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3 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-next-allmodconfig updated (e56e313c -> 10843f1a)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-next-allmodconfig in repository toolchain/ci/base-artifacts. discards e56e313c 2: update: binutils-gcc-linux-qemu: 21252 new 10843f1a 2: update: binutils-gcc-qemu: 21252 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (e56e313c) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 281 +- 02-prepare_abe/console.log | 260 +- 03-build_abe-binutils/console.log | 11586 ++++++------- 04-build_abe-stage1/console.log | 13769 ++++++++-------- 05-build_linux/console.log | 540 +- 08-check_regression/console.log | 8 +- 08-check_regression/results.regressions | 6 +- 09-update_baseline/console.log | 66 +- 09-update_baseline/results.regressions | 6 +- console.log | 26448 +++++++++++++++--------------- jenkins/manifest.sh | 12 +- 11 files changed, 26344 insertions(+), 26638 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_bmk_tx1/gnu-master-aarch64-spec2k6-O3 updated (7f227da3e60 -> 4a369d199bf)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/gnu-master-aarch64-spec2k6-O3 in repository toolchain/ci/gcc. from 7f227da3e60 Use EAF_RETURN_ARG in tree-ssa-ccp.c adds e94de06fd60 RISC-V: Refine riscv_parse_arch_string adds 0365b9e4af2 Fix fnspec of math builtins adds 79e61a6361f [Ada] Improve EINTR error handling on "poll" system call adds b36ec51873b [Ada] New flag Transform_Function_Array adds 0c1eba1a6a9 [Ada] Remove Digits_From_Size and Width_From_Size adds b3ad829bd17 [Ada] CUDA: handle parameter associations in expansion of C [...] adds fb00cc7032b [Ada] Multidimensional arrays with Iterated_Component_Associations adds a026b59e771 [Ada] Fix GNATprove support for iterated_component_associations adds 39706328c46 [Ada] Warnings on g-spogwa.adb adds 5cb0dbd6b19 [Ada] vx7r2cert: port ARM, PowerPC and x86 targets adds 21508c47f9a Re-enable fnspec checking once fortran frontend is fixed. adds 14e19b82c1e gcov-profile: use static pool for TOPN first adds e419ede8915 d: Merge upstream dmd 0fcdaab32 adds d249ba878cc d: Remove the d_critsec_size target hook. adds 4e6e941db7c [RS6000] Unsupported test options for -m32 adds 5af1e827bbb Avoid uniform lane BB vectorization adds 4a369d199bf SLP vectorize across PHI nodes No new revisions were added by this update. Summary of changes: gcc/ada/Makefile.rtl | 6 + gcc/ada/ada_get_targ.adb | 32 - gcc/ada/exp_ch6.adb | 4 +- gcc/ada/exp_prag.adb | 11 +- gcc/ada/exp_spark.adb | 172 ++++-- gcc/ada/exp_unst.adb | 4 +- gcc/ada/freeze.adb | 2 +- gcc/ada/get_targ.adb | 32 - gcc/ada/get_targ.ads | 4 - gcc/ada/gnat1drv.adb | 18 +- gcc/ada/libgnat/g-socpol.adb | 3 +- gcc/ada/libgnat/g-spogwa.adb | 6 +- gcc/ada/opt.ads | 6 + gcc/ada/sem_aggr.adb | 57 +- gcc/ada/sem_ch6.adb | 29 +- gcc/ada/ttypes.ads | 31 - gcc/ada/vxworks7-cert-rtp-link.spec | 9 + gcc/builtin-attrs.def | 6 + gcc/builtins.def | 5 +- gcc/common/config/riscv/riscv-common.c | 84 ++- gcc/config/aarch64/aarch64-linux.h | 2 - gcc/config/glibc-d.c | 16 - gcc/config/i386/linux-common.h | 3 - gcc/config/sol2-d.c | 12 - gcc/d/d-target.cc | 10 - gcc/d/d-target.def | 10 - gcc/d/dmd/MERGE | 2 +- gcc/d/dmd/dtemplate.c | 66 +- gcc/d/dmd/idgen.c | 2 +- gcc/d/dmd/statementsem.c | 14 +- gcc/d/dmd/target.h | 2 - gcc/doc/tm.texi | 7 - gcc/doc/tm.texi.in | 2 - gcc/gcov-io.h | 2 +- gcc/gimple.h | 2 + gcc/testsuite/g++.dg/vect/simd-11.cc | 61 ++ gcc/testsuite/gcc.dg/tree-prof/pr97461.c | 58 ++ gcc/testsuite/gcc.dg/vect/bb-slp-54.c | 23 + gcc/testsuite/gcc.dg/vect/bb-slp-55.c | 18 + gcc/testsuite/gcc.dg/vect/bb-slp-56.c | 17 + gcc/testsuite/gcc.dg/vect/bb-slp-57.c | 38 ++ gcc/testsuite/gcc.dg/vect/bb-slp-58.c | 23 + gcc/testsuite/gcc.dg/vect/bb-slp-59.c | 25 + gcc/testsuite/gcc.dg/vect/bb-slp-60.c | 18 + gcc/testsuite/gcc.dg/vect/bb-slp-61.c | 26 + gcc/testsuite/gcc.dg/vect/bb-slp-62.c | 21 + gcc/testsuite/gcc.dg/vect/bb-slp-63.c | 21 + gcc/testsuite/gcc.dg/vect/bb-slp-64.c | 11 + gcc/testsuite/gcc.dg/vect/bb-slp-65.c | 15 + gcc/testsuite/gcc.dg/vect/bb-slp-66.c | 32 + gcc/testsuite/gcc.dg/vect/vect-outer-slp-1.c | 31 + gcc/testsuite/gcc.target/i386/pr95866-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-22.c | 2 +- .../gdc.test/compilable/imports/test21299/func.d | 8 + .../gdc.test/compilable/imports/test21299/mtype.d | 8 + .../compilable/imports/test21299/rootstringtable.d | 96 +++ gcc/testsuite/gdc.test/compilable/test21299a.d | 4 + gcc/testsuite/gdc.test/compilable/test21299b.d | 4 + gcc/testsuite/gdc.test/compilable/test21299c.d | 5 + gcc/testsuite/gdc.test/compilable/test21299d.d | 27 + gcc/testsuite/gfortran.dg/vect/O3-bb-slp-1.f | 28 + gcc/testsuite/gfortran.dg/vect/O3-bb-slp-2.f | 40 ++ gcc/tree-ssa-alias.c | 5 +- gcc/tree-vect-loop-manip.c | 27 + gcc/tree-vect-loop.c | 112 +++- gcc/tree-vect-slp.c | 686 ++++++++++++++------- gcc/tree-vect-stmts.c | 8 +- gcc/tree-vectorizer.c | 3 +- gcc/tree-vectorizer.h | 2 + libgcc/libgcov.h | 24 +- libphobos/libdruntime/MERGE | 2 +- libphobos/libdruntime/rt/critical_.d | 18 + 72 files changed, 1643 insertions(+), 579 deletions(-) create mode 100644 gcc/ada/vxworks7-cert-rtp-link.spec create mode 100644 gcc/testsuite/g++.dg/vect/simd-11.cc create mode 100644 gcc/testsuite/gcc.dg/tree-prof/pr97461.c create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-54.c create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-55.c create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-56.c create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-57.c create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-58.c create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-59.c create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-60.c create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-61.c create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-62.c create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-63.c create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-64.c create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-65.c create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-66.c create mode 100644 gcc/testsuite/gcc.dg/vect/vect-outer-slp-1.c create mode 100644 gcc/testsuite/gdc.test/compilable/imports/test21299/func.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/test21299/mtype.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/test21299/rootstringtable.d create mode 100644 gcc/testsuite/gdc.test/compilable/test21299a.d create mode 100644 gcc/testsuite/gdc.test/compilable/test21299b.d create mode 100644 gcc/testsuite/gdc.test/compilable/test21299c.d create mode 100644 gcc/testsuite/gdc.test/compilable/test21299d.d create mode 100644 gcc/testsuite/gfortran.dg/vect/O3-bb-slp-1.f create mode 100644 gcc/testsuite/gfortran.dg/vect/O3-bb-slp-2.f -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk_tx1/gnu-master-aarch64-spec2k6-O3 updated (761845d7 -> daedbafd)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/gnu-master-aarch64-spec2k6-O3 in repository toolchain/ci/base-artifacts. from 761845d7 7: update: binutils-b634d11d61e3236f4602e9461dba67d1320f65e3: 1 new daedbafd 8: reset: gcc-4a369d199bf2f34e037030b18d0da923e8a24997: 1 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 186 +- 02-prepare_abe/console.log | 445 +- 03-build_abe-binutils/console.log | 11844 +- 04-build_abe-stage1/console.log | 15984 +-- 05-build_abe-linux/console.log | 2006 +- 06-build_abe-glibc/console.log | 136767 +++++++++---------- 07-build_abe-stage2/console.log | 32856 ++--- 09-benchmark--O3/benchmark-start.log | 2 +- 09-benchmark--O3/benchmark.log | 8 +- 09-benchmark--O3/console.log | 486 +- 10-check_regression/console.log | 3867 +- 10-check_regression/extra-bisect-params | 2 +- 10-check_regression/results-0.csv | 3088 +- 10-check_regression/results-1.csv | 3180 +- 10-check_regression/results-brief.csv | 54 +- 10-check_regression/results-compare.csv | 20 +- 10-check_regression/results-full.csv | 3388 +- 10-check_regression/results.csv | 246 +- 10-check_regression/results.log | 3846 +- 10-check_regression/results.regressions | 3 + 10-check_regression/trigger-bisect | 4 + 11-update_baseline/console.log | 4799 +- 11-update_baseline/extra-bisect-params | 2 +- 11-update_baseline/results-0.csv | 3247 +- 11-update_baseline/results-1.csv | 3180 +- 11-update_baseline/results-brief.csv | 58 +- 11-update_baseline/results-compare.csv | 24 +- 11-update_baseline/results-full.csv | 3392 +- 11-update_baseline/results.csv | 250 +- 11-update_baseline/results.log | 3996 +- 11-update_baseline/results.regressions | 6 +- console.log | 209506 ++++++++++++++--------------- jenkins/manifest.sh | 14 +- reset-baseline | 0 results | 3 + results_id | 2 +- 36 files changed, 219765 insertions(+), 226996 deletions(-) create mode 100644 10-check_regression/results.regressions create mode 100644 10-check_regression/trigger-bisect create mode 100644 reset-baseline -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-stable-defconfig updated (ed0aa6151e7 -> 5d201f32885)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-stable-defconfig in repository toolchain/ci/gcc. from ed0aa6151e7 Daily bump. adds 5d201f32885 Daily bump. No new revisions were added by this update. Summary of changes: gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

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