Tcwg-commits January 2021

tcwg-commits@lists.linaro.org

5 participants
9360 discussions

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-defconfig updated (5ee88057889b -> 1d94330a437a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-defconfig in repository toolchain/ci/linux. from 5ee88057889b Merge tag 'drm-fixes-2021-01-15' of git://anongit.freedesk [...] adds 3b050680c841 drm/nouveau/core: recognise GA10[024] adds 70afbe4bdc0a drm/nouveau/pci/ga10[024]: initial support adds a34632482f1e drm/nouveau/bios/ga10[024]: initial support adds 7ddf5e9597fa drm/nouveau/devinit/ga10[024]: initial support adds 5961c62d2075 drm/nouveau/mc/ga10[024]: initial support adds e0df4bbfc336 drm/nouveau/privring/ga10[024]: initial support adds de4781d0f22b drm/nouveau/imem/ga10[024]: initial support adds 41ba806f40a9 drm/nouveau/fb/ga10[024]: initial support adds 6f300e0a0ba8 drm/nouveau/timer/ga10[024]: initial support adds a3abc23ac401 drm/nouveau/mmu/ga10[024]: initial support adds f5cbe7c8bd1a drm/nouveau/bar/ga10[024]: initial support adds c28efb15f9e5 drm/nouveau/gpio/ga10[024]: initial support adds 8a0412265f06 drm/nouveau/i2c/ga10[024]: initial support adds a6cf0320aad0 drm/nouveau/dmaobj/ga10[24]: initial support adds 8ef23b6f6a79 drm/nouveau/disp/ga10[24]: initial support adds 584265dfec70 Merge branch '04.01-ampere-lite' of git://github.com/skegg [...] adds 02c06dc3750b Merge tag 'topic/nouveau-ampere-modeset-2021-01-15' of git [...] adds 2d6ffc63f124 iommu/vt-d: Fix unaligned addresses for intel_flush_svm_ra [...] adds b812834b5329 iommu: arm-smmu-qcom: Add sdm630/msm8998 compatibles for q [...] adds 694a1c0adebe iommu/vt-d: Fix duplicate included linux/dma-map-ops.h adds 7aec71cd9c1f Merge tag 'iommu-fixes' of git://git.kernel.org/pub/scm/li [...] adds ef3a575baf53 xen/privcmd: allow fetching resource sizes adds 3499ba8198ca xen: Fix event channel callback via INTX/GSI adds 8f4fd86aa5d6 xen: Set platform PCI device INTX affinity to CPU0 adds b36b0fe96af1 x86/xen: Add xen_no_vector_callback option to test PCI INT [...] adds 4621dc6a5bf1 x86/xen: Don't register Xen IPIs when they aren't going to [...] adds 3d7746bea925 x86/xen: Fix xen_hvm_smp_init() when vector callback not a [...] adds dcda487c9c2e Merge tag 'for-linus-5.11-rc4-tag' of git://git.kernel.org [...] adds a58015d638cd ACPI: scan: Harden acpi_device_add() against device ID overflows adds 3c516e038f0c Documentation: ACPI: EINJ: Fix error type values for PCIe errors adds 179892adb043 Merge branch 'acpi-docs' adds f4e087c666f5 Merge tag 'acpi-5.11-rc4' of git://git.kernel.org/pub/scm/ [...] adds 4d4f9c1a17a3 MIPS: boot: Fix unaligned access with CONFIG_MIPS_RAW_APPE [...] adds 698222457465 MIPS: Fix malformed NT_FILE and NT_SIGINFO in 32bit coredumps adds 69e976831cd5 MIPS: relocatable: fix possible boot hangup with KASLR enabled adds 7b490a8ab0f2 MIPS: OCTEON: fix unreachable code in octeon_irq_init_ciu adds f288c895622f Merge tag 'mips_fixes_5.11.1' of git://git.kernel.org/pub/ [...] adds d78050ee3544 arm64: Remove arm64_dma32_phys_limit and its uses adds df06824767cc arm64: entry: remove redundant IRQ flag tracing adds b90d72a6bfdb Revert "arm64: Enable perf events based hard lockup detector" adds 71e70184f1d1 arm64: rename S_FRAME_SIZE to PT_REGS_SIZE adds c35a824c3183 arm64: make atomic helpers __always_inline adds dca5244d2f5b compiler.h: Raise minimum version of GCC to 5.1 for arm64 adds b6d8878d24e3 arm64: syscall: include prototype for EL0 SVC functions adds 3a57a643a851 arm64: selftests: Fix spelling of 'Mismatch' adds 82821be8a2e1 Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/li [...] adds 77b6ec01c29a cifs: check pointer before freeing adds 2659d3bff3e1 cifs: fix interrupted close commands adds c13e7af04227 fs: cifs: remove unneeded variable in smb3_fs_context_dup adds ed6b1920f84b cifs: connect: style: Simplify bool comparison adds e54fd0716c3d cifs: style: replace one-element array with flexible-array adds 7cd3c4126188 Merge tag '5.11-rc3-smb3' of git://git.samba.org/sfrench/cifs-2.6 adds e789ca0cc1d5 ext4: combine ext4_handle_error() and save_error_info() adds 4392fbc4bab5 ext4: drop sync argument of ext4_commit_super() adds 05c2c00f3769 ext4: protect superblock modifications with a buffer lock adds 2d01ddc86606 ext4: save error info to sb through journal if available adds e92ad03fa534 ext4: use sbi instead of EXT4_SB(sb) in ext4_update_super() adds dfd56c2c0c0d ext4: fix superblock checksum failure when setting password salt adds a3f5cf14ff91 ext4: drop ext4_handle_dirty_super() adds 5a3b590d4b2d ext4: don't leak old mountpoint samples adds 23dd561ad9ea ext4: use IS_ERR instead of IS_ERR_OR_NULL and set inode n [...] adds 31e203e09f03 ext4: fix wrong list_splice in ext4_fc_cleanup adds 6b4b8e6b4ad8 ext4: fix bug for rename with RENAME_WHITEOUT adds e9f53353e166 ext4: remove expensive flush on fast commit adds 0bc9bc1d8b2f Merge tag 'ext4_for_linus_stable' of git://git.kernel.org/ [...] adds 8ae291cc95e4 RDMA/ucma: Do not miss ctx destruction steps in some cases adds 3c638cdb8ecc RDMA/restrack: Don't treat as an error allocation ID wrapping adds a306aba9c8d8 RDMA/usnic: Fix memleak in find_free_vf_and_create_qp_grp adds f2bc3af6353c RDMA/ocrdma: Fix use after free in ocrdma_dealloc_ucontext_pd() adds b79f2dc5ffe1 RDMA/umem: Avoid undefined behavior of rounddown_pow_of_two() adds 2cb091f6293d IB/mlx5: Fix error unwinding when set_has_smi_cap fails adds 1c3aa6bd0b82 RDMA/mlx5: Fix wrong free of blue flame register on error adds 7c7b3e5d9aee RDMA/cma: Fix error flow in default_roce_mode_store adds 8cbe71e7e01a Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linu [...] adds 8ff60eb052ee mm, slub: consider rest of partial list if acquire_slab() fails adds ce8f86ee94fa mm/page_alloc: add a missing mm_page_alloc_zone_locked() t [...] adds 7ea510b92c7c mm/memcontrol: fix warning in mem_cgroup_page_lruvec() adds 29970dc24faf arm/kasan: fix the array size of kasan_early_shadow_pte[] adds c22ee5284cf5 mm/vmalloc.c: fix potential memory leak adds f555befd185d mm: migrate: initialize err in do_migrate_pages adds 0eb98f1588c2 mm/hugetlb: fix potential missing huge page size info adds 7e5f1126b54a MAINTAINERS: add Vlastimil as slab allocators maintainer adds 6696d2a6f38c mm,hwpoison: fix printing of page flags adds eb351d75ce1e mm/process_vm_access.c: include compat.h adds b45e2da6e444 Merge branch 'akpm' (patches from Andrew) adds cc07d72bf350 dm raid: fix discard limits for raid1 adds f7b347acb5f6 dm integrity: select CRYPTO_SKCIPHER adds b690bd546b22 dm zoned: select CONFIG_CRC32 adds 8abec36d1274 dm crypt: do not wait for backlogged crypto request comple [...] adds d68b29584c25 dm crypt: use GFP_ATOMIC when allocating crypto requests f [...] adds fcc42338375a dm snapshot: flush merged data before committing metadata adds 0378c625afe8 dm: eliminate potential source of excessive kernel log noise adds 9b5948267adc dm integrity: fix flush with external metadata device adds 8e14f610159d dm crypt: do not call bio_endio() from the dm-crypt tasklet adds 17ffc193cdc6 dm integrity: fix the maximum number of arguments adds c87a95dc28b1 dm crypt: defer decryption to a tasklet if interrupts disabled adds 1d94330a437a Merge tag 'for-5.11/dm-fixes-1' of git://git.kernel.org/pu [...] No new revisions were added by this update. Summary of changes: Documentation/admin-guide/kernel-parameters.txt | 4 + Documentation/firmware-guide/acpi/apei/einj.rst | 4 +- MAINTAINERS | 1 + arch/arm/xen/enlighten.c | 2 +- arch/arm64/Kconfig | 2 - arch/arm64/include/asm/atomic.h | 10 +- arch/arm64/include/asm/processor.h | 3 +- arch/arm64/kernel/asm-offsets.c | 2 +- arch/arm64/kernel/entry-ftrace.S | 12 +- arch/arm64/kernel/entry.S | 14 +- arch/arm64/kernel/perf_event.c | 41 +---- arch/arm64/kernel/probes/kprobes_trampoline.S | 6 +- arch/arm64/kernel/signal.c | 7 - arch/arm64/kernel/syscall.c | 10 +- arch/arm64/mm/init.c | 33 ++-- arch/mips/boot/compressed/decompress.c | 3 +- arch/mips/cavium-octeon/octeon-irq.c | 2 +- arch/mips/kernel/binfmt_elfn32.c | 7 + arch/mips/kernel/binfmt_elfo32.c | 7 + arch/mips/kernel/relocate.c | 10 +- arch/x86/xen/enlighten_hvm.c | 15 +- arch/x86/xen/smp_hvm.c | 27 +-- drivers/acpi/internal.h | 2 +- drivers/acpi/scan.c | 15 +- drivers/gpu/drm/nouveau/dispnv50/Kbuild | 1 + drivers/gpu/drm/nouveau/dispnv50/core.c | 1 + drivers/gpu/drm/nouveau/dispnv50/curs.c | 1 + drivers/gpu/drm/nouveau/dispnv50/wimm.c | 1 + drivers/gpu/drm/nouveau/dispnv50/wndw.c | 1 + drivers/gpu/drm/nouveau/dispnv50/wndw.h | 8 + drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c | 10 +- drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c | 106 ++++++++++++ drivers/gpu/drm/nouveau/include/nvif/cl0080.h | 1 + drivers/gpu/drm/nouveau/include/nvif/class.h | 5 + drivers/gpu/drm/nouveau/include/nvkm/core/device.h | 1 + drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h | 1 + .../gpu/drm/nouveau/include/nvkm/subdev/devinit.h | 1 + drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h | 2 + drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h | 1 + drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h | 1 + drivers/gpu/drm/nouveau/nouveau_backlight.c | 1 + drivers/gpu/drm/nouveau/nvif/disp.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 75 +++++++- drivers/gpu/drm/nouveau/nvkm/engine/device/user.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild | 3 + drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c | 33 +++- .../{dispnv50/wimm.c => nvkm/engine/disp/ga102.c} | 44 +++-- drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h | 4 + drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h | 2 + .../curs.c => nvkm/engine/disp/rootga102.c} | 53 +++--- .../gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h | 1 + .../nvkm/engine/disp/{sortu102.c => sorga102.c} | 57 ++++--- .../gpu/drm/nouveau/nvkm/engine/disp/sortu102.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c | 2 +- .../gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c | 3 + drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild | 1 + .../nvkm/subdev/devinit/{tu102.c => ga100.c} | 33 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h | 1 + .../gpu/drm/nouveau/nvkm/subdev/devinit/tu102.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild | 3 + .../nouveau/nvkm/subdev/fb/{gv100.c => ga100.c} | 23 +-- .../nouveau/nvkm/subdev/fb/{gv100.c => ga102.c} | 25 +-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h | 2 + drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h | 1 + .../{dispnv50/wimm.c => nvkm/subdev/fb/ramga102.c} | 36 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/gpio/ga102.c | 118 +++++++++++++ drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/mc/ga100.c | 74 ++++++++ drivers/infiniband/core/cma_configfs.c | 4 +- drivers/infiniband/core/restrack.c | 1 + drivers/infiniband/core/ucma.c | 135 ++++++++------- drivers/infiniband/core/umem.c | 2 +- drivers/infiniband/hw/mlx5/main.c | 4 +- drivers/infiniband/hw/ocrdma/ocrdma_verbs.c | 2 +- drivers/infiniband/hw/usnic/usnic_ib_verbs.c | 3 + drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 + drivers/iommu/intel/iommu.c | 1 - drivers/iommu/intel/svm.c | 22 ++- drivers/md/Kconfig | 2 + drivers/md/dm-bufio.c | 6 + drivers/md/dm-crypt.c | 170 ++++++++++++++++-- drivers/md/dm-integrity.c | 62 +++++-- drivers/md/dm-raid.c | 6 +- drivers/md/dm-snap.c | 24 +++ drivers/md/dm.c | 2 +- drivers/perf/arm_pmu.c | 5 - drivers/xen/events/events_base.c | 10 -- drivers/xen/platform-pci.c | 8 +- drivers/xen/privcmd.c | 25 ++- drivers/xen/xenbus/xenbus.h | 1 + drivers/xen/xenbus/xenbus_comms.c | 8 - drivers/xen/xenbus/xenbus_probe.c | 81 +++++++-- fs/cifs/connect.c | 2 +- fs/cifs/dfs_cache.c | 3 +- fs/cifs/fs_context.c | 4 +- fs/cifs/smb2pdu.c | 2 +- fs/cifs/smb2pdu.h | 2 +- fs/ext4/ext4_jbd2.c | 17 -- fs/ext4/ext4_jbd2.h | 5 - fs/ext4/fast_commit.c | 35 ++-- fs/ext4/file.c | 7 +- fs/ext4/inode.c | 6 +- fs/ext4/ioctl.c | 3 + fs/ext4/namei.c | 27 +-- fs/ext4/resize.c | 20 ++- fs/ext4/super.c | 190 +++++++++++++-------- fs/ext4/xattr.c | 5 +- include/asm-generic/bitops/atomic.h | 6 +- include/linux/compiler-gcc.h | 6 + include/linux/dm-bufio.h | 1 + include/linux/kasan.h | 6 +- include/linux/memcontrol.h | 2 +- include/linux/perf/arm_pmu.h | 2 - include/xen/xenbus.h | 2 +- mm/hugetlb.c | 2 +- mm/kasan/init.c | 3 +- mm/memory-failure.c | 2 +- mm/mempolicy.c | 2 +- mm/page_alloc.c | 31 ++-- mm/process_vm_access.c | 1 + mm/slub.c | 2 +- mm/vmalloc.c | 4 +- tools/testing/selftests/arm64/fp/fpsimd-test.S | 2 +- tools/testing/selftests/arm64/fp/sve-test.S | 2 +- 126 files changed, 1368 insertions(+), 608 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c copy drivers/gpu/drm/nouveau/{dispnv50/wimm.c => nvkm/engine/disp/ga102.c} (61%) copy drivers/gpu/drm/nouveau/{dispnv50/curs.c => nvkm/engine/disp/rootga102.c} (56%) copy drivers/gpu/drm/nouveau/nvkm/engine/disp/{sortu102.c => sorga102.c} (78%) copy drivers/gpu/drm/nouveau/nvkm/subdev/devinit/{tu102.c => ga100.c} (70%) copy drivers/gpu/drm/nouveau/nvkm/subdev/fb/{gv100.c => ga100.c} (67%) copy drivers/gpu/drm/nouveau/nvkm/subdev/fb/{gv100.c => ga102.c} (66%) copy drivers/gpu/drm/nouveau/{dispnv50/wimm.c => nvkm/subdev/fb/ramga102.c} (63%) create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/ga102.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/mc/ga100.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-defconfig updated (b0ccd3922f5 -> 2c356f221bb)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-defconfig in repository toolchain/ci/gcc. from b0ccd3922f5 compiler: add support for reading embedcfg files adds c4eec1efae0 testsuite: Fix sed script errors in complex tests adds 2ea6f4a377e tree-optimization/98685 - fix placement of extern converts adds 7432f255b70 arm: Auto-vectorization for MVE: vshl adds bfab355012c arm: Auto-vectorization for MVE: vshr adds 0411ae7f08e libatomic, libgomp, libitc: Fix bootstrap [PR70454] adds cb60334b716 testsuite/96098 - remove redundant testcase adds 1a630642009 arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics adds d03f14c354a testsuite/96147 - remove scanning for ! vect_hw_misalign adds e1bd80fb706 testsuite/96147 - key scanning on vect_hw_misalign adds aa4ee5798fe testsuite/96147 - scan for vectorized load adds b36c9cd0947 testsuite/96147 - align vector access adds dc8475e3348 Pytest in tests: improve adds 446703ccc2c tree-optimization/96376 - do not check alignment for invari [...] adds f1d054017ef Revert "arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 [...] adds 63999d751df arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics adds f9a577927eb IBM Z: Fix linking to libatomic in target test cases adds 7f6cdaa9a8d rtl-ssa: Fix a silly typo adds f2cc526f47a recog: Fix insn_change_watermark destructor adds 5a783f42d77 aarch64: Add a minipass for fusing CC insns [PR88836] adds 492b90f33df c++: Fix langspecs with -fsyntax-only [PR98591] adds 1ba71fabb78 preprocessor: Make quoting : [PR 95253] adds 7d0df0aeb67 i386: Use cpp_define_formatted for __SIZEOF_FLOAT80__ definition adds d3959070aa4 [PATCH] aarch64: Implement vmlsl[_high]* intrinsics using builtins adds 50dbced2f37 openmp: Change the way of building of reduction array type adds adb520606ce c-family: Improve MEM_REF printing for diagnostics [PR98597] adds a3128bf0128 bootstrap: fix failing diagnostic selftest on Windows [PR98696] adds aaec739250b testsuite: Add testcase coverage for already fixed [PR96671] adds c0194736b47 gcc.dg/analyzer tests: use __builtin_alloca, not alloca.h adds cd09079cfd5 c++: Fix list-init of array of no-copy type [PR63707] adds ad260343385 AArch64: Add NEON, SVE and SVE2 RTL patterns for Multiply, [...] adds 424deca72b6 c++: Fix copy elision for base initialization adds d75199f7823 c++: Avoid redundant copy in {} init [PR98642] adds e63c2161d09 drop -dumpbase-ext from producer string adds 5c046034e3e match.pd: Optimize (x < 0) ^ (y < 0) to (x ^ y) < 0 etc. [PR96681] adds 0425f4c1b63 match.pd: Generalize the PR64309 simplifications [PR96669] adds e1efa6af61a preprocessor: Make quoting : [PR 95253] adds 9beb6d88eff c++: Fix qualified array-type construction [PR 98538] adds b90e4a97419 fortran: Fixes a bug in ISO_Fortran_binding.c. adds c029fcb5680 Reset force_source_line in final.c adds f1ad419ebfd rs6000, vector integer multiply/divide/modulo instructions adds 2f7f0d32e74 Daily bump. adds 2c356f221bb libstdc++-v3: Add -fcf-protection=none to -march=i486 No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 170 +++++++++ gcc/DATESTAMP | 2 +- gcc/Makefile.in | 7 + gcc/c-family/ChangeLog | 12 + gcc/c-family/c-pretty-print.c | 259 +++++++++++--- gcc/c/ChangeLog | 6 + gcc/c/c-typeck.c | 4 +- gcc/config.gcc | 2 +- gcc/config/aarch64/aarch64-cc-fusion.cc | 296 +++++++++++++++ gcc/config/aarch64/aarch64-passes.def | 1 + gcc/config/aarch64/aarch64-protos.h | 1 + gcc/config/aarch64/aarch64-simd-builtins.def | 8 + gcc/config/aarch64/aarch64-simd.md | 56 ++- gcc/config/aarch64/aarch64-sve.md | 56 +++ gcc/config/aarch64/aarch64-sve2.md | 42 +++ gcc/config/aarch64/arm_neon.h | 84 +---- gcc/config/aarch64/iterators.md | 109 +++++- gcc/config/aarch64/t-aarch64 | 6 + gcc/config/arm/arm_neon.h | 31 ++ gcc/config/arm/mve.md | 47 ++- gcc/config/arm/neon.md | 53 --- gcc/config/arm/vec-common.md | 58 +++ gcc/config/i386/i386-c.c | 9 +- gcc/config/rs6000/altivec.h | 4 + gcc/config/rs6000/altivec.md | 2 - gcc/config/rs6000/rs6000-builtin.def | 21 ++ gcc/config/rs6000/rs6000-call.c | 53 +++ gcc/config/rs6000/rs6000.md | 5 +- gcc/config/rs6000/vsx.md | 211 ++++++++--- gcc/cp/ChangeLog | 35 ++ gcc/cp/call.c | 145 ++++++-- gcc/cp/cp-tree.h | 3 +- gcc/cp/lang-specs.h | 40 ++- gcc/cp/tree.c | 18 +- gcc/cp/typeck2.c | 21 +- gcc/diagnostic.c | 12 +- gcc/doc/extend.texi | 120 +++++++ gcc/doc/install.texi | 2 +- gcc/doc/sourcebuild.texi | 4 + gcc/final.c | 1 + gcc/go/ChangeLog | 4 + gcc/match.pd | 39 +- gcc/opts.c | 1 + gcc/recog.h | 8 +- gcc/rtl-ssa/functions.h | 2 +- gcc/rtl-ssa/member-fns.inl | 2 +- gcc/testsuite/ChangeLog | 156 ++++++++ gcc/testsuite/g++.dg/cpp0x/initlist-array13.C | 16 + gcc/testsuite/g++.dg/cpp1z/elide4.C | 24 ++ gcc/testsuite/g++.dg/cpp1z/elide5.C | 15 + gcc/testsuite/g++.dg/modules/dep-1_a.C | 4 +- gcc/testsuite/g++.dg/modules/dep-1_b.C | 4 +- gcc/testsuite/g++.dg/modules/dep-2.C | 6 +- gcc/testsuite/g++.dg/modules/pr98591.H | 3 + gcc/testsuite/g++.dg/template/pr98538.C | 18 + gcc/testsuite/gcc.dg/analyzer/alloca-leak.c | 4 +- gcc/testsuite/gcc.dg/analyzer/data-model-1.c | 5 +- gcc/testsuite/gcc.dg/analyzer/malloc-1.c | 3 +- gcc/testsuite/gcc.dg/analyzer/malloc-paths-8.c | 7 +- gcc/testsuite/gcc.dg/tree-ssa/pr96669-1.c | 59 +++ gcc/testsuite/gcc.dg/tree-ssa/pr96671-1.c | 51 +++ gcc/testsuite/gcc.dg/tree-ssa/pr96671-2.c | 51 +++ gcc/testsuite/gcc.dg/tree-ssa/pr96681.c | 35 ++ gcc/testsuite/gcc.dg/uninit-38.c | 80 ++--- gcc/testsuite/gcc.dg/uninit-40.c | 50 +++ gcc/testsuite/gcc.dg/vect/bb-slp-32.c | 1 + gcc/testsuite/gcc.dg/vect/bb-slp-9.c | 2 +- gcc/testsuite/gcc.dg/vect/bb-slp-pr68892.c | 20 -- gcc/testsuite/gcc.dg/vect/bb-slp-pr98685.c | 15 + .../gcc.dg/vect/complex/complex-mla-template.c | 28 +- .../gcc.dg/vect/complex/complex-mls-template.c | 28 +- gcc/testsuite/gcc.dg/vect/slp-43.c | 4 +- gcc/testsuite/gcc.dg/vect/slp-45.c | 2 +- .../aarch64/advsimd-intrinsics/p64_p128.c | 46 ++- .../gcc.target/aarch64/sve/acle/general/ldff1_8.c | 32 ++ gcc/testsuite/gcc.target/aarch64/sve/ptest_1.c | 10 + gcc/testsuite/gcc.target/arm/simd/mve-vshl.c | 62 ++++ gcc/testsuite/gcc.target/arm/simd/mve-vshr.c | 59 +++ gcc/testsuite/gcc.target/arm/simd/vceqz_p64.c | 17 + gcc/testsuite/gcc.target/arm/simd/vceqzq_p64.c | 17 + .../gcc.target/powerpc/builtins-1-p10-runnable.c | 398 +++++++++++++++++++++ .../gcc.target/s390/md/atomic_exchange-1.c | 2 +- gcc/testsuite/gcc.target/s390/s390.exp | 4 + .../iso_fortran_binding_uint8_array.f90 | 11 + .../iso_fortran_binding_uint8_array_driver.c | 25 ++ gcc/testsuite/lib/gcov.exp | 31 +- gcc/tree-vect-slp.c | 11 +- gcc/tree-vect-stmts.c | 23 +- libatomic/ChangeLog | 9 + libatomic/configure.tgt | 56 +-- libcpp/ChangeLog | 5 + libcpp/mkdeps.c | 1 - libgfortran/ChangeLog | 6 + libgfortran/runtime/ISO_Fortran_binding.c | 3 +- libgomp/ChangeLog | 7 + libgomp/configure.tgt | 35 +- libitm/ChangeLog | 7 + libitm/configure.tgt | 37 +- .../atomic_flag/test_and_set/explicit-hle.cc | 2 +- 99 files changed, 3167 insertions(+), 512 deletions(-) create mode 100644 gcc/config/aarch64/aarch64-cc-fusion.cc create mode 100644 gcc/testsuite/g++.dg/cpp0x/initlist-array13.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/elide4.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/elide5.C create mode 100644 gcc/testsuite/g++.dg/modules/pr98591.H create mode 100644 gcc/testsuite/g++.dg/template/pr98538.C create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr96669-1.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr96671-1.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr96671-2.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr96681.c create mode 100644 gcc/testsuite/gcc.dg/uninit-40.c delete mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-pr68892.c create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-pr98685.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/ldff1_8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/ptest_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vshl.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vshr.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vceqz_p64.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vceqzq_p64.c create mode 100644 gcc/testsuite/gcc.target/powerpc/builtins-1-p10-runnable.c create mode 100644 gcc/testsuite/gfortran.dg/iso_fortran_binding_uint8_array.f90 create mode 100644 gcc/testsuite/gfortran.dg/iso_fortran_binding_uint8_array_driver.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-defconfig updated (bb3eddb5bd -> 68b007788a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-defconfig in repository toolchain/ci/binutils-gdb. from bb3eddb5bd sim: testsuite: delete configure script adds dcd709e056 RISC-V: Comments tidy and improvement. adds b800637e76 RISC-V: Error and warning messages tidy. adds 1942a04836 RISC-V: Indent and GNU coding standards tidy, also aligned t [...] adds 4bb5732e27 RISC-V: Fixed the indent that caused by the previous commits [...] adds 10f92414d6 [gdb/testsuite] Fix gdb.fortran/array-slices.exp with -m32 adds 5a11fff005 gdb/tui: compare pointer to nullptr, not 0 adds e403a898b5 Automatic date update in version.in adds 1368b914e9 sim: testsuite: flatten tree adds eb6e6af8c1 PR26002 undefined symbol VER_NDX_GLOBAL vs. VER_NDX_LOCAL adds ad92f33d38 Tidy inflateEnd calls adds 68b007788a ld/x86: Add -z report-relative-reloc No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 45 + bfd/compress.c | 3 +- bfd/elf-linker-x86.h | 3 + bfd/elf32-i386.c | 36 + bfd/elf64-x86-64.c | 33 + bfd/elflink.c | 2 +- bfd/elfnn-riscv.c | 319 +++-- bfd/elfxx-riscv.c | 54 +- bfd/elfxx-riscv.h | 4 +- bfd/elfxx-x86.c | 47 + bfd/elfxx-x86.h | 4 + bfd/version.h | 2 +- binutils/ChangeLog | 4 + binutils/readelf.c | 4 +- gas/ChangeLog | 23 + gas/config/tc-riscv.c | 521 ++++--- gas/config/tc-riscv.h | 6 +- gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 6 +- .../gas/riscv/priv-reg-fail-read-only-01.l | 136 +- .../gas/riscv/priv-reg-fail-read-only-02.l | 48 +- gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 130 +- .../gas/riscv/priv-reg-fail-version-1p10.l | 48 +- .../gas/riscv/priv-reg-fail-version-1p11.l | 46 +- .../gas/riscv/priv-reg-fail-version-1p9p1.l | 54 +- gdb/ChangeLog | 4 + gdb/testsuite/ChangeLog | 6 + gdb/testsuite/gdb.fortran/array-slices.exp | 2 +- gdb/tui/tui.c | 4 +- include/ChangeLog | 11 + include/elf/riscv.h | 3 +- include/opcode/riscv-opc.h | 16 +- include/opcode/riscv.h | 127 +- ld/ChangeLog | 35 + ld/NEWS | 3 + ld/emulparams/elf32_x86_64.sh | 1 + ld/emulparams/elf_i386.sh | 1 + ld/emulparams/elf_x86_64.sh | 1 + ld/emulparams/x86-report-relative.sh | 11 + ld/ld.texi | 4 + ld/testsuite/ld-elfvers/vers16.dsym | 2 +- ld/testsuite/ld-elfvers/vers6.dsym | 2 +- ld/testsuite/ld-i386/i386.exp | 1 + ld/testsuite/ld-i386/report-reloc-1.d | 10 + ld/testsuite/ld-i386/report-reloc-1.l | 2 + ld/testsuite/ld-i386/report-reloc-1.s | 12 + .../ld-riscv-elf/attr-merge-priv-spec-failed-01.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-02.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-03.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-04.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-05.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-06.d | 4 +- ld/testsuite/ld-x86-64/report-reloc-1-x32.d | 10 + ld/testsuite/ld-x86-64/report-reloc-1.d | 10 + ld/testsuite/ld-x86-64/report-reloc-1.l | 2 + ld/testsuite/ld-x86-64/report-reloc-1.s | 12 + ld/testsuite/ld-x86-64/x86-64.exp | 2 + opcodes/ChangeLog | 16 + opcodes/riscv-dis.c | 30 +- opcodes/riscv-opc.c | 1456 ++++++++++---------- sim/testsuite/ChangeLog | 5 + sim/testsuite/Makefile.in | 1 - sim/testsuite/{sim => }/aarch64/ChangeLog | 0 sim/testsuite/{sim => }/aarch64/adds.s | 0 sim/testsuite/{sim => }/aarch64/addv.s | 0 sim/testsuite/{sim => }/aarch64/allinsn.exp | 0 sim/testsuite/{sim => }/aarch64/bit.s | 0 sim/testsuite/{sim => }/aarch64/cmtst.s | 0 sim/testsuite/{sim => }/aarch64/cnt.s | 0 sim/testsuite/{sim => }/aarch64/fcmXX.s | 0 sim/testsuite/{sim => }/aarch64/fcmp.s | 0 sim/testsuite/{sim => }/aarch64/fcsel.s | 0 sim/testsuite/{sim => }/aarch64/fcvtl.s | 0 sim/testsuite/{sim => }/aarch64/fcvtz.s | 0 sim/testsuite/{sim => }/aarch64/fminnm.s | 0 sim/testsuite/{sim => }/aarch64/fstur.s | 0 sim/testsuite/{sim => }/aarch64/ldn_multiple.s | 0 sim/testsuite/{sim => }/aarch64/ldn_single.s | 0 sim/testsuite/{sim => }/aarch64/ldnr.s | 0 sim/testsuite/{sim => }/aarch64/mla.s | 0 sim/testsuite/{sim => }/aarch64/mls.s | 0 sim/testsuite/{sim => }/aarch64/mul.s | 0 sim/testsuite/{sim => }/aarch64/pass.s | 0 sim/testsuite/{sim => }/aarch64/stn_multiple.s | 0 sim/testsuite/{sim => }/aarch64/stn_single.s | 0 sim/testsuite/{sim => }/aarch64/sumov.s | 0 sim/testsuite/{sim => }/aarch64/sumulh.s | 0 sim/testsuite/{sim => }/aarch64/tbnz.s | 0 sim/testsuite/{sim => }/aarch64/testutils.inc | 0 sim/testsuite/{sim => }/aarch64/uzp.s | 0 sim/testsuite/{sim => }/aarch64/xtl.s | 0 sim/testsuite/{sim => }/aarch64/xtn.s | 0 sim/testsuite/{sim => }/arm/ChangeLog | 0 sim/testsuite/{sim => }/arm/adc.cgs | 0 sim/testsuite/{sim => }/arm/add.cgs | 0 sim/testsuite/{sim => }/arm/allinsn.exp | 0 sim/testsuite/{sim => }/arm/and.cgs | 0 sim/testsuite/{sim => }/arm/b.cgs | 0 sim/testsuite/{sim => }/arm/bic.cgs | 0 sim/testsuite/{sim => }/arm/bl.cgs | 0 sim/testsuite/{sim => }/arm/bx.cgs | 0 sim/testsuite/{sim => }/arm/cmn.cgs | 0 sim/testsuite/{sim => }/arm/cmp.cgs | 0 sim/testsuite/{sim => }/arm/eor.cgs | 0 sim/testsuite/{sim => }/arm/hello.ms | 0 sim/testsuite/{sim => }/arm/iwmmxt/iwmmxt.exp | 0 sim/testsuite/{sim => }/arm/iwmmxt/tbcst.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/testutils.inc | 0 sim/testsuite/{sim => }/arm/iwmmxt/textrm.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tinsr.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmia.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmiaph.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmiaxy.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmovmsk.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wacc.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wadd.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/waligni.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/walignr.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wand.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wandn.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wavg2.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wcmpeq.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wcmpgt.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmac.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmadd.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmax.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmin.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmov.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmul.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wor.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wpack.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wror.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsad.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wshufh.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsll.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsra.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsrl.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsub.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckeh.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckel.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckih.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckil.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wxor.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wzero.cgs | 0 sim/testsuite/{sim => }/arm/ldm.cgs | 0 sim/testsuite/{sim => }/arm/ldr.cgs | 0 sim/testsuite/{sim => }/arm/ldrb.cgs | 0 sim/testsuite/{sim => }/arm/ldrh.cgs | 0 sim/testsuite/{sim => }/arm/ldrsb.cgs | 0 sim/testsuite/{sim => }/arm/ldrsh.cgs | 0 sim/testsuite/{sim => }/arm/misaligned1.ms | 0 sim/testsuite/{sim => }/arm/misaligned2.ms | 0 sim/testsuite/{sim => }/arm/misaligned3.ms | 0 sim/testsuite/{sim => }/arm/misc.exp | 0 sim/testsuite/{sim => }/arm/mla.cgs | 0 sim/testsuite/{sim => }/arm/mov.cgs | 0 sim/testsuite/{sim => }/arm/movw-movt.ms | 0 sim/testsuite/{sim => }/arm/mrs.cgs | 0 sim/testsuite/{sim => }/arm/msr.cgs | 0 sim/testsuite/{sim => }/arm/mul.cgs | 0 sim/testsuite/{sim => }/arm/mvn.cgs | 0 sim/testsuite/{sim => }/arm/orr.cgs | 0 sim/testsuite/{sim => }/arm/rsb.cgs | 0 sim/testsuite/{sim => }/arm/rsc.cgs | 0 sim/testsuite/{sim => }/arm/sbc.cgs | 0 sim/testsuite/{sim => }/arm/smlal.cgs | 0 sim/testsuite/{sim => }/arm/smull.cgs | 0 sim/testsuite/{sim => }/arm/stm.cgs | 0 sim/testsuite/{sim => }/arm/str.cgs | 0 sim/testsuite/{sim => }/arm/strb.cgs | 0 sim/testsuite/{sim => }/arm/strh.cgs | 0 sim/testsuite/{sim => }/arm/sub.cgs | 0 sim/testsuite/{sim => }/arm/swi.cgs | 0 sim/testsuite/{sim => }/arm/swp.cgs | 0 sim/testsuite/{sim => }/arm/swpb.cgs | 0 sim/testsuite/{sim => }/arm/teq.cgs | 0 sim/testsuite/{sim => }/arm/testutils.inc | 0 sim/testsuite/{sim => }/arm/thumb/adc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add-hd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add-hd-rs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add-rd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add-sp.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add.cgs | 0 sim/testsuite/{sim => }/arm/thumb/addi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/addi8.cgs | 0 sim/testsuite/{sim => }/arm/thumb/allthumb.exp | 0 sim/testsuite/{sim => }/arm/thumb/and.cgs | 0 sim/testsuite/{sim => }/arm/thumb/asr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/b.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bcc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bcs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/beq.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bge.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bgt.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bhi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bic.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bl-hi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bl-lo.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ble.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bls.cgs | 0 sim/testsuite/{sim => }/arm/thumb/blt.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bmi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bne.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bpl.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bvc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bvs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bx-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bx-rs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmn.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmp-hd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmp-hd-rs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmp-rd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmp.cgs | 0 sim/testsuite/{sim => }/arm/thumb/eor.cgs | 0 sim/testsuite/{sim => }/arm/thumb/lda-pc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/lda-sp.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldmia.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldr-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldr-pc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldr-sprel.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldrb-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldrb.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldrh-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldrh.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldsb.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldsh.cgs | 0 sim/testsuite/{sim => }/arm/thumb/lsl.cgs | 0 sim/testsuite/{sim => }/arm/thumb/lsr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mov-hd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mov-hd-rs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mov-rd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mov.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mul.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mvn.cgs | 0 sim/testsuite/{sim => }/arm/thumb/neg.cgs | 0 sim/testsuite/{sim => }/arm/thumb/orr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/pop-pc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/pop.cgs | 0 sim/testsuite/{sim => }/arm/thumb/push-lr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/push.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ror.cgs | 0 sim/testsuite/{sim => }/arm/thumb/sbc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/stmia.cgs | 0 sim/testsuite/{sim => }/arm/thumb/str-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/str-sprel.cgs | 0 sim/testsuite/{sim => }/arm/thumb/str.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strb-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strb.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strh-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strh.cgs | 0 sim/testsuite/{sim => }/arm/thumb/sub-sp.cgs | 0 sim/testsuite/{sim => }/arm/thumb/sub.cgs | 0 sim/testsuite/{sim => }/arm/thumb/subi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/subi8.cgs | 0 sim/testsuite/{sim => }/arm/thumb/swi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/testutils.inc | 0 sim/testsuite/{sim => }/arm/thumb/tst.cgs | 0 sim/testsuite/{sim => }/arm/tst.cgs | 0 sim/testsuite/{sim => }/arm/umlal.cgs | 0 sim/testsuite/{sim => }/arm/umull.cgs | 0 sim/testsuite/{sim => }/arm/xscale/blx.cgs | 0 sim/testsuite/{sim => }/arm/xscale/mia.cgs | 0 sim/testsuite/{sim => }/arm/xscale/miaph.cgs | 0 sim/testsuite/{sim => }/arm/xscale/miaxy.cgs | 0 sim/testsuite/{sim => }/arm/xscale/mra.cgs | 0 sim/testsuite/{sim => }/arm/xscale/testutils.inc | 0 sim/testsuite/{sim => }/arm/xscale/xscale.exp | 0 sim/testsuite/{sim => }/avr/ChangeLog | 0 sim/testsuite/{sim => }/avr/allinsn.exp | 0 sim/testsuite/{sim => }/avr/pass.s | 0 sim/testsuite/{sim => }/avr/testutils.inc | 0 sim/testsuite/{sim => }/bfin/.gitignore | 0 sim/testsuite/{sim => }/bfin/10272_small.s | 0 sim/testsuite/{sim => }/bfin/10436.s | 0 sim/testsuite/{sim => }/bfin/10622.s | 0 sim/testsuite/{sim => }/bfin/10742.s | 0 sim/testsuite/{sim => }/bfin/10799.s | 0 sim/testsuite/{sim => }/bfin/11080.s | 0 sim/testsuite/{sim => }/bfin/7641.s | 0 sim/testsuite/{sim => }/bfin/ChangeLog | 0 sim/testsuite/{sim => }/bfin/PN_generator.s | 0 sim/testsuite/{sim => }/bfin/a0.s | 0 sim/testsuite/{sim => }/bfin/a0shift.S | 0 sim/testsuite/{sim => }/bfin/a1.s | 0 sim/testsuite/{sim => }/bfin/a10.s | 0 sim/testsuite/{sim => }/bfin/a11.S | 0 sim/testsuite/{sim => }/bfin/a12.s | 0 sim/testsuite/{sim => }/bfin/a2.s | 0 sim/testsuite/{sim => }/bfin/a20.S | 0 sim/testsuite/{sim => }/bfin/a21.s | 0 sim/testsuite/{sim => }/bfin/a22.s | 0 sim/testsuite/{sim => }/bfin/a23.s | 0 sim/testsuite/{sim => }/bfin/a24.s | 0 sim/testsuite/{sim => }/bfin/a25.s | 0 sim/testsuite/{sim => }/bfin/a26.s | 0 sim/testsuite/{sim => }/bfin/a3.s | 0 sim/testsuite/{sim => }/bfin/a30.s | 0 sim/testsuite/{sim => }/bfin/a4.s | 0 sim/testsuite/{sim => }/bfin/a5.s | 0 sim/testsuite/{sim => }/bfin/a6.s | 0 sim/testsuite/{sim => }/bfin/a7.s | 0 sim/testsuite/{sim => }/bfin/a8.s | 0 sim/testsuite/{sim => }/bfin/a9.s | 0 sim/testsuite/{sim => }/bfin/abs-2.S | 0 sim/testsuite/{sim => }/bfin/abs-3.S | 0 sim/testsuite/{sim => }/bfin/abs-4.S | 0 sim/testsuite/{sim => }/bfin/abs.S | 0 sim/testsuite/{sim => }/bfin/abs_acc.s | 0 sim/testsuite/{sim => }/bfin/acc-rot.s | 0 sim/testsuite/{sim => }/bfin/acp5_19.s | 0 sim/testsuite/{sim => }/bfin/acp5_4.s | 0 sim/testsuite/{sim => }/bfin/add_imm7.s | 0 sim/testsuite/{sim => }/bfin/add_shift.S | 0 sim/testsuite/{sim => }/bfin/add_sub_acc.s | 0 sim/testsuite/{sim => }/bfin/addsub_flags.S | 0 sim/testsuite/{sim => }/bfin/algnbug1.s | 0 sim/testsuite/{sim => }/bfin/algnbug2.s | 0 sim/testsuite/{sim => }/bfin/allinsn.exp | 0 sim/testsuite/{sim => }/bfin/argc.c | 0 sim/testsuite/{sim => }/bfin/ashift.s | 0 sim/testsuite/{sim => }/bfin/ashift_flags.s | 0 sim/testsuite/{sim => }/bfin/ashift_left.s | 0 sim/testsuite/{sim => }/bfin/b0.S | 0 sim/testsuite/{sim => }/bfin/b1.s | 0 sim/testsuite/{sim => }/bfin/b2.S | 0 sim/testsuite/{sim => }/bfin/brcc.s | 0 sim/testsuite/{sim => }/bfin/brevadd.s | 0 sim/testsuite/{sim => }/bfin/byteop16m.s | 0 sim/testsuite/{sim => }/bfin/byteop16p.s | 0 sim/testsuite/{sim => }/bfin/byteop1p.s | 0 sim/testsuite/{sim => }/bfin/byteop2p.s | 0 sim/testsuite/{sim => }/bfin/byteop3p.s | 0 sim/testsuite/{sim => }/bfin/byteunpack.s | 0 .../{sim => }/bfin/c_alu2op_arith_r_sft.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_b.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_h.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_mix.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_neg.s | 0 .../{sim => }/bfin/c_alu2op_conv_toggle.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_xb.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_xh.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_divq.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_divs.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_log_l_sft.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_log_r_sft.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_shadd_1.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_shadd_2.s | 0 sim/testsuite/{sim => }/bfin/c_br_preg_killed_ac.s | 0 .../{sim => }/bfin/c_br_preg_killed_ex1.s | 0 sim/testsuite/{sim => }/bfin/c_br_preg_stall_ac.s | 0 sim/testsuite/{sim => }/bfin/c_br_preg_stall_ex1.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_bp1.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_bp2.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_bp3.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_bp4.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_bp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_bp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_nbp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_fbkwd.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_nbp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brt_bp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brt_nbp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_kills_dhits.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_kills_dmiss.s | 0 sim/testsuite/{sim => }/bfin/c_cactrl_iflush_pr.s | 0 .../{sim => }/bfin/c_cactrl_iflush_pr_pp.s | 0 sim/testsuite/{sim => }/bfin/c_calla_ljump.s | 0 sim/testsuite/{sim => }/bfin/c_calla_subr.s | 0 sim/testsuite/{sim => }/bfin/c_cc2dreg.s | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_ac.S | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_an.s | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_aq.s | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av0.S | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av1.S | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_az.s | 0 .../{sim => }/bfin/c_cc_flag_ccmv_depend.S | 0 .../{sim => }/bfin/c_cc_flagdreg_mvbrsft.s | 0 .../{sim => }/bfin/c_cc_flagdreg_mvbrsft_s1.s | 0 .../{sim => }/bfin/c_cc_flagdreg_mvbrsft_sn.s | 0 .../{sim => }/bfin/c_cc_regmvlogi_mvbrsft.s | 0 .../{sim => }/bfin/c_cc_regmvlogi_mvbrsft_s1.s | 0 .../{sim => }/bfin/c_cc_regmvlogi_mvbrsft_sn.S | 0 sim/testsuite/{sim => }/bfin/c_ccflag_a0a1.S | 0 sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr_uu.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3_uu.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3_uu.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr_uu.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_cc_pr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_ncc_pr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_comp3op_dr_and_dr.s | 0 .../{sim => }/bfin/c_comp3op_dr_minus_dr.s | 0 sim/testsuite/{sim => }/bfin/c_comp3op_dr_mix.s | 0 sim/testsuite/{sim => }/bfin/c_comp3op_dr_or_dr.s | 0 .../{sim => }/bfin/c_comp3op_dr_plus_dr.s | 0 sim/testsuite/{sim => }/bfin/c_comp3op_dr_xor_dr.s | 0 .../{sim => }/bfin/c_comp3op_pr_plus_pr_sh1.s | 0 .../{sim => }/bfin/c_comp3op_pr_plus_pr_sh2.s | 0 .../{sim => }/bfin/c_compi2opd_dr_add_i7_n.s | 0 .../{sim => }/bfin/c_compi2opd_dr_add_i7_p.s | 0 .../{sim => }/bfin/c_compi2opd_dr_eq_i7_n.s | 0 .../{sim => }/bfin/c_compi2opd_dr_eq_i7_p.s | 0 sim/testsuite/{sim => }/bfin/c_compi2opd_flags.S | 0 sim/testsuite/{sim => }/bfin/c_compi2opd_flags_2.S | 0 .../{sim => }/bfin/c_compi2opp_pr_add_i7_n.s | 0 .../{sim => }/bfin/c_compi2opp_pr_add_i7_p.s | 0 .../{sim => }/bfin/c_compi2opp_pr_eq_i7_n.s | 0 .../{sim => }/bfin/c_compi2opp_pr_eq_i7_p.s | 0 .../{sim => }/bfin/c_dagmodik_lnz_imgebl.s | 0 .../{sim => }/bfin/c_dagmodik_lnz_imltbl.s | 0 .../{sim => }/bfin/c_dagmodik_lz_inc_dec.s | 0 .../{sim => }/bfin/c_dagmodim_lnz_imgebl.s | 0 .../{sim => }/bfin/c_dagmodim_lnz_imltbl.s | 0 .../{sim => }/bfin/c_dagmodim_lz_inc_dec.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_a0_pm_a1.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_a0a1s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_a_abs_a.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_a_neg_a.s | 0 .../{sim => }/bfin/c_dsp32alu_aa_absabs.s | 0 .../{sim => }/bfin/c_dsp32alu_aa_negneg.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_abs.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_absabs.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_alhwx.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_awx.s | 0 .../{sim => }/bfin/c_dsp32alu_byteop1ew.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop2.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop3.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_bytepack.s | 0 .../{sim => }/bfin/c_dsp32alu_byteunpack.s | 0 .../{sim => }/bfin/c_dsp32alu_disalnexcpt.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_max.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_maxmax.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_min.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_minmin.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_mix.s | 0 .../{sim => }/bfin/c_dsp32alu_r_lh_a0pa1.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_r_negneg.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_p.s | 0 .../{sim => }/bfin/c_dsp32alu_rh_rnd12_m.s | 0 .../{sim => }/bfin/c_dsp32alu_rh_rnd12_p.s | 0 .../{sim => }/bfin/c_dsp32alu_rh_rnd20_m.s | 0 .../{sim => }/bfin/c_dsp32alu_rh_rnd20_p.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_p.s | 0 .../{sim => }/bfin/c_dsp32alu_rl_rnd12_m.s | 0 .../{sim => }/bfin/c_dsp32alu_rl_rnd12_p.s | 0 .../{sim => }/bfin/c_dsp32alu_rl_rnd20_m.s | 0 .../{sim => }/bfin/c_dsp32alu_rl_rnd20_p.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rlh_rnd.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rm.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rmm.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rmp.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rp.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rpm.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rpp.s | 0 .../{sim => }/bfin/c_dsp32alu_rr_lph_a1a0.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm_aa.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp.s | 0 .../{sim => }/bfin/c_dsp32alu_rrpmmp_sft.s | 0 .../{sim => }/bfin/c_dsp32alu_rrpmmp_sft_x.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm.s | 0 .../{sim => }/bfin/c_dsp32alu_rrppmm_sft.s | 0 .../{sim => }/bfin/c_dsp32alu_rrppmm_sft_x.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_saa.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_sat_aa.S | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_search.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_sgn.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0.s | 0 .../{sim => }/bfin/c_dsp32mac_a1a0_iuw32.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_i.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_ih.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_is.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_iu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_t.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_tu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_i.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_ih.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_is.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_iu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_t.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_tu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0.s | 0 .../{sim => }/bfin/c_dsp32mac_dr_a1a0_iutsh.s | 0 .../{sim => }/bfin/c_dsp32mac_dr_a1a0_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_mix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a0_i.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a0_is.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a0_m.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a0_s.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a0_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1_i.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1_is.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1_m.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1_s.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1_u.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0_i.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0_is.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0_m.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0_s.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_mix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_i.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_ih.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_is.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_iu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_i.s | 0 .../{sim => }/bfin/c_dsp32mult_dr_m_iutsh.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_t.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_mix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_t.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_tu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_i.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_is.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m.s | 0 .../{sim => }/bfin/c_dsp32mult_pair_m_i.s | 0 .../{sim => }/bfin/c_dsp32mult_pair_m_is.s | 0 .../{sim => }/bfin/c_dsp32mult_pair_m_s.s | 0 .../{sim => }/bfin/c_dsp32mult_pair_m_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_a0alr.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_af.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_af_s.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_ln.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_ln_s.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_lp.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_lp_s.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_rn.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_rn_s.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_rp.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_rp_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh_s.s | 0 .../{sim => }/bfin/c_dsp32shift_align16.s | 0 .../{sim => }/bfin/c_dsp32shift_align24.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_align8.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_amix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_bitmux.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_bxor.s | 0 .../{sim => }/bfin/c_dsp32shift_expadj_h.s | 0 .../{sim => }/bfin/c_dsp32shift_expadj_l.s | 0 .../{sim => }/bfin/c_dsp32shift_expadj_r.s | 0 .../{sim => }/bfin/c_dsp32shift_expexp_r.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_fdepx.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_fextx.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_lf.s | 0 .../{sim => }/bfin/c_dsp32shift_lhalf_ln.s | 0 .../{sim => }/bfin/c_dsp32shift_lhalf_lp.s | 0 .../{sim => }/bfin/c_dsp32shift_lhalf_rn.s | 0 .../{sim => }/bfin/c_dsp32shift_lhalf_rp.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_lhh.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_lmix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_ones.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_pack.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_rot.s | 0 .../{sim => }/bfin/c_dsp32shift_rot_mix.s | 0 .../{sim => }/bfin/c_dsp32shift_signbits_r.s | 0 .../{sim => }/bfin/c_dsp32shift_signbits_rh.s | 0 .../{sim => }/bfin/c_dsp32shift_signbits_rl.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_vmax.s | 0 .../{sim => }/bfin/c_dsp32shift_vmaxvmax.s | 0 .../{sim => }/bfin/c_dsp32shiftim_a0alr.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af_s.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_ln.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_ln_s.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_lp.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_lp_s.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_rn.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_rn_s.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_rp.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_rp_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahh_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_amix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lf.s | 0 .../{sim => }/bfin/c_dsp32shiftim_lhalf_ln.s | 0 .../{sim => }/bfin/c_dsp32shiftim_lhalf_lp.s | 0 .../{sim => }/bfin/c_dsp32shiftim_lhalf_rn.s | 0 .../{sim => }/bfin/c_dsp32shiftim_lhalf_rp.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhh.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lmix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_rot.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_i.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ipp.s | 0 .../{sim => }/bfin/c_dspldst_ld_dr_ippm.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_i.s | 0 .../{sim => }/bfin/c_dspldst_ld_drhi_ipp.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_i.s | 0 .../{sim => }/bfin/c_dspldst_ld_drlo_ipp.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_i.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ipp.s | 0 .../{sim => }/bfin/c_dspldst_st_dr_ippm.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_i.s | 0 .../{sim => }/bfin/c_dspldst_st_drhi_ipp.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_i.s | 0 .../{sim => }/bfin/c_dspldst_st_drlo_ipp.s | 0 sim/testsuite/{sim => }/bfin/c_except_illopcode.S | 0 sim/testsuite/{sim => }/bfin/c_except_sys_sstep.S | 0 sim/testsuite/{sim => }/bfin/c_except_user_mode.S | 0 sim/testsuite/{sim => }/bfin/c_interr_disable.S | 0 .../{sim => }/bfin/c_interr_disable_enable.S | 0 sim/testsuite/{sim => }/bfin/c_interr_excpt.S | 0 .../{sim => }/bfin/c_interr_loopsetup_stld.S | 0 sim/testsuite/{sim => }/bfin/c_interr_nested.S | 0 sim/testsuite/{sim => }/bfin/c_interr_nmi.S | 0 sim/testsuite/{sim => }/bfin/c_interr_pending.S | 0 sim/testsuite/{sim => }/bfin/c_interr_pending_2.S | 0 sim/testsuite/{sim => }/bfin/c_interr_timer.S | 0 .../{sim => }/bfin/c_interr_timer_reload.S | 0 .../{sim => }/bfin/c_interr_timer_tcount.S | 0 .../{sim => }/bfin/c_interr_timer_tscale.S | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_drhi.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_drlo.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_ibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_ibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_ibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_dr.s | 0 .../{sim => }/bfin/c_ldimmhalf_lzhi_ibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_pibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xb.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xb.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xh.s | 0 .../{sim => }/bfin/c_ldst_ld_d_p_ppmm_hbx.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xb.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_mm.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_pp.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_p.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_mm.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_pp.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xb.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_st_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_ld_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_ld_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_st_dr_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_st_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_st_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstiifp_st_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstiifp_st_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_hi.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_lo.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_h_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_lohi.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_hi.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_lo.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_st_lohi.s | 0 sim/testsuite/{sim => }/bfin/c_linkage.s | 0 .../{sim => }/bfin/c_logi2op_alshft_mix.s | 0 .../{sim => }/bfin/c_logi2op_arith_shft.s | 0 sim/testsuite/{sim => }/bfin/c_logi2op_bitclr.s | 0 sim/testsuite/{sim => }/bfin/c_logi2op_bitset.s | 0 sim/testsuite/{sim => }/bfin/c_logi2op_bittgl.s | 0 sim/testsuite/{sim => }/bfin/c_logi2op_bittst.s | 0 .../{sim => }/bfin/c_logi2op_log_l_shft.s | 0 .../{sim => }/bfin/c_logi2op_log_l_shft_astat.S | 0 .../{sim => }/bfin/c_logi2op_log_r_shft.s | 0 .../{sim => }/bfin/c_logi2op_log_r_shft_astat.S | 0 sim/testsuite/{sim => }/bfin/c_logi2op_nbittst.s | 0 sim/testsuite/{sim => }/bfin/c_loopsetup_nested.s | 0 .../{sim => }/bfin/c_loopsetup_nested_bot.s | 0 .../{sim => }/bfin/c_loopsetup_nested_prelc.s | 0 .../{sim => }/bfin/c_loopsetup_nested_top.s | 0 sim/testsuite/{sim => }/bfin/c_loopsetup_overlap.s | 0 .../{sim => }/bfin/c_loopsetup_preg_div2_lc0.s | 0 .../{sim => }/bfin/c_loopsetup_preg_div2_lc1.s | 0 .../{sim => }/bfin/c_loopsetup_preg_lc0.s | 0 .../{sim => }/bfin/c_loopsetup_preg_lc1.s | 0 .../{sim => }/bfin/c_loopsetup_preg_stld.s | 0 sim/testsuite/{sim => }/bfin/c_loopsetup_prelc.s | 0 .../{sim => }/bfin/c_loopsetup_topbotcntr.s | 0 sim/testsuite/{sim => }/bfin/c_mmr_interr_ctl.s | 0 sim/testsuite/{sim => }/bfin/c_mmr_loop.S | 0 .../{sim => }/bfin/c_mmr_loop_user_except.S | 0 .../{sim => }/bfin/c_mmr_ppop_illegal_adr.S | 0 .../{sim => }/bfin/c_mmr_ppopm_illegal_adr.S | 0 sim/testsuite/{sim => }/bfin/c_mmr_timer.S | 0 sim/testsuite/{sim => }/bfin/c_mode_supervisor.S | 0 sim/testsuite/{sim => }/bfin/c_mode_user.S | 0 .../{sim => }/bfin/c_mode_user_superivsor.S | 0 .../{sim => }/bfin/c_multi_issue_dsp_ld_ld.s | 0 .../{sim => }/bfin/c_multi_issue_dsp_ldst_1.s | 0 .../{sim => }/bfin/c_multi_issue_dsp_ldst_2.s | 0 .../{sim => }/bfin/c_progctrl_call_pcpr.s | 0 sim/testsuite/{sim => }/bfin/c_progctrl_call_pr.s | 0 .../{sim => }/bfin/c_progctrl_clisti_interr.S | 0 .../{sim => }/bfin/c_progctrl_csync_mmr.S | 0 .../{sim => }/bfin/c_progctrl_except_rtx.S | 0 sim/testsuite/{sim => }/bfin/c_progctrl_excpt.S | 0 .../{sim => }/bfin/c_progctrl_jump_pcpr.s | 0 sim/testsuite/{sim => }/bfin/c_progctrl_jump_pr.s | 0 sim/testsuite/{sim => }/bfin/c_progctrl_nop.s | 0 .../{sim => }/bfin/c_progctrl_raise_rt_i_n.S | 0 sim/testsuite/{sim => }/bfin/c_progctrl_rts.s | 0 sim/testsuite/{sim => }/bfin/c_ptr2op_pr_neg_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ptr2op_pr_sft_2_1.s | 0 .../{sim => }/bfin/c_ptr2op_pr_shadd_1_2.s | 0 .../{sim => }/bfin/c_pushpopmultiple_dp.s | 0 .../{sim => }/bfin/c_pushpopmultiple_dp_pair.s | 0 .../{sim => }/bfin/c_pushpopmultiple_dreg.s | 0 .../{sim => }/bfin/c_pushpopmultiple_preg.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_acc_acc.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_dag_lz_dep.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_dr_acc_acc.s | 0 .../{sim => }/bfin/c_regmv_dr_dep_nostall.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_dr_dr.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_dr_imlb.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_dr_pr.s | 0 .../{sim => }/bfin/c_regmv_imlb_dep_nostall.s | 0 .../{sim => }/bfin/c_regmv_imlb_dep_stall.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_imlb_dr.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_imlb_imlb.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_imlb_pr.s | 0 .../{sim => }/bfin/c_regmv_pr_dep_nostall.s | 0 .../{sim => }/bfin/c_regmv_pr_dep_stall.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_pr_dr.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_pr_imlb.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_pr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_seq_ac_raise_mv.S | 0 .../{sim => }/bfin/c_seq_ac_raise_mv_ppop.S | 0 .../{sim => }/bfin/c_seq_ac_regmv_pushpop.S | 0 .../{sim => }/bfin/c_seq_dec_raise_pushpop.S | 0 .../{sim => }/bfin/c_seq_ex1_brcc_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex1_call_mv_pop.S | 0 sim/testsuite/{sim => }/bfin/c_seq_ex1_j_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex1_raise_brcc_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex1_raise_call_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex1_raise_j_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex2_brcc_mp_mv_pop.S | 0 sim/testsuite/{sim => }/bfin/c_seq_ex2_mmr_mvpop.S | 0 .../{sim => }/bfin/c_seq_ex2_mmrj_mvpop.S | 0 .../{sim => }/bfin/c_seq_ex2_raise_mmr_mvpop.S | 0 .../{sim => }/bfin/c_seq_ex2_raise_mmrj_mvpop.S | 0 .../{sim => }/bfin/c_seq_ex3_ls_brcc_mvp.S | 0 .../{sim => }/bfin/c_seq_ex3_ls_mmr_mvp.S | 0 .../{sim => }/bfin/c_seq_ex3_ls_mmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_cs_lsmmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_rti_lsmmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_rtn_lsmmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_rtx_lsmmrj_mvp.S | 0 sim/testsuite/{sim => }/bfin/c_ujump.s | 0 sim/testsuite/{sim => }/bfin/cc-alu.S | 0 sim/testsuite/{sim => }/bfin/cc-astat-bits.s | 0 sim/testsuite/{sim => }/bfin/cc0.s | 0 sim/testsuite/{sim => }/bfin/cc1.s | 0 sim/testsuite/{sim => }/bfin/cc5.S | 0 sim/testsuite/{sim => }/bfin/cec-exact-exception.S | 0 sim/testsuite/{sim => }/bfin/cec-ifetch.S | 0 sim/testsuite/{sim => }/bfin/cec-multi-pending.S | 0 sim/testsuite/{sim => }/bfin/cec-no-snen-reti.S | 0 .../{sim => }/bfin/cec-non-operating-env.s | 0 sim/testsuite/{sim => }/bfin/cec-raise-reti.S | 0 sim/testsuite/{sim => }/bfin/cec-snen-reti.S | 0 sim/testsuite/{sim => }/bfin/cec-syscfg-ssstep.S | 0 sim/testsuite/{sim => }/bfin/cec-system-call.S | 0 sim/testsuite/{sim => }/bfin/cir.s | 0 sim/testsuite/{sim => }/bfin/cir1.s | 0 sim/testsuite/{sim => }/bfin/cli-sti.s | 0 sim/testsuite/{sim => }/bfin/cmpacc.s | 0 sim/testsuite/{sim => }/bfin/cmpdreg.S | 0 sim/testsuite/{sim => }/bfin/compare.s | 0 sim/testsuite/{sim => }/bfin/conv_enc_gen.s | 0 sim/testsuite/{sim => }/bfin/cycles.s | 0 sim/testsuite/{sim => }/bfin/d0.s | 0 sim/testsuite/{sim => }/bfin/d1.s | 0 sim/testsuite/{sim => }/bfin/d2.s | 0 .../{sim => }/bfin/dbg_brprd_ntkn_src_kill.S | 0 .../{sim => }/bfin/dbg_brtkn_nprd_src_kill.S | 0 sim/testsuite/{sim => }/bfin/dbg_jmp_src_kill.S | 0 sim/testsuite/{sim => }/bfin/dbg_tr_basic.S | 0 sim/testsuite/{sim => }/bfin/dbg_tr_simplejp.S | 0 sim/testsuite/{sim => }/bfin/dbg_tr_tbuf0.S | 0 sim/testsuite/{sim => }/bfin/dbg_tr_umode.S | 0 .../{sim => }/bfin/disalnexcpt_implicit.S | 0 sim/testsuite/{sim => }/bfin/div0.s | 0 sim/testsuite/{sim => }/bfin/divq.s | 0 sim/testsuite/{sim => }/bfin/dotproduct.s | 0 sim/testsuite/{sim => }/bfin/dotproduct2.s | 0 sim/testsuite/{sim => }/bfin/double_prec_mult.s | 0 sim/testsuite/{sim => }/bfin/dsp_a4.s | 0 sim/testsuite/{sim => }/bfin/dsp_a7.s | 0 sim/testsuite/{sim => }/bfin/dsp_a8.s | 0 sim/testsuite/{sim => }/bfin/dsp_d0.s | 0 sim/testsuite/{sim => }/bfin/dsp_d1.s | 0 sim/testsuite/{sim => }/bfin/dsp_neg.S | 0 sim/testsuite/{sim => }/bfin/dsp_s1.s | 0 sim/testsuite/{sim => }/bfin/e0.s | 0 sim/testsuite/{sim => }/bfin/edn_snafu.s | 0 sim/testsuite/{sim => }/bfin/eu_dsp32mac_s.s | 0 sim/testsuite/{sim => }/bfin/events.s | 0 sim/testsuite/{sim => }/bfin/f221.s | 0 sim/testsuite/{sim => }/bfin/fact.s | 0 sim/testsuite/{sim => }/bfin/fir.s | 0 sim/testsuite/{sim => }/bfin/fsm.s | 0 sim/testsuite/{sim => }/bfin/greg2.s | 0 sim/testsuite/{sim => }/bfin/hwloop-bits.S | 0 sim/testsuite/{sim => }/bfin/hwloop-branch-in.s | 0 sim/testsuite/{sim => }/bfin/hwloop-branch-out.s | 0 sim/testsuite/{sim => }/bfin/hwloop-lt-bits.s | 0 sim/testsuite/{sim => }/bfin/hwloop-nested.s | 0 sim/testsuite/{sim => }/bfin/i0.s | 0 sim/testsuite/{sim => }/bfin/iir.s | 0 sim/testsuite/{sim => }/bfin/issue103.s | 0 sim/testsuite/{sim => }/bfin/issue109.s | 0 sim/testsuite/{sim => }/bfin/issue112.s | 0 sim/testsuite/{sim => }/bfin/issue113.s | 0 sim/testsuite/{sim => }/bfin/issue117.s | 0 sim/testsuite/{sim => }/bfin/issue118.s | 0 sim/testsuite/{sim => }/bfin/issue119.s | 0 sim/testsuite/{sim => }/bfin/issue121.s | 0 sim/testsuite/{sim => }/bfin/issue123.s | 0 sim/testsuite/{sim => }/bfin/issue124.s | 0 sim/testsuite/{sim => }/bfin/issue125.s | 0 sim/testsuite/{sim => }/bfin/issue126.s | 0 sim/testsuite/{sim => }/bfin/issue127.s | 0 sim/testsuite/{sim => }/bfin/issue129.s | 0 sim/testsuite/{sim => }/bfin/issue139.S | 0 sim/testsuite/{sim => }/bfin/issue140.S | 0 sim/testsuite/{sim => }/bfin/issue142.s | 0 sim/testsuite/{sim => }/bfin/issue144.s | 0 sim/testsuite/{sim => }/bfin/issue146.S | 0 sim/testsuite/{sim => }/bfin/issue175.s | 0 sim/testsuite/{sim => }/bfin/issue205.s | 0 sim/testsuite/{sim => }/bfin/issue257.s | 0 sim/testsuite/{sim => }/bfin/issue272.S | 0 sim/testsuite/{sim => }/bfin/issue83.s | 0 sim/testsuite/{sim => }/bfin/issue89.s | 0 sim/testsuite/{sim => }/bfin/l0.s | 0 sim/testsuite/{sim => }/bfin/l0shift.s | 0 sim/testsuite/{sim => }/bfin/l2_loop.s | 0 sim/testsuite/{sim => }/bfin/link-2.s | 0 sim/testsuite/{sim => }/bfin/link.s | 0 sim/testsuite/{sim => }/bfin/lmu_cplb_multiple0.S | 0 sim/testsuite/{sim => }/bfin/lmu_cplb_multiple1.S | 0 sim/testsuite/{sim => }/bfin/lmu_excpt_align.S | 0 sim/testsuite/{sim => }/bfin/lmu_excpt_default.S | 0 sim/testsuite/{sim => }/bfin/lmu_excpt_illaddr.S | 0 sim/testsuite/{sim => }/bfin/lmu_excpt_prot0.S | 0 sim/testsuite/{sim => }/bfin/lmu_excpt_prot1.S | 0 sim/testsuite/{sim => }/bfin/load.s | 0 sim/testsuite/{sim => }/bfin/logic.s | 0 sim/testsuite/{sim => }/bfin/loop_snafu.s | 0 sim/testsuite/{sim => }/bfin/loop_strncpy.s | 0 sim/testsuite/{sim => }/bfin/lp0.s | 0 sim/testsuite/{sim => }/bfin/lp1.s | 0 sim/testsuite/{sim => }/bfin/lsetup.s | 0 sim/testsuite/{sim => }/bfin/m0boundary.s | 0 sim/testsuite/{sim => }/bfin/m1.S | 0 sim/testsuite/{sim => }/bfin/m10.s | 0 sim/testsuite/{sim => }/bfin/m11.s | 0 sim/testsuite/{sim => }/bfin/m12.s | 0 sim/testsuite/{sim => }/bfin/m13.s | 0 sim/testsuite/{sim => }/bfin/m14.s | 0 sim/testsuite/{sim => }/bfin/m15.s | 0 sim/testsuite/{sim => }/bfin/m16.s | 0 sim/testsuite/{sim => }/bfin/m17.s | 0 sim/testsuite/{sim => }/bfin/m2.s | 0 sim/testsuite/{sim => }/bfin/m3.s | 0 sim/testsuite/{sim => }/bfin/m4.s | 0 sim/testsuite/{sim => }/bfin/m5.s | 0 sim/testsuite/{sim => }/bfin/m6.s | 0 sim/testsuite/{sim => }/bfin/m7.s | 0 sim/testsuite/{sim => }/bfin/m8.s | 0 sim/testsuite/{sim => }/bfin/m9.s | 0 sim/testsuite/{sim => }/bfin/mac2halfreg.S | 0 sim/testsuite/{sim => }/bfin/math.s | 0 sim/testsuite/{sim => }/bfin/max_min_flags.s | 0 sim/testsuite/{sim => }/bfin/mc_s2.s | 0 .../{sim => }/bfin/mdma-32bit-1d-neg-count.c | 0 sim/testsuite/{sim => }/bfin/mdma-32bit-1d.c | 0 .../{sim => }/bfin/mdma-8bit-1d-neg-count.c | 0 sim/testsuite/{sim => }/bfin/mdma-8bit-1d.c | 0 sim/testsuite/{sim => }/bfin/mdma-skel.h | 0 sim/testsuite/{sim => }/bfin/mem3.s | 0 sim/testsuite/{sim => }/bfin/mmr-exception.s | 0 sim/testsuite/{sim => }/bfin/move.s | 0 sim/testsuite/{sim => }/bfin/msa_acp_5.10.S | 0 sim/testsuite/{sim => }/bfin/msa_acp_5.12_1.S | 0 sim/testsuite/{sim => }/bfin/msa_acp_5.12_2.S | 0 sim/testsuite/{sim => }/bfin/msa_acp_5_10.s | 0 sim/testsuite/{sim => }/bfin/mult.s | 0 sim/testsuite/{sim => }/bfin/neg-2.S | 0 sim/testsuite/{sim => }/bfin/neg-3.S | 0 sim/testsuite/{sim => }/bfin/neg.S | 0 sim/testsuite/{sim => }/bfin/nshift.s | 0 sim/testsuite/{sim => }/bfin/pr.s | 0 sim/testsuite/{sim => }/bfin/push-pop-multiple.s | 0 sim/testsuite/{sim => }/bfin/push-pop.s | 0 sim/testsuite/{sim => }/bfin/pushpopreg_1.s | 0 sim/testsuite/{sim => }/bfin/quadaddsub.s | 0 sim/testsuite/{sim => }/bfin/random_0001.s | 0 sim/testsuite/{sim => }/bfin/random_0002.S | 0 sim/testsuite/{sim => }/bfin/random_0003.S | 0 sim/testsuite/{sim => }/bfin/random_0004.S | 0 sim/testsuite/{sim => }/bfin/random_0005.S | 0 sim/testsuite/{sim => }/bfin/random_0006.S | 0 sim/testsuite/{sim => }/bfin/random_0007.S | 0 sim/testsuite/{sim => }/bfin/random_0008.S | 0 sim/testsuite/{sim => }/bfin/random_0009.S | 0 sim/testsuite/{sim => }/bfin/random_0010.S | 0 sim/testsuite/{sim => }/bfin/random_0011.S | 0 sim/testsuite/{sim => }/bfin/random_0012.S | 0 sim/testsuite/{sim => }/bfin/random_0013.S | 0 sim/testsuite/{sim => }/bfin/random_0014.S | 0 sim/testsuite/{sim => }/bfin/random_0015.S | 0 sim/testsuite/{sim => }/bfin/random_0016.S | 0 sim/testsuite/{sim => }/bfin/random_0017.S | 0 sim/testsuite/{sim => }/bfin/random_0018.S | 0 sim/testsuite/{sim => }/bfin/random_0019.S | 0 sim/testsuite/{sim => }/bfin/random_0020.S | 0 sim/testsuite/{sim => }/bfin/random_0021.S | 0 sim/testsuite/{sim => }/bfin/random_0022.S | 0 sim/testsuite/{sim => }/bfin/random_0023.S | 0 sim/testsuite/{sim => }/bfin/random_0024.S | 0 sim/testsuite/{sim => }/bfin/random_0025.S | 0 sim/testsuite/{sim => }/bfin/random_0026.S | 0 sim/testsuite/{sim => }/bfin/random_0027.S | 0 sim/testsuite/{sim => }/bfin/random_0028.S | 0 sim/testsuite/{sim => }/bfin/random_0029.S | 0 sim/testsuite/{sim => }/bfin/random_0030.S | 0 sim/testsuite/{sim => }/bfin/random_0031.S | 0 sim/testsuite/{sim => }/bfin/random_0032.S | 0 sim/testsuite/{sim => }/bfin/random_0033.S | 0 sim/testsuite/{sim => }/bfin/random_0034.S | 0 sim/testsuite/{sim => }/bfin/random_0035.S | 0 sim/testsuite/{sim => }/bfin/random_0036.S | 0 sim/testsuite/{sim => }/bfin/random_0037.S | 0 sim/testsuite/{sim => }/bfin/run-tests.sh | 0 sim/testsuite/{sim => }/bfin/s0.s | 0 sim/testsuite/{sim => }/bfin/s1.s | 0 sim/testsuite/{sim => }/bfin/s10.s | 0 sim/testsuite/{sim => }/bfin/s11.s | 0 sim/testsuite/{sim => }/bfin/s12.s | 0 sim/testsuite/{sim => }/bfin/s13.s | 0 sim/testsuite/{sim => }/bfin/s14.s | 0 sim/testsuite/{sim => }/bfin/s15.s | 0 sim/testsuite/{sim => }/bfin/s16.s | 0 sim/testsuite/{sim => }/bfin/s17.s | 0 sim/testsuite/{sim => }/bfin/s18.s | 0 sim/testsuite/{sim => }/bfin/s19.s | 0 sim/testsuite/{sim => }/bfin/s2.s | 0 sim/testsuite/{sim => }/bfin/s20.s | 0 sim/testsuite/{sim => }/bfin/s21.s | 0 sim/testsuite/{sim => }/bfin/s3.s | 0 sim/testsuite/{sim => }/bfin/s30.s | 0 sim/testsuite/{sim => }/bfin/s4.s | 0 sim/testsuite/{sim => }/bfin/s5.s | 0 sim/testsuite/{sim => }/bfin/s6.s | 0 sim/testsuite/{sim => }/bfin/s7.s | 0 sim/testsuite/{sim => }/bfin/s8.s | 0 sim/testsuite/{sim => }/bfin/s9.s | 0 sim/testsuite/{sim => }/bfin/saatest.s | 0 sim/testsuite/{sim => }/bfin/se_all16bitopcodes.S | 0 sim/testsuite/{sim => }/bfin/se_all32bitopcodes.S | 0 .../{sim => }/bfin/se_all32bitopcodes.lds | 0 .../{sim => }/bfin/se_all64bitg0opcodes.S | 0 .../{sim => }/bfin/se_all64bitg1opcodes.S | 0 .../{sim => }/bfin/se_all64bitg2opcodes.S | 0 sim/testsuite/{sim => }/bfin/se_allopcodes.h | 0 sim/testsuite/{sim => }/bfin/se_brtarget_stall.S | 0 sim/testsuite/{sim => }/bfin/se_bug_ui.S | 0 sim/testsuite/{sim => }/bfin/se_bug_ui2.S | 0 sim/testsuite/{sim => }/bfin/se_bug_ui3.S | 0 sim/testsuite/{sim => }/bfin/se_cc2stat_haz.S | 0 sim/testsuite/{sim => }/bfin/se_cc_kill.S | 0 sim/testsuite/{sim => }/bfin/se_cof.S | 0 sim/testsuite/{sim => }/bfin/se_event_quad.S | 0 .../{sim => }/bfin/se_excpt_dagprotviol.S | 0 sim/testsuite/{sim => }/bfin/se_excpt_ifprotviol.S | 0 sim/testsuite/{sim => }/bfin/se_excpt_ssstep.S | 0 .../{sim => }/bfin/se_illegalcombination.S | 0 sim/testsuite/{sim => }/bfin/se_kill_wbbr.S | 0 sim/testsuite/{sim => }/bfin/se_kills2.S | 0 sim/testsuite/{sim => }/bfin/se_loop_disable.S | 0 sim/testsuite/{sim => }/bfin/se_loop_kill.S | 0 sim/testsuite/{sim => }/bfin/se_loop_kill_01.S | 0 sim/testsuite/{sim => }/bfin/se_loop_kill_dcr.S | 0 sim/testsuite/{sim => }/bfin/se_loop_kill_dcr_01.S | 0 sim/testsuite/{sim => }/bfin/se_loop_lr.S | 0 sim/testsuite/{sim => }/bfin/se_loop_mv2lb_stall.S | 0 sim/testsuite/{sim => }/bfin/se_loop_mv2lc.S | 0 sim/testsuite/{sim => }/bfin/se_loop_mv2lc_stall.S | 0 sim/testsuite/{sim => }/bfin/se_loop_mv2lt_stall.S | 0 sim/testsuite/{sim => }/bfin/se_loop_nest_ppm.S | 0 sim/testsuite/{sim => }/bfin/se_loop_nest_ppm_1.S | 0 sim/testsuite/{sim => }/bfin/se_loop_nest_ppm_2.S | 0 sim/testsuite/{sim => }/bfin/se_loop_ppm.S | 0 sim/testsuite/{sim => }/bfin/se_loop_ppm_1.S | 0 sim/testsuite/{sim => }/bfin/se_loop_ppm_int.S | 0 sim/testsuite/{sim => }/bfin/se_lsetup_kill.S | 0 sim/testsuite/{sim => }/bfin/se_misaligned_fetch.S | 0 sim/testsuite/{sim => }/bfin/se_more_ret_haz.S | 0 sim/testsuite/{sim => }/bfin/se_mv2lp.S | 0 sim/testsuite/{sim => }/bfin/se_oneins_zoff.S | 0 sim/testsuite/{sim => }/bfin/se_popkill.S | 0 sim/testsuite/{sim => }/bfin/se_regmv_usp_sysreg.S | 0 sim/testsuite/{sim => }/bfin/se_rets_hazard.s | 0 sim/testsuite/{sim => }/bfin/se_rts_rti.S | 0 .../{sim => }/bfin/se_ssstep_dagprotviol.S | 0 sim/testsuite/{sim => }/bfin/se_ssync.S | 0 sim/testsuite/{sim => }/bfin/se_stall_if2.S | 0 .../{sim => }/bfin/se_undefinedinstruction1.S | 0 .../{sim => }/bfin/se_undefinedinstruction2.S | 0 .../{sim => }/bfin/se_undefinedinstruction3.S | 0 .../{sim => }/bfin/se_undefinedinstruction4.S | 0 .../{sim => }/bfin/se_usermode_protviol.S | 0 sim/testsuite/{sim => }/bfin/seqstat.s | 0 sim/testsuite/{sim => }/bfin/sign.s | 0 sim/testsuite/{sim => }/bfin/simple0.s | 0 sim/testsuite/{sim => }/bfin/sri.s | 0 sim/testsuite/{sim => }/bfin/stk.s | 0 sim/testsuite/{sim => }/bfin/stk2.s | 0 sim/testsuite/{sim => }/bfin/stk3.s | 0 sim/testsuite/{sim => }/bfin/stk4.s | 0 sim/testsuite/{sim => }/bfin/stk5.s | 0 sim/testsuite/{sim => }/bfin/stk6.s | 0 sim/testsuite/{sim => }/bfin/syscfg.s | 0 sim/testsuite/{sim => }/bfin/tar10622.s | 0 sim/testsuite/{sim => }/bfin/test-dma.h | 0 sim/testsuite/{sim => }/bfin/test.h | 0 sim/testsuite/{sim => }/bfin/testset.s | 0 sim/testsuite/{sim => }/bfin/testset2.s | 0 sim/testsuite/{sim => }/bfin/testutils.inc | 0 sim/testsuite/{sim => }/bfin/unlink.S | 0 sim/testsuite/{sim => }/bfin/up0.s | 0 sim/testsuite/{sim => }/bfin/usp.S | 0 sim/testsuite/{sim => }/bfin/vec-abs-2.S | 0 sim/testsuite/{sim => }/bfin/vec-abs-3.S | 0 sim/testsuite/{sim => }/bfin/vec-abs.S | 0 sim/testsuite/{sim => }/bfin/vec-neg-2.S | 0 sim/testsuite/{sim => }/bfin/vec-neg-3.S | 0 sim/testsuite/{sim => }/bfin/vec-neg.S | 0 sim/testsuite/{sim => }/bfin/vecadd.s | 0 sim/testsuite/{sim => }/bfin/vit_max.s | 0 sim/testsuite/{sim => }/bfin/vit_max2.s | 0 sim/testsuite/{sim => }/bfin/viterbi2.s | 0 sim/testsuite/{sim => }/bfin/wtf.s | 0 sim/testsuite/{sim => }/bfin/x1.s | 0 sim/testsuite/{sim => }/bfin/zcall.s | 0 sim/testsuite/{sim => }/bfin/zeroflagrnd.s | 0 sim/testsuite/{sim => }/bpf/ChangeLog | 0 sim/testsuite/{sim => }/bpf/allinsn.exp | 0 sim/testsuite/{sim => }/bpf/alu.s | 0 sim/testsuite/{sim => }/bpf/alu32.s | 0 sim/testsuite/{sim => }/bpf/endbe.s | 0 sim/testsuite/{sim => }/bpf/endle.s | 0 sim/testsuite/{sim => }/bpf/jmp.s | 0 sim/testsuite/{sim => }/bpf/jmp32.s | 0 sim/testsuite/{sim => }/bpf/ldabs.s | 0 sim/testsuite/{sim => }/bpf/mem.s | 0 sim/testsuite/{sim => }/bpf/mov.s | 0 sim/testsuite/{sim => }/bpf/testutils.inc | 0 sim/testsuite/{sim => }/bpf/xadd.s | 0 sim/testsuite/{sim => }/cr16/ChangeLog | 0 sim/testsuite/{sim => }/cr16/addb.cgs | 0 sim/testsuite/{sim => }/cr16/addd.cgs | 0 sim/testsuite/{sim => }/cr16/addi.cgs | 0 sim/testsuite/{sim => }/cr16/addw.cgs | 0 sim/testsuite/{sim => }/cr16/allinsn.exp | 0 sim/testsuite/{sim => }/cr16/andb.cgs | 0 sim/testsuite/{sim => }/cr16/andd.cgs | 0 sim/testsuite/{sim => }/cr16/andw.cgs | 0 sim/testsuite/{sim => }/cr16/ashub.cgs | 0 sim/testsuite/{sim => }/cr16/ashub_i.cgs | 0 sim/testsuite/{sim => }/cr16/ashud.cgs | 0 sim/testsuite/{sim => }/cr16/ashud_i.cgs | 0 sim/testsuite/{sim => }/cr16/ashuw.cgs | 0 sim/testsuite/{sim => }/cr16/ashuw_i.cgs | 0 sim/testsuite/{sim => }/cr16/bal1_24.cgs | 0 sim/testsuite/{sim => }/cr16/bal2_24.cgs | 0 sim/testsuite/{sim => }/cr16/bcc.cgs | 0 sim/testsuite/{sim => }/cr16/bcs.cgs | 0 sim/testsuite/{sim => }/cr16/beq.cgs | 0 sim/testsuite/{sim => }/cr16/beq0b.cgs | 0 sim/testsuite/{sim => }/cr16/beq0w.cgs | 0 sim/testsuite/{sim => }/cr16/bge.cgs | 0 sim/testsuite/{sim => }/cr16/bgt.cgs | 0 sim/testsuite/{sim => }/cr16/bhi.cgs | 0 sim/testsuite/{sim => }/cr16/bhs.cgs | 0 sim/testsuite/{sim => }/cr16/bht.cgs | 0 sim/testsuite/{sim => }/cr16/blo.cgs | 0 sim/testsuite/{sim => }/cr16/bls.cgs | 0 sim/testsuite/{sim => }/cr16/blt.cgs | 0 sim/testsuite/{sim => }/cr16/bne.cgs | 0 sim/testsuite/{sim => }/cr16/bne0b.cgs | 0 sim/testsuite/{sim => }/cr16/bne0w.cgs | 0 sim/testsuite/{sim => }/cr16/br.cgs | 0 sim/testsuite/{sim => }/cr16/cbitb.cgs | 0 sim/testsuite/{sim => }/cr16/cbitw.cgs | 0 sim/testsuite/{sim => }/cr16/cmpb.cgs | 0 sim/testsuite/{sim => }/cr16/cmpb_i.cgs | 0 sim/testsuite/{sim => }/cr16/cmpd.cgs | 0 sim/testsuite/{sim => }/cr16/cmpd_i.cgs | 0 sim/testsuite/{sim => }/cr16/cmpi.cgs | 0 sim/testsuite/{sim => }/cr16/cmpw.cgs | 0 sim/testsuite/{sim => }/cr16/cmpw_i.cgs | 0 sim/testsuite/{sim => }/cr16/excp.cgs | 0 sim/testsuite/{sim => }/cr16/hello.ms | 0 sim/testsuite/{sim => }/cr16/hw-trap.ms | 0 sim/testsuite/{sim => }/cr16/jal.cgs | 0 sim/testsuite/{sim => }/cr16/jcc.cgs | 0 sim/testsuite/{sim => }/cr16/jcs.cgs | 0 sim/testsuite/{sim => }/cr16/jeq.cgs | 0 sim/testsuite/{sim => }/cr16/jfc.cgs | 0 sim/testsuite/{sim => }/cr16/jfs.cgs | 0 sim/testsuite/{sim => }/cr16/jge.cgs | 0 sim/testsuite/{sim => }/cr16/jgt.cgs | 0 sim/testsuite/{sim => }/cr16/jhi.cgs | 0 sim/testsuite/{sim => }/cr16/jhs.cgs | 0 sim/testsuite/{sim => }/cr16/jlo.cgs | 0 sim/testsuite/{sim => }/cr16/jls.cgs | 0 sim/testsuite/{sim => }/cr16/jlt.cgs | 0 sim/testsuite/{sim => }/cr16/jne.cgs | 0 sim/testsuite/{sim => }/cr16/jump.cgs | 0 sim/testsuite/{sim => }/cr16/loadb.cgs | 0 sim/testsuite/{sim => }/cr16/loadd.cgs | 0 sim/testsuite/{sim => }/cr16/loadm.cgs | 0 sim/testsuite/{sim => }/cr16/loadmp.cgs | 0 sim/testsuite/{sim => }/cr16/loadw.cgs | 0 sim/testsuite/{sim => }/cr16/lpr-spr.cgs | 0 sim/testsuite/{sim => }/cr16/lprd-sprd.cgs | 0 sim/testsuite/{sim => }/cr16/lshb.cgs | 0 sim/testsuite/{sim => }/cr16/lshb_i.cgs | 0 sim/testsuite/{sim => }/cr16/lshd.cgs | 0 sim/testsuite/{sim => }/cr16/lshd_i.cgs | 0 sim/testsuite/{sim => }/cr16/lshw.cgs | 0 sim/testsuite/{sim => }/cr16/lshw_i.cgs | 0 sim/testsuite/{sim => }/cr16/macqw.cgs | 0 sim/testsuite/{sim => }/cr16/macsw.cgs | 0 sim/testsuite/{sim => }/cr16/macuw.cgs | 0 sim/testsuite/{sim => }/cr16/misc.exp | 0 sim/testsuite/{sim => }/cr16/movb.cgs | 0 sim/testsuite/{sim => }/cr16/movd.cgs | 0 sim/testsuite/{sim => }/cr16/movw.cgs | 0 sim/testsuite/{sim => }/cr16/movxb.cgs | 0 sim/testsuite/{sim => }/cr16/movxw.cgs | 0 sim/testsuite/{sim => }/cr16/movzb.cgs | 0 sim/testsuite/{sim => }/cr16/movzw.cgs | 0 sim/testsuite/{sim => }/cr16/mulb.cgs | 0 sim/testsuite/{sim => }/cr16/mulsb.cgs | 0 sim/testsuite/{sim => }/cr16/mulsw.cgs | 0 sim/testsuite/{sim => }/cr16/muluw.cgs | 0 sim/testsuite/{sim => }/cr16/mulw.cgs | 0 sim/testsuite/{sim => }/cr16/nop.cgs | 0 sim/testsuite/{sim => }/cr16/orb.cgs | 0 sim/testsuite/{sim => }/cr16/ord.cgs | 0 sim/testsuite/{sim => }/cr16/orw.cgs | 0 sim/testsuite/{sim => }/cr16/pop1.cgs | 0 sim/testsuite/{sim => }/cr16/pop2.cgs | 0 sim/testsuite/{sim => }/cr16/pop3.cgs | 0 sim/testsuite/{sim => }/cr16/popret1.cgs | 0 sim/testsuite/{sim => }/cr16/popret2.cgs | 0 sim/testsuite/{sim => }/cr16/popret3.cgs | 0 sim/testsuite/{sim => }/cr16/push1.cgs | 0 sim/testsuite/{sim => }/cr16/push2.cgs | 0 sim/testsuite/{sim => }/cr16/push3.cgs | 0 sim/testsuite/{sim => }/cr16/sbitb.cgs | 0 sim/testsuite/{sim => }/cr16/sbitw.cgs | 0 sim/testsuite/{sim => }/cr16/scc.cgs | 0 sim/testsuite/{sim => }/cr16/scs.cgs | 0 sim/testsuite/{sim => }/cr16/seq.cgs | 0 sim/testsuite/{sim => }/cr16/sfc.cgs | 0 sim/testsuite/{sim => }/cr16/sfs.cgs | 0 sim/testsuite/{sim => }/cr16/sge.cgs | 0 sim/testsuite/{sim => }/cr16/sgt.cgs | 0 sim/testsuite/{sim => }/cr16/shi.cgs | 0 sim/testsuite/{sim => }/cr16/shs.cgs | 0 sim/testsuite/{sim => }/cr16/slo.cgs | 0 sim/testsuite/{sim => }/cr16/sls.cgs | 0 sim/testsuite/{sim => }/cr16/slt.cgs | 0 sim/testsuite/{sim => }/cr16/sne.cgs | 0 sim/testsuite/{sim => }/cr16/storb.cgs | 0 sim/testsuite/{sim => }/cr16/stord.cgs | 0 sim/testsuite/{sim => }/cr16/storw.cgs | 0 sim/testsuite/{sim => }/cr16/subb.cgs | 0 sim/testsuite/{sim => }/cr16/subd.cgs | 0 sim/testsuite/{sim => }/cr16/subi.cgs | 0 sim/testsuite/{sim => }/cr16/subw.cgs | 0 sim/testsuite/{sim => }/cr16/tbit.cgs | 0 sim/testsuite/{sim => }/cr16/tbitb.cgs | 0 sim/testsuite/{sim => }/cr16/tbitw.cgs | 0 sim/testsuite/{sim => }/cr16/testutils.inc | 0 sim/testsuite/{sim => }/cr16/uread16.ms | 0 sim/testsuite/{sim => }/cr16/uread32.ms | 0 sim/testsuite/{sim => }/cr16/xorb.cgs | 0 sim/testsuite/{sim => }/cr16/xord.cgs | 0 sim/testsuite/{sim => }/cr16/xorw.cgs | 0 sim/testsuite/{sim => }/cris/ChangeLog | 0 sim/testsuite/{sim => }/cris/asm/abs.ms | 0 sim/testsuite/{sim => }/cris/asm/addc.ms | 0 sim/testsuite/{sim => }/cris/asm/addcpc.ms | 0 sim/testsuite/{sim => }/cris/asm/addcv32c.ms | 0 sim/testsuite/{sim => }/cris/asm/addcv32m.ms | 0 sim/testsuite/{sim => }/cris/asm/addcv32r.ms | 0 sim/testsuite/{sim => }/cris/asm/addi.ms | 0 sim/testsuite/{sim => }/cris/asm/addiv32.ms | 0 sim/testsuite/{sim => }/cris/asm/addm.ms | 0 sim/testsuite/{sim => }/cris/asm/addoc.ms | 0 sim/testsuite/{sim => }/cris/asm/addom.ms | 0 sim/testsuite/{sim => }/cris/asm/addoq.ms | 0 sim/testsuite/{sim => }/cris/asm/addq.ms | 0 sim/testsuite/{sim => }/cris/asm/addqpc.ms | 0 sim/testsuite/{sim => }/cris/asm/addr.ms | 0 sim/testsuite/{sim => }/cris/asm/addswpc.ms | 0 sim/testsuite/{sim => }/cris/asm/addxc.ms | 0 sim/testsuite/{sim => }/cris/asm/addxm.ms | 0 sim/testsuite/{sim => }/cris/asm/addxr.ms | 0 sim/testsuite/{sim => }/cris/asm/andc.ms | 0 sim/testsuite/{sim => }/cris/asm/andm.ms | 0 sim/testsuite/{sim => }/cris/asm/andq.ms | 0 sim/testsuite/{sim => }/cris/asm/andr.ms | 0 sim/testsuite/{sim => }/cris/asm/asm.exp | 0 sim/testsuite/{sim => }/cris/asm/asr.ms | 0 sim/testsuite/{sim => }/cris/asm/ba.ms | 0 sim/testsuite/{sim => }/cris/asm/badarch1.ms | 0 sim/testsuite/{sim => }/cris/asm/bare1.ms | 0 sim/testsuite/{sim => }/cris/asm/bare2.ms | 0 sim/testsuite/{sim => }/cris/asm/bare3.ms | 0 sim/testsuite/{sim => }/cris/asm/bas.ms | 0 sim/testsuite/{sim => }/cris/asm/bccb.ms | 0 sim/testsuite/{sim => }/cris/asm/bdapc.ms | 0 sim/testsuite/{sim => }/cris/asm/bdapm.ms | 0 sim/testsuite/{sim => }/cris/asm/bdapq.ms | 0 sim/testsuite/{sim => }/cris/asm/bdapqpc.ms | 0 sim/testsuite/{sim => }/cris/asm/biap.ms | 0 sim/testsuite/{sim => }/cris/asm/boundc.ms | 0 sim/testsuite/{sim => }/cris/asm/boundm.ms | 0 sim/testsuite/{sim => }/cris/asm/boundmv32.ms | 0 sim/testsuite/{sim => }/cris/asm/boundr.ms | 0 sim/testsuite/{sim => }/cris/asm/break.ms | 0 sim/testsuite/{sim => }/cris/asm/btst.ms | 0 sim/testsuite/{sim => }/cris/asm/ccr-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/ccs-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/clearfv10.ms | 0 sim/testsuite/{sim => }/cris/asm/clearfv32.ms | 0 sim/testsuite/{sim => }/cris/asm/clrjmp1.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpc.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpm.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpq.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpr.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpxc.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpxm.ms | 0 sim/testsuite/{sim => }/cris/asm/dflags.ms | 0 sim/testsuite/{sim => }/cris/asm/dip.ms | 0 sim/testsuite/{sim => }/cris/asm/dstep.ms | 0 sim/testsuite/{sim => }/cris/asm/fidxd.ms | 0 sim/testsuite/{sim => }/cris/asm/fidxi.ms | 0 sim/testsuite/{sim => }/cris/asm/ftagd.ms | 0 sim/testsuite/{sim => }/cris/asm/ftagi.ms | 0 sim/testsuite/{sim => }/cris/asm/halt.ms | 0 sim/testsuite/{sim => }/cris/asm/io1.ms | 0 sim/testsuite/{sim => }/cris/asm/io2.ms | 0 sim/testsuite/{sim => }/cris/asm/io3.ms | 0 sim/testsuite/{sim => }/cris/asm/io4.ms | 0 sim/testsuite/{sim => }/cris/asm/io5.ms | 0 sim/testsuite/{sim => }/cris/asm/io6.ms | 0 sim/testsuite/{sim => }/cris/asm/io7.ms | 0 sim/testsuite/{sim => }/cris/asm/io8.ms | 0 sim/testsuite/{sim => }/cris/asm/io9.ms | 0 sim/testsuite/{sim => }/cris/asm/jsr.ms | 0 sim/testsuite/{sim => }/cris/asm/jsrmv10.ms | 0 sim/testsuite/{sim => }/cris/asm/jumpmp.ms | 0 sim/testsuite/{sim => }/cris/asm/jumppv32.ms | 0 sim/testsuite/{sim => }/cris/asm/lapc.ms | 0 sim/testsuite/{sim => }/cris/asm/lsl.ms | 0 sim/testsuite/{sim => }/cris/asm/lsr.ms | 0 sim/testsuite/{sim => }/cris/asm/lz.ms | 0 sim/testsuite/{sim => }/cris/asm/mcp.ms | 0 sim/testsuite/{sim => }/cris/asm/movdelsr1.ms | 0 sim/testsuite/{sim => }/cris/asm/movecpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movecr.ms | 0 sim/testsuite/{sim => }/cris/asm/movecrt10.ms | 0 sim/testsuite/{sim => }/cris/asm/movecrt32.ms | 0 sim/testsuite/{sim => }/cris/asm/movect10.ms | 0 sim/testsuite/{sim => }/cris/asm/movei.ms | 0 sim/testsuite/{sim => }/cris/asm/movempc.ms | 0 sim/testsuite/{sim => }/cris/asm/movemr.ms | 0 sim/testsuite/{sim => }/cris/asm/movemrv10.ms | 0 sim/testsuite/{sim => }/cris/asm/movemrv32.ms | 0 sim/testsuite/{sim => }/cris/asm/movepcb.ms | 0 sim/testsuite/{sim => }/cris/asm/movepcd.ms | 0 sim/testsuite/{sim => }/cris/asm/movepcw.ms | 0 sim/testsuite/{sim => }/cris/asm/moveq.ms | 0 sim/testsuite/{sim => }/cris/asm/moveqpc.ms | 0 sim/testsuite/{sim => }/cris/asm/mover.ms | 0 sim/testsuite/{sim => }/cris/asm/moverbpc.ms | 0 sim/testsuite/{sim => }/cris/asm/moverdpc.ms | 0 sim/testsuite/{sim => }/cris/asm/moverm.ms | 0 sim/testsuite/{sim => }/cris/asm/moverpcb.ms | 0 sim/testsuite/{sim => }/cris/asm/moverpcd.ms | 0 sim/testsuite/{sim => }/cris/asm/moverpcw.ms | 0 sim/testsuite/{sim => }/cris/asm/moverwpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movesmp.ms | 0 sim/testsuite/{sim => }/cris/asm/movmp.ms | 0 sim/testsuite/{sim => }/cris/asm/movmp8.ms | 0 sim/testsuite/{sim => }/cris/asm/movpmv10.ms | 0 sim/testsuite/{sim => }/cris/asm/movpmv32.ms | 0 sim/testsuite/{sim => }/cris/asm/movppc.ms | 0 sim/testsuite/{sim => }/cris/asm/movpr.ms | 0 sim/testsuite/{sim => }/cris/asm/movprv10.ms | 0 sim/testsuite/{sim => }/cris/asm/movprv32.ms | 0 sim/testsuite/{sim => }/cris/asm/movrss.ms | 0 sim/testsuite/{sim => }/cris/asm/movscpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movscr.ms | 0 sim/testsuite/{sim => }/cris/asm/movsm.ms | 0 sim/testsuite/{sim => }/cris/asm/movsmpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movsr.ms | 0 sim/testsuite/{sim => }/cris/asm/movsrpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movssr.ms | 0 sim/testsuite/{sim => }/cris/asm/movucpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movucr.ms | 0 sim/testsuite/{sim => }/cris/asm/movum.ms | 0 sim/testsuite/{sim => }/cris/asm/movumpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movur.ms | 0 sim/testsuite/{sim => }/cris/asm/movurpc.ms | 0 sim/testsuite/{sim => }/cris/asm/mstep.ms | 0 sim/testsuite/{sim => }/cris/asm/msteppc1.ms | 0 sim/testsuite/{sim => }/cris/asm/msteppc2.ms | 0 sim/testsuite/{sim => }/cris/asm/msteppc3.ms | 0 sim/testsuite/{sim => }/cris/asm/mulv10.ms | 0 sim/testsuite/{sim => }/cris/asm/mulv32.ms | 0 sim/testsuite/{sim => }/cris/asm/mulx.ms | 0 sim/testsuite/{sim => }/cris/asm/neg.ms | 0 sim/testsuite/{sim => }/cris/asm/nonvcv32.ms | 0 sim/testsuite/{sim => }/cris/asm/nopv10t.ms | 0 sim/testsuite/{sim => }/cris/asm/nopv32t.ms | 0 sim/testsuite/{sim => }/cris/asm/nopv32t2.ms | 0 sim/testsuite/{sim => }/cris/asm/nopv32t3.ms | 0 sim/testsuite/{sim => }/cris/asm/nopv32t4.ms | 0 sim/testsuite/{sim => }/cris/asm/not.ms | 0 sim/testsuite/{sim => }/cris/asm/op3.ms | 0 sim/testsuite/{sim => }/cris/asm/opterr1.ms | 0 sim/testsuite/{sim => }/cris/asm/opterr2.ms | 0 sim/testsuite/{sim => }/cris/asm/opterr3.ms | 0 sim/testsuite/{sim => }/cris/asm/opterr4.ms | 0 sim/testsuite/{sim => }/cris/asm/opterr5.ms | 0 sim/testsuite/{sim => }/cris/asm/option1.ms | 0 sim/testsuite/{sim => }/cris/asm/option2.ms | 0 sim/testsuite/{sim => }/cris/asm/option3.ms | 0 sim/testsuite/{sim => }/cris/asm/option4.ms | 0 sim/testsuite/{sim => }/cris/asm/orc.ms | 0 sim/testsuite/{sim => }/cris/asm/orm.ms | 0 sim/testsuite/{sim => }/cris/asm/orq.ms | 0 sim/testsuite/{sim => }/cris/asm/orr.ms | 0 sim/testsuite/{sim => }/cris/asm/pcplus.ms | 0 sim/testsuite/{sim => }/cris/asm/pid1.ms | 0 sim/testsuite/{sim => }/cris/asm/raw1.ms | 0 sim/testsuite/{sim => }/cris/asm/raw10.ms | 0 sim/testsuite/{sim => }/cris/asm/raw11.ms | 0 sim/testsuite/{sim => }/cris/asm/raw12.ms | 0 sim/testsuite/{sim => }/cris/asm/raw13.ms | 0 sim/testsuite/{sim => }/cris/asm/raw14.ms | 0 sim/testsuite/{sim => }/cris/asm/raw15.ms | 0 sim/testsuite/{sim => }/cris/asm/raw16.ms | 0 sim/testsuite/{sim => }/cris/asm/raw17.ms | 0 sim/testsuite/{sim => }/cris/asm/raw2.ms | 0 sim/testsuite/{sim => }/cris/asm/raw3.ms | 0 sim/testsuite/{sim => }/cris/asm/raw4.ms | 0 sim/testsuite/{sim => }/cris/asm/raw5.ms | 0 sim/testsuite/{sim => }/cris/asm/raw6.ms | 0 sim/testsuite/{sim => }/cris/asm/raw7.ms | 0 sim/testsuite/{sim => }/cris/asm/raw8.ms | 0 sim/testsuite/{sim => }/cris/asm/raw9.ms | 0 sim/testsuite/{sim => }/cris/asm/ret.ms | 0 sim/testsuite/{sim => }/cris/asm/rfe.ms | 0 sim/testsuite/{sim => }/cris/asm/rfg.ms | 0 sim/testsuite/{sim => }/cris/asm/rfn.ms | 0 sim/testsuite/{sim => }/cris/asm/sbfs.ms | 0 sim/testsuite/{sim => }/cris/asm/scc.ms | 0 sim/testsuite/{sim => }/cris/asm/sfe.ms | 0 sim/testsuite/{sim => }/cris/asm/subc.ms | 0 sim/testsuite/{sim => }/cris/asm/subm.ms | 0 sim/testsuite/{sim => }/cris/asm/subq.ms | 0 sim/testsuite/{sim => }/cris/asm/subqpc.ms | 0 sim/testsuite/{sim => }/cris/asm/subr.ms | 0 sim/testsuite/{sim => }/cris/asm/subxc.ms | 0 sim/testsuite/{sim => }/cris/asm/subxm.ms | 0 sim/testsuite/{sim => }/cris/asm/subxr.ms | 0 sim/testsuite/{sim => }/cris/asm/swap.ms | 0 sim/testsuite/{sim => }/cris/asm/tb.ms | 0 sim/testsuite/{sim => }/cris/asm/test.ms | 0 sim/testsuite/{sim => }/cris/asm/testutils.inc | 0 sim/testsuite/{sim => }/cris/asm/tjmpsrv32-2.ms | 0 sim/testsuite/{sim => }/cris/asm/tjmpsrv32.ms | 0 sim/testsuite/{sim => }/cris/asm/tjsrcv10.ms | 0 sim/testsuite/{sim => }/cris/asm/tjsrcv32.ms | 0 sim/testsuite/{sim => }/cris/asm/tmemv10.ms | 0 sim/testsuite/{sim => }/cris/asm/tmemv32.ms | 0 sim/testsuite/{sim => }/cris/asm/tmulv10.ms | 0 sim/testsuite/{sim => }/cris/asm/tmulv32.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvm1.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvm2.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvmrv10.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvmrv32.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvrmv10.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvrmv32.ms | 0 sim/testsuite/{sim => }/cris/asm/user.ms | 0 sim/testsuite/{sim => }/cris/asm/x0-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x0-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x1-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x1-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x10-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x2-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x2-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x3-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x3-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x4-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x5-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x5-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x6-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x6-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x7-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x7-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x8-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x9-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/xor.ms | 0 sim/testsuite/{sim => }/cris/c/access1.c | 0 sim/testsuite/{sim => }/cris/c/append1.c | 0 sim/testsuite/{sim => }/cris/c/badldso1.c | 0 sim/testsuite/{sim => }/cris/c/badldso2.c | 0 sim/testsuite/{sim => }/cris/c/badldso3.c | 0 sim/testsuite/{sim => }/cris/c/c.exp | 0 sim/testsuite/{sim => }/cris/c/clone1.c | 0 sim/testsuite/{sim => }/cris/c/clone2.c | 0 sim/testsuite/{sim => }/cris/c/clone3.c | 0 sim/testsuite/{sim => }/cris/c/clone4.c | 0 sim/testsuite/{sim => }/cris/c/clone5.c | 0 sim/testsuite/{sim => }/cris/c/clone6.c | 0 sim/testsuite/{sim => }/cris/c/ex1.c | 0 sim/testsuite/{sim => }/cris/c/exitg1.c | 0 sim/testsuite/{sim => }/cris/c/exitg2.c | 0 sim/testsuite/{sim => }/cris/c/fcntl1.c | 0 sim/testsuite/{sim => }/cris/c/fcntl2.c | 0 sim/testsuite/{sim => }/cris/c/fdopen1.c | 0 sim/testsuite/{sim => }/cris/c/fdopen2.c | 0 sim/testsuite/{sim => }/cris/c/freopen1.c | 0 sim/testsuite/{sim => }/cris/c/freopen2.c | 0 sim/testsuite/{sim => }/cris/c/ftruncate1.c | 0 sim/testsuite/{sim => }/cris/c/ftruncate2.c | 0 sim/testsuite/{sim => }/cris/c/getcwd1.c | 0 sim/testsuite/{sim => }/cris/c/gettod.c | 0 sim/testsuite/{sim => }/cris/c/hello.c | 0 sim/testsuite/{sim => }/cris/c/helloaout.c | 0 sim/testsuite/{sim => }/cris/c/hellodyn.c | 0 sim/testsuite/{sim => }/cris/c/hellodyn2.c | 0 sim/testsuite/{sim => }/cris/c/hellodyn3.c | 0 sim/testsuite/{sim => }/cris/c/kill1.c | 0 sim/testsuite/{sim => }/cris/c/kill2.c | 0 sim/testsuite/{sim => }/cris/c/kill3.c | 0 sim/testsuite/{sim => }/cris/c/mapbrk.c | 0 sim/testsuite/{sim => }/cris/c/mmap1.c | 0 sim/testsuite/{sim => }/cris/c/mmap2.c | 0 sim/testsuite/{sim => }/cris/c/mmap3.c | 0 sim/testsuite/{sim => }/cris/c/mmap4.c | 0 sim/testsuite/{sim => }/cris/c/mmap5.c | 0 sim/testsuite/{sim => }/cris/c/mmap6.c | 0 sim/testsuite/{sim => }/cris/c/mmap7.c | 0 sim/testsuite/{sim => }/cris/c/mmap8.c | 0 sim/testsuite/{sim => }/cris/c/mprotect1.c | 0 sim/testsuite/{sim => }/cris/c/mprotect2.c | 0 sim/testsuite/{sim => }/cris/c/mremap.c | 0 sim/testsuite/{sim => }/cris/c/openpf1.c | 0 sim/testsuite/{sim => }/cris/c/openpf2.c | 0 sim/testsuite/{sim => }/cris/c/openpf3.c | 0 sim/testsuite/{sim => }/cris/c/openpf4.c | 0 sim/testsuite/{sim => }/cris/c/openpf5.c | 0 sim/testsuite/{sim => }/cris/c/pipe1.c | 0 sim/testsuite/{sim => }/cris/c/pipe2.c | 0 sim/testsuite/{sim => }/cris/c/pipe3.c | 0 sim/testsuite/{sim => }/cris/c/pipe4.c | 0 sim/testsuite/{sim => }/cris/c/pipe5.c | 0 sim/testsuite/{sim => }/cris/c/pipe6.c | 0 sim/testsuite/{sim => }/cris/c/pipe7.c | 0 sim/testsuite/{sim => }/cris/c/readlink1.c | 0 sim/testsuite/{sim => }/cris/c/readlink10.c | 0 sim/testsuite/{sim => }/cris/c/readlink11.c | 0 sim/testsuite/{sim => }/cris/c/readlink2.c | 0 sim/testsuite/{sim => }/cris/c/readlink3.c | 0 sim/testsuite/{sim => }/cris/c/readlink4.c | 0 sim/testsuite/{sim => }/cris/c/readlink5.c | 0 sim/testsuite/{sim => }/cris/c/readlink6.c | 0 sim/testsuite/{sim => }/cris/c/readlink7.c | 0 sim/testsuite/{sim => }/cris/c/readlink8.c | 0 sim/testsuite/{sim => }/cris/c/readlink9.c | 0 sim/testsuite/{sim => }/cris/c/rename2.c | 0 sim/testsuite/{sim => }/cris/c/rtsigprocmask1.c | 0 sim/testsuite/{sim => }/cris/c/rtsigprocmask2.c | 0 sim/testsuite/{sim => }/cris/c/rtsigsuspend1.c | 0 sim/testsuite/{sim => }/cris/c/rtsigsuspend2.c | 0 sim/testsuite/{sim => }/cris/c/sched1.c | 0 sim/testsuite/{sim => }/cris/c/sched2.c | 0 sim/testsuite/{sim => }/cris/c/sched3.c | 0 sim/testsuite/{sim => }/cris/c/sched4.c | 0 sim/testsuite/{sim => }/cris/c/sched5.c | 0 sim/testsuite/{sim => }/cris/c/sched6.c | 0 sim/testsuite/{sim => }/cris/c/sched7.c | 0 sim/testsuite/{sim => }/cris/c/sched8.c | 0 sim/testsuite/{sim => }/cris/c/sched9.c | 0 sim/testsuite/{sim => }/cris/c/seek1.c | 0 sim/testsuite/{sim => }/cris/c/seek2.c | 0 sim/testsuite/{sim => }/cris/c/seek3.c | 0 sim/testsuite/{sim => }/cris/c/seek4.c | 0 sim/testsuite/{sim => }/cris/c/setrlimit1.c | 0 sim/testsuite/{sim => }/cris/c/settls1.c | 0 sim/testsuite/{sim => }/cris/c/sig1.c | 0 sim/testsuite/{sim => }/cris/c/sig10.c | 0 sim/testsuite/{sim => }/cris/c/sig11.c | 0 sim/testsuite/{sim => }/cris/c/sig12.c | 0 sim/testsuite/{sim => }/cris/c/sig13.c | 0 sim/testsuite/{sim => }/cris/c/sig2.c | 0 sim/testsuite/{sim => }/cris/c/sig3.c | 0 sim/testsuite/{sim => }/cris/c/sig4.c | 0 sim/testsuite/{sim => }/cris/c/sig5.c | 0 sim/testsuite/{sim => }/cris/c/sig6.c | 0 sim/testsuite/{sim => }/cris/c/sig7.c | 0 sim/testsuite/{sim => }/cris/c/sig8.c | 0 sim/testsuite/{sim => }/cris/c/sig9.c | 0 sim/testsuite/{sim => }/cris/c/sigreturn1.c | 0 sim/testsuite/{sim => }/cris/c/sigreturn2.c | 0 sim/testsuite/{sim => }/cris/c/sigreturn3.c | 0 sim/testsuite/{sim => }/cris/c/sigreturn4.c | 0 sim/testsuite/{sim => }/cris/c/sjlj.c | 0 sim/testsuite/{sim => }/cris/c/sock1.c | 0 sim/testsuite/{sim => }/cris/c/stat1.c | 0 sim/testsuite/{sim => }/cris/c/stat2.c | 0 sim/testsuite/{sim => }/cris/c/stat3.c | 0 sim/testsuite/{sim => }/cris/c/stat4.c | 0 sim/testsuite/{sim => }/cris/c/stat5.c | 0 sim/testsuite/{sim => }/cris/c/stat7.c | 0 sim/testsuite/{sim => }/cris/c/stat8.c | 0 sim/testsuite/{sim => }/cris/c/syscall1.c | 0 sim/testsuite/{sim => }/cris/c/syscall2.c | 0 sim/testsuite/{sim => }/cris/c/syscall3.c | 0 sim/testsuite/{sim => }/cris/c/syscall4.c | 0 sim/testsuite/{sim => }/cris/c/syscall5.c | 0 sim/testsuite/{sim => }/cris/c/syscall6.c | 0 sim/testsuite/{sim => }/cris/c/syscall7.c | 0 sim/testsuite/{sim => }/cris/c/syscall8.c | 0 sim/testsuite/{sim => }/cris/c/sysctl1.c | 0 sim/testsuite/{sim => }/cris/c/sysctl2.c | 0 sim/testsuite/{sim => }/cris/c/sysctl3.c | 0 sim/testsuite/{sim => }/cris/c/thread2.c | 0 sim/testsuite/{sim => }/cris/c/thread3.c | 0 sim/testsuite/{sim => }/cris/c/thread4.c | 0 sim/testsuite/{sim => }/cris/c/thread5.c | 0 sim/testsuite/{sim => }/cris/c/time1.c | 0 sim/testsuite/{sim => }/cris/c/time2.c | 0 sim/testsuite/{sim => }/cris/c/truncate1.c | 0 sim/testsuite/{sim => }/cris/c/truncate2.c | 0 sim/testsuite/{sim => }/cris/c/ugetrlimit1.c | 0 sim/testsuite/{sim => }/cris/c/uname1.c | 0 sim/testsuite/{sim => }/cris/c/writev1.c | 0 sim/testsuite/{sim => }/cris/c/writev2.c | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/host1.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq1.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq2.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq3.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq4.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq5.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq6.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/mbox1.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/mem1.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/mem2.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/poll1.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/quit.s | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/rvc.exp | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/std.dev | 0 .../{sim => }/cris/hw/rv-n-cris/testutils.inc | 0 .../{sim => }/cris/hw/rv-n-cris/trivial1.ms | 0 .../{sim => }/cris/hw/rv-n-cris/trivial2.ms | 0 .../{sim => }/cris/hw/rv-n-cris/trivial3.ms | 0 .../{sim => }/cris/hw/rv-n-cris/trivial4.ms | 0 .../{sim => }/cris/hw/rv-n-cris/trivial4.r | 0 .../{sim => }/cris/hw/rv-n-cris/trivial5.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/wd1.ms | 0 sim/testsuite/{sim => }/d10v/ChangeLog | 0 sim/testsuite/{sim => }/d10v/allinsn.exp | 0 sim/testsuite/{sim => }/d10v/exit47.s | 0 sim/testsuite/{sim => }/d10v/hello.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld-d.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld-i.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld-id.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld-im.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld-ip.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld2w-d.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld2w-i.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld2w-id.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld2w-im.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld2w-ip.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st-d.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st-i.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st-id.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st-im.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st-ip.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st-is.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st2w-d.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st2w-i.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st2w-id.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st2w-im.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st2w-ip.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st2w-is.s | 0 sim/testsuite/{sim => }/d10v/t-dbt.s | 0 sim/testsuite/{sim => }/d10v/t-ld-st.s | 0 sim/testsuite/{sim => }/d10v/t-mac.s | 0 sim/testsuite/{sim => }/d10v/t-macros.i | 0 sim/testsuite/{sim => }/d10v/t-mod-ld-pre.s | 0 sim/testsuite/{sim => }/d10v/t-msbu.s | 0 sim/testsuite/{sim => }/d10v/t-mulxu.s | 0 sim/testsuite/{sim => }/d10v/t-mvtac.s | 0 sim/testsuite/{sim => }/d10v/t-mvtc.s | 0 sim/testsuite/{sim => }/d10v/t-rac.s | 0 sim/testsuite/{sim => }/d10v/t-rachi.s | 0 sim/testsuite/{sim => }/d10v/t-rdt.s | 0 sim/testsuite/{sim => }/d10v/t-rep.s | 0 sim/testsuite/{sim => }/d10v/t-rie-xx.s | 0 sim/testsuite/{sim => }/d10v/t-rte.s | 0 sim/testsuite/{sim => }/d10v/t-sac.s | 0 sim/testsuite/{sim => }/d10v/t-sachi.s | 0 sim/testsuite/{sim => }/d10v/t-sadd.s | 0 sim/testsuite/{sim => }/d10v/t-slae.s | 0 sim/testsuite/{sim => }/d10v/t-sp.s | 0 sim/testsuite/{sim => }/d10v/t-sub.s | 0 sim/testsuite/{sim => }/d10v/t-sub2w.s | 0 sim/testsuite/{sim => }/d10v/t-subi.s | 0 sim/testsuite/{sim => }/d10v/t-trap.s | 0 sim/testsuite/{sim => }/frv/ChangeLog | 0 sim/testsuite/{sim => }/frv/add.cgs | 0 sim/testsuite/{sim => }/frv/add.pcgs | 0 sim/testsuite/{sim => }/frv/addcc.cgs | 0 sim/testsuite/{sim => }/frv/addi.cgs | 0 sim/testsuite/{sim => }/frv/addicc.cgs | 0 sim/testsuite/{sim => }/frv/addx.cgs | 0 sim/testsuite/{sim => }/frv/addxcc.cgs | 0 sim/testsuite/{sim => }/frv/addxi.cgs | 0 sim/testsuite/{sim => }/frv/addxicc.cgs | 0 sim/testsuite/{sim => }/frv/allinsn.exp | 0 sim/testsuite/{sim => }/frv/and.cgs | 0 sim/testsuite/{sim => }/frv/andcc.cgs | 0 sim/testsuite/{sim => }/frv/andcr.cgs | 0 sim/testsuite/{sim => }/frv/andi.cgs | 0 sim/testsuite/{sim => }/frv/andicc.cgs | 0 sim/testsuite/{sim => }/frv/andncr.cgs | 0 sim/testsuite/{sim => }/frv/bar.cgs | 0 sim/testsuite/{sim => }/frv/bc.cgs | 0 sim/testsuite/{sim => }/frv/bcclr.cgs | 0 sim/testsuite/{sim => }/frv/bceqlr.cgs | 0 sim/testsuite/{sim => }/frv/bcgelr.cgs | 0 sim/testsuite/{sim => }/frv/bcgtlr.cgs | 0 sim/testsuite/{sim => }/frv/bchilr.cgs | 0 sim/testsuite/{sim => }/frv/bclelr.cgs | 0 sim/testsuite/{sim => }/frv/bclr.cgs | 0 sim/testsuite/{sim => }/frv/bclslr.cgs | 0 sim/testsuite/{sim => }/frv/bcltlr.cgs | 0 sim/testsuite/{sim => }/frv/bcnclr.cgs | 0 sim/testsuite/{sim => }/frv/bcnelr.cgs | 0 sim/testsuite/{sim => }/frv/bcnlr.cgs | 0 sim/testsuite/{sim => }/frv/bcnolr.cgs | 0 sim/testsuite/{sim => }/frv/bcnvlr.cgs | 0 sim/testsuite/{sim => }/frv/bcplr.cgs | 0 sim/testsuite/{sim => }/frv/bcralr.cgs | 0 sim/testsuite/{sim => }/frv/bctrlr.cgs | 0 sim/testsuite/{sim => }/frv/bcvlr.cgs | 0 sim/testsuite/{sim => }/frv/beq.cgs | 0 sim/testsuite/{sim => }/frv/beqlr.cgs | 0 sim/testsuite/{sim => }/frv/bge.cgs | 0 sim/testsuite/{sim => }/frv/bgelr.cgs | 0 sim/testsuite/{sim => }/frv/bgt.cgs | 0 sim/testsuite/{sim => }/frv/bgtlr.cgs | 0 sim/testsuite/{sim => }/frv/bhi.cgs | 0 sim/testsuite/{sim => }/frv/bhilr.cgs | 0 sim/testsuite/{sim => }/frv/ble.cgs | 0 sim/testsuite/{sim => }/frv/blelr.cgs | 0 sim/testsuite/{sim => }/frv/bls.cgs | 0 sim/testsuite/{sim => }/frv/blslr.cgs | 0 sim/testsuite/{sim => }/frv/blt.cgs | 0 sim/testsuite/{sim => }/frv/bltlr.cgs | 0 sim/testsuite/{sim => }/frv/bn.cgs | 0 sim/testsuite/{sim => }/frv/bnc.cgs | 0 sim/testsuite/{sim => }/frv/bnclr.cgs | 0 sim/testsuite/{sim => }/frv/bne.cgs | 0 sim/testsuite/{sim => }/frv/bnelr.cgs | 0 sim/testsuite/{sim => }/frv/bnlr.cgs | 0 sim/testsuite/{sim => }/frv/bno.cgs | 0 sim/testsuite/{sim => }/frv/bnolr.cgs | 0 sim/testsuite/{sim => }/frv/bnv.cgs | 0 sim/testsuite/{sim => }/frv/bnvlr.cgs | 0 sim/testsuite/{sim => }/frv/bp.cgs | 0 sim/testsuite/{sim => }/frv/bplr.cgs | 0 sim/testsuite/{sim => }/frv/bra.cgs | 0 sim/testsuite/{sim => }/frv/bralr.cgs | 0 sim/testsuite/{sim => }/frv/branch.pcgs | 0 sim/testsuite/{sim => }/frv/break.cgs | 0 sim/testsuite/{sim => }/frv/bv.cgs | 0 sim/testsuite/{sim => }/frv/bvlr.cgs | 0 sim/testsuite/{sim => }/frv/cache.ms | 0 sim/testsuite/{sim => }/frv/cadd.cgs | 0 sim/testsuite/{sim => }/frv/caddcc.cgs | 0 sim/testsuite/{sim => }/frv/call.cgs | 0 sim/testsuite/{sim => }/frv/call.pcgs | 0 sim/testsuite/{sim => }/frv/callil.cgs | 0 sim/testsuite/{sim => }/frv/calll.cgs | 0 sim/testsuite/{sim => }/frv/cand.cgs | 0 sim/testsuite/{sim => }/frv/candcc.cgs | 0 sim/testsuite/{sim => }/frv/ccalll.cgs | 0 sim/testsuite/{sim => }/frv/cckc.cgs | 0 sim/testsuite/{sim => }/frv/cckeq.cgs | 0 sim/testsuite/{sim => }/frv/cckge.cgs | 0 sim/testsuite/{sim => }/frv/cckgt.cgs | 0 sim/testsuite/{sim => }/frv/cckhi.cgs | 0 sim/testsuite/{sim => }/frv/cckle.cgs | 0 sim/testsuite/{sim => }/frv/cckls.cgs | 0 sim/testsuite/{sim => }/frv/ccklt.cgs | 0 sim/testsuite/{sim => }/frv/cckn.cgs | 0 sim/testsuite/{sim => }/frv/ccknc.cgs | 0 sim/testsuite/{sim => }/frv/cckne.cgs | 0 sim/testsuite/{sim => }/frv/cckno.cgs | 0 sim/testsuite/{sim => }/frv/ccknv.cgs | 0 sim/testsuite/{sim => }/frv/cckp.cgs | 0 sim/testsuite/{sim => }/frv/cckra.cgs | 0 sim/testsuite/{sim => }/frv/cckv.cgs | 0 sim/testsuite/{sim => }/frv/ccmp.cgs | 0 sim/testsuite/{sim => }/frv/cfabss.cgs | 0 sim/testsuite/{sim => }/frv/cfadds.cgs | 0 sim/testsuite/{sim => }/frv/cfckeq.cgs | 0 sim/testsuite/{sim => }/frv/cfckge.cgs | 0 sim/testsuite/{sim => }/frv/cfckgt.cgs | 0 sim/testsuite/{sim => }/frv/cfckle.cgs | 0 sim/testsuite/{sim => }/frv/cfcklg.cgs | 0 sim/testsuite/{sim => }/frv/cfcklt.cgs | 0 sim/testsuite/{sim => }/frv/cfckne.cgs | 0 sim/testsuite/{sim => }/frv/cfckno.cgs | 0 sim/testsuite/{sim => }/frv/cfcko.cgs | 0 sim/testsuite/{sim => }/frv/cfckra.cgs | 0 sim/testsuite/{sim => }/frv/cfcku.cgs | 0 sim/testsuite/{sim => }/frv/cfckue.cgs | 0 sim/testsuite/{sim => }/frv/cfckug.cgs | 0 sim/testsuite/{sim => }/frv/cfckuge.cgs | 0 sim/testsuite/{sim => }/frv/cfckul.cgs | 0 sim/testsuite/{sim => }/frv/cfckule.cgs | 0 sim/testsuite/{sim => }/frv/cfcmps.cgs | 0 sim/testsuite/{sim => }/frv/cfdivs.cgs | 0 sim/testsuite/{sim => }/frv/cfitos.cgs | 0 sim/testsuite/{sim => }/frv/cfmadds.cgs | 0 sim/testsuite/{sim => }/frv/cfmas.cgs | 0 sim/testsuite/{sim => }/frv/cfmovs.cgs | 0 sim/testsuite/{sim => }/frv/cfmss.cgs | 0 sim/testsuite/{sim => }/frv/cfmsubs.cgs | 0 sim/testsuite/{sim => }/frv/cfmuls.cgs | 0 sim/testsuite/{sim => }/frv/cfnegs.cgs | 0 sim/testsuite/{sim => }/frv/cfsqrts.cgs | 0 sim/testsuite/{sim => }/frv/cfstoi.cgs | 0 sim/testsuite/{sim => }/frv/cfsubs.cgs | 0 sim/testsuite/{sim => }/frv/cjmpl.cgs | 0 sim/testsuite/{sim => }/frv/ckc.cgs | 0 sim/testsuite/{sim => }/frv/ckeq.cgs | 0 sim/testsuite/{sim => }/frv/ckge.cgs | 0 sim/testsuite/{sim => }/frv/ckgt.cgs | 0 sim/testsuite/{sim => }/frv/ckhi.cgs | 0 sim/testsuite/{sim => }/frv/ckle.cgs | 0 sim/testsuite/{sim => }/frv/ckls.cgs | 0 sim/testsuite/{sim => }/frv/cklt.cgs | 0 sim/testsuite/{sim => }/frv/ckn.cgs | 0 sim/testsuite/{sim => }/frv/cknc.cgs | 0 sim/testsuite/{sim => }/frv/ckne.cgs | 0 sim/testsuite/{sim => }/frv/ckno.cgs | 0 sim/testsuite/{sim => }/frv/cknv.cgs | 0 sim/testsuite/{sim => }/frv/ckp.cgs | 0 sim/testsuite/{sim => }/frv/ckra.cgs | 0 sim/testsuite/{sim => }/frv/ckv.cgs | 0 sim/testsuite/{sim => }/frv/cld.cgs | 0 sim/testsuite/{sim => }/frv/cldbf.cgs | 0 sim/testsuite/{sim => }/frv/cldbfu.cgs | 0 sim/testsuite/{sim => }/frv/cldd.cgs | 0 sim/testsuite/{sim => }/frv/clddf.cgs | 0 sim/testsuite/{sim => }/frv/clddfu.cgs | 0 sim/testsuite/{sim => }/frv/clddu.cgs | 0 sim/testsuite/{sim => }/frv/cldf.cgs | 0 sim/testsuite/{sim => }/frv/cldfu.cgs | 0 sim/testsuite/{sim => }/frv/cldhf.cgs | 0 sim/testsuite/{sim => }/frv/cldhfu.cgs | 0 sim/testsuite/{sim => }/frv/cldq.cgs | 0 sim/testsuite/{sim => }/frv/cldqu.cgs | 0 sim/testsuite/{sim => }/frv/cldsb.cgs | 0 sim/testsuite/{sim => }/frv/cldsbu.cgs | 0 sim/testsuite/{sim => }/frv/cldsh.cgs | 0 sim/testsuite/{sim => }/frv/cldshu.cgs | 0 sim/testsuite/{sim => }/frv/cldu.cgs | 0 sim/testsuite/{sim => }/frv/cldub.cgs | 0 sim/testsuite/{sim => }/frv/cldubu.cgs | 0 sim/testsuite/{sim => }/frv/clduh.cgs | 0 sim/testsuite/{sim => }/frv/clduhu.cgs | 0 sim/testsuite/{sim => }/frv/clrfa.cgs | 0 sim/testsuite/{sim => }/frv/clrfr.cgs | 0 sim/testsuite/{sim => }/frv/clrga.cgs | 0 sim/testsuite/{sim => }/frv/clrgr.cgs | 0 sim/testsuite/{sim => }/frv/cmaddhss.cgs | 0 sim/testsuite/{sim => }/frv/cmaddhus.cgs | 0 sim/testsuite/{sim => }/frv/cmand.cgs | 0 sim/testsuite/{sim => }/frv/cmbtoh.cgs | 0 sim/testsuite/{sim => }/frv/cmbtohe.cgs | 0 sim/testsuite/{sim => }/frv/cmcpxis.cgs | 0 sim/testsuite/{sim => }/frv/cmcpxiu.cgs | 0 sim/testsuite/{sim => }/frv/cmcpxrs.cgs | 0 sim/testsuite/{sim => }/frv/cmcpxru.cgs | 0 sim/testsuite/{sim => }/frv/cmexpdhd.cgs | 0 sim/testsuite/{sim => }/frv/cmexpdhw.cgs | 0 sim/testsuite/{sim => }/frv/cmhtob.cgs | 0 sim/testsuite/{sim => }/frv/cmmachs.cgs | 0 sim/testsuite/{sim => }/frv/cmmachu.cgs | 0 sim/testsuite/{sim => }/frv/cmmulhs.cgs | 0 sim/testsuite/{sim => }/frv/cmmulhu.cgs | 0 sim/testsuite/{sim => }/frv/cmnot.cgs | 0 sim/testsuite/{sim => }/frv/cmor.cgs | 0 sim/testsuite/{sim => }/frv/cmov.cgs | 0 sim/testsuite/{sim => }/frv/cmovfg.cgs | 0 sim/testsuite/{sim => }/frv/cmovfgd.cgs | 0 sim/testsuite/{sim => }/frv/cmovgf.cgs | 0 sim/testsuite/{sim => }/frv/cmovgfd.cgs | 0 sim/testsuite/{sim => }/frv/cmp.cgs | 0 sim/testsuite/{sim => }/frv/cmpb.cgs | 0 sim/testsuite/{sim => }/frv/cmpba.cgs | 0 sim/testsuite/{sim => }/frv/cmpi.cgs | 0 sim/testsuite/{sim => }/frv/cmqmachs.cgs | 0 sim/testsuite/{sim => }/frv/cmqmachu.cgs | 0 sim/testsuite/{sim => }/frv/cmqmulhs.cgs | 0 sim/testsuite/{sim => }/frv/cmqmulhu.cgs | 0 sim/testsuite/{sim => }/frv/cmsubhss.cgs | 0 sim/testsuite/{sim => }/frv/cmsubhus.cgs | 0 sim/testsuite/{sim => }/frv/cmxor.cgs | 0 sim/testsuite/{sim => }/frv/cnot.cgs | 0 sim/testsuite/{sim => }/frv/commitfa.cgs | 0 sim/testsuite/{sim => }/frv/commitfr.cgs | 0 sim/testsuite/{sim => }/frv/commitga.cgs | 0 sim/testsuite/{sim => }/frv/commitgr.cgs | 0 sim/testsuite/{sim => }/frv/cop1.cgs | 0 sim/testsuite/{sim => }/frv/cop2.cgs | 0 sim/testsuite/{sim => }/frv/cor.cgs | 0 sim/testsuite/{sim => }/frv/corcc.cgs | 0 sim/testsuite/{sim => }/frv/cscan.cgs | 0 sim/testsuite/{sim => }/frv/csdiv.cgs | 0 sim/testsuite/{sim => }/frv/csll.cgs | 0 sim/testsuite/{sim => }/frv/csllcc.cgs | 0 sim/testsuite/{sim => }/frv/csmul.cgs | 0 sim/testsuite/{sim => }/frv/csmulcc.cgs | 0 sim/testsuite/{sim => }/frv/csra.cgs | 0 sim/testsuite/{sim => }/frv/csracc.cgs | 0 sim/testsuite/{sim => }/frv/csrl.cgs | 0 sim/testsuite/{sim => }/frv/csrlcc.cgs | 0 sim/testsuite/{sim => }/frv/cst.cgs | 0 sim/testsuite/{sim => }/frv/cstb.cgs | 0 sim/testsuite/{sim => }/frv/cstbf.cgs | 0 sim/testsuite/{sim => }/frv/cstbfu.cgs | 0 sim/testsuite/{sim => }/frv/cstbu.cgs | 0 sim/testsuite/{sim => }/frv/cstd.cgs | 0 sim/testsuite/{sim => }/frv/cstdf.cgs | 0 sim/testsuite/{sim => }/frv/cstdfu.cgs | 0 sim/testsuite/{sim => }/frv/cstdu.cgs | 0 sim/testsuite/{sim => }/frv/cstf.cgs | 0 sim/testsuite/{sim => }/frv/cstfu.cgs | 0 sim/testsuite/{sim => }/frv/csth.cgs | 0 sim/testsuite/{sim => }/frv/csthf.cgs | 0 sim/testsuite/{sim => }/frv/csthfu.cgs | 0 sim/testsuite/{sim => }/frv/csthu.cgs | 0 sim/testsuite/{sim => }/frv/cstq.cgs | 0 sim/testsuite/{sim => }/frv/cstu.cgs | 0 sim/testsuite/{sim => }/frv/csub.cgs | 0 sim/testsuite/{sim => }/frv/csubcc.cgs | 0 sim/testsuite/{sim => }/frv/cswap.cgs | 0 sim/testsuite/{sim => }/frv/cudiv.cgs | 0 sim/testsuite/{sim => }/frv/cxor.cgs | 0 sim/testsuite/{sim => }/frv/cxorcc.cgs | 0 sim/testsuite/{sim => }/frv/dcef.cgs | 0 sim/testsuite/{sim => }/frv/dcei.cgs | 0 sim/testsuite/{sim => }/frv/dcf.cgs | 0 sim/testsuite/{sim => }/frv/dci.cgs | 0 sim/testsuite/{sim => }/frv/exit47.ms | 0 sim/testsuite/{sim => }/frv/fabsd.cgs | 0 sim/testsuite/{sim => }/frv/fabss.cgs | 0 sim/testsuite/{sim => }/frv/faddd.cgs | 0 sim/testsuite/{sim => }/frv/fadds.cgs | 0 sim/testsuite/{sim => }/frv/fbeq.cgs | 0 sim/testsuite/{sim => }/frv/fbeqlr.cgs | 0 sim/testsuite/{sim => }/frv/fbge.cgs | 0 sim/testsuite/{sim => }/frv/fbgelr.cgs | 0 sim/testsuite/{sim => }/frv/fbgt.cgs | 0 sim/testsuite/{sim => }/frv/fbgtlr.cgs | 0 sim/testsuite/{sim => }/frv/fble.cgs | 0 sim/testsuite/{sim => }/frv/fblelr.cgs | 0 sim/testsuite/{sim => }/frv/fblg.cgs | 0 sim/testsuite/{sim => }/frv/fblglr.cgs | 0 sim/testsuite/{sim => }/frv/fblt.cgs | 0 sim/testsuite/{sim => }/frv/fbltlr.cgs | 0 sim/testsuite/{sim => }/frv/fbne.cgs | 0 sim/testsuite/{sim => }/frv/fbnelr.cgs | 0 sim/testsuite/{sim => }/frv/fbno.cgs | 0 sim/testsuite/{sim => }/frv/fbnolr.cgs | 0 sim/testsuite/{sim => }/frv/fbo.cgs | 0 sim/testsuite/{sim => }/frv/fbolr.cgs | 0 sim/testsuite/{sim => }/frv/fbra.cgs | 0 sim/testsuite/{sim => }/frv/fbralr.cgs | 0 sim/testsuite/{sim => }/frv/fbu.cgs | 0 sim/testsuite/{sim => }/frv/fbue.cgs | 0 sim/testsuite/{sim => }/frv/fbuelr.cgs | 0 sim/testsuite/{sim => }/frv/fbug.cgs | 0 sim/testsuite/{sim => }/frv/fbuge.cgs | 0 sim/testsuite/{sim => }/frv/fbugelr.cgs | 0 sim/testsuite/{sim => }/frv/fbuglr.cgs | 0 sim/testsuite/{sim => }/frv/fbul.cgs | 0 sim/testsuite/{sim => }/frv/fbule.cgs | 0 sim/testsuite/{sim => }/frv/fbulelr.cgs | 0 sim/testsuite/{sim => }/frv/fbullr.cgs | 0 sim/testsuite/{sim => }/frv/fbulr.cgs | 0 sim/testsuite/{sim => }/frv/fcbeqlr.cgs | 0 sim/testsuite/{sim => }/frv/fcbgelr.cgs | 0 sim/testsuite/{sim => }/frv/fcbgtlr.cgs | 0 sim/testsuite/{sim => }/frv/fcblelr.cgs | 0 sim/testsuite/{sim => }/frv/fcblglr.cgs | 0 sim/testsuite/{sim => }/frv/fcbltlr.cgs | 0 sim/testsuite/{sim => }/frv/fcbnelr.cgs | 0 sim/testsuite/{sim => }/frv/fcbnolr.cgs | 0 sim/testsuite/{sim => }/frv/fcbolr.cgs | 0 sim/testsuite/{sim => }/frv/fcbralr.cgs | 0 sim/testsuite/{sim => }/frv/fcbuelr.cgs | 0 sim/testsuite/{sim => }/frv/fcbugelr.cgs | 0 sim/testsuite/{sim => }/frv/fcbuglr.cgs | 0 sim/testsuite/{sim => }/frv/fcbulelr.cgs | 0 sim/testsuite/{sim => }/frv/fcbullr.cgs | 0 sim/testsuite/{sim => }/frv/fcbulr.cgs | 0 sim/testsuite/{sim => }/frv/fckeq.cgs | 0 sim/testsuite/{sim => }/frv/fckge.cgs | 0 sim/testsuite/{sim => }/frv/fckgt.cgs | 0 sim/testsuite/{sim => }/frv/fckle.cgs | 0 sim/testsuite/{sim => }/frv/fcklg.cgs | 0 sim/testsuite/{sim => }/frv/fcklt.cgs | 0 sim/testsuite/{sim => }/frv/fckne.cgs | 0 sim/testsuite/{sim => }/frv/fckno.cgs | 0 sim/testsuite/{sim => }/frv/fcko.cgs | 0 sim/testsuite/{sim => }/frv/fckra.cgs | 0 sim/testsuite/{sim => }/frv/fcku.cgs | 0 sim/testsuite/{sim => }/frv/fckue.cgs | 0 sim/testsuite/{sim => }/frv/fckug.cgs | 0 sim/testsuite/{sim => }/frv/fckuge.cgs | 0 sim/testsuite/{sim => }/frv/fckul.cgs | 0 sim/testsuite/{sim => }/frv/fckule.cgs | 0 sim/testsuite/{sim => }/frv/fcmpd.cgs | 0 sim/testsuite/{sim => }/frv/fcmps.cgs | 0 sim/testsuite/{sim => }/frv/fdabss.cgs | 0 sim/testsuite/{sim => }/frv/fdadds.cgs | 0 sim/testsuite/{sim => }/frv/fdcmps.cgs | 0 sim/testsuite/{sim => }/frv/fddivs.cgs | 0 sim/testsuite/{sim => }/frv/fditos.cgs | 0 sim/testsuite/{sim => }/frv/fdivd.cgs | 0 sim/testsuite/{sim => }/frv/fdivs.cgs | 0 sim/testsuite/{sim => }/frv/fdmadds.cgs | 0 sim/testsuite/{sim => }/frv/fdmas.cgs | 0 sim/testsuite/{sim => }/frv/fdmovs.cgs | 0 sim/testsuite/{sim => }/frv/fdmss.cgs | 0 sim/testsuite/{sim => }/frv/fdmulcs.cgs | 0 sim/testsuite/{sim => }/frv/fdmuls.cgs | 0 sim/testsuite/{sim => }/frv/fdnegs.cgs | 0 sim/testsuite/{sim => }/frv/fdsads.cgs | 0 sim/testsuite/{sim => }/frv/fdsqrts.cgs | 0 sim/testsuite/{sim => }/frv/fdstoi.cgs | 0 sim/testsuite/{sim => }/frv/fdsubs.cgs | 0 sim/testsuite/{sim => }/frv/fdtoi.cgs | 0 sim/testsuite/{sim => }/frv/fitod.cgs | 0 sim/testsuite/{sim => }/frv/fitos.cgs | 0 sim/testsuite/{sim => }/frv/fmad.cgs | 0 sim/testsuite/{sim => }/frv/fmaddd.cgs | 0 sim/testsuite/{sim => }/frv/fmadds.cgs | 0 sim/testsuite/{sim => }/frv/fmas.cgs | 0 sim/testsuite/{sim => }/frv/fmovd.cgs | 0 sim/testsuite/{sim => }/frv/fmovs.cgs | 0 sim/testsuite/{sim => }/frv/fmsd.cgs | 0 sim/testsuite/{sim => }/frv/fmss.cgs | 0 sim/testsuite/{sim => }/frv/fmsubd.cgs | 0 sim/testsuite/{sim => }/frv/fmsubs.cgs | 0 sim/testsuite/{sim => }/frv/fmuld.cgs | 0 sim/testsuite/{sim => }/frv/fmuls.cgs | 0 sim/testsuite/{sim => }/frv/fnegd.cgs | 0 sim/testsuite/{sim => }/frv/fnegs.cgs | 0 sim/testsuite/{sim => }/frv/fnop.cgs | 0 sim/testsuite/{sim => }/frv/fr400/addss.cgs | 0 sim/testsuite/{sim => }/frv/fr400/allinsn.exp | 0 sim/testsuite/{sim => }/frv/fr400/csdiv.cgs | 0 sim/testsuite/{sim => }/frv/fr400/maddaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr400/masaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr400/maveh.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mclracc.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhdseth.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhdsets.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhsethih.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhsethis.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhsetloh.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhsetlos.cgs | 0 sim/testsuite/{sim => }/frv/fr400/movgs.cgs | 0 sim/testsuite/{sim => }/frv/fr400/movsg.cgs | 0 sim/testsuite/{sim => }/frv/fr400/msubaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr400/scutss.cgs | 0 sim/testsuite/{sim => }/frv/fr400/sdiv.cgs | 0 sim/testsuite/{sim => }/frv/fr400/sdivi.cgs | 0 sim/testsuite/{sim => }/frv/fr400/slass.cgs | 0 sim/testsuite/{sim => }/frv/fr400/smass.cgs | 0 sim/testsuite/{sim => }/frv/fr400/smsss.cgs | 0 sim/testsuite/{sim => }/frv/fr400/smu.cgs | 0 sim/testsuite/{sim => }/frv/fr400/subss.cgs | 0 sim/testsuite/{sim => }/frv/fr400/udiv.cgs | 0 sim/testsuite/{sim => }/frv/fr400/udivi.cgs | 0 sim/testsuite/{sim => }/frv/fr500/allinsn.exp | 0 sim/testsuite/{sim => }/frv/fr500/cmqaddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr500/cmqaddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr500/cmqsubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr500/cmqsubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr500/dcpl.cgs | 0 sim/testsuite/{sim => }/frv/fr500/dcul.cgs | 0 sim/testsuite/{sim => }/frv/fr500/mclracc.cgs | 0 sim/testsuite/{sim => }/frv/fr500/mqaddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr500/mqaddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr500/mqsubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr500/mqsubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/allinsn.exp | 0 sim/testsuite/{sim => }/frv/fr550/cmaddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmaddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmcpxiu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmcpxru.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmmachs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmmachu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqaddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqaddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqmachs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqmachu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqsubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqsubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmsubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmsubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/dcpl.cgs | 0 sim/testsuite/{sim => }/frv/fr550/dcul.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mabshs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/maddaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/maddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/maddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/masaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mdaddaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mdasaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mdsubaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mmachs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mmachu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mmrdhs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mmrdhu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqaddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqaddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqmachs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqmachu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqmacxhs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqsubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqsubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqxmachs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqxmacxhs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/msubaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/msubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/msubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mtrap.cgs | 0 sim/testsuite/{sim => }/frv/fr550/udiv.cgs | 0 sim/testsuite/{sim => }/frv/fr550/udivi.cgs | 0 sim/testsuite/{sim => }/frv/fsqrtd.cgs | 0 sim/testsuite/{sim => }/frv/fsqrts.cgs | 0 sim/testsuite/{sim => }/frv/fstoi.cgs | 0 sim/testsuite/{sim => }/frv/fsubd.cgs | 0 sim/testsuite/{sim => }/frv/fsubs.cgs | 0 sim/testsuite/{sim => }/frv/fteq.cgs | 0 sim/testsuite/{sim => }/frv/ftge.cgs | 0 sim/testsuite/{sim => }/frv/ftgt.cgs | 0 sim/testsuite/{sim => }/frv/ftieq.cgs | 0 sim/testsuite/{sim => }/frv/ftige.cgs | 0 sim/testsuite/{sim => }/frv/ftigt.cgs | 0 sim/testsuite/{sim => }/frv/ftile.cgs | 0 sim/testsuite/{sim => }/frv/ftilg.cgs | 0 sim/testsuite/{sim => }/frv/ftilt.cgs | 0 sim/testsuite/{sim => }/frv/ftine.cgs | 0 sim/testsuite/{sim => }/frv/ftino.cgs | 0 sim/testsuite/{sim => }/frv/ftio.cgs | 0 sim/testsuite/{sim => }/frv/ftira.cgs | 0 sim/testsuite/{sim => }/frv/ftiu.cgs | 0 sim/testsuite/{sim => }/frv/ftiue.cgs | 0 sim/testsuite/{sim => }/frv/ftiug.cgs | 0 sim/testsuite/{sim => }/frv/ftiuge.cgs | 0 sim/testsuite/{sim => }/frv/ftiul.cgs | 0 sim/testsuite/{sim => }/frv/ftle.cgs | 0 sim/testsuite/{sim => }/frv/ftlg.cgs | 0 sim/testsuite/{sim => }/frv/ftlt.cgs | 0 sim/testsuite/{sim => }/frv/ftne.cgs | 0 sim/testsuite/{sim => }/frv/ftno.cgs | 0 sim/testsuite/{sim => }/frv/fto.cgs | 0 sim/testsuite/{sim => }/frv/ftra.cgs | 0 sim/testsuite/{sim => }/frv/ftu.cgs | 0 sim/testsuite/{sim => }/frv/ftue.cgs | 0 sim/testsuite/{sim => }/frv/ftug.cgs | 0 sim/testsuite/{sim => }/frv/ftuge.cgs | 0 sim/testsuite/{sim => }/frv/ftul.cgs | 0 sim/testsuite/{sim => }/frv/ftule.cgs | 0 sim/testsuite/{sim => }/frv/grloop.ms | 0 sim/testsuite/{sim => }/frv/hello.ms | 0 sim/testsuite/{sim => }/frv/icei.cgs | 0 sim/testsuite/{sim => }/frv/ici.cgs | 0 sim/testsuite/{sim => }/frv/icpl.cgs | 0 sim/testsuite/{sim => }/frv/icul.cgs | 0 sim/testsuite/{sim => }/frv/interrupts.exp | 0 .../{sim => }/frv/interrupts/Ipipe-fr400.cgs | 0 .../{sim => }/frv/interrupts/Ipipe-fr500.cgs | 0 .../{sim => }/frv/interrupts/badalign-fr550.cgs | 0 .../{sim => }/frv/interrupts/badalign.cgs | 0 .../{sim => }/frv/interrupts/compound-fr550.cgs | 0 .../{sim => }/frv/interrupts/compound.cgs | 0 .../frv/interrupts/data_store_error-fr550.cgs | 0 .../{sim => }/frv/interrupts/data_store_error.cgs | 0 .../frv/interrupts/fp_exception-fr550.cgs | 0 .../{sim => }/frv/interrupts/fp_exception.cgs | 0 sim/testsuite/{sim => }/frv/interrupts/illinsn.cgs | 0 .../frv/interrupts/insn_access_error-fr550.cgs | 0 .../{sim => }/frv/interrupts/insn_access_error.cgs | 0 .../{sim => }/frv/interrupts/mp_exception.cgs | 0 .../frv/interrupts/privileged_instruction.cgs | 0 .../{sim => }/frv/interrupts/regalign.cgs | 0 sim/testsuite/{sim => }/frv/interrupts/reset.cgs | 0 .../{sim => }/frv/interrupts/shadow_regs.cgs | 0 sim/testsuite/{sim => }/frv/interrupts/timer.cgs | 0 sim/testsuite/{sim => }/frv/jmpil.cgs | 0 sim/testsuite/{sim => }/frv/jmpl.cgs | 0 sim/testsuite/{sim => }/frv/jmpl.pcgs | 0 sim/testsuite/{sim => }/frv/ld.cgs | 0 sim/testsuite/{sim => }/frv/ldbf.cgs | 0 sim/testsuite/{sim => }/frv/ldbfi.cgs | 0 sim/testsuite/{sim => }/frv/ldbfu.cgs | 0 sim/testsuite/{sim => }/frv/ldc.cgs | 0 sim/testsuite/{sim => }/frv/ldcu.cgs | 0 sim/testsuite/{sim => }/frv/ldd.cgs | 0 sim/testsuite/{sim => }/frv/lddc.cgs | 0 sim/testsuite/{sim => }/frv/lddcu.cgs | 0 sim/testsuite/{sim => }/frv/lddf.cgs | 0 sim/testsuite/{sim => }/frv/lddfi.cgs | 0 sim/testsuite/{sim => }/frv/lddfu.cgs | 0 sim/testsuite/{sim => }/frv/lddi.cgs | 0 sim/testsuite/{sim => }/frv/lddu.cgs | 0 sim/testsuite/{sim => }/frv/ldf.cgs | 0 sim/testsuite/{sim => }/frv/ldfi.cgs | 0 sim/testsuite/{sim => }/frv/ldfu.cgs | 0 sim/testsuite/{sim => }/frv/ldhf.cgs | 0 sim/testsuite/{sim => }/frv/ldhfi.cgs | 0 sim/testsuite/{sim => }/frv/ldhfu.cgs | 0 sim/testsuite/{sim => }/frv/ldi.cgs | 0 sim/testsuite/{sim => }/frv/ldq.cgs | 0 sim/testsuite/{sim => }/frv/ldqc.cgs | 0 sim/testsuite/{sim => }/frv/ldqcu.cgs | 0 sim/testsuite/{sim => }/frv/ldqf.cgs | 0 sim/testsuite/{sim => }/frv/ldqfi.cgs | 0 sim/testsuite/{sim => }/frv/ldqfu.cgs | 0 sim/testsuite/{sim => }/frv/ldqi.cgs | 0 sim/testsuite/{sim => }/frv/ldqu.cgs | 0 sim/testsuite/{sim => }/frv/ldsb.cgs | 0 sim/testsuite/{sim => }/frv/ldsbi.cgs | 0 sim/testsuite/{sim => }/frv/ldsbu.cgs | 0 sim/testsuite/{sim => }/frv/ldsh.cgs | 0 sim/testsuite/{sim => }/frv/ldshi.cgs | 0 sim/testsuite/{sim => }/frv/ldshu.cgs | 0 sim/testsuite/{sim => }/frv/ldu.cgs | 0 sim/testsuite/{sim => }/frv/ldub.cgs | 0 sim/testsuite/{sim => }/frv/ldubi.cgs | 0 sim/testsuite/{sim => }/frv/ldubu.cgs | 0 sim/testsuite/{sim => }/frv/lduh.cgs | 0 sim/testsuite/{sim => }/frv/lduhi.cgs | 0 sim/testsuite/{sim => }/frv/lduhu.cgs | 0 sim/testsuite/{sim => }/frv/lrbranch.pcgs | 0 sim/testsuite/{sim => }/frv/mabshs.cgs | 0 sim/testsuite/{sim => }/frv/maddhss.cgs | 0 sim/testsuite/{sim => }/frv/maddhus.cgs | 0 sim/testsuite/{sim => }/frv/mand.cgs | 0 sim/testsuite/{sim => }/frv/maveh.cgs | 0 sim/testsuite/{sim => }/frv/mbtoh.cgs | 0 sim/testsuite/{sim => }/frv/mbtohe.cgs | 0 sim/testsuite/{sim => }/frv/mclracc.cgs | 0 sim/testsuite/{sim => }/frv/mcmpsh.cgs | 0 sim/testsuite/{sim => }/frv/mcmpuh.cgs | 0 sim/testsuite/{sim => }/frv/mcop1.cgs | 0 sim/testsuite/{sim => }/frv/mcop2.cgs | 0 sim/testsuite/{sim => }/frv/mcplhi.cgs | 0 sim/testsuite/{sim => }/frv/mcpli.cgs | 0 sim/testsuite/{sim => }/frv/mcpxis.cgs | 0 sim/testsuite/{sim => }/frv/mcpxiu.cgs | 0 sim/testsuite/{sim => }/frv/mcpxrs.cgs | 0 sim/testsuite/{sim => }/frv/mcpxru.cgs | 0 sim/testsuite/{sim => }/frv/mcut.cgs | 0 sim/testsuite/{sim => }/frv/mcuti.cgs | 0 sim/testsuite/{sim => }/frv/mcutss.cgs | 0 sim/testsuite/{sim => }/frv/mcutssi.cgs | 0 sim/testsuite/{sim => }/frv/mdaddaccs.cgs | 0 sim/testsuite/{sim => }/frv/mdasaccs.cgs | 0 sim/testsuite/{sim => }/frv/mdcutssi.cgs | 0 sim/testsuite/{sim => }/frv/mdpackh.cgs | 0 sim/testsuite/{sim => }/frv/mdrotli.cgs | 0 sim/testsuite/{sim => }/frv/mdsubaccs.cgs | 0 sim/testsuite/{sim => }/frv/mdunpackh.cgs | 0 sim/testsuite/{sim => }/frv/membar.cgs | 0 sim/testsuite/{sim => }/frv/mexpdhd.cgs | 0 sim/testsuite/{sim => }/frv/mexpdhw.cgs | 0 sim/testsuite/{sim => }/frv/mhdseth.cgs | 0 sim/testsuite/{sim => }/frv/mhdsets.cgs | 0 sim/testsuite/{sim => }/frv/mhsethih.cgs | 0 sim/testsuite/{sim => }/frv/mhsethis.cgs | 0 sim/testsuite/{sim => }/frv/mhsetloh.cgs | 0 sim/testsuite/{sim => }/frv/mhsetlos.cgs | 0 sim/testsuite/{sim => }/frv/mhtob.cgs | 0 sim/testsuite/{sim => }/frv/misc.exp | 0 sim/testsuite/{sim => }/frv/mmachs.cgs | 0 sim/testsuite/{sim => }/frv/mmachu.cgs | 0 sim/testsuite/{sim => }/frv/mmrdhs.cgs | 0 sim/testsuite/{sim => }/frv/mmrdhu.cgs | 0 sim/testsuite/{sim => }/frv/mmulhs.cgs | 0 sim/testsuite/{sim => }/frv/mmulhu.cgs | 0 sim/testsuite/{sim => }/frv/mmulxhs.cgs | 0 sim/testsuite/{sim => }/frv/mmulxhu.cgs | 0 sim/testsuite/{sim => }/frv/mnop.cgs | 0 sim/testsuite/{sim => }/frv/mnot.cgs | 0 sim/testsuite/{sim => }/frv/mor.cgs | 0 sim/testsuite/{sim => }/frv/mov.cgs | 0 sim/testsuite/{sim => }/frv/movfg.cgs | 0 sim/testsuite/{sim => }/frv/movfgd.cgs | 0 sim/testsuite/{sim => }/frv/movfgq.cgs | 0 sim/testsuite/{sim => }/frv/movgf.cgs | 0 sim/testsuite/{sim => }/frv/movgfd.cgs | 0 sim/testsuite/{sim => }/frv/movgfq.cgs | 0 sim/testsuite/{sim => }/frv/movgs.cgs | 0 sim/testsuite/{sim => }/frv/movsg.cgs | 0 sim/testsuite/{sim => }/frv/mpackh.cgs | 0 sim/testsuite/{sim => }/frv/mqcpxis.cgs | 0 sim/testsuite/{sim => }/frv/mqcpxiu.cgs | 0 sim/testsuite/{sim => }/frv/mqcpxrs.cgs | 0 sim/testsuite/{sim => }/frv/mqcpxru.cgs | 0 sim/testsuite/{sim => }/frv/mqlclrhs.cgs | 0 sim/testsuite/{sim => }/frv/mqlmths.cgs | 0 sim/testsuite/{sim => }/frv/mqmachs.cgs | 0 sim/testsuite/{sim => }/frv/mqmachu.cgs | 0 sim/testsuite/{sim => }/frv/mqmacxhs.cgs | 0 sim/testsuite/{sim => }/frv/mqmulhs.cgs | 0 sim/testsuite/{sim => }/frv/mqmulhu.cgs | 0 sim/testsuite/{sim => }/frv/mqmulxhs.cgs | 0 sim/testsuite/{sim => }/frv/mqmulxhu.cgs | 0 sim/testsuite/{sim => }/frv/mqsaths.cgs | 0 sim/testsuite/{sim => }/frv/mqsllhi.cgs | 0 sim/testsuite/{sim => }/frv/mqsrahi.cgs | 0 sim/testsuite/{sim => }/frv/mqxmachs.cgs | 0 sim/testsuite/{sim => }/frv/mqxmacxhs.cgs | 0 sim/testsuite/{sim => }/frv/mrdacc.cgs | 0 sim/testsuite/{sim => }/frv/mrdaccg.cgs | 0 sim/testsuite/{sim => }/frv/mrotli.cgs | 0 sim/testsuite/{sim => }/frv/mrotri.cgs | 0 sim/testsuite/{sim => }/frv/msaths.cgs | 0 sim/testsuite/{sim => }/frv/msathu.cgs | 0 sim/testsuite/{sim => }/frv/msllhi.cgs | 0 sim/testsuite/{sim => }/frv/msrahi.cgs | 0 sim/testsuite/{sim => }/frv/msrlhi.cgs | 0 sim/testsuite/{sim => }/frv/msubhss.cgs | 0 sim/testsuite/{sim => }/frv/msubhus.cgs | 0 sim/testsuite/{sim => }/frv/mtrap.cgs | 0 sim/testsuite/{sim => }/frv/munpackh.cgs | 0 sim/testsuite/{sim => }/frv/mwcut.cgs | 0 sim/testsuite/{sim => }/frv/mwcuti.cgs | 0 sim/testsuite/{sim => }/frv/mwtacc.cgs | 0 sim/testsuite/{sim => }/frv/mwtaccg.cgs | 0 sim/testsuite/{sim => }/frv/mxor.cgs | 0 sim/testsuite/{sim => }/frv/nandcr.cgs | 0 sim/testsuite/{sim => }/frv/nandncr.cgs | 0 sim/testsuite/{sim => }/frv/nfadds.cgs | 0 sim/testsuite/{sim => }/frv/nfdadds.cgs | 0 sim/testsuite/{sim => }/frv/nfdcmps.cgs | 0 sim/testsuite/{sim => }/frv/nfddivs.cgs | 0 sim/testsuite/{sim => }/frv/nfditos.cgs | 0 sim/testsuite/{sim => }/frv/nfdivs.cgs | 0 sim/testsuite/{sim => }/frv/nfdmadds.cgs | 0 sim/testsuite/{sim => }/frv/nfdmas.cgs | 0 sim/testsuite/{sim => }/frv/nfdmss.cgs | 0 sim/testsuite/{sim => }/frv/nfdmulcs.cgs | 0 sim/testsuite/{sim => }/frv/nfdmuls.cgs | 0 sim/testsuite/{sim => }/frv/nfdsads.cgs | 0 sim/testsuite/{sim => }/frv/nfdsqrts.cgs | 0 sim/testsuite/{sim => }/frv/nfdstoi.cgs | 0 sim/testsuite/{sim => }/frv/nfdsubs.cgs | 0 sim/testsuite/{sim => }/frv/nfitos.cgs | 0 sim/testsuite/{sim => }/frv/nfmadds.cgs | 0 sim/testsuite/{sim => }/frv/nfmas.cgs | 0 sim/testsuite/{sim => }/frv/nfmss.cgs | 0 sim/testsuite/{sim => }/frv/nfmsubs.cgs | 0 sim/testsuite/{sim => }/frv/nfmuls.cgs | 0 sim/testsuite/{sim => }/frv/nfsqrts.cgs | 0 sim/testsuite/{sim => }/frv/nfstoi.cgs | 0 sim/testsuite/{sim => }/frv/nfsubs.cgs | 0 sim/testsuite/{sim => }/frv/nld.cgs | 0 sim/testsuite/{sim => }/frv/nldbf.cgs | 0 sim/testsuite/{sim => }/frv/nldbfi.cgs | 0 sim/testsuite/{sim => }/frv/nldbfu.cgs | 0 sim/testsuite/{sim => }/frv/nldd.cgs | 0 sim/testsuite/{sim => }/frv/nlddf.cgs | 0 sim/testsuite/{sim => }/frv/nlddfi.cgs | 0 sim/testsuite/{sim => }/frv/nlddfu.cgs | 0 sim/testsuite/{sim => }/frv/nlddi.cgs | 0 sim/testsuite/{sim => }/frv/nlddu.cgs | 0 sim/testsuite/{sim => }/frv/nldf.cgs | 0 sim/testsuite/{sim => }/frv/nldfi.cgs | 0 sim/testsuite/{sim => }/frv/nldfu.cgs | 0 sim/testsuite/{sim => }/frv/nldhf.cgs | 0 sim/testsuite/{sim => }/frv/nldhfi.cgs | 0 sim/testsuite/{sim => }/frv/nldhfu.cgs | 0 sim/testsuite/{sim => }/frv/nldi.cgs | 0 sim/testsuite/{sim => }/frv/nldq.cgs | 0 sim/testsuite/{sim => }/frv/nldqf.cgs | 0 sim/testsuite/{sim => }/frv/nldqfi.cgs | 0 sim/testsuite/{sim => }/frv/nldqfu.cgs | 0 sim/testsuite/{sim => }/frv/nldqu.cgs | 0 sim/testsuite/{sim => }/frv/nldsb.cgs | 0 sim/testsuite/{sim => }/frv/nldsbi.cgs | 0 sim/testsuite/{sim => }/frv/nldsbu.cgs | 0 sim/testsuite/{sim => }/frv/nldsh.cgs | 0 sim/testsuite/{sim => }/frv/nldshi.cgs | 0 sim/testsuite/{sim => }/frv/nldshu.cgs | 0 sim/testsuite/{sim => }/frv/nldu.cgs | 0 sim/testsuite/{sim => }/frv/nldub.cgs | 0 sim/testsuite/{sim => }/frv/nldubi.cgs | 0 sim/testsuite/{sim => }/frv/nldubu.cgs | 0 sim/testsuite/{sim => }/frv/nlduh.cgs | 0 sim/testsuite/{sim => }/frv/nlduhi.cgs | 0 sim/testsuite/{sim => }/frv/nlduhu.cgs | 0 sim/testsuite/{sim => }/frv/nop.cgs | 0 sim/testsuite/{sim => }/frv/norcr.cgs | 0 sim/testsuite/{sim => }/frv/norncr.cgs | 0 sim/testsuite/{sim => }/frv/not.cgs | 0 sim/testsuite/{sim => }/frv/notcr.cgs | 0 sim/testsuite/{sim => }/frv/nsdiv.cgs | 0 sim/testsuite/{sim => }/frv/nsdivi.cgs | 0 sim/testsuite/{sim => }/frv/nudiv.cgs | 0 sim/testsuite/{sim => }/frv/nudivi.cgs | 0 sim/testsuite/{sim => }/frv/or.cgs | 0 sim/testsuite/{sim => }/frv/orcc.cgs | 0 sim/testsuite/{sim => }/frv/orcr.cgs | 0 sim/testsuite/{sim => }/frv/ori.cgs | 0 sim/testsuite/{sim => }/frv/oricc.cgs | 0 sim/testsuite/{sim => }/frv/orncr.cgs | 0 sim/testsuite/{sim => }/frv/parallel.exp | 0 sim/testsuite/{sim => }/frv/ret.cgs | 0 sim/testsuite/{sim => }/frv/rett.cgs | 0 sim/testsuite/{sim => }/frv/scan.cgs | 0 sim/testsuite/{sim => }/frv/scani.cgs | 0 sim/testsuite/{sim => }/frv/sdiv.cgs | 0 sim/testsuite/{sim => }/frv/sdivi.cgs | 0 sim/testsuite/{sim => }/frv/sethi.cgs | 0 sim/testsuite/{sim => }/frv/sethilo.pcgs | 0 sim/testsuite/{sim => }/frv/setlo.cgs | 0 sim/testsuite/{sim => }/frv/setlos.cgs | 0 sim/testsuite/{sim => }/frv/sll.cgs | 0 sim/testsuite/{sim => }/frv/sllcc.cgs | 0 sim/testsuite/{sim => }/frv/slli.cgs | 0 sim/testsuite/{sim => }/frv/sllicc.cgs | 0 sim/testsuite/{sim => }/frv/smul.cgs | 0 sim/testsuite/{sim => }/frv/smulcc.cgs | 0 sim/testsuite/{sim => }/frv/smuli.cgs | 0 sim/testsuite/{sim => }/frv/smulicc.cgs | 0 sim/testsuite/{sim => }/frv/sra.cgs | 0 sim/testsuite/{sim => }/frv/sracc.cgs | 0 sim/testsuite/{sim => }/frv/srai.cgs | 0 sim/testsuite/{sim => }/frv/sraicc.cgs | 0 sim/testsuite/{sim => }/frv/srl.cgs | 0 sim/testsuite/{sim => }/frv/srlcc.cgs | 0 sim/testsuite/{sim => }/frv/srli.cgs | 0 sim/testsuite/{sim => }/frv/srlicc.cgs | 0 sim/testsuite/{sim => }/frv/st.cgs | 0 sim/testsuite/{sim => }/frv/stb.cgs | 0 sim/testsuite/{sim => }/frv/stbf.cgs | 0 sim/testsuite/{sim => }/frv/stbfi.cgs | 0 sim/testsuite/{sim => }/frv/stbfu.cgs | 0 sim/testsuite/{sim => }/frv/stbi.cgs | 0 sim/testsuite/{sim => }/frv/stbu.cgs | 0 sim/testsuite/{sim => }/frv/stc.cgs | 0 sim/testsuite/{sim => }/frv/stcu.cgs | 0 sim/testsuite/{sim => }/frv/std.cgs | 0 sim/testsuite/{sim => }/frv/std.pcgs | 0 sim/testsuite/{sim => }/frv/stdc.cgs | 0 sim/testsuite/{sim => }/frv/stdc.pcgs | 0 sim/testsuite/{sim => }/frv/stdcu.cgs | 0 sim/testsuite/{sim => }/frv/stdf.cgs | 0 sim/testsuite/{sim => }/frv/stdf.pcgs | 0 sim/testsuite/{sim => }/frv/stdfi.cgs | 0 sim/testsuite/{sim => }/frv/stdfu.cgs | 0 sim/testsuite/{sim => }/frv/stdi.cgs | 0 sim/testsuite/{sim => }/frv/stdu.cgs | 0 sim/testsuite/{sim => }/frv/stf.cgs | 0 sim/testsuite/{sim => }/frv/stfi.cgs | 0 sim/testsuite/{sim => }/frv/stfu.cgs | 0 sim/testsuite/{sim => }/frv/sth.cgs | 0 sim/testsuite/{sim => }/frv/sthf.cgs | 0 sim/testsuite/{sim => }/frv/sthfi.cgs | 0 sim/testsuite/{sim => }/frv/sthfu.cgs | 0 sim/testsuite/{sim => }/frv/sthi.cgs | 0 sim/testsuite/{sim => }/frv/sthu.cgs | 0 sim/testsuite/{sim => }/frv/sti.cgs | 0 sim/testsuite/{sim => }/frv/stq.cgs | 0 sim/testsuite/{sim => }/frv/stq.pcgs | 0 sim/testsuite/{sim => }/frv/stqc.cgs | 0 sim/testsuite/{sim => }/frv/stqc.pcgs | 0 sim/testsuite/{sim => }/frv/stqcu.cgs | 0 sim/testsuite/{sim => }/frv/stqf.cgs | 0 sim/testsuite/{sim => }/frv/stqf.pcgs | 0 sim/testsuite/{sim => }/frv/stqfi.cgs | 0 sim/testsuite/{sim => }/frv/stqfu.cgs | 0 sim/testsuite/{sim => }/frv/stqi.cgs | 0 sim/testsuite/{sim => }/frv/stqu.cgs | 0 sim/testsuite/{sim => }/frv/stu.cgs | 0 sim/testsuite/{sim => }/frv/sub.cgs | 0 sim/testsuite/{sim => }/frv/subcc.cgs | 0 sim/testsuite/{sim => }/frv/subi.cgs | 0 sim/testsuite/{sim => }/frv/subicc.cgs | 0 sim/testsuite/{sim => }/frv/subx.cgs | 0 sim/testsuite/{sim => }/frv/subxcc.cgs | 0 sim/testsuite/{sim => }/frv/subxi.cgs | 0 sim/testsuite/{sim => }/frv/subxicc.cgs | 0 sim/testsuite/{sim => }/frv/swap.cgs | 0 sim/testsuite/{sim => }/frv/swapi.cgs | 0 sim/testsuite/{sim => }/frv/tc.cgs | 0 sim/testsuite/{sim => }/frv/teq.cgs | 0 sim/testsuite/{sim => }/frv/testutils.inc | 0 sim/testsuite/{sim => }/frv/tge.cgs | 0 sim/testsuite/{sim => }/frv/tgt.cgs | 0 sim/testsuite/{sim => }/frv/thi.cgs | 0 sim/testsuite/{sim => }/frv/tic.cgs | 0 sim/testsuite/{sim => }/frv/tieq.cgs | 0 sim/testsuite/{sim => }/frv/tige.cgs | 0 sim/testsuite/{sim => }/frv/tigt.cgs | 0 sim/testsuite/{sim => }/frv/tihi.cgs | 0 sim/testsuite/{sim => }/frv/tile.cgs | 0 sim/testsuite/{sim => }/frv/tils.cgs | 0 sim/testsuite/{sim => }/frv/tilt.cgs | 0 sim/testsuite/{sim => }/frv/tin.cgs | 0 sim/testsuite/{sim => }/frv/tinc.cgs | 0 sim/testsuite/{sim => }/frv/tine.cgs | 0 sim/testsuite/{sim => }/frv/tino.cgs | 0 sim/testsuite/{sim => }/frv/tinv.cgs | 0 sim/testsuite/{sim => }/frv/tip.cgs | 0 sim/testsuite/{sim => }/frv/tira.cgs | 0 sim/testsuite/{sim => }/frv/tiv.cgs | 0 sim/testsuite/{sim => }/frv/tle.cgs | 0 sim/testsuite/{sim => }/frv/tls.cgs | 0 sim/testsuite/{sim => }/frv/tlt.cgs | 0 sim/testsuite/{sim => }/frv/tn.cgs | 0 sim/testsuite/{sim => }/frv/tnc.cgs | 0 sim/testsuite/{sim => }/frv/tne.cgs | 0 sim/testsuite/{sim => }/frv/tno.cgs | 0 sim/testsuite/{sim => }/frv/tnv.cgs | 0 sim/testsuite/{sim => }/frv/tp.cgs | 0 sim/testsuite/{sim => }/frv/tra.cgs | 0 sim/testsuite/{sim => }/frv/tv.cgs | 0 sim/testsuite/{sim => }/frv/udiv.cgs | 0 sim/testsuite/{sim => }/frv/udivi.cgs | 0 sim/testsuite/{sim => }/frv/umul.cgs | 0 sim/testsuite/{sim => }/frv/umulcc.cgs | 0 sim/testsuite/{sim => }/frv/umuli.cgs | 0 sim/testsuite/{sim => }/frv/umulicc.cgs | 0 sim/testsuite/{sim => }/frv/xor.cgs | 0 sim/testsuite/{sim => }/frv/xorcc.cgs | 0 sim/testsuite/{sim => }/frv/xorcr.cgs | 0 sim/testsuite/{sim => }/frv/xori.cgs | 0 sim/testsuite/{sim => }/frv/xoricc.cgs | 0 sim/testsuite/{sim => }/ft32/ChangeLog | 0 sim/testsuite/{sim => }/ft32/allinsn.exp | 0 sim/testsuite/{sim => }/ft32/basic.s | 0 sim/testsuite/{sim => }/ft32/testutils.inc | 0 sim/testsuite/{sim => }/h8300/ChangeLog | 0 sim/testsuite/{sim => }/h8300/addb.s | 0 sim/testsuite/{sim => }/h8300/addl.s | 0 sim/testsuite/{sim => }/h8300/adds.s | 0 sim/testsuite/{sim => }/h8300/addw.s | 0 sim/testsuite/{sim => }/h8300/addx.s | 0 sim/testsuite/{sim => }/h8300/allinsn.exp | 0 sim/testsuite/{sim => }/h8300/andb.s | 0 sim/testsuite/{sim => }/h8300/andl.s | 0 sim/testsuite/{sim => }/h8300/andw.s | 0 sim/testsuite/{sim => }/h8300/band.s | 0 sim/testsuite/{sim => }/h8300/bfld.s | 0 sim/testsuite/{sim => }/h8300/biand.s | 0 sim/testsuite/{sim => }/h8300/bra.s | 0 sim/testsuite/{sim => }/h8300/brabc.s | 0 sim/testsuite/{sim => }/h8300/bset.s | 0 sim/testsuite/{sim => }/h8300/cmpb.s | 0 sim/testsuite/{sim => }/h8300/cmpl.s | 0 sim/testsuite/{sim => }/h8300/cmpw.s | 0 sim/testsuite/{sim => }/h8300/daa.s | 0 sim/testsuite/{sim => }/h8300/das.s | 0 sim/testsuite/{sim => }/h8300/dec.s | 0 sim/testsuite/{sim => }/h8300/div.s | 0 sim/testsuite/{sim => }/h8300/extl.s | 0 sim/testsuite/{sim => }/h8300/extw.s | 0 sim/testsuite/{sim => }/h8300/inc.s | 0 sim/testsuite/{sim => }/h8300/jmp.s | 0 sim/testsuite/{sim => }/h8300/ldc.s | 0 sim/testsuite/{sim => }/h8300/ldm.s | 0 sim/testsuite/{sim => }/h8300/mac.s | 0 sim/testsuite/{sim => }/h8300/mova.s | 0 sim/testsuite/{sim => }/h8300/movb.s | 0 sim/testsuite/{sim => }/h8300/movl.s | 0 sim/testsuite/{sim => }/h8300/movmd.s | 0 sim/testsuite/{sim => }/h8300/movsd.s | 0 sim/testsuite/{sim => }/h8300/movw.s | 0 sim/testsuite/{sim => }/h8300/mul.s | 0 sim/testsuite/{sim => }/h8300/neg.s | 0 sim/testsuite/{sim => }/h8300/nop.s | 0 sim/testsuite/{sim => }/h8300/not.s | 0 sim/testsuite/{sim => }/h8300/orb.s | 0 sim/testsuite/{sim => }/h8300/orl.s | 0 sim/testsuite/{sim => }/h8300/orw.s | 0 sim/testsuite/{sim => }/h8300/rotl.s | 0 sim/testsuite/{sim => }/h8300/rotr.s | 0 sim/testsuite/{sim => }/h8300/rotxl.s | 0 sim/testsuite/{sim => }/h8300/rotxr.s | 0 sim/testsuite/{sim => }/h8300/shal.s | 0 sim/testsuite/{sim => }/h8300/shar.s | 0 sim/testsuite/{sim => }/h8300/shll.s | 0 sim/testsuite/{sim => }/h8300/shlr.s | 0 sim/testsuite/{sim => }/h8300/stack.s | 0 sim/testsuite/{sim => }/h8300/stc.s | 0 sim/testsuite/{sim => }/h8300/subb.s | 0 sim/testsuite/{sim => }/h8300/subl.s | 0 sim/testsuite/{sim => }/h8300/subs.s | 0 sim/testsuite/{sim => }/h8300/subw.s | 0 sim/testsuite/{sim => }/h8300/subx.s | 0 sim/testsuite/{sim => }/h8300/tas.s | 0 sim/testsuite/{sim => }/h8300/testutils.inc | 0 sim/testsuite/{sim => }/h8300/xorb.s | 0 sim/testsuite/{sim => }/h8300/xorl.s | 0 sim/testsuite/{sim => }/h8300/xorw.s | 0 sim/testsuite/{sim => }/iq2000/ChangeLog | 0 sim/testsuite/{sim => }/iq2000/allinsn.exp | 0 sim/testsuite/{sim => }/iq2000/pass.s | 0 sim/testsuite/{sim => }/iq2000/testutils.inc | 0 sim/testsuite/{sim => }/lm32/ChangeLog | 0 sim/testsuite/{sim => }/lm32/allinsn.exp | 0 sim/testsuite/{sim => }/lm32/pass.s | 0 sim/testsuite/{sim => }/lm32/testutils.inc | 0 sim/testsuite/{sim => }/m32c/ChangeLog | 0 sim/testsuite/{sim => }/m32c/allinsn.exp | 0 sim/testsuite/{sim => }/m32c/blinky.s | 0 sim/testsuite/{sim => }/m32c/fail.s | 0 sim/testsuite/{sim => }/m32c/gloss.s | 0 sim/testsuite/{sim => }/m32c/pass.s | 0 sim/testsuite/{sim => }/m32c/sample.ld | 0 sim/testsuite/{sim => }/m32c/sample.s | 0 sim/testsuite/{sim => }/m32c/sample2.c | 0 sim/testsuite/{sim => }/m32c/testutils.inc | 0 sim/testsuite/{sim => }/m32r/ChangeLog | 0 sim/testsuite/{sim => }/m32r/add.cgs | 0 sim/testsuite/{sim => }/m32r/add3.cgs | 0 sim/testsuite/{sim => }/m32r/addi.cgs | 0 sim/testsuite/{sim => }/m32r/addv.cgs | 0 sim/testsuite/{sim => }/m32r/addv3.cgs | 0 sim/testsuite/{sim => }/m32r/addx.cgs | 0 sim/testsuite/{sim => }/m32r/allinsn.exp | 0 sim/testsuite/{sim => }/m32r/and.cgs | 0 sim/testsuite/{sim => }/m32r/and3.cgs | 0 sim/testsuite/{sim => }/m32r/bc24.cgs | 0 sim/testsuite/{sim => }/m32r/bc8.cgs | 0 sim/testsuite/{sim => }/m32r/beq.cgs | 0 sim/testsuite/{sim => }/m32r/beqz.cgs | 0 sim/testsuite/{sim => }/m32r/bgez.cgs | 0 sim/testsuite/{sim => }/m32r/bgtz.cgs | 0 sim/testsuite/{sim => }/m32r/bl24.cgs | 0 sim/testsuite/{sim => }/m32r/bl8.cgs | 0 sim/testsuite/{sim => }/m32r/blez.cgs | 0 sim/testsuite/{sim => }/m32r/bltz.cgs | 0 sim/testsuite/{sim => }/m32r/bnc24.cgs | 0 sim/testsuite/{sim => }/m32r/bnc8.cgs | 0 sim/testsuite/{sim => }/m32r/bne.cgs | 0 sim/testsuite/{sim => }/m32r/bnez.cgs | 0 sim/testsuite/{sim => }/m32r/bra24.cgs | 0 sim/testsuite/{sim => }/m32r/bra8.cgs | 0 sim/testsuite/{sim => }/m32r/cmp.cgs | 0 sim/testsuite/{sim => }/m32r/cmpi.cgs | 0 sim/testsuite/{sim => }/m32r/cmpu.cgs | 0 sim/testsuite/{sim => }/m32r/cmpui.cgs | 0 sim/testsuite/{sim => }/m32r/div.cgs | 0 sim/testsuite/{sim => }/m32r/divu.cgs | 0 sim/testsuite/{sim => }/m32r/exit47.ms | 0 sim/testsuite/{sim => }/m32r/hello.ms | 0 sim/testsuite/{sim => }/m32r/hw-trap.ms | 0 sim/testsuite/{sim => }/m32r/jl.cgs | 0 sim/testsuite/{sim => }/m32r/jmp.cgs | 0 sim/testsuite/{sim => }/m32r/ld-d.cgs | 0 sim/testsuite/{sim => }/m32r/ld-plus.cgs | 0 sim/testsuite/{sim => }/m32r/ld.cgs | 0 sim/testsuite/{sim => }/m32r/ld24.cgs | 0 sim/testsuite/{sim => }/m32r/ldb-d.cgs | 0 sim/testsuite/{sim => }/m32r/ldb.cgs | 0 sim/testsuite/{sim => }/m32r/ldh-d.cgs | 0 sim/testsuite/{sim => }/m32r/ldh.cgs | 0 sim/testsuite/{sim => }/m32r/ldi16.cgs | 0 sim/testsuite/{sim => }/m32r/ldi8.cgs | 0 sim/testsuite/{sim => }/m32r/ldub-d.cgs | 0 sim/testsuite/{sim => }/m32r/ldub.cgs | 0 sim/testsuite/{sim => }/m32r/lduh-d.cgs | 0 sim/testsuite/{sim => }/m32r/lduh.cgs | 0 sim/testsuite/{sim => }/m32r/lock.cgs | 0 sim/testsuite/{sim => }/m32r/machi.cgs | 0 sim/testsuite/{sim => }/m32r/maclo.cgs | 0 sim/testsuite/{sim => }/m32r/macwhi.cgs | 0 sim/testsuite/{sim => }/m32r/macwlo.cgs | 0 sim/testsuite/{sim => }/m32r/misc.exp | 0 sim/testsuite/{sim => }/m32r/mul.cgs | 0 sim/testsuite/{sim => }/m32r/mulhi.cgs | 0 sim/testsuite/{sim => }/m32r/mullo.cgs | 0 sim/testsuite/{sim => }/m32r/mulwhi.cgs | 0 sim/testsuite/{sim => }/m32r/mulwlo.cgs | 0 sim/testsuite/{sim => }/m32r/mv.cgs | 0 sim/testsuite/{sim => }/m32r/mvfachi.cgs | 0 sim/testsuite/{sim => }/m32r/mvfaclo.cgs | 0 sim/testsuite/{sim => }/m32r/mvfacmi.cgs | 0 sim/testsuite/{sim => }/m32r/mvfc.cgs | 0 sim/testsuite/{sim => }/m32r/mvtachi.cgs | 0 sim/testsuite/{sim => }/m32r/mvtaclo.cgs | 0 sim/testsuite/{sim => }/m32r/mvtc.cgs | 0 sim/testsuite/{sim => }/m32r/neg.cgs | 0 sim/testsuite/{sim => }/m32r/nop.cgs | 0 sim/testsuite/{sim => }/m32r/not.cgs | 0 sim/testsuite/{sim => }/m32r/or.cgs | 0 sim/testsuite/{sim => }/m32r/or3.cgs | 0 sim/testsuite/{sim => }/m32r/rac.cgs | 0 sim/testsuite/{sim => }/m32r/rach.cgs | 0 sim/testsuite/{sim => }/m32r/rem.cgs | 0 sim/testsuite/{sim => }/m32r/remu.cgs | 0 sim/testsuite/{sim => }/m32r/rte.cgs | 0 sim/testsuite/{sim => }/m32r/seth.cgs | 0 sim/testsuite/{sim => }/m32r/sll.cgs | 0 sim/testsuite/{sim => }/m32r/sll3.cgs | 0 sim/testsuite/{sim => }/m32r/slli.cgs | 0 sim/testsuite/{sim => }/m32r/sra.cgs | 0 sim/testsuite/{sim => }/m32r/sra3.cgs | 0 sim/testsuite/{sim => }/m32r/srai.cgs | 0 sim/testsuite/{sim => }/m32r/srl.cgs | 0 sim/testsuite/{sim => }/m32r/srl3.cgs | 0 sim/testsuite/{sim => }/m32r/srli.cgs | 0 sim/testsuite/{sim => }/m32r/st-d.cgs | 0 sim/testsuite/{sim => }/m32r/st-minus.cgs | 0 sim/testsuite/{sim => }/m32r/st-plus.cgs | 0 sim/testsuite/{sim => }/m32r/st.cgs | 0 sim/testsuite/{sim => }/m32r/stb-d.cgs | 0 sim/testsuite/{sim => }/m32r/stb.cgs | 0 sim/testsuite/{sim => }/m32r/sth-d.cgs | 0 sim/testsuite/{sim => }/m32r/sth.cgs | 0 sim/testsuite/{sim => }/m32r/sub.cgs | 0 sim/testsuite/{sim => }/m32r/subv.cgs | 0 sim/testsuite/{sim => }/m32r/subx.cgs | 0 sim/testsuite/{sim => }/m32r/testutils.inc | 0 sim/testsuite/{sim => }/m32r/trap.cgs | 0 sim/testsuite/{sim => }/m32r/unlock.cgs | 0 sim/testsuite/{sim => }/m32r/uread16.ms | 0 sim/testsuite/{sim => }/m32r/uread32.ms | 0 sim/testsuite/{sim => }/m32r/uwrite16.ms | 0 sim/testsuite/{sim => }/m32r/uwrite32.ms | 0 sim/testsuite/{sim => }/m32r/xor.cgs | 0 sim/testsuite/{sim => }/m32r/xor3.cgs | 0 sim/testsuite/{sim => }/m68hc11/ChangeLog | 0 sim/testsuite/{sim => }/m68hc11/allinsn.exp | 0 sim/testsuite/{sim => }/m68hc11/pass.s | 0 sim/testsuite/{sim => }/m68hc11/testutils.inc | 0 sim/testsuite/{sim => }/mcore/ChangeLog | 0 sim/testsuite/{sim => }/mcore/allinsn.exp | 0 sim/testsuite/{sim => }/mcore/fail.s | 0 sim/testsuite/{sim => }/mcore/pass.s | 0 sim/testsuite/{sim => }/mcore/testutils.inc | 0 sim/testsuite/{sim => }/microblaze/ChangeLog | 0 sim/testsuite/{sim => }/microblaze/allinsn.exp | 0 sim/testsuite/{sim => }/microblaze/pass.s | 0 sim/testsuite/{sim => }/microblaze/testutils.inc | 0 sim/testsuite/{sim => }/mips/ChangeLog | 0 sim/testsuite/{sim => }/mips/basic.exp | 0 sim/testsuite/{sim => }/mips/fpu64-ps-sb1.s | 0 sim/testsuite/{sim => }/mips/fpu64-ps.s | 0 sim/testsuite/{sim => }/mips/hilo-hazard-1.s | 0 sim/testsuite/{sim => }/mips/hilo-hazard-2.s | 0 sim/testsuite/{sim => }/mips/hilo-hazard-3.s | 0 sim/testsuite/{sim => }/mips/hilo-hazard-4.s | 0 sim/testsuite/{sim => }/mips/mdmx-ob-sb1.s | 0 sim/testsuite/{sim => }/mips/mdmx-ob.s | 0 sim/testsuite/{sim => }/mips/mips32-dsp.s | 0 sim/testsuite/{sim => }/mips/mips32-dsp2.s | 0 sim/testsuite/{sim => }/mips/sanity.s | 0 sim/testsuite/{sim => }/mips/testutils.inc | 0 sim/testsuite/{sim => }/mips/utils-dsp.inc | 0 sim/testsuite/{sim => }/mips/utils-fpu.inc | 0 sim/testsuite/{sim => }/mips/utils-mdmx.inc | 0 sim/testsuite/{sim => }/mn10300/ChangeLog | 0 sim/testsuite/{sim => }/mn10300/allinsn.exp | 0 sim/testsuite/{sim => }/mn10300/pass.s | 0 sim/testsuite/{sim => }/mn10300/testutils.inc | 0 sim/testsuite/{sim => }/moxie/ChangeLog | 0 sim/testsuite/{sim => }/moxie/allinsn.exp | 0 sim/testsuite/{sim => }/moxie/pass.s | 0 sim/testsuite/{sim => }/moxie/testutils.inc | 0 sim/testsuite/{sim => }/msp430/ChangeLog | 0 sim/testsuite/{sim => }/msp430/add.s | 0 sim/testsuite/{sim => }/msp430/allinsn.exp | 0 sim/testsuite/{sim => }/msp430/mpyull_hwmult.s | 0 sim/testsuite/{sim => }/msp430/rrux.s | 0 sim/testsuite/{sim => }/msp430/testutils.inc | 0 sim/testsuite/{sim => }/or1k/ChangeLog | 0 sim/testsuite/{sim => }/or1k/add.S | 0 sim/testsuite/{sim => }/or1k/adrp.S | 0 sim/testsuite/{sim => }/or1k/alltests.exp | 0 sim/testsuite/{sim => }/or1k/and.S | 0 sim/testsuite/{sim => }/or1k/basic.S | 0 sim/testsuite/{sim => }/or1k/div.S | 0 sim/testsuite/{sim => }/or1k/ext.S | 0 sim/testsuite/{sim => }/or1k/find.S | 0 sim/testsuite/{sim => }/or1k/flag.S | 0 sim/testsuite/{sim => }/or1k/fpu-unordered.S | 0 sim/testsuite/{sim => }/or1k/fpu.S | 0 sim/testsuite/{sim => }/or1k/fpu64a32-unordered.S | 0 sim/testsuite/{sim => }/or1k/fpu64a32.S | 0 sim/testsuite/{sim => }/or1k/jump.S | 0 sim/testsuite/{sim => }/or1k/load.S | 0 sim/testsuite/{sim => }/or1k/mac.S | 0 sim/testsuite/{sim => }/or1k/mfspr.S | 0 sim/testsuite/{sim => }/or1k/mul.S | 0 sim/testsuite/{sim => }/or1k/or.S | 0 sim/testsuite/{sim => }/or1k/or1k-asm-test-env.h | 0 .../{sim => }/or1k/or1k-asm-test-helpers.h | 0 sim/testsuite/{sim => }/or1k/or1k-asm-test.h | 0 sim/testsuite/{sim => }/or1k/or1k-asm.h | 0 sim/testsuite/{sim => }/or1k/or1k-test.ld | 0 sim/testsuite/{sim => }/or1k/ror.S | 0 sim/testsuite/{sim => }/or1k/shift.S | 0 sim/testsuite/{sim => }/or1k/spr-defs.h | 0 sim/testsuite/{sim => }/or1k/sub.S | 0 sim/testsuite/{sim => }/or1k/xor.S | 0 sim/testsuite/{sim => }/pru/ChangeLog | 0 sim/testsuite/{sim => }/pru/add.s | 0 sim/testsuite/{sim => }/pru/allinsn.exp | 0 sim/testsuite/{sim => }/pru/dmem-zero-pass.s | 0 sim/testsuite/{sim => }/pru/dmem-zero-trap.s | 0 sim/testsuite/{sim => }/pru/dram.s | 0 sim/testsuite/{sim => }/pru/jmp.s | 0 sim/testsuite/{sim => }/pru/lmbd.s | 0 sim/testsuite/{sim => }/pru/loop-imm.s | 0 sim/testsuite/{sim => }/pru/loop-reg.s | 0 sim/testsuite/{sim => }/pru/mul.s | 0 sim/testsuite/{sim => }/pru/subreg.s | 0 sim/testsuite/{sim => }/pru/testutils.inc | 0 sim/testsuite/{sim => }/sh/ChangeLog | 0 sim/testsuite/{sim => }/sh/add.s | 0 sim/testsuite/{sim => }/sh/allinsn.exp | 0 sim/testsuite/{sim => }/sh/and.s | 0 sim/testsuite/{sim => }/sh/bandor.s | 0 sim/testsuite/{sim => }/sh/bandornot.s | 0 sim/testsuite/{sim => }/sh/bclr.s | 0 sim/testsuite/{sim => }/sh/bld.s | 0 sim/testsuite/{sim => }/sh/bldnot.s | 0 sim/testsuite/{sim => }/sh/bset.s | 0 sim/testsuite/{sim => }/sh/bst.s | 0 sim/testsuite/{sim => }/sh/bxor.s | 0 sim/testsuite/{sim => }/sh/clip.s | 0 sim/testsuite/{sim => }/sh/div.s | 0 sim/testsuite/{sim => }/sh/dmxy.s | 0 sim/testsuite/{sim => }/sh/fabs.s | 0 sim/testsuite/{sim => }/sh/fadd.s | 0 sim/testsuite/{sim => }/sh/fail.s | 0 sim/testsuite/{sim => }/sh/fcmpeq.s | 0 sim/testsuite/{sim => }/sh/fcmpgt.s | 0 sim/testsuite/{sim => }/sh/fcnvds.s | 0 sim/testsuite/{sim => }/sh/fcnvsd.s | 0 sim/testsuite/{sim => }/sh/fdiv.s | 0 sim/testsuite/{sim => }/sh/fipr.s | 0 sim/testsuite/{sim => }/sh/fldi0.s | 0 sim/testsuite/{sim => }/sh/fldi1.s | 0 sim/testsuite/{sim => }/sh/flds.s | 0 sim/testsuite/{sim => }/sh/float.s | 0 sim/testsuite/{sim => }/sh/fmac.s | 0 sim/testsuite/{sim => }/sh/fmov.s | 0 sim/testsuite/{sim => }/sh/fmul.s | 0 sim/testsuite/{sim => }/sh/fneg.s | 0 sim/testsuite/{sim => }/sh/fpchg.s | 0 sim/testsuite/{sim => }/sh/frchg.s | 0 sim/testsuite/{sim => }/sh/fsca.s | 0 sim/testsuite/{sim => }/sh/fschg.s | 0 sim/testsuite/{sim => }/sh/fsqrt.s | 0 sim/testsuite/{sim => }/sh/fsrra.s | 0 sim/testsuite/{sim => }/sh/fsub.s | 0 sim/testsuite/{sim => }/sh/ftrc.s | 0 sim/testsuite/{sim => }/sh/ldrc.s | 0 sim/testsuite/{sim => }/sh/loop.s | 0 sim/testsuite/{sim => }/sh/macl.s | 0 sim/testsuite/{sim => }/sh/macw.s | 0 sim/testsuite/{sim => }/sh/mov.s | 0 sim/testsuite/{sim => }/sh/movi.s | 0 sim/testsuite/{sim => }/sh/movli.s | 0 sim/testsuite/{sim => }/sh/movua.s | 0 sim/testsuite/{sim => }/sh/movxy.s | 0 sim/testsuite/{sim => }/sh/mulr.s | 0 sim/testsuite/{sim => }/sh/pabs.s | 0 sim/testsuite/{sim => }/sh/padd.s | 0 sim/testsuite/{sim => }/sh/paddc.s | 0 sim/testsuite/{sim => }/sh/pand.s | 0 sim/testsuite/{sim => }/sh/pass.s | 0 sim/testsuite/{sim => }/sh/pclr.s | 0 sim/testsuite/{sim => }/sh/pdec.s | 0 sim/testsuite/{sim => }/sh/pdmsb.s | 0 sim/testsuite/{sim => }/sh/pinc.s | 0 sim/testsuite/{sim => }/sh/pmuls.s | 0 sim/testsuite/{sim => }/sh/prnd.s | 0 sim/testsuite/{sim => }/sh/pshai.s | 0 sim/testsuite/{sim => }/sh/pshar.s | 0 sim/testsuite/{sim => }/sh/pshli.s | 0 sim/testsuite/{sim => }/sh/pshlr.s | 0 sim/testsuite/{sim => }/sh/psub.s | 0 sim/testsuite/{sim => }/sh/pswap.s | 0 sim/testsuite/{sim => }/sh/pushpop.s | 0 sim/testsuite/{sim => }/sh/resbank.s | 0 sim/testsuite/{sim => }/sh/sett.s | 0 sim/testsuite/{sim => }/sh/shll.s | 0 sim/testsuite/{sim => }/sh/shll16.s | 0 sim/testsuite/{sim => }/sh/shll2.s | 0 sim/testsuite/{sim => }/sh/shll8.s | 0 sim/testsuite/{sim => }/sh/shlr.s | 0 sim/testsuite/{sim => }/sh/shlr16.s | 0 sim/testsuite/{sim => }/sh/shlr2.s | 0 sim/testsuite/{sim => }/sh/shlr8.s | 0 sim/testsuite/{sim => }/sh/swap.s | 0 sim/testsuite/{sim => }/sh/testutils.inc | 0 sim/testsuite/{sim => }/v850/ChangeLog | 0 sim/testsuite/{sim => }/v850/allinsns.exp | 0 sim/testsuite/{sim => }/v850/bsh.cgs | 0 sim/testsuite/{sim => }/v850/div.cgs | 0 sim/testsuite/{sim => }/v850/divh.cgs | 0 sim/testsuite/{sim => }/v850/divh_3.cgs | 0 sim/testsuite/{sim => }/v850/divhu.cgs | 0 sim/testsuite/{sim => }/v850/divu.cgs | 0 sim/testsuite/{sim => }/v850/sar.cgs | 0 sim/testsuite/{sim => }/v850/satadd.cgs | 0 sim/testsuite/{sim => }/v850/satsub.cgs | 0 sim/testsuite/{sim => }/v850/satsubi.cgs | 0 sim/testsuite/{sim => }/v850/satsubr.cgs | 0 sim/testsuite/{sim => }/v850/shl.cgs | 0 sim/testsuite/{sim => }/v850/shr.cgs | 0 sim/testsuite/{sim => }/v850/testutils.cgs | 0 sim/testsuite/{sim => }/v850/testutils.inc | 0 2919 files changed, 1854 insertions(+), 1550 deletions(-) create mode 100644 ld/emulparams/x86-report-relative.sh create mode 100644 ld/testsuite/ld-i386/report-reloc-1.d create mode 100644 ld/testsuite/ld-i386/report-reloc-1.l create mode 100644 ld/testsuite/ld-i386/report-reloc-1.s create mode 100644 ld/testsuite/ld-x86-64/report-reloc-1-x32.d create mode 100644 ld/testsuite/ld-x86-64/report-reloc-1.d create mode 100644 ld/testsuite/ld-x86-64/report-reloc-1.l create mode 100644 ld/testsuite/ld-x86-64/report-reloc-1.s rename sim/testsuite/{sim => }/aarch64/ChangeLog (100%) rename sim/testsuite/{sim => }/aarch64/adds.s (100%) rename sim/testsuite/{sim => }/aarch64/addv.s (100%) rename sim/testsuite/{sim => }/aarch64/allinsn.exp (100%) rename sim/testsuite/{sim => }/aarch64/bit.s (100%) rename sim/testsuite/{sim => }/aarch64/cmtst.s (100%) rename sim/testsuite/{sim => }/aarch64/cnt.s (100%) rename sim/testsuite/{sim => }/aarch64/fcmXX.s (100%) rename sim/testsuite/{sim => }/aarch64/fcmp.s (100%) rename sim/testsuite/{sim => }/aarch64/fcsel.s (100%) rename sim/testsuite/{sim => }/aarch64/fcvtl.s (100%) rename sim/testsuite/{sim => }/aarch64/fcvtz.s (100%) rename sim/testsuite/{sim => }/aarch64/fminnm.s (100%) rename sim/testsuite/{sim => }/aarch64/fstur.s (100%) rename sim/testsuite/{sim => }/aarch64/ldn_multiple.s (100%) rename sim/testsuite/{sim => }/aarch64/ldn_single.s (100%) rename sim/testsuite/{sim => }/aarch64/ldnr.s (100%) rename sim/testsuite/{sim => }/aarch64/mla.s (100%) rename sim/testsuite/{sim => }/aarch64/mls.s (100%) rename sim/testsuite/{sim => }/aarch64/mul.s (100%) rename sim/testsuite/{sim => }/aarch64/pass.s (100%) rename sim/testsuite/{sim => }/aarch64/stn_multiple.s (100%) rename sim/testsuite/{sim => }/aarch64/stn_single.s (100%) rename sim/testsuite/{sim => }/aarch64/sumov.s (100%) rename sim/testsuite/{sim => }/aarch64/sumulh.s (100%) rename sim/testsuite/{sim => }/aarch64/tbnz.s (100%) rename sim/testsuite/{sim => }/aarch64/testutils.inc (100%) rename sim/testsuite/{sim => }/aarch64/uzp.s (100%) rename sim/testsuite/{sim => }/aarch64/xtl.s (100%) rename sim/testsuite/{sim => }/aarch64/xtn.s (100%) rename sim/testsuite/{sim => }/arm/ChangeLog (100%) rename sim/testsuite/{sim => }/arm/adc.cgs (100%) rename sim/testsuite/{sim => }/arm/add.cgs (100%) rename sim/testsuite/{sim => }/arm/allinsn.exp (100%) rename sim/testsuite/{sim => }/arm/and.cgs (100%) rename sim/testsuite/{sim => }/arm/b.cgs (100%) rename sim/testsuite/{sim => }/arm/bic.cgs (100%) rename sim/testsuite/{sim => }/arm/bl.cgs (100%) rename sim/testsuite/{sim => }/arm/bx.cgs (100%) rename sim/testsuite/{sim => }/arm/cmn.cgs (100%) rename sim/testsuite/{sim => }/arm/cmp.cgs (100%) rename sim/testsuite/{sim => }/arm/eor.cgs (100%) rename sim/testsuite/{sim => }/arm/hello.ms (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/iwmmxt.exp (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/tbcst.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/testutils.inc (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/textrm.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/tinsr.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/tmia.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/tmiaph.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/tmiaxy.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/tmovmsk.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wacc.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wadd.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/waligni.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/walignr.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wand.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wandn.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wavg2.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wcmpeq.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wcmpgt.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wmac.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wmadd.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wmax.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wmin.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wmov.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wmul.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wor.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wpack.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wror.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wsad.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wshufh.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wsll.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wsra.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wsrl.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wsub.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wunpckeh.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wunpckel.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wunpckih.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wunpckil.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wxor.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wzero.cgs (100%) rename sim/testsuite/{sim => }/arm/ldm.cgs (100%) rename sim/testsuite/{sim => }/arm/ldr.cgs (100%) rename sim/testsuite/{sim => }/arm/ldrb.cgs (100%) rename sim/testsuite/{sim => }/arm/ldrh.cgs (100%) rename sim/testsuite/{sim => }/arm/ldrsb.cgs (100%) rename sim/testsuite/{sim => }/arm/ldrsh.cgs (100%) rename sim/testsuite/{sim => }/arm/misaligned1.ms (100%) rename sim/testsuite/{sim => }/arm/misaligned2.ms (100%) rename sim/testsuite/{sim => }/arm/misaligned3.ms (100%) rename sim/testsuite/{sim => }/arm/misc.exp (100%) rename sim/testsuite/{sim => }/arm/mla.cgs (100%) rename sim/testsuite/{sim => }/arm/mov.cgs (100%) rename sim/testsuite/{sim => }/arm/movw-movt.ms (100%) rename sim/testsuite/{sim => }/arm/mrs.cgs (100%) rename sim/testsuite/{sim => }/arm/msr.cgs (100%) rename sim/testsuite/{sim => }/arm/mul.cgs (100%) rename sim/testsuite/{sim => }/arm/mvn.cgs (100%) rename sim/testsuite/{sim => }/arm/orr.cgs (100%) rename sim/testsuite/{sim => }/arm/rsb.cgs (100%) rename sim/testsuite/{sim => }/arm/rsc.cgs (100%) rename sim/testsuite/{sim => }/arm/sbc.cgs (100%) rename sim/testsuite/{sim => }/arm/smlal.cgs (100%) rename sim/testsuite/{sim => }/arm/smull.cgs (100%) rename sim/testsuite/{sim => }/arm/stm.cgs (100%) rename sim/testsuite/{sim => }/arm/str.cgs (100%) rename sim/testsuite/{sim => }/arm/strb.cgs (100%) rename sim/testsuite/{sim => }/arm/strh.cgs (100%) rename sim/testsuite/{sim => }/arm/sub.cgs (100%) rename sim/testsuite/{sim => }/arm/swi.cgs (100%) rename sim/testsuite/{sim => }/arm/swp.cgs (100%) rename sim/testsuite/{sim => }/arm/swpb.cgs (100%) rename sim/testsuite/{sim => }/arm/teq.cgs (100%) rename sim/testsuite/{sim => }/arm/testutils.inc (100%) rename sim/testsuite/{sim => }/arm/thumb/adc.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/add-hd-hs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/add-hd-rs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/add-rd-hs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/add-sp.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/add.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/addi.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/addi8.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/allthumb.exp (100%) rename sim/testsuite/{sim => }/arm/thumb/and.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/asr.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/b.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bcc.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bcs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/beq.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bge.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bgt.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bhi.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bic.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bl-hi.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bl-lo.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ble.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bls.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/blt.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bmi.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bne.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bpl.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bvc.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bvs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bx-hs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bx-rs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/cmn.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/cmp-hd-hs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/cmp-hd-rs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/cmp-rd-hs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/cmp.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/eor.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/lda-pc.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/lda-sp.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldmia.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldr-imm.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldr-pc.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldr-sprel.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldr.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldrb-imm.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldrb.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldrh-imm.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldrh.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldsb.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldsh.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/lsl.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/lsr.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/mov-hd-hs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/mov-hd-rs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/mov-rd-hs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/mov.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/mul.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/mvn.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/neg.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/orr.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/pop-pc.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/pop.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/push-lr.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/push.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ror.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/sbc.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/stmia.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/str-imm.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/str-sprel.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/str.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/strb-imm.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/strb.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/strh-imm.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/strh.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/sub-sp.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/sub.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/subi.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/subi8.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/swi.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/testutils.inc (100%) rename sim/testsuite/{sim => }/arm/thumb/tst.cgs (100%) rename sim/testsuite/{sim => }/arm/tst.cgs (100%) rename sim/testsuite/{sim => }/arm/umlal.cgs (100%) rename sim/testsuite/{sim => }/arm/umull.cgs (100%) rename sim/testsuite/{sim => }/arm/xscale/blx.cgs (100%) rename sim/testsuite/{sim => }/arm/xscale/mia.cgs (100%) rename sim/testsuite/{sim => }/arm/xscale/miaph.cgs (100%) rename sim/testsuite/{sim => }/arm/xscale/miaxy.cgs (100%) rename sim/testsuite/{sim => }/arm/xscale/mra.cgs (100%) rename sim/testsuite/{sim => }/arm/xscale/testutils.inc (100%) rename sim/testsuite/{sim => }/arm/xscale/xscale.exp (100%) rename sim/testsuite/{sim => }/avr/ChangeLog (100%) rename sim/testsuite/{sim => }/avr/allinsn.exp (100%) rename sim/testsuite/{sim => }/avr/pass.s (100%) rename sim/testsuite/{sim => }/avr/testutils.inc (100%) rename sim/testsuite/{sim => }/bfin/.gitignore (100%) rename sim/testsuite/{sim => }/bfin/10272_small.s (100%) rename sim/testsuite/{sim => }/bfin/10436.s (100%) rename sim/testsuite/{sim => }/bfin/10622.s (100%) rename sim/testsuite/{sim => }/bfin/10742.s (100%) rename sim/testsuite/{sim => }/bfin/10799.s (100%) rename sim/testsuite/{sim => }/bfin/11080.s (100%) rename sim/testsuite/{sim => }/bfin/7641.s (100%) rename sim/testsuite/{sim => }/bfin/ChangeLog (100%) rename sim/testsuite/{sim => }/bfin/PN_generator.s (100%) rename sim/testsuite/{sim => }/bfin/a0.s (100%) rename sim/testsuite/{sim => }/bfin/a0shift.S (100%) rename sim/testsuite/{sim => }/bfin/a1.s (100%) rename sim/testsuite/{sim => }/bfin/a10.s (100%) rename sim/testsuite/{sim => }/bfin/a11.S (100%) rename sim/testsuite/{sim => }/bfin/a12.s (100%) rename sim/testsuite/{sim => }/bfin/a2.s (100%) rename sim/testsuite/{sim => }/bfin/a20.S (100%) rename sim/testsuite/{sim => }/bfin/a21.s (100%) rename sim/testsuite/{sim => }/bfin/a22.s (100%) rename sim/testsuite/{sim => }/bfin/a23.s (100%) rename sim/testsuite/{sim => }/bfin/a24.s (100%) rename sim/testsuite/{sim => }/bfin/a25.s (100%) rename sim/testsuite/{sim => }/bfin/a26.s (100%) rename sim/testsuite/{sim => }/bfin/a3.s (100%) rename sim/testsuite/{sim => }/bfin/a30.s (100%) rename sim/testsuite/{sim => }/bfin/a4.s (100%) rename sim/testsuite/{sim => }/bfin/a5.s (100%) rename sim/testsuite/{sim => }/bfin/a6.s (100%) rename sim/testsuite/{sim => }/bfin/a7.s (100%) rename sim/testsuite/{sim => }/bfin/a8.s (100%) rename sim/testsuite/{sim => }/bfin/a9.s (100%) rename sim/testsuite/{sim => }/bfin/abs-2.S (100%) rename sim/testsuite/{sim => }/bfin/abs-3.S (100%) rename sim/testsuite/{sim => }/bfin/abs-4.S (100%) rename sim/testsuite/{sim => }/bfin/abs.S (100%) rename sim/testsuite/{sim => }/bfin/abs_acc.s (100%) rename sim/testsuite/{sim => }/bfin/acc-rot.s (100%) rename sim/testsuite/{sim => }/bfin/acp5_19.s (100%) rename sim/testsuite/{sim => }/bfin/acp5_4.s (100%) rename sim/testsuite/{sim => }/bfin/add_imm7.s (100%) rename sim/testsuite/{sim => }/bfin/add_shift.S (100%) rename sim/testsuite/{sim => }/bfin/add_sub_acc.s (100%) rename sim/testsuite/{sim => }/bfin/addsub_flags.S (100%) rename sim/testsuite/{sim => }/bfin/algnbug1.s (100%) rename sim/testsuite/{sim => }/bfin/algnbug2.s (100%) rename sim/testsuite/{sim => }/bfin/allinsn.exp (100%) rename sim/testsuite/{sim => }/bfin/argc.c (100%) rename sim/testsuite/{sim => }/bfin/ashift.s (100%) rename sim/testsuite/{sim => }/bfin/ashift_flags.s (100%) rename sim/testsuite/{sim => }/bfin/ashift_left.s (100%) rename sim/testsuite/{sim => }/bfin/b0.S (100%) rename sim/testsuite/{sim => }/bfin/b1.s (100%) rename sim/testsuite/{sim => }/bfin/b2.S (100%) rename sim/testsuite/{sim => }/bfin/brcc.s (100%) rename sim/testsuite/{sim => }/bfin/brevadd.s (100%) rename sim/testsuite/{sim => }/bfin/byteop16m.s (100%) rename sim/testsuite/{sim => }/bfin/byteop16p.s (100%) rename sim/testsuite/{sim => }/bfin/byteop1p.s (100%) rename sim/testsuite/{sim => }/bfin/byteop2p.s (100%) rename sim/testsuite/{sim => }/bfin/byteop3p.s (100%) rename sim/testsuite/{sim => }/bfin/byteunpack.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_arith_r_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_neg.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_toggle.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_divq.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_divs.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_log_l_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_log_r_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_shadd_1.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_shadd_2.s (100%) rename sim/testsuite/{sim => }/bfin/c_br_preg_killed_ac.s (100%) rename sim/testsuite/{sim => }/bfin/c_br_preg_killed_ex1.s (100%) rename sim/testsuite/{sim => }/bfin/c_br_preg_stall_ac.s (100%) rename sim/testsuite/{sim => }/bfin/c_br_preg_stall_ex1.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_bp1.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_bp2.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_bp3.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_bp4.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brf_bp.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_bp.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_nbp.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brf_fbkwd.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brf_nbp.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brt_bp.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brt_nbp.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_kills_dhits.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_kills_dmiss.s (100%) rename sim/testsuite/{sim => }/bfin/c_cactrl_iflush_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_cactrl_iflush_pr_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_calla_ljump.s (100%) rename sim/testsuite/{sim => }/bfin/c_calla_subr.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc2dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_ac.S (100%) rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_an.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_aq.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av0.S (100%) rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av1.S (100%) rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_az.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc_flag_ccmv_depend.S (100%) rename sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft_s1.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft_sn.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft_s1.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft_sn.S (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_a0a1.S (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr_uu.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3_uu.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3_uu.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr_uu.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_cc_pr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_ncc_pr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_and_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_minus_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_or_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_plus_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_xor_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_pr_plus_pr_sh1.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_pr_plus_pr_sh2.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_add_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_add_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_eq_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_eq_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_flags.S (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_flags_2.S (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_add_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_add_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_eq_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_eq_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodik_lnz_imgebl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodik_lnz_imltbl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodik_lz_inc_dec.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodim_lnz_imgebl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodim_lnz_imltbl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodim_lz_inc_dec.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a0_pm_a1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a0a1s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a_abs_a.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a_neg_a.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_aa_absabs.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_aa_negneg.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_abs.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_absabs.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_alhwx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_awx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop1ew.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop2.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop3.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_bytepack.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteunpack.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_disalnexcpt.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_max.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_maxmax.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_min.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_minmin.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_r_lh_a0pa1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_r_negneg.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd12_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd12_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd20_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd20_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd12_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd12_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd20_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd20_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rlh_rnd.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rmm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rmp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rpm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rpp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rr_lph_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm_aa.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp_sft_x.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm_sft_x.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_saa.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_sat_aa.S (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_search.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_sgn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_iuw32.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_ih.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_iu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_tu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_ih.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_iu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_tu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0_iutsh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_ih.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_iu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_iutsh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_tu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_a0alr.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_af.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_af_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align16.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align24.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align8.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_amix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bitmux.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bxor.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_l.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expexp_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fdepx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fextx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lf.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lmix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ones.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_pack.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_rot.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_rot_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_rh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_rl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_vmax.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_vmaxvmax.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_a0alr.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_ln_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_lp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rn_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_amix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lf.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lmix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_rot.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ippm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ippm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_except_illopcode.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_sys_sstep.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_user_mode.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable_enable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_excpt.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_loopsetup_stld.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nested.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nmi.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending_2.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_reload.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_tcount.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_tscale.S (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_drhi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_drlo.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_pibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_ppmm_hbx.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_st_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_st_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_st_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_hi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_lo.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_h_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_lohi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_hi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_lo.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_lohi.s (100%) rename sim/testsuite/{sim => }/bfin/c_linkage.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_alshft_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_arith_shft.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bitclr.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bitset.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bittgl.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bittst.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_l_shft.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_l_shft_astat.S (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_r_shft.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_r_shft_astat.S (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_nbittst.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_bot.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_prelc.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_top.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_overlap.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_div2_lc0.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_div2_lc1.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_lc0.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_lc1.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_stld.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_prelc.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_topbotcntr.s (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_interr_ctl.s (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_loop.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_loop_user_except.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_ppop_illegal_adr.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_ppopm_illegal_adr.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_timer.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_supervisor.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_user.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_user_superivsor.S (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ld_ld.s (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ldst_1.s (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ldst_2.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_call_pcpr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_call_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_clisti_interr.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_csync_mmr.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_except_rtx.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_excpt.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_jump_pcpr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_jump_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_nop.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_raise_rt_i_n.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_rts.s (100%) rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_neg_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_sft_2_1.s (100%) rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_shadd_1_2.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dp.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dp_pair.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_acc_acc.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dag_lz_dep.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_acc_acc.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_dep_nostall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_imlb.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dep_nostall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dep_stall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_imlb.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dep_nostall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dep_stall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_imlb.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ac_raise_mv.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ac_raise_mv_ppop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ac_regmv_pushpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_dec_raise_pushpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_brcc_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_call_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_j_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_brcc_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_call_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_j_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_brcc_mp_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_mmr_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_mmrj_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_raise_mmr_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_raise_mmrj_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_brcc_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_mmr_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_mmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_cs_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_rti_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_rtn_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_rtx_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_ujump.s (100%) rename sim/testsuite/{sim => }/bfin/cc-alu.S (100%) rename sim/testsuite/{sim => }/bfin/cc-astat-bits.s (100%) rename sim/testsuite/{sim => }/bfin/cc0.s (100%) rename sim/testsuite/{sim => }/bfin/cc1.s (100%) rename sim/testsuite/{sim => }/bfin/cc5.S (100%) rename sim/testsuite/{sim => }/bfin/cec-exact-exception.S (100%) rename sim/testsuite/{sim => }/bfin/cec-ifetch.S (100%) rename sim/testsuite/{sim => }/bfin/cec-multi-pending.S (100%) rename sim/testsuite/{sim => }/bfin/cec-no-snen-reti.S (100%) rename sim/testsuite/{sim => }/bfin/cec-non-operating-env.s (100%) rename sim/testsuite/{sim => }/bfin/cec-raise-reti.S (100%) rename sim/testsuite/{sim => }/bfin/cec-snen-reti.S (100%) rename sim/testsuite/{sim => }/bfin/cec-syscfg-ssstep.S (100%) rename sim/testsuite/{sim => }/bfin/cec-system-call.S (100%) rename sim/testsuite/{sim => }/bfin/cir.s (100%) rename sim/testsuite/{sim => }/bfin/cir1.s (100%) rename sim/testsuite/{sim => }/bfin/cli-sti.s (100%) rename sim/testsuite/{sim => }/bfin/cmpacc.s (100%) rename sim/testsuite/{sim => }/bfin/cmpdreg.S (100%) rename sim/testsuite/{sim => }/bfin/compare.s (100%) rename sim/testsuite/{sim => }/bfin/conv_enc_gen.s (100%) rename sim/testsuite/{sim => }/bfin/cycles.s (100%) rename sim/testsuite/{sim => }/bfin/d0.s (100%) rename sim/testsuite/{sim => }/bfin/d1.s (100%) rename sim/testsuite/{sim => }/bfin/d2.s (100%) rename sim/testsuite/{sim => }/bfin/dbg_brprd_ntkn_src_kill.S (100%) rename sim/testsuite/{sim => }/bfin/dbg_brtkn_nprd_src_kill.S (100%) rename sim/testsuite/{sim => }/bfin/dbg_jmp_src_kill.S (100%) rename sim/testsuite/{sim => }/bfin/dbg_tr_basic.S (100%) rename sim/testsuite/{sim => }/bfin/dbg_tr_simplejp.S (100%) rename sim/testsuite/{sim => }/bfin/dbg_tr_tbuf0.S (100%) rename sim/testsuite/{sim => }/bfin/dbg_tr_umode.S (100%) rename sim/testsuite/{sim => }/bfin/disalnexcpt_implicit.S (100%) rename sim/testsuite/{sim => }/bfin/div0.s (100%) rename sim/testsuite/{sim => }/bfin/divq.s (100%) rename sim/testsuite/{sim => }/bfin/dotproduct.s (100%) rename sim/testsuite/{sim => }/bfin/dotproduct2.s (100%) rename sim/testsuite/{sim => }/bfin/double_prec_mult.s (100%) rename sim/testsuite/{sim => }/bfin/dsp_a4.s (100%) rename sim/testsuite/{sim => }/bfin/dsp_a7.s (100%) rename sim/testsuite/{sim => }/bfin/dsp_a8.s (100%) rename sim/testsuite/{sim => }/bfin/dsp_d0.s (100%) rename sim/testsuite/{sim => }/bfin/dsp_d1.s (100%) rename sim/testsuite/{sim => }/bfin/dsp_neg.S (100%) rename sim/testsuite/{sim => }/bfin/dsp_s1.s (100%) rename sim/testsuite/{sim => }/bfin/e0.s (100%) rename sim/testsuite/{sim => }/bfin/edn_snafu.s (100%) rename sim/testsuite/{sim => }/bfin/eu_dsp32mac_s.s (100%) rename sim/testsuite/{sim => }/bfin/events.s (100%) rename sim/testsuite/{sim => }/bfin/f221.s (100%) rename sim/testsuite/{sim => }/bfin/fact.s (100%) rename sim/testsuite/{sim => }/bfin/fir.s (100%) rename sim/testsuite/{sim => }/bfin/fsm.s (100%) rename sim/testsuite/{sim => }/bfin/greg2.s (100%) rename sim/testsuite/{sim => }/bfin/hwloop-bits.S (100%) rename sim/testsuite/{sim => }/bfin/hwloop-branch-in.s (100%) rename sim/testsuite/{sim => }/bfin/hwloop-branch-out.s (100%) rename sim/testsuite/{sim => }/bfin/hwloop-lt-bits.s (100%) rename sim/testsuite/{sim => }/bfin/hwloop-nested.s (100%) rename sim/testsuite/{sim => }/bfin/i0.s (100%) rename sim/testsuite/{sim => }/bfin/iir.s (100%) rename sim/testsuite/{sim => }/bfin/issue103.s (100%) rename sim/testsuite/{sim => }/bfin/issue109.s (100%) rename sim/testsuite/{sim => }/bfin/issue112.s (100%) rename sim/testsuite/{sim => }/bfin/issue113.s (100%) rename sim/testsuite/{sim => }/bfin/issue117.s (100%) rename sim/testsuite/{sim => }/bfin/issue118.s (100%) rename sim/testsuite/{sim => }/bfin/issue119.s (100%) rename sim/testsuite/{sim => }/bfin/issue121.s (100%) rename sim/testsuite/{sim => }/bfin/issue123.s (100%) rename sim/testsuite/{sim => }/bfin/issue124.s (100%) rename sim/testsuite/{sim => }/bfin/issue125.s (100%) rename sim/testsuite/{sim => }/bfin/issue126.s (100%) rename sim/testsuite/{sim => }/bfin/issue127.s (100%) rename sim/testsuite/{sim => }/bfin/issue129.s (100%) rename sim/testsuite/{sim => }/bfin/issue139.S (100%) rename sim/testsuite/{sim => }/bfin/issue140.S (100%) rename sim/testsuite/{sim => }/bfin/issue142.s (100%) rename sim/testsuite/{sim => }/bfin/issue144.s (100%) rename sim/testsuite/{sim => }/bfin/issue146.S (100%) rename sim/testsuite/{sim => }/bfin/issue175.s (100%) rename sim/testsuite/{sim => }/bfin/issue205.s (100%) rename sim/testsuite/{sim => }/bfin/issue257.s (100%) rename sim/testsuite/{sim => }/bfin/issue272.S (100%) rename sim/testsuite/{sim => }/bfin/issue83.s (100%) rename sim/testsuite/{sim => }/bfin/issue89.s (100%) rename sim/testsuite/{sim => }/bfin/l0.s (100%) rename sim/testsuite/{sim => }/bfin/l0shift.s (100%) rename sim/testsuite/{sim => }/bfin/l2_loop.s (100%) rename sim/testsuite/{sim => }/bfin/link-2.s (100%) rename sim/testsuite/{sim => }/bfin/link.s (100%) rename sim/testsuite/{sim => }/bfin/lmu_cplb_multiple0.S (100%) rename sim/testsuite/{sim => }/bfin/lmu_cplb_multiple1.S (100%) rename sim/testsuite/{sim => }/bfin/lmu_excpt_align.S (100%) rename sim/testsuite/{sim => }/bfin/lmu_excpt_default.S (100%) rename sim/testsuite/{sim => }/bfin/lmu_excpt_illaddr.S (100%) rename sim/testsuite/{sim => }/bfin/lmu_excpt_prot0.S (100%) rename sim/testsuite/{sim => }/bfin/lmu_excpt_prot1.S (100%) rename sim/testsuite/{sim => }/bfin/load.s (100%) rename sim/testsuite/{sim => }/bfin/logic.s (100%) rename sim/testsuite/{sim => }/bfin/loop_snafu.s (100%) rename sim/testsuite/{sim => }/bfin/loop_strncpy.s (100%) rename sim/testsuite/{sim => }/bfin/lp0.s (100%) rename sim/testsuite/{sim => }/bfin/lp1.s (100%) rename sim/testsuite/{sim => }/bfin/lsetup.s (100%) rename sim/testsuite/{sim => }/bfin/m0boundary.s (100%) rename sim/testsuite/{sim => }/bfin/m1.S (100%) rename sim/testsuite/{sim => }/bfin/m10.s (100%) rename sim/testsuite/{sim => }/bfin/m11.s (100%) rename sim/testsuite/{sim => }/bfin/m12.s (100%) rename sim/testsuite/{sim => }/bfin/m13.s (100%) rename sim/testsuite/{sim => }/bfin/m14.s (100%) rename sim/testsuite/{sim => }/bfin/m15.s (100%) rename sim/testsuite/{sim => }/bfin/m16.s (100%) rename sim/testsuite/{sim => }/bfin/m17.s (100%) rename sim/testsuite/{sim => }/bfin/m2.s (100%) rename sim/testsuite/{sim => }/bfin/m3.s (100%) rename sim/testsuite/{sim => }/bfin/m4.s (100%) rename sim/testsuite/{sim => }/bfin/m5.s (100%) rename sim/testsuite/{sim => }/bfin/m6.s (100%) rename sim/testsuite/{sim => }/bfin/m7.s (100%) rename sim/testsuite/{sim => }/bfin/m8.s (100%) rename sim/testsuite/{sim => }/bfin/m9.s (100%) rename sim/testsuite/{sim => }/bfin/mac2halfreg.S (100%) rename sim/testsuite/{sim => }/bfin/math.s (100%) rename sim/testsuite/{sim => }/bfin/max_min_flags.s (100%) rename sim/testsuite/{sim => }/bfin/mc_s2.s (100%) rename sim/testsuite/{sim => }/bfin/mdma-32bit-1d-neg-count.c (100%) rename sim/testsuite/{sim => }/bfin/mdma-32bit-1d.c (100%) rename sim/testsuite/{sim => }/bfin/mdma-8bit-1d-neg-count.c (100%) rename sim/testsuite/{sim => }/bfin/mdma-8bit-1d.c (100%) rename sim/testsuite/{sim => }/bfin/mdma-skel.h (100%) rename sim/testsuite/{sim => }/bfin/mem3.s (100%) rename sim/testsuite/{sim => }/bfin/mmr-exception.s (100%) rename sim/testsuite/{sim => }/bfin/move.s (100%) rename sim/testsuite/{sim => }/bfin/msa_acp_5.10.S (100%) rename sim/testsuite/{sim => }/bfin/msa_acp_5.12_1.S (100%) rename sim/testsuite/{sim => }/bfin/msa_acp_5.12_2.S (100%) rename sim/testsuite/{sim => }/bfin/msa_acp_5_10.s (100%) rename sim/testsuite/{sim => }/bfin/mult.s (100%) rename sim/testsuite/{sim => }/bfin/neg-2.S (100%) rename sim/testsuite/{sim => }/bfin/neg-3.S (100%) rename sim/testsuite/{sim => }/bfin/neg.S (100%) rename sim/testsuite/{sim => }/bfin/nshift.s (100%) rename sim/testsuite/{sim => }/bfin/pr.s (100%) rename sim/testsuite/{sim => }/bfin/push-pop-multiple.s (100%) rename sim/testsuite/{sim => }/bfin/push-pop.s (100%) rename sim/testsuite/{sim => }/bfin/pushpopreg_1.s (100%) rename sim/testsuite/{sim => }/bfin/quadaddsub.s (100%) rename sim/testsuite/{sim => }/bfin/random_0001.s (100%) rename sim/testsuite/{sim => }/bfin/random_0002.S (100%) rename sim/testsuite/{sim => }/bfin/random_0003.S (100%) rename sim/testsuite/{sim => }/bfin/random_0004.S (100%) rename sim/testsuite/{sim => }/bfin/random_0005.S (100%) rename sim/testsuite/{sim => }/bfin/random_0006.S (100%) rename sim/testsuite/{sim => }/bfin/random_0007.S (100%) rename sim/testsuite/{sim => }/bfin/random_0008.S (100%) rename sim/testsuite/{sim => }/bfin/random_0009.S (100%) rename sim/testsuite/{sim => }/bfin/random_0010.S (100%) rename sim/testsuite/{sim => }/bfin/random_0011.S (100%) rename sim/testsuite/{sim => }/bfin/random_0012.S (100%) rename sim/testsuite/{sim => }/bfin/random_0013.S (100%) rename sim/testsuite/{sim => }/bfin/random_0014.S (100%) rename sim/testsuite/{sim => }/bfin/random_0015.S (100%) rename sim/testsuite/{sim => }/bfin/random_0016.S (100%) rename sim/testsuite/{sim => }/bfin/random_0017.S (100%) rename sim/testsuite/{sim => }/bfin/random_0018.S (100%) rename sim/testsuite/{sim => }/bfin/random_0019.S (100%) rename sim/testsuite/{sim => }/bfin/random_0020.S (100%) rename sim/testsuite/{sim => }/bfin/random_0021.S (100%) rename sim/testsuite/{sim => }/bfin/random_0022.S (100%) rename sim/testsuite/{sim => }/bfin/random_0023.S (100%) rename sim/testsuite/{sim => }/bfin/random_0024.S (100%) rename sim/testsuite/{sim => }/bfin/random_0025.S (100%) rename sim/testsuite/{sim => }/bfin/random_0026.S (100%) rename sim/testsuite/{sim => }/bfin/random_0027.S (100%) rename sim/testsuite/{sim => }/bfin/random_0028.S (100%) rename sim/testsuite/{sim => }/bfin/random_0029.S (100%) rename sim/testsuite/{sim => }/bfin/random_0030.S (100%) rename sim/testsuite/{sim => }/bfin/random_0031.S (100%) rename sim/testsuite/{sim => }/bfin/random_0032.S (100%) rename sim/testsuite/{sim => }/bfin/random_0033.S (100%) rename sim/testsuite/{sim => }/bfin/random_0034.S (100%) rename sim/testsuite/{sim => }/bfin/random_0035.S (100%) rename sim/testsuite/{sim => }/bfin/random_0036.S (100%) rename sim/testsuite/{sim => }/bfin/random_0037.S (100%) rename sim/testsuite/{sim => }/bfin/run-tests.sh (100%) rename sim/testsuite/{sim => }/bfin/s0.s (100%) rename sim/testsuite/{sim => }/bfin/s1.s (100%) rename sim/testsuite/{sim => }/bfin/s10.s (100%) rename sim/testsuite/{sim => }/bfin/s11.s (100%) rename sim/testsuite/{sim => }/bfin/s12.s (100%) rename sim/testsuite/{sim => }/bfin/s13.s (100%) rename sim/testsuite/{sim => }/bfin/s14.s (100%) rename sim/testsuite/{sim => }/bfin/s15.s (100%) rename sim/testsuite/{sim => }/bfin/s16.s (100%) rename sim/testsuite/{sim => }/bfin/s17.s (100%) rename sim/testsuite/{sim => }/bfin/s18.s (100%) rename sim/testsuite/{sim => }/bfin/s19.s (100%) rename sim/testsuite/{sim => }/bfin/s2.s (100%) rename sim/testsuite/{sim => }/bfin/s20.s (100%) rename sim/testsuite/{sim => }/bfin/s21.s (100%) rename sim/testsuite/{sim => }/bfin/s3.s (100%) rename sim/testsuite/{sim => }/bfin/s30.s (100%) rename sim/testsuite/{sim => }/bfin/s4.s (100%) rename sim/testsuite/{sim => }/bfin/s5.s (100%) rename sim/testsuite/{sim => }/bfin/s6.s (100%) rename sim/testsuite/{sim => }/bfin/s7.s (100%) rename sim/testsuite/{sim => }/bfin/s8.s (100%) rename sim/testsuite/{sim => }/bfin/s9.s (100%) rename sim/testsuite/{sim => }/bfin/saatest.s (100%) rename sim/testsuite/{sim => }/bfin/se_all16bitopcodes.S (100%) rename sim/testsuite/{sim => }/bfin/se_all32bitopcodes.S (100%) rename sim/testsuite/{sim => }/bfin/se_all32bitopcodes.lds (100%) rename sim/testsuite/{sim => }/bfin/se_all64bitg0opcodes.S (100%) rename sim/testsuite/{sim => }/bfin/se_all64bitg1opcodes.S (100%) rename sim/testsuite/{sim => }/bfin/se_all64bitg2opcodes.S (100%) rename sim/testsuite/{sim => }/bfin/se_allopcodes.h (100%) rename sim/testsuite/{sim => }/bfin/se_brtarget_stall.S (100%) rename sim/testsuite/{sim => }/bfin/se_bug_ui.S (100%) rename sim/testsuite/{sim => }/bfin/se_bug_ui2.S (100%) rename sim/testsuite/{sim => }/bfin/se_bug_ui3.S (100%) rename sim/testsuite/{sim => }/bfin/se_cc2stat_haz.S (100%) rename sim/testsuite/{sim => }/bfin/se_cc_kill.S (100%) rename sim/testsuite/{sim => }/bfin/se_cof.S (100%) rename sim/testsuite/{sim => }/bfin/se_event_quad.S (100%) rename sim/testsuite/{sim => }/bfin/se_excpt_dagprotviol.S (100%) rename sim/testsuite/{sim => }/bfin/se_excpt_ifprotviol.S (100%) rename sim/testsuite/{sim => }/bfin/se_excpt_ssstep.S (100%) rename sim/testsuite/{sim => }/bfin/se_illegalcombination.S (100%) rename sim/testsuite/{sim => }/bfin/se_kill_wbbr.S (100%) rename sim/testsuite/{sim => }/bfin/se_kills2.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_disable.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_kill.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_kill_01.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_kill_dcr.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_kill_dcr_01.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_lr.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_mv2lb_stall.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_mv2lc.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_mv2lc_stall.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_mv2lt_stall.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_nest_ppm.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_nest_ppm_1.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_nest_ppm_2.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_ppm.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_ppm_1.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_ppm_int.S (100%) rename sim/testsuite/{sim => }/bfin/se_lsetup_kill.S (100%) rename sim/testsuite/{sim => }/bfin/se_misaligned_fetch.S (100%) rename sim/testsuite/{sim => }/bfin/se_more_ret_haz.S (100%) rename sim/testsuite/{sim => }/bfin/se_mv2lp.S (100%) rename sim/testsuite/{sim => }/bfin/se_oneins_zoff.S (100%) rename sim/testsuite/{sim => }/bfin/se_popkill.S (100%) rename sim/testsuite/{sim => }/bfin/se_regmv_usp_sysreg.S (100%) rename sim/testsuite/{sim => }/bfin/se_rets_hazard.s (100%) rename sim/testsuite/{sim => }/bfin/se_rts_rti.S (100%) rename sim/testsuite/{sim => }/bfin/se_ssstep_dagprotviol.S (100%) rename sim/testsuite/{sim => }/bfin/se_ssync.S (100%) rename sim/testsuite/{sim => }/bfin/se_stall_if2.S (100%) rename sim/testsuite/{sim => }/bfin/se_undefinedinstruction1.S (100%) rename sim/testsuite/{sim => }/bfin/se_undefinedinstruction2.S (100%) rename sim/testsuite/{sim => }/bfin/se_undefinedinstruction3.S (100%) rename sim/testsuite/{sim => }/bfin/se_undefinedinstruction4.S (100%) rename sim/testsuite/{sim => }/bfin/se_usermode_protviol.S (100%) rename sim/testsuite/{sim => }/bfin/seqstat.s (100%) rename sim/testsuite/{sim => }/bfin/sign.s (100%) rename sim/testsuite/{sim => }/bfin/simple0.s (100%) rename sim/testsuite/{sim => }/bfin/sri.s (100%) rename sim/testsuite/{sim => }/bfin/stk.s (100%) rename sim/testsuite/{sim => }/bfin/stk2.s (100%) rename sim/testsuite/{sim => }/bfin/stk3.s (100%) rename sim/testsuite/{sim => }/bfin/stk4.s (100%) rename sim/testsuite/{sim => }/bfin/stk5.s (100%) rename sim/testsuite/{sim => }/bfin/stk6.s (100%) rename sim/testsuite/{sim => }/bfin/syscfg.s (100%) rename sim/testsuite/{sim => }/bfin/tar10622.s (100%) rename sim/testsuite/{sim => }/bfin/test-dma.h (100%) rename sim/testsuite/{sim => }/bfin/test.h (100%) rename sim/testsuite/{sim => }/bfin/testset.s (100%) rename sim/testsuite/{sim => }/bfin/testset2.s (100%) rename sim/testsuite/{sim => }/bfin/testutils.inc (100%) rename sim/testsuite/{sim => }/bfin/unlink.S (100%) rename sim/testsuite/{sim => }/bfin/up0.s (100%) rename sim/testsuite/{sim => }/bfin/usp.S (100%) rename sim/testsuite/{sim => }/bfin/vec-abs-2.S (100%) rename sim/testsuite/{sim => }/bfin/vec-abs-3.S (100%) rename sim/testsuite/{sim => }/bfin/vec-abs.S (100%) rename sim/testsuite/{sim => }/bfin/vec-neg-2.S (100%) rename sim/testsuite/{sim => }/bfin/vec-neg-3.S (100%) rename sim/testsuite/{sim => }/bfin/vec-neg.S (100%) rename sim/testsuite/{sim => }/bfin/vecadd.s (100%) rename sim/testsuite/{sim => }/bfin/vit_max.s (100%) rename sim/testsuite/{sim => }/bfin/vit_max2.s (100%) rename sim/testsuite/{sim => }/bfin/viterbi2.s (100%) rename sim/testsuite/{sim => }/bfin/wtf.s (100%) rename sim/testsuite/{sim => }/bfin/x1.s (100%) rename sim/testsuite/{sim => }/bfin/zcall.s (100%) rename sim/testsuite/{sim => }/bfin/zeroflagrnd.s (100%) rename sim/testsuite/{sim => }/bpf/ChangeLog (100%) rename sim/testsuite/{sim => }/bpf/allinsn.exp (100%) rename sim/testsuite/{sim => }/bpf/alu.s (100%) rename sim/testsuite/{sim => }/bpf/alu32.s (100%) rename sim/testsuite/{sim => }/bpf/endbe.s (100%) rename sim/testsuite/{sim => }/bpf/endle.s (100%) rename sim/testsuite/{sim => }/bpf/jmp.s (100%) rename sim/testsuite/{sim => }/bpf/jmp32.s (100%) rename sim/testsuite/{sim => }/bpf/ldabs.s (100%) rename sim/testsuite/{sim => }/bpf/mem.s (100%) rename sim/testsuite/{sim => }/bpf/mov.s (100%) rename sim/testsuite/{sim => }/bpf/testutils.inc (100%) rename sim/testsuite/{sim => }/bpf/xadd.s (100%) rename sim/testsuite/{sim => }/cr16/ChangeLog (100%) rename sim/testsuite/{sim => }/cr16/addb.cgs (100%) rename sim/testsuite/{sim => }/cr16/addd.cgs (100%) rename sim/testsuite/{sim => }/cr16/addi.cgs (100%) rename sim/testsuite/{sim => }/cr16/addw.cgs (100%) rename sim/testsuite/{sim => }/cr16/allinsn.exp (100%) rename sim/testsuite/{sim => }/cr16/andb.cgs (100%) rename sim/testsuite/{sim => }/cr16/andd.cgs (100%) rename sim/testsuite/{sim => }/cr16/andw.cgs (100%) rename sim/testsuite/{sim => }/cr16/ashub.cgs (100%) rename sim/testsuite/{sim => }/cr16/ashub_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/ashud.cgs (100%) rename sim/testsuite/{sim => }/cr16/ashud_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/ashuw.cgs (100%) rename sim/testsuite/{sim => }/cr16/ashuw_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/bal1_24.cgs (100%) rename sim/testsuite/{sim => }/cr16/bal2_24.cgs (100%) rename sim/testsuite/{sim => }/cr16/bcc.cgs (100%) rename sim/testsuite/{sim => }/cr16/bcs.cgs (100%) rename sim/testsuite/{sim => }/cr16/beq.cgs (100%) rename sim/testsuite/{sim => }/cr16/beq0b.cgs (100%) rename sim/testsuite/{sim => }/cr16/beq0w.cgs (100%) rename sim/testsuite/{sim => }/cr16/bge.cgs (100%) rename sim/testsuite/{sim => }/cr16/bgt.cgs (100%) rename sim/testsuite/{sim => }/cr16/bhi.cgs (100%) rename sim/testsuite/{sim => }/cr16/bhs.cgs (100%) rename sim/testsuite/{sim => }/cr16/bht.cgs (100%) rename sim/testsuite/{sim => }/cr16/blo.cgs (100%) rename sim/testsuite/{sim => }/cr16/bls.cgs (100%) rename sim/testsuite/{sim => }/cr16/blt.cgs (100%) rename sim/testsuite/{sim => }/cr16/bne.cgs (100%) rename sim/testsuite/{sim => }/cr16/bne0b.cgs (100%) rename sim/testsuite/{sim => }/cr16/bne0w.cgs (100%) rename sim/testsuite/{sim => }/cr16/br.cgs (100%) rename sim/testsuite/{sim => }/cr16/cbitb.cgs (100%) rename sim/testsuite/{sim => }/cr16/cbitw.cgs (100%) rename sim/testsuite/{sim => }/cr16/cmpb.cgs (100%) rename sim/testsuite/{sim => }/cr16/cmpb_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/cmpd.cgs (100%) rename sim/testsuite/{sim => }/cr16/cmpd_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/cmpi.cgs (100%) rename sim/testsuite/{sim => }/cr16/cmpw.cgs (100%) rename sim/testsuite/{sim => }/cr16/cmpw_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/excp.cgs (100%) rename sim/testsuite/{sim => }/cr16/hello.ms (100%) rename sim/testsuite/{sim => }/cr16/hw-trap.ms (100%) rename sim/testsuite/{sim => }/cr16/jal.cgs (100%) rename sim/testsuite/{sim => }/cr16/jcc.cgs (100%) rename sim/testsuite/{sim => }/cr16/jcs.cgs (100%) rename sim/testsuite/{sim => }/cr16/jeq.cgs (100%) rename sim/testsuite/{sim => }/cr16/jfc.cgs (100%) rename sim/testsuite/{sim => }/cr16/jfs.cgs (100%) rename sim/testsuite/{sim => }/cr16/jge.cgs (100%) rename sim/testsuite/{sim => }/cr16/jgt.cgs (100%) rename sim/testsuite/{sim => }/cr16/jhi.cgs (100%) rename sim/testsuite/{sim => }/cr16/jhs.cgs (100%) rename sim/testsuite/{sim => }/cr16/jlo.cgs (100%) rename sim/testsuite/{sim => }/cr16/jls.cgs (100%) rename sim/testsuite/{sim => }/cr16/jlt.cgs (100%) rename sim/testsuite/{sim => }/cr16/jne.cgs (100%) rename sim/testsuite/{sim => }/cr16/jump.cgs (100%) rename sim/testsuite/{sim => }/cr16/loadb.cgs (100%) rename sim/testsuite/{sim => }/cr16/loadd.cgs (100%) rename sim/testsuite/{sim => }/cr16/loadm.cgs (100%) rename sim/testsuite/{sim => }/cr16/loadmp.cgs (100%) rename sim/testsuite/{sim => }/cr16/loadw.cgs (100%) rename sim/testsuite/{sim => }/cr16/lpr-spr.cgs (100%) rename sim/testsuite/{sim => }/cr16/lprd-sprd.cgs (100%) rename sim/testsuite/{sim => }/cr16/lshb.cgs (100%) rename sim/testsuite/{sim => }/cr16/lshb_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/lshd.cgs (100%) rename sim/testsuite/{sim => }/cr16/lshd_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/lshw.cgs (100%) rename sim/testsuite/{sim => }/cr16/lshw_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/macqw.cgs (100%) rename sim/testsuite/{sim => }/cr16/macsw.cgs (100%) rename sim/testsuite/{sim => }/cr16/macuw.cgs (100%) rename sim/testsuite/{sim => }/cr16/misc.exp (100%) rename sim/testsuite/{sim => }/cr16/movb.cgs (100%) rename sim/testsuite/{sim => }/cr16/movd.cgs (100%) rename sim/testsuite/{sim => }/cr16/movw.cgs (100%) rename sim/testsuite/{sim => }/cr16/movxb.cgs (100%) rename sim/testsuite/{sim => }/cr16/movxw.cgs (100%) rename sim/testsuite/{sim => }/cr16/movzb.cgs (100%) rename sim/testsuite/{sim => }/cr16/movzw.cgs (100%) rename sim/testsuite/{sim => }/cr16/mulb.cgs (100%) rename sim/testsuite/{sim => }/cr16/mulsb.cgs (100%) rename sim/testsuite/{sim => }/cr16/mulsw.cgs (100%) rename sim/testsuite/{sim => }/cr16/muluw.cgs (100%) rename sim/testsuite/{sim => }/cr16/mulw.cgs (100%) rename sim/testsuite/{sim => }/cr16/nop.cgs (100%) rename sim/testsuite/{sim => }/cr16/orb.cgs (100%) rename sim/testsuite/{sim => }/cr16/ord.cgs (100%) rename sim/testsuite/{sim => }/cr16/orw.cgs (100%) rename sim/testsuite/{sim => }/cr16/pop1.cgs (100%) rename sim/testsuite/{sim => }/cr16/pop2.cgs (100%) rename sim/testsuite/{sim => }/cr16/pop3.cgs (100%) rename sim/testsuite/{sim => }/cr16/popret1.cgs (100%) rename sim/testsuite/{sim => }/cr16/popret2.cgs (100%) rename sim/testsuite/{sim => }/cr16/popret3.cgs (100%) rename sim/testsuite/{sim => }/cr16/push1.cgs (100%) rename sim/testsuite/{sim => }/cr16/push2.cgs (100%) rename sim/testsuite/{sim => }/cr16/push3.cgs (100%) rename sim/testsuite/{sim => }/cr16/sbitb.cgs (100%) rename sim/testsuite/{sim => }/cr16/sbitw.cgs (100%) rename sim/testsuite/{sim => }/cr16/scc.cgs (100%) rename sim/testsuite/{sim => }/cr16/scs.cgs (100%) rename sim/testsuite/{sim => }/cr16/seq.cgs (100%) rename sim/testsuite/{sim => }/cr16/sfc.cgs (100%) rename sim/testsuite/{sim => }/cr16/sfs.cgs (100%) rename sim/testsuite/{sim => }/cr16/sge.cgs (100%) rename sim/testsuite/{sim => }/cr16/sgt.cgs (100%) rename sim/testsuite/{sim => }/cr16/shi.cgs (100%) rename sim/testsuite/{sim => }/cr16/shs.cgs (100%) rename sim/testsuite/{sim => }/cr16/slo.cgs (100%) rename sim/testsuite/{sim => }/cr16/sls.cgs (100%) rename sim/testsuite/{sim => }/cr16/slt.cgs (100%) rename sim/testsuite/{sim => }/cr16/sne.cgs (100%) rename sim/testsuite/{sim => }/cr16/storb.cgs (100%) rename sim/testsuite/{sim => }/cr16/stord.cgs (100%) rename sim/testsuite/{sim => }/cr16/storw.cgs (100%) rename sim/testsuite/{sim => }/cr16/subb.cgs (100%) rename sim/testsuite/{sim => }/cr16/subd.cgs (100%) rename sim/testsuite/{sim => }/cr16/subi.cgs (100%) rename sim/testsuite/{sim => }/cr16/subw.cgs (100%) rename sim/testsuite/{sim => }/cr16/tbit.cgs (100%) rename sim/testsuite/{sim => }/cr16/tbitb.cgs (100%) rename sim/testsuite/{sim => }/cr16/tbitw.cgs (100%) rename sim/testsuite/{sim => }/cr16/testutils.inc (100%) rename sim/testsuite/{sim => }/cr16/uread16.ms (100%) rename sim/testsuite/{sim => }/cr16/uread32.ms (100%) rename sim/testsuite/{sim => }/cr16/xorb.cgs (100%) rename sim/testsuite/{sim => }/cr16/xord.cgs (100%) rename sim/testsuite/{sim => }/cr16/xorw.cgs (100%) rename sim/testsuite/{sim => }/cris/ChangeLog (100%) rename sim/testsuite/{sim => }/cris/asm/abs.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addcpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addcv32c.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addcv32m.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addcv32r.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addi.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addiv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addoc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addom.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addoq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addqpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addswpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addxc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addxm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addxr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/andc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/andm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/andq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/andr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/asm.exp (100%) rename sim/testsuite/{sim => }/cris/asm/asr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/ba.ms (100%) rename sim/testsuite/{sim => }/cris/asm/badarch1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bare1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bare2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bare3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bas.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bccb.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bdapc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bdapm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bdapq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bdapqpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/biap.ms (100%) rename sim/testsuite/{sim => }/cris/asm/boundc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/boundm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/boundmv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/boundr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/break.ms (100%) rename sim/testsuite/{sim => }/cris/asm/btst.ms (100%) rename sim/testsuite/{sim => }/cris/asm/ccr-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/ccs-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/clearfv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/clearfv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/clrjmp1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/cmpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/cmpm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/cmpq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/cmpr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/cmpxc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/cmpxm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/dflags.ms (100%) rename sim/testsuite/{sim => }/cris/asm/dip.ms (100%) rename sim/testsuite/{sim => }/cris/asm/dstep.ms (100%) rename sim/testsuite/{sim => }/cris/asm/fidxd.ms (100%) rename sim/testsuite/{sim => }/cris/asm/fidxi.ms (100%) rename sim/testsuite/{sim => }/cris/asm/ftagd.ms (100%) rename sim/testsuite/{sim => }/cris/asm/ftagi.ms (100%) rename sim/testsuite/{sim => }/cris/asm/halt.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io4.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io5.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io6.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io7.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io8.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io9.ms (100%) rename sim/testsuite/{sim => }/cris/asm/jsr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/jsrmv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/jumpmp.ms (100%) rename sim/testsuite/{sim => }/cris/asm/jumppv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/lapc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/lsl.ms (100%) rename sim/testsuite/{sim => }/cris/asm/lsr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/lz.ms (100%) rename sim/testsuite/{sim => }/cris/asm/mcp.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movdelsr1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movecpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movecr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movecrt10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movecrt32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movect10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movei.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movempc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movemr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movemrv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movemrv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movepcb.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movepcd.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movepcw.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moveq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moveqpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/mover.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverbpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverdpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverpcb.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverpcd.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverpcw.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverwpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movesmp.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movmp.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movmp8.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movpmv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movpmv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movppc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movpr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movprv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movprv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movrss.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movscpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movscr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movsm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movsmpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movsr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movsrpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movssr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movucpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movucr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movum.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movumpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movur.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movurpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/mstep.ms (100%) rename sim/testsuite/{sim => }/cris/asm/msteppc1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/msteppc2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/msteppc3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/mulv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/mulv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/mulx.ms (100%) rename sim/testsuite/{sim => }/cris/asm/neg.ms (100%) rename sim/testsuite/{sim => }/cris/asm/nonvcv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/nopv10t.ms (100%) rename sim/testsuite/{sim => }/cris/asm/nopv32t.ms (100%) rename sim/testsuite/{sim => }/cris/asm/nopv32t2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/nopv32t3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/nopv32t4.ms (100%) rename sim/testsuite/{sim => }/cris/asm/not.ms (100%) rename sim/testsuite/{sim => }/cris/asm/op3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/opterr1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/opterr2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/opterr3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/opterr4.ms (100%) rename sim/testsuite/{sim => }/cris/asm/opterr5.ms (100%) rename sim/testsuite/{sim => }/cris/asm/option1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/option2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/option3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/option4.ms (100%) rename sim/testsuite/{sim => }/cris/asm/orc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/orm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/orq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/orr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/pcplus.ms (100%) rename sim/testsuite/{sim => }/cris/asm/pid1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw11.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw12.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw13.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw14.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw15.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw16.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw17.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw4.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw5.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw6.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw7.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw8.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw9.ms (100%) rename sim/testsuite/{sim => }/cris/asm/ret.ms (100%) rename sim/testsuite/{sim => }/cris/asm/rfe.ms (100%) rename sim/testsuite/{sim => }/cris/asm/rfg.ms (100%) rename sim/testsuite/{sim => }/cris/asm/rfn.ms (100%) rename sim/testsuite/{sim => }/cris/asm/sbfs.ms (100%) rename sim/testsuite/{sim => }/cris/asm/scc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/sfe.ms (100%) rename sim/testsuite/{sim => }/cris/asm/subc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/subm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/subq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/subqpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/subr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/subxc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/subxm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/subxr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/swap.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tb.ms (100%) rename sim/testsuite/{sim => }/cris/asm/test.ms (100%) rename sim/testsuite/{sim => }/cris/asm/testutils.inc (100%) rename sim/testsuite/{sim => }/cris/asm/tjmpsrv32-2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tjmpsrv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tjsrcv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tjsrcv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmemv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmemv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmulv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmulv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmvm1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmvm2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmvmrv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmvmrv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmvrmv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmvrmv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/user.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x0-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x0-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x1-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x1-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x10-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x2-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x2-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x3-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x3-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x4-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x5-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x5-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x6-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x6-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x7-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x7-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x8-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x9-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/xor.ms (100%) rename sim/testsuite/{sim => }/cris/c/access1.c (100%) rename sim/testsuite/{sim => }/cris/c/append1.c (100%) rename sim/testsuite/{sim => }/cris/c/badldso1.c (100%) rename sim/testsuite/{sim => }/cris/c/badldso2.c (100%) rename sim/testsuite/{sim => }/cris/c/badldso3.c (100%) rename sim/testsuite/{sim => }/cris/c/c.exp (100%) rename sim/testsuite/{sim => }/cris/c/clone1.c (100%) rename sim/testsuite/{sim => }/cris/c/clone2.c (100%) rename sim/testsuite/{sim => }/cris/c/clone3.c (100%) rename sim/testsuite/{sim => }/cris/c/clone4.c (100%) rename sim/testsuite/{sim => }/cris/c/clone5.c (100%) rename sim/testsuite/{sim => }/cris/c/clone6.c (100%) rename sim/testsuite/{sim => }/cris/c/ex1.c (100%) rename sim/testsuite/{sim => }/cris/c/exitg1.c (100%) rename sim/testsuite/{sim => }/cris/c/exitg2.c (100%) rename sim/testsuite/{sim => }/cris/c/fcntl1.c (100%) rename sim/testsuite/{sim => }/cris/c/fcntl2.c (100%) rename sim/testsuite/{sim => }/cris/c/fdopen1.c (100%) rename sim/testsuite/{sim => }/cris/c/fdopen2.c (100%) rename sim/testsuite/{sim => }/cris/c/freopen1.c (100%) rename sim/testsuite/{sim => }/cris/c/freopen2.c (100%) rename sim/testsuite/{sim => }/cris/c/ftruncate1.c (100%) rename sim/testsuite/{sim => }/cris/c/ftruncate2.c (100%) rename sim/testsuite/{sim => }/cris/c/getcwd1.c (100%) rename sim/testsuite/{sim => }/cris/c/gettod.c (100%) rename sim/testsuite/{sim => }/cris/c/hello.c (100%) rename sim/testsuite/{sim => }/cris/c/helloaout.c (100%) rename sim/testsuite/{sim => }/cris/c/hellodyn.c (100%) rename sim/testsuite/{sim => }/cris/c/hellodyn2.c (100%) rename sim/testsuite/{sim => }/cris/c/hellodyn3.c (100%) rename sim/testsuite/{sim => }/cris/c/kill1.c (100%) rename sim/testsuite/{sim => }/cris/c/kill2.c (100%) rename sim/testsuite/{sim => }/cris/c/kill3.c (100%) rename sim/testsuite/{sim => }/cris/c/mapbrk.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap1.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap2.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap3.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap4.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap5.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap6.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap7.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap8.c (100%) rename sim/testsuite/{sim => }/cris/c/mprotect1.c (100%) rename sim/testsuite/{sim => }/cris/c/mprotect2.c (100%) rename sim/testsuite/{sim => }/cris/c/mremap.c (100%) rename sim/testsuite/{sim => }/cris/c/openpf1.c (100%) rename sim/testsuite/{sim => }/cris/c/openpf2.c (100%) rename sim/testsuite/{sim => }/cris/c/openpf3.c (100%) rename sim/testsuite/{sim => }/cris/c/openpf4.c (100%) rename sim/testsuite/{sim => }/cris/c/openpf5.c (100%) rename sim/testsuite/{sim => }/cris/c/pipe1.c (100%) rename sim/testsuite/{sim => }/cris/c/pipe2.c (100%) rename sim/testsuite/{sim => }/cris/c/pipe3.c (100%) rename sim/testsuite/{sim => }/cris/c/pipe4.c (100%) rename sim/testsuite/{sim => }/cris/c/pipe5.c (100%) rename sim/testsuite/{sim => }/cris/c/pipe6.c (100%) rename sim/testsuite/{sim => }/cris/c/pipe7.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink1.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink10.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink11.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink2.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink3.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink4.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink5.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink6.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink7.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink8.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink9.c (100%) rename sim/testsuite/{sim => }/cris/c/rename2.c (100%) rename sim/testsuite/{sim => }/cris/c/rtsigprocmask1.c (100%) rename sim/testsuite/{sim => }/cris/c/rtsigprocmask2.c (100%) rename sim/testsuite/{sim => }/cris/c/rtsigsuspend1.c (100%) rename sim/testsuite/{sim => }/cris/c/rtsigsuspend2.c (100%) rename sim/testsuite/{sim => }/cris/c/sched1.c (100%) rename sim/testsuite/{sim => }/cris/c/sched2.c (100%) rename sim/testsuite/{sim => }/cris/c/sched3.c (100%) rename sim/testsuite/{sim => }/cris/c/sched4.c (100%) rename sim/testsuite/{sim => }/cris/c/sched5.c (100%) rename sim/testsuite/{sim => }/cris/c/sched6.c (100%) rename sim/testsuite/{sim => }/cris/c/sched7.c (100%) rename sim/testsuite/{sim => }/cris/c/sched8.c (100%) rename sim/testsuite/{sim => }/cris/c/sched9.c (100%) rename sim/testsuite/{sim => }/cris/c/seek1.c (100%) rename sim/testsuite/{sim => }/cris/c/seek2.c (100%) rename sim/testsuite/{sim => }/cris/c/seek3.c (100%) rename sim/testsuite/{sim => }/cris/c/seek4.c (100%) rename sim/testsuite/{sim => }/cris/c/setrlimit1.c (100%) rename sim/testsuite/{sim => }/cris/c/settls1.c (100%) rename sim/testsuite/{sim => }/cris/c/sig1.c (100%) rename sim/testsuite/{sim => }/cris/c/sig10.c (100%) rename sim/testsuite/{sim => }/cris/c/sig11.c (100%) rename sim/testsuite/{sim => }/cris/c/sig12.c (100%) rename sim/testsuite/{sim => }/cris/c/sig13.c (100%) rename sim/testsuite/{sim => }/cris/c/sig2.c (100%) rename sim/testsuite/{sim => }/cris/c/sig3.c (100%) rename sim/testsuite/{sim => }/cris/c/sig4.c (100%) rename sim/testsuite/{sim => }/cris/c/sig5.c (100%) rename sim/testsuite/{sim => }/cris/c/sig6.c (100%) rename sim/testsuite/{sim => }/cris/c/sig7.c (100%) rename sim/testsuite/{sim => }/cris/c/sig8.c (100%) rename sim/testsuite/{sim => }/cris/c/sig9.c (100%) rename sim/testsuite/{sim => }/cris/c/sigreturn1.c (100%) rename sim/testsuite/{sim => }/cris/c/sigreturn2.c (100%) rename sim/testsuite/{sim => }/cris/c/sigreturn3.c (100%) rename sim/testsuite/{sim => }/cris/c/sigreturn4.c (100%) rename sim/testsuite/{sim => }/cris/c/sjlj.c (100%) rename sim/testsuite/{sim => }/cris/c/sock1.c (100%) rename sim/testsuite/{sim => }/cris/c/stat1.c (100%) rename sim/testsuite/{sim => }/cris/c/stat2.c (100%) rename sim/testsuite/{sim => }/cris/c/stat3.c (100%) rename sim/testsuite/{sim => }/cris/c/stat4.c (100%) rename sim/testsuite/{sim => }/cris/c/stat5.c (100%) rename sim/testsuite/{sim => }/cris/c/stat7.c (100%) rename sim/testsuite/{sim => }/cris/c/stat8.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall1.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall2.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall3.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall4.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall5.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall6.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall7.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall8.c (100%) rename sim/testsuite/{sim => }/cris/c/sysctl1.c (100%) rename sim/testsuite/{sim => }/cris/c/sysctl2.c (100%) rename sim/testsuite/{sim => }/cris/c/sysctl3.c (100%) rename sim/testsuite/{sim => }/cris/c/thread2.c (100%) rename sim/testsuite/{sim => }/cris/c/thread3.c (100%) rename sim/testsuite/{sim => }/cris/c/thread4.c (100%) rename sim/testsuite/{sim => }/cris/c/thread5.c (100%) rename sim/testsuite/{sim => }/cris/c/time1.c (100%) rename sim/testsuite/{sim => }/cris/c/time2.c (100%) rename sim/testsuite/{sim => }/cris/c/truncate1.c (100%) rename sim/testsuite/{sim => }/cris/c/truncate2.c (100%) rename sim/testsuite/{sim => }/cris/c/ugetrlimit1.c (100%) rename sim/testsuite/{sim => }/cris/c/uname1.c (100%) rename sim/testsuite/{sim => }/cris/c/writev1.c (100%) rename sim/testsuite/{sim => }/cris/c/writev2.c (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/host1.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq1.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq2.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq3.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq4.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq5.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq6.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/mbox1.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/mem1.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/mem2.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/poll1.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/quit.s (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/rvc.exp (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/std.dev (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/testutils.inc (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/trivial1.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/trivial2.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/trivial3.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/trivial4.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/trivial4.r (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/trivial5.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/wd1.ms (100%) rename sim/testsuite/{sim => }/d10v/ChangeLog (100%) rename sim/testsuite/{sim => }/d10v/allinsn.exp (100%) rename sim/testsuite/{sim => }/d10v/exit47.s (100%) rename sim/testsuite/{sim => }/d10v/hello.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-ld-d.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-ld-i.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-ld-id.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-ld-im.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-ld-ip.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-ld2w-d.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-ld2w-i.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-ld2w-id.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-ld2w-im.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-ld2w-ip.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-st-d.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-st-i.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-st-id.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-st-im.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-st-ip.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-st-is.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-st2w-d.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-st2w-i.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-st2w-id.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-st2w-im.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-st2w-ip.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-st2w-is.s (100%) rename sim/testsuite/{sim => }/d10v/t-dbt.s (100%) rename sim/testsuite/{sim => }/d10v/t-ld-st.s (100%) rename sim/testsuite/{sim => }/d10v/t-mac.s (100%) rename sim/testsuite/{sim => }/d10v/t-macros.i (100%) rename sim/testsuite/{sim => }/d10v/t-mod-ld-pre.s (100%) rename sim/testsuite/{sim => }/d10v/t-msbu.s (100%) rename sim/testsuite/{sim => }/d10v/t-mulxu.s (100%) rename sim/testsuite/{sim => }/d10v/t-mvtac.s (100%) rename sim/testsuite/{sim => }/d10v/t-mvtc.s (100%) rename sim/testsuite/{sim => }/d10v/t-rac.s (100%) rename sim/testsuite/{sim => }/d10v/t-rachi.s (100%) rename sim/testsuite/{sim => }/d10v/t-rdt.s (100%) rename sim/testsuite/{sim => }/d10v/t-rep.s (100%) rename sim/testsuite/{sim => }/d10v/t-rie-xx.s (100%) rename sim/testsuite/{sim => }/d10v/t-rte.s (100%) rename sim/testsuite/{sim => }/d10v/t-sac.s (100%) rename sim/testsuite/{sim => }/d10v/t-sachi.s (100%) rename sim/testsuite/{sim => }/d10v/t-sadd.s (100%) rename sim/testsuite/{sim => }/d10v/t-slae.s (100%) rename sim/testsuite/{sim => }/d10v/t-sp.s (100%) rename sim/testsuite/{sim => }/d10v/t-sub.s (100%) rename sim/testsuite/{sim => }/d10v/t-sub2w.s (100%) rename sim/testsuite/{sim => }/d10v/t-subi.s (100%) rename sim/testsuite/{sim => }/d10v/t-trap.s (100%) rename sim/testsuite/{sim => }/frv/ChangeLog (100%) rename sim/testsuite/{sim => }/frv/add.cgs (100%) rename sim/testsuite/{sim => }/frv/add.pcgs (100%) rename sim/testsuite/{sim => }/frv/addcc.cgs (100%) rename sim/testsuite/{sim => }/frv/addi.cgs (100%) rename sim/testsuite/{sim => }/frv/addicc.cgs (100%) rename sim/testsuite/{sim => }/frv/addx.cgs (100%) rename sim/testsuite/{sim => }/frv/addxcc.cgs (100%) rename sim/testsuite/{sim => }/frv/addxi.cgs (100%) rename sim/testsuite/{sim => }/frv/addxicc.cgs (100%) rename sim/testsuite/{sim => }/frv/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/and.cgs (100%) rename sim/testsuite/{sim => }/frv/andcc.cgs (100%) rename sim/testsuite/{sim => }/frv/andcr.cgs (100%) rename sim/testsuite/{sim => }/frv/andi.cgs (100%) rename sim/testsuite/{sim => }/frv/andicc.cgs (100%) rename sim/testsuite/{sim => }/frv/andncr.cgs (100%) rename sim/testsuite/{sim => }/frv/bar.cgs (100%) rename sim/testsuite/{sim => }/frv/bc.cgs (100%) rename sim/testsuite/{sim => }/frv/bcclr.cgs (100%) rename sim/testsuite/{sim => }/frv/bceqlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcgelr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcgtlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bchilr.cgs (100%) rename sim/testsuite/{sim => }/frv/bclelr.cgs (100%) rename sim/testsuite/{sim => }/frv/bclr.cgs (100%) rename sim/testsuite/{sim => }/frv/bclslr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcltlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcnclr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcnelr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcnlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcnolr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcnvlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcplr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcralr.cgs (100%) rename sim/testsuite/{sim => }/frv/bctrlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcvlr.cgs (100%) rename sim/testsuite/{sim => }/frv/beq.cgs (100%) rename sim/testsuite/{sim => }/frv/beqlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bge.cgs (100%) rename sim/testsuite/{sim => }/frv/bgelr.cgs (100%) rename sim/testsuite/{sim => }/frv/bgt.cgs (100%) rename sim/testsuite/{sim => }/frv/bgtlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bhi.cgs (100%) rename sim/testsuite/{sim => }/frv/bhilr.cgs (100%) rename sim/testsuite/{sim => }/frv/ble.cgs (100%) rename sim/testsuite/{sim => }/frv/blelr.cgs (100%) rename sim/testsuite/{sim => }/frv/bls.cgs (100%) rename sim/testsuite/{sim => }/frv/blslr.cgs (100%) rename sim/testsuite/{sim => }/frv/blt.cgs (100%) rename sim/testsuite/{sim => }/frv/bltlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bn.cgs (100%) rename sim/testsuite/{sim => }/frv/bnc.cgs (100%) rename sim/testsuite/{sim => }/frv/bnclr.cgs (100%) rename sim/testsuite/{sim => }/frv/bne.cgs (100%) rename sim/testsuite/{sim => }/frv/bnelr.cgs (100%) rename sim/testsuite/{sim => }/frv/bnlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bno.cgs (100%) rename sim/testsuite/{sim => }/frv/bnolr.cgs (100%) rename sim/testsuite/{sim => }/frv/bnv.cgs (100%) rename sim/testsuite/{sim => }/frv/bnvlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bp.cgs (100%) rename sim/testsuite/{sim => }/frv/bplr.cgs (100%) rename sim/testsuite/{sim => }/frv/bra.cgs (100%) rename sim/testsuite/{sim => }/frv/bralr.cgs (100%) rename sim/testsuite/{sim => }/frv/branch.pcgs (100%) rename sim/testsuite/{sim => }/frv/break.cgs (100%) rename sim/testsuite/{sim => }/frv/bv.cgs (100%) rename sim/testsuite/{sim => }/frv/bvlr.cgs (100%) rename sim/testsuite/{sim => }/frv/cache.ms (100%) rename sim/testsuite/{sim => }/frv/cadd.cgs (100%) rename sim/testsuite/{sim => }/frv/caddcc.cgs (100%) rename sim/testsuite/{sim => }/frv/call.cgs (100%) rename sim/testsuite/{sim => }/frv/call.pcgs (100%) rename sim/testsuite/{sim => }/frv/callil.cgs (100%) rename sim/testsuite/{sim => }/frv/calll.cgs (100%) rename sim/testsuite/{sim => }/frv/cand.cgs (100%) rename sim/testsuite/{sim => }/frv/candcc.cgs (100%) rename sim/testsuite/{sim => }/frv/ccalll.cgs (100%) rename sim/testsuite/{sim => }/frv/cckc.cgs (100%) rename sim/testsuite/{sim => }/frv/cckeq.cgs (100%) rename sim/testsuite/{sim => }/frv/cckge.cgs (100%) rename sim/testsuite/{sim => }/frv/cckgt.cgs (100%) rename sim/testsuite/{sim => }/frv/cckhi.cgs (100%) rename sim/testsuite/{sim => }/frv/cckle.cgs (100%) rename sim/testsuite/{sim => }/frv/cckls.cgs (100%) rename sim/testsuite/{sim => }/frv/ccklt.cgs (100%) rename sim/testsuite/{sim => }/frv/cckn.cgs (100%) rename sim/testsuite/{sim => }/frv/ccknc.cgs (100%) rename sim/testsuite/{sim => }/frv/cckne.cgs (100%) rename sim/testsuite/{sim => }/frv/cckno.cgs (100%) rename sim/testsuite/{sim => }/frv/ccknv.cgs (100%) rename sim/testsuite/{sim => }/frv/cckp.cgs (100%) rename sim/testsuite/{sim => }/frv/cckra.cgs (100%) rename sim/testsuite/{sim => }/frv/cckv.cgs (100%) rename sim/testsuite/{sim => }/frv/ccmp.cgs (100%) rename sim/testsuite/{sim => }/frv/cfabss.cgs (100%) rename sim/testsuite/{sim => }/frv/cfadds.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckeq.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckge.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckgt.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckle.cgs (100%) rename sim/testsuite/{sim => }/frv/cfcklg.cgs (100%) rename sim/testsuite/{sim => }/frv/cfcklt.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckne.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckno.cgs (100%) rename sim/testsuite/{sim => }/frv/cfcko.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckra.cgs (100%) rename sim/testsuite/{sim => }/frv/cfcku.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckue.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckug.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckuge.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckul.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckule.cgs (100%) rename sim/testsuite/{sim => }/frv/cfcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/cfdivs.cgs (100%) rename sim/testsuite/{sim => }/frv/cfitos.cgs (100%) rename sim/testsuite/{sim => }/frv/cfmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/cfmas.cgs (100%) rename sim/testsuite/{sim => }/frv/cfmovs.cgs (100%) rename sim/testsuite/{sim => }/frv/cfmss.cgs (100%) rename sim/testsuite/{sim => }/frv/cfmsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/cfmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/cfnegs.cgs (100%) rename sim/testsuite/{sim => }/frv/cfsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/cfstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/cfsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/cjmpl.cgs (100%) rename sim/testsuite/{sim => }/frv/ckc.cgs (100%) rename sim/testsuite/{sim => }/frv/ckeq.cgs (100%) rename sim/testsuite/{sim => }/frv/ckge.cgs (100%) rename sim/testsuite/{sim => }/frv/ckgt.cgs (100%) rename sim/testsuite/{sim => }/frv/ckhi.cgs (100%) rename sim/testsuite/{sim => }/frv/ckle.cgs (100%) rename sim/testsuite/{sim => }/frv/ckls.cgs (100%) rename sim/testsuite/{sim => }/frv/cklt.cgs (100%) rename sim/testsuite/{sim => }/frv/ckn.cgs (100%) rename sim/testsuite/{sim => }/frv/cknc.cgs (100%) rename sim/testsuite/{sim => }/frv/ckne.cgs (100%) rename sim/testsuite/{sim => }/frv/ckno.cgs (100%) rename sim/testsuite/{sim => }/frv/cknv.cgs (100%) rename sim/testsuite/{sim => }/frv/ckp.cgs (100%) rename sim/testsuite/{sim => }/frv/ckra.cgs (100%) rename sim/testsuite/{sim => }/frv/ckv.cgs (100%) rename sim/testsuite/{sim => }/frv/cld.cgs (100%) rename sim/testsuite/{sim => }/frv/cldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/cldbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldd.cgs (100%) rename sim/testsuite/{sim => }/frv/clddf.cgs (100%) rename sim/testsuite/{sim => }/frv/clddfu.cgs (100%) rename sim/testsuite/{sim => }/frv/clddu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldf.cgs (100%) rename sim/testsuite/{sim => }/frv/cldfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldhf.cgs (100%) rename sim/testsuite/{sim => }/frv/cldhfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldq.cgs (100%) rename sim/testsuite/{sim => }/frv/cldqu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldsb.cgs (100%) rename sim/testsuite/{sim => }/frv/cldsbu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldsh.cgs (100%) rename sim/testsuite/{sim => }/frv/cldshu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldub.cgs (100%) rename sim/testsuite/{sim => }/frv/cldubu.cgs (100%) rename sim/testsuite/{sim => }/frv/clduh.cgs (100%) rename sim/testsuite/{sim => }/frv/clduhu.cgs (100%) rename sim/testsuite/{sim => }/frv/clrfa.cgs (100%) rename sim/testsuite/{sim => }/frv/clrfr.cgs (100%) rename sim/testsuite/{sim => }/frv/clrga.cgs (100%) rename sim/testsuite/{sim => }/frv/clrgr.cgs (100%) rename sim/testsuite/{sim => }/frv/cmaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/cmaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/cmand.cgs (100%) rename sim/testsuite/{sim => }/frv/cmbtoh.cgs (100%) rename sim/testsuite/{sim => }/frv/cmbtohe.cgs (100%) rename sim/testsuite/{sim => }/frv/cmcpxis.cgs (100%) rename sim/testsuite/{sim => }/frv/cmcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmcpxrs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/cmexpdhd.cgs (100%) rename sim/testsuite/{sim => }/frv/cmexpdhw.cgs (100%) rename sim/testsuite/{sim => }/frv/cmhtob.cgs (100%) rename sim/testsuite/{sim => }/frv/cmmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmnot.cgs (100%) rename sim/testsuite/{sim => }/frv/cmor.cgs (100%) rename sim/testsuite/{sim => }/frv/cmov.cgs (100%) rename sim/testsuite/{sim => }/frv/cmovfg.cgs (100%) rename sim/testsuite/{sim => }/frv/cmovfgd.cgs (100%) rename sim/testsuite/{sim => }/frv/cmovgf.cgs (100%) rename sim/testsuite/{sim => }/frv/cmovgfd.cgs (100%) rename sim/testsuite/{sim => }/frv/cmp.cgs (100%) rename sim/testsuite/{sim => }/frv/cmpb.cgs (100%) rename sim/testsuite/{sim => }/frv/cmpba.cgs (100%) rename sim/testsuite/{sim => }/frv/cmpi.cgs (100%) rename sim/testsuite/{sim => }/frv/cmqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmqmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmqmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/cmsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/cmxor.cgs (100%) rename sim/testsuite/{sim => }/frv/cnot.cgs (100%) rename sim/testsuite/{sim => }/frv/commitfa.cgs (100%) rename sim/testsuite/{sim => }/frv/commitfr.cgs (100%) rename sim/testsuite/{sim => }/frv/commitga.cgs (100%) rename sim/testsuite/{sim => }/frv/commitgr.cgs (100%) rename sim/testsuite/{sim => }/frv/cop1.cgs (100%) rename sim/testsuite/{sim => }/frv/cop2.cgs (100%) rename sim/testsuite/{sim => }/frv/cor.cgs (100%) rename sim/testsuite/{sim => }/frv/corcc.cgs (100%) rename sim/testsuite/{sim => }/frv/cscan.cgs (100%) rename sim/testsuite/{sim => }/frv/csdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/csll.cgs (100%) rename sim/testsuite/{sim => }/frv/csllcc.cgs (100%) rename sim/testsuite/{sim => }/frv/csmul.cgs (100%) rename sim/testsuite/{sim => }/frv/csmulcc.cgs (100%) rename sim/testsuite/{sim => }/frv/csra.cgs (100%) rename sim/testsuite/{sim => }/frv/csracc.cgs (100%) rename sim/testsuite/{sim => }/frv/csrl.cgs (100%) rename sim/testsuite/{sim => }/frv/csrlcc.cgs (100%) rename sim/testsuite/{sim => }/frv/cst.cgs (100%) rename sim/testsuite/{sim => }/frv/cstb.cgs (100%) rename sim/testsuite/{sim => }/frv/cstbf.cgs (100%) rename sim/testsuite/{sim => }/frv/cstbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstbu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstd.cgs (100%) rename sim/testsuite/{sim => }/frv/cstdf.cgs (100%) rename sim/testsuite/{sim => }/frv/cstdfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstdu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstf.cgs (100%) rename sim/testsuite/{sim => }/frv/cstfu.cgs (100%) rename sim/testsuite/{sim => }/frv/csth.cgs (100%) rename sim/testsuite/{sim => }/frv/csthf.cgs (100%) rename sim/testsuite/{sim => }/frv/csthfu.cgs (100%) rename sim/testsuite/{sim => }/frv/csthu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstq.cgs (100%) rename sim/testsuite/{sim => }/frv/cstu.cgs (100%) rename sim/testsuite/{sim => }/frv/csub.cgs (100%) rename sim/testsuite/{sim => }/frv/csubcc.cgs (100%) rename sim/testsuite/{sim => }/frv/cswap.cgs (100%) rename sim/testsuite/{sim => }/frv/cudiv.cgs (100%) rename sim/testsuite/{sim => }/frv/cxor.cgs (100%) rename sim/testsuite/{sim => }/frv/cxorcc.cgs (100%) rename sim/testsuite/{sim => }/frv/dcef.cgs (100%) rename sim/testsuite/{sim => }/frv/dcei.cgs (100%) rename sim/testsuite/{sim => }/frv/dcf.cgs (100%) rename sim/testsuite/{sim => }/frv/dci.cgs (100%) rename sim/testsuite/{sim => }/frv/exit47.ms (100%) rename sim/testsuite/{sim => }/frv/fabsd.cgs (100%) rename sim/testsuite/{sim => }/frv/fabss.cgs (100%) rename sim/testsuite/{sim => }/frv/faddd.cgs (100%) rename sim/testsuite/{sim => }/frv/fadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fbeq.cgs (100%) rename sim/testsuite/{sim => }/frv/fbeqlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbge.cgs (100%) rename sim/testsuite/{sim => }/frv/fbgelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbgt.cgs (100%) rename sim/testsuite/{sim => }/frv/fbgtlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fble.cgs (100%) rename sim/testsuite/{sim => }/frv/fblelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fblg.cgs (100%) rename sim/testsuite/{sim => }/frv/fblglr.cgs (100%) rename sim/testsuite/{sim => }/frv/fblt.cgs (100%) rename sim/testsuite/{sim => }/frv/fbltlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbne.cgs (100%) rename sim/testsuite/{sim => }/frv/fbnelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbno.cgs (100%) rename sim/testsuite/{sim => }/frv/fbnolr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbo.cgs (100%) rename sim/testsuite/{sim => }/frv/fbolr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbra.cgs (100%) rename sim/testsuite/{sim => }/frv/fbralr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbu.cgs (100%) rename sim/testsuite/{sim => }/frv/fbue.cgs (100%) rename sim/testsuite/{sim => }/frv/fbuelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbug.cgs (100%) rename sim/testsuite/{sim => }/frv/fbuge.cgs (100%) rename sim/testsuite/{sim => }/frv/fbugelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbuglr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbul.cgs (100%) rename sim/testsuite/{sim => }/frv/fbule.cgs (100%) rename sim/testsuite/{sim => }/frv/fbulelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbullr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbulr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbeqlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbgelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbgtlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcblelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcblglr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbltlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbnelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbnolr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbolr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbralr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbuelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbugelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbuglr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbulelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbullr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbulr.cgs (100%) rename sim/testsuite/{sim => }/frv/fckeq.cgs (100%) rename sim/testsuite/{sim => }/frv/fckge.cgs (100%) rename sim/testsuite/{sim => }/frv/fckgt.cgs (100%) rename sim/testsuite/{sim => }/frv/fckle.cgs (100%) rename sim/testsuite/{sim => }/frv/fcklg.cgs (100%) rename sim/testsuite/{sim => }/frv/fcklt.cgs (100%) rename sim/testsuite/{sim => }/frv/fckne.cgs (100%) rename sim/testsuite/{sim => }/frv/fckno.cgs (100%) rename sim/testsuite/{sim => }/frv/fcko.cgs (100%) rename sim/testsuite/{sim => }/frv/fckra.cgs (100%) rename sim/testsuite/{sim => }/frv/fcku.cgs (100%) rename sim/testsuite/{sim => }/frv/fckue.cgs (100%) rename sim/testsuite/{sim => }/frv/fckug.cgs (100%) rename sim/testsuite/{sim => }/frv/fckuge.cgs (100%) rename sim/testsuite/{sim => }/frv/fckul.cgs (100%) rename sim/testsuite/{sim => }/frv/fckule.cgs (100%) rename sim/testsuite/{sim => }/frv/fcmpd.cgs (100%) rename sim/testsuite/{sim => }/frv/fcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/fdabss.cgs (100%) rename sim/testsuite/{sim => }/frv/fdadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fdcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/fddivs.cgs (100%) rename sim/testsuite/{sim => }/frv/fditos.cgs (100%) rename sim/testsuite/{sim => }/frv/fdivd.cgs (100%) rename sim/testsuite/{sim => }/frv/fdivs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmas.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmovs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmss.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmulcs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/fdnegs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdsads.cgs (100%) rename sim/testsuite/{sim => }/frv/fdsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/fdstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/fdsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdtoi.cgs (100%) rename sim/testsuite/{sim => }/frv/fitod.cgs (100%) rename sim/testsuite/{sim => }/frv/fitos.cgs (100%) rename sim/testsuite/{sim => }/frv/fmad.cgs (100%) rename sim/testsuite/{sim => }/frv/fmaddd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fmas.cgs (100%) rename sim/testsuite/{sim => }/frv/fmovd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmovs.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmss.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsubd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fmuld.cgs (100%) rename sim/testsuite/{sim => }/frv/fmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/fnegd.cgs (100%) rename sim/testsuite/{sim => }/frv/fnegs.cgs (100%) rename sim/testsuite/{sim => }/frv/fnop.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/addss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr400/csdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/maddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/masaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/maveh.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhdseth.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhdsets.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsethih.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsethis.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsetloh.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsetlos.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/movgs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/movsg.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/msubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/scutss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/sdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/sdivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/slass.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smass.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smsss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/subss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/udiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/udivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/dcpl.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/dcul.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr550/cmaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/dcpl.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/dcul.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mabshs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/masaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdaddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdasaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdsubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmrdhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmrdhu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqxmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqxmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/msubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/msubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/msubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mtrap.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/udiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/udivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fsqrtd.cgs (100%) rename sim/testsuite/{sim => }/frv/fsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/fstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/fsubd.cgs (100%) rename sim/testsuite/{sim => }/frv/fsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fteq.cgs (100%) rename sim/testsuite/{sim => }/frv/ftge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftgt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftieq.cgs (100%) rename sim/testsuite/{sim => }/frv/ftige.cgs (100%) rename sim/testsuite/{sim => }/frv/ftigt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftile.cgs (100%) rename sim/testsuite/{sim => }/frv/ftilg.cgs (100%) rename sim/testsuite/{sim => }/frv/ftilt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftine.cgs (100%) rename sim/testsuite/{sim => }/frv/ftino.cgs (100%) rename sim/testsuite/{sim => }/frv/ftio.cgs (100%) rename sim/testsuite/{sim => }/frv/ftira.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiu.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiue.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiug.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiuge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiul.cgs (100%) rename sim/testsuite/{sim => }/frv/ftle.cgs (100%) rename sim/testsuite/{sim => }/frv/ftlg.cgs (100%) rename sim/testsuite/{sim => }/frv/ftlt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftne.cgs (100%) rename sim/testsuite/{sim => }/frv/ftno.cgs (100%) rename sim/testsuite/{sim => }/frv/fto.cgs (100%) rename sim/testsuite/{sim => }/frv/ftra.cgs (100%) rename sim/testsuite/{sim => }/frv/ftu.cgs (100%) rename sim/testsuite/{sim => }/frv/ftue.cgs (100%) rename sim/testsuite/{sim => }/frv/ftug.cgs (100%) rename sim/testsuite/{sim => }/frv/ftuge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftul.cgs (100%) rename sim/testsuite/{sim => }/frv/ftule.cgs (100%) rename sim/testsuite/{sim => }/frv/grloop.ms (100%) rename sim/testsuite/{sim => }/frv/hello.ms (100%) rename sim/testsuite/{sim => }/frv/icei.cgs (100%) rename sim/testsuite/{sim => }/frv/ici.cgs (100%) rename sim/testsuite/{sim => }/frv/icpl.cgs (100%) rename sim/testsuite/{sim => }/frv/icul.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts.exp (100%) rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr400.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr500.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/badalign-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/badalign.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/compound-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/compound.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/data_store_error-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/data_store_error.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/fp_exception-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/fp_exception.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/illinsn.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/mp_exception.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/privileged_instruction.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/regalign.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/reset.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/shadow_regs.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/timer.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpil.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.pcgs (100%) rename sim/testsuite/{sim => }/frv/ld.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldc.cgs (100%) rename sim/testsuite/{sim => }/frv/ldcu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldd.cgs (100%) rename sim/testsuite/{sim => }/frv/lddc.cgs (100%) rename sim/testsuite/{sim => }/frv/lddcu.cgs (100%) rename sim/testsuite/{sim => }/frv/lddf.cgs (100%) rename sim/testsuite/{sim => }/frv/lddfi.cgs (100%) rename sim/testsuite/{sim => }/frv/lddfu.cgs (100%) rename sim/testsuite/{sim => }/frv/lddi.cgs (100%) rename sim/testsuite/{sim => }/frv/lddu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldq.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqc.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqcu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsb.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsbi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsbu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsh.cgs (100%) rename sim/testsuite/{sim => }/frv/ldshi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldshu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldub.cgs (100%) rename sim/testsuite/{sim => }/frv/ldubi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldubu.cgs (100%) rename sim/testsuite/{sim => }/frv/lduh.cgs (100%) rename sim/testsuite/{sim => }/frv/lduhi.cgs (100%) rename sim/testsuite/{sim => }/frv/lduhu.cgs (100%) rename sim/testsuite/{sim => }/frv/lrbranch.pcgs (100%) rename sim/testsuite/{sim => }/frv/mabshs.cgs (100%) rename sim/testsuite/{sim => }/frv/maddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/maddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/mand.cgs (100%) rename sim/testsuite/{sim => }/frv/maveh.cgs (100%) rename sim/testsuite/{sim => }/frv/mbtoh.cgs (100%) rename sim/testsuite/{sim => }/frv/mbtohe.cgs (100%) rename sim/testsuite/{sim => }/frv/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/mcmpsh.cgs (100%) rename sim/testsuite/{sim => }/frv/mcmpuh.cgs (100%) rename sim/testsuite/{sim => }/frv/mcop1.cgs (100%) rename sim/testsuite/{sim => }/frv/mcop2.cgs (100%) rename sim/testsuite/{sim => }/frv/mcplhi.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpli.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxis.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxrs.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/mcut.cgs (100%) rename sim/testsuite/{sim => }/frv/mcuti.cgs (100%) rename sim/testsuite/{sim => }/frv/mcutss.cgs (100%) rename sim/testsuite/{sim => }/frv/mcutssi.cgs (100%) rename sim/testsuite/{sim => }/frv/mdaddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdasaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdcutssi.cgs (100%) rename sim/testsuite/{sim => }/frv/mdpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mdrotli.cgs (100%) rename sim/testsuite/{sim => }/frv/mdsubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdunpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/membar.cgs (100%) rename sim/testsuite/{sim => }/frv/mexpdhd.cgs (100%) rename sim/testsuite/{sim => }/frv/mexpdhw.cgs (100%) rename sim/testsuite/{sim => }/frv/mhdseth.cgs (100%) rename sim/testsuite/{sim => }/frv/mhdsets.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsethih.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsethis.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsetloh.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsetlos.cgs (100%) rename sim/testsuite/{sim => }/frv/mhtob.cgs (100%) rename sim/testsuite/{sim => }/frv/misc.exp (100%) rename sim/testsuite/{sim => }/frv/mmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmrdhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmrdhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulxhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mnop.cgs (100%) rename sim/testsuite/{sim => }/frv/mnot.cgs (100%) rename sim/testsuite/{sim => }/frv/mor.cgs (100%) rename sim/testsuite/{sim => }/frv/mov.cgs (100%) rename sim/testsuite/{sim => }/frv/movfg.cgs (100%) rename sim/testsuite/{sim => }/frv/movfgd.cgs (100%) rename sim/testsuite/{sim => }/frv/movfgq.cgs (100%) rename sim/testsuite/{sim => }/frv/movgf.cgs (100%) rename sim/testsuite/{sim => }/frv/movgfd.cgs (100%) rename sim/testsuite/{sim => }/frv/movgfq.cgs (100%) rename sim/testsuite/{sim => }/frv/movgs.cgs (100%) rename sim/testsuite/{sim => }/frv/movsg.cgs (100%) rename sim/testsuite/{sim => }/frv/mpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxis.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxrs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/mqlclrhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqlmths.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulxhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsaths.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsllhi.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsrahi.cgs (100%) rename sim/testsuite/{sim => }/frv/mqxmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqxmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mrdacc.cgs (100%) rename sim/testsuite/{sim => }/frv/mrdaccg.cgs (100%) rename sim/testsuite/{sim => }/frv/mrotli.cgs (100%) rename sim/testsuite/{sim => }/frv/mrotri.cgs (100%) rename sim/testsuite/{sim => }/frv/msaths.cgs (100%) rename sim/testsuite/{sim => }/frv/msathu.cgs (100%) rename sim/testsuite/{sim => }/frv/msllhi.cgs (100%) rename sim/testsuite/{sim => }/frv/msrahi.cgs (100%) rename sim/testsuite/{sim => }/frv/msrlhi.cgs (100%) rename sim/testsuite/{sim => }/frv/msubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/msubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/mtrap.cgs (100%) rename sim/testsuite/{sim => }/frv/munpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mwcut.cgs (100%) rename sim/testsuite/{sim => }/frv/mwcuti.cgs (100%) rename sim/testsuite/{sim => }/frv/mwtacc.cgs (100%) rename sim/testsuite/{sim => }/frv/mwtaccg.cgs (100%) rename sim/testsuite/{sim => }/frv/mxor.cgs (100%) rename sim/testsuite/{sim => }/frv/nandcr.cgs (100%) rename sim/testsuite/{sim => }/frv/nandncr.cgs (100%) rename sim/testsuite/{sim => }/frv/nfadds.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdadds.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/nfddivs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfditos.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdivs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmas.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmss.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmulcs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdsads.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfitos.cgs (100%) rename sim/testsuite/{sim => }/frv/nfmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/nfmas.cgs (100%) rename sim/testsuite/{sim => }/frv/nfmss.cgs (100%) rename sim/testsuite/{sim => }/frv/nfmsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/nfsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/nfstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/nfsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/nld.cgs (100%) rename sim/testsuite/{sim => }/frv/nldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldbfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldd.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddf.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddi.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldhf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldhfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldhfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldq.cgs (100%) rename sim/testsuite/{sim => }/frv/nldqf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldqfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldqfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldqu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldsb.cgs (100%) rename sim/testsuite/{sim => }/frv/nldsbi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldsbu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldsh.cgs (100%) rename sim/testsuite/{sim => }/frv/nldshi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldshu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldub.cgs (100%) rename sim/testsuite/{sim => }/frv/nldubi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldubu.cgs (100%) rename sim/testsuite/{sim => }/frv/nlduh.cgs (100%) rename sim/testsuite/{sim => }/frv/nlduhi.cgs (100%) rename sim/testsuite/{sim => }/frv/nlduhu.cgs (100%) rename sim/testsuite/{sim => }/frv/nop.cgs (100%) rename sim/testsuite/{sim => }/frv/norcr.cgs (100%) rename sim/testsuite/{sim => }/frv/norncr.cgs (100%) rename sim/testsuite/{sim => }/frv/not.cgs (100%) rename sim/testsuite/{sim => }/frv/notcr.cgs (100%) rename sim/testsuite/{sim => }/frv/nsdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/nsdivi.cgs (100%) rename sim/testsuite/{sim => }/frv/nudiv.cgs (100%) rename sim/testsuite/{sim => }/frv/nudivi.cgs (100%) rename sim/testsuite/{sim => }/frv/or.cgs (100%) rename sim/testsuite/{sim => }/frv/orcc.cgs (100%) rename sim/testsuite/{sim => }/frv/orcr.cgs (100%) rename sim/testsuite/{sim => }/frv/ori.cgs (100%) rename sim/testsuite/{sim => }/frv/oricc.cgs (100%) rename sim/testsuite/{sim => }/frv/orncr.cgs (100%) rename sim/testsuite/{sim => }/frv/parallel.exp (100%) rename sim/testsuite/{sim => }/frv/ret.cgs (100%) rename sim/testsuite/{sim => }/frv/rett.cgs (100%) rename sim/testsuite/{sim => }/frv/scan.cgs (100%) rename sim/testsuite/{sim => }/frv/scani.cgs (100%) rename sim/testsuite/{sim => }/frv/sdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/sdivi.cgs (100%) rename sim/testsuite/{sim => }/frv/sethi.cgs (100%) rename sim/testsuite/{sim => }/frv/sethilo.pcgs (100%) rename sim/testsuite/{sim => }/frv/setlo.cgs (100%) rename sim/testsuite/{sim => }/frv/setlos.cgs (100%) rename sim/testsuite/{sim => }/frv/sll.cgs (100%) rename sim/testsuite/{sim => }/frv/sllcc.cgs (100%) rename sim/testsuite/{sim => }/frv/slli.cgs (100%) rename sim/testsuite/{sim => }/frv/sllicc.cgs (100%) rename sim/testsuite/{sim => }/frv/smul.cgs (100%) rename sim/testsuite/{sim => }/frv/smulcc.cgs (100%) rename sim/testsuite/{sim => }/frv/smuli.cgs (100%) rename sim/testsuite/{sim => }/frv/smulicc.cgs (100%) rename sim/testsuite/{sim => }/frv/sra.cgs (100%) rename sim/testsuite/{sim => }/frv/sracc.cgs (100%) rename sim/testsuite/{sim => }/frv/srai.cgs (100%) rename sim/testsuite/{sim => }/frv/sraicc.cgs (100%) rename sim/testsuite/{sim => }/frv/srl.cgs (100%) rename sim/testsuite/{sim => }/frv/srlcc.cgs (100%) rename sim/testsuite/{sim => }/frv/srli.cgs (100%) rename sim/testsuite/{sim => }/frv/srlicc.cgs (100%) rename sim/testsuite/{sim => }/frv/st.cgs (100%) rename sim/testsuite/{sim => }/frv/stb.cgs (100%) rename sim/testsuite/{sim => }/frv/stbf.cgs (100%) rename sim/testsuite/{sim => }/frv/stbfi.cgs (100%) rename sim/testsuite/{sim => }/frv/stbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/stbi.cgs (100%) rename sim/testsuite/{sim => }/frv/stbu.cgs (100%) rename sim/testsuite/{sim => }/frv/stc.cgs (100%) rename sim/testsuite/{sim => }/frv/stcu.cgs (100%) rename sim/testsuite/{sim => }/frv/std.cgs (100%) rename sim/testsuite/{sim => }/frv/std.pcgs (100%) rename sim/testsuite/{sim => }/frv/stdc.cgs (100%) rename sim/testsuite/{sim => }/frv/stdc.pcgs (100%) rename sim/testsuite/{sim => }/frv/stdcu.cgs (100%) rename sim/testsuite/{sim => }/frv/stdf.cgs (100%) rename sim/testsuite/{sim => }/frv/stdf.pcgs (100%) rename sim/testsuite/{sim => }/frv/stdfi.cgs (100%) rename sim/testsuite/{sim => }/frv/stdfu.cgs (100%) rename sim/testsuite/{sim => }/frv/stdi.cgs (100%) rename sim/testsuite/{sim => }/frv/stdu.cgs (100%) rename sim/testsuite/{sim => }/frv/stf.cgs (100%) rename sim/testsuite/{sim => }/frv/stfi.cgs (100%) rename sim/testsuite/{sim => }/frv/stfu.cgs (100%) rename sim/testsuite/{sim => }/frv/sth.cgs (100%) rename sim/testsuite/{sim => }/frv/sthf.cgs (100%) rename sim/testsuite/{sim => }/frv/sthfi.cgs (100%) rename sim/testsuite/{sim => }/frv/sthfu.cgs (100%) rename sim/testsuite/{sim => }/frv/sthi.cgs (100%) rename sim/testsuite/{sim => }/frv/sthu.cgs (100%) rename sim/testsuite/{sim => }/frv/sti.cgs (100%) rename sim/testsuite/{sim => }/frv/stq.cgs (100%) rename sim/testsuite/{sim => }/frv/stq.pcgs (100%) rename sim/testsuite/{sim => }/frv/stqc.cgs (100%) rename sim/testsuite/{sim => }/frv/stqc.pcgs (100%) rename sim/testsuite/{sim => }/frv/stqcu.cgs (100%) rename sim/testsuite/{sim => }/frv/stqf.cgs (100%) rename sim/testsuite/{sim => }/frv/stqf.pcgs (100%) rename sim/testsuite/{sim => }/frv/stqfi.cgs (100%) rename sim/testsuite/{sim => }/frv/stqfu.cgs (100%) rename sim/testsuite/{sim => }/frv/stqi.cgs (100%) rename sim/testsuite/{sim => }/frv/stqu.cgs (100%) rename sim/testsuite/{sim => }/frv/stu.cgs (100%) rename sim/testsuite/{sim => }/frv/sub.cgs (100%) rename sim/testsuite/{sim => }/frv/subcc.cgs (100%) rename sim/testsuite/{sim => }/frv/subi.cgs (100%) rename sim/testsuite/{sim => }/frv/subicc.cgs (100%) rename sim/testsuite/{sim => }/frv/subx.cgs (100%) rename sim/testsuite/{sim => }/frv/subxcc.cgs (100%) rename sim/testsuite/{sim => }/frv/subxi.cgs (100%) rename sim/testsuite/{sim => }/frv/subxicc.cgs (100%) rename sim/testsuite/{sim => }/frv/swap.cgs (100%) rename sim/testsuite/{sim => }/frv/swapi.cgs (100%) rename sim/testsuite/{sim => }/frv/tc.cgs (100%) rename sim/testsuite/{sim => }/frv/teq.cgs (100%) rename sim/testsuite/{sim => }/frv/testutils.inc (100%) rename sim/testsuite/{sim => }/frv/tge.cgs (100%) rename sim/testsuite/{sim => }/frv/tgt.cgs (100%) rename sim/testsuite/{sim => }/frv/thi.cgs (100%) rename sim/testsuite/{sim => }/frv/tic.cgs (100%) rename sim/testsuite/{sim => }/frv/tieq.cgs (100%) rename sim/testsuite/{sim => }/frv/tige.cgs (100%) rename sim/testsuite/{sim => }/frv/tigt.cgs (100%) rename sim/testsuite/{sim => }/frv/tihi.cgs (100%) rename sim/testsuite/{sim => }/frv/tile.cgs (100%) rename sim/testsuite/{sim => }/frv/tils.cgs (100%) rename sim/testsuite/{sim => }/frv/tilt.cgs (100%) rename sim/testsuite/{sim => }/frv/tin.cgs (100%) rename sim/testsuite/{sim => }/frv/tinc.cgs (100%) rename sim/testsuite/{sim => }/frv/tine.cgs (100%) rename sim/testsuite/{sim => }/frv/tino.cgs (100%) rename sim/testsuite/{sim => }/frv/tinv.cgs (100%) rename sim/testsuite/{sim => }/frv/tip.cgs (100%) rename sim/testsuite/{sim => }/frv/tira.cgs (100%) rename sim/testsuite/{sim => }/frv/tiv.cgs (100%) rename sim/testsuite/{sim => }/frv/tle.cgs (100%) rename sim/testsuite/{sim => }/frv/tls.cgs (100%) rename sim/testsuite/{sim => }/frv/tlt.cgs (100%) rename sim/testsuite/{sim => }/frv/tn.cgs (100%) rename sim/testsuite/{sim => }/frv/tnc.cgs (100%) rename sim/testsuite/{sim => }/frv/tne.cgs (100%) rename sim/testsuite/{sim => }/frv/tno.cgs (100%) rename sim/testsuite/{sim => }/frv/tnv.cgs (100%) rename sim/testsuite/{sim => }/frv/tp.cgs (100%) rename sim/testsuite/{sim => }/frv/tra.cgs (100%) rename sim/testsuite/{sim => }/frv/tv.cgs (100%) rename sim/testsuite/{sim => }/frv/udiv.cgs (100%) rename sim/testsuite/{sim => }/frv/udivi.cgs (100%) rename sim/testsuite/{sim => }/frv/umul.cgs (100%) rename sim/testsuite/{sim => }/frv/umulcc.cgs (100%) rename sim/testsuite/{sim => }/frv/umuli.cgs (100%) rename sim/testsuite/{sim => }/frv/umulicc.cgs (100%) rename sim/testsuite/{sim => }/frv/xor.cgs (100%) rename sim/testsuite/{sim => }/frv/xorcc.cgs (100%) rename sim/testsuite/{sim => }/frv/xorcr.cgs (100%) rename sim/testsuite/{sim => }/frv/xori.cgs (100%) rename sim/testsuite/{sim => }/frv/xoricc.cgs (100%) rename sim/testsuite/{sim => }/ft32/ChangeLog (100%) rename sim/testsuite/{sim => }/ft32/allinsn.exp (100%) rename sim/testsuite/{sim => }/ft32/basic.s (100%) rename sim/testsuite/{sim => }/ft32/testutils.inc (100%) rename sim/testsuite/{sim => }/h8300/ChangeLog (100%) rename sim/testsuite/{sim => }/h8300/addb.s (100%) rename sim/testsuite/{sim => }/h8300/addl.s (100%) rename sim/testsuite/{sim => }/h8300/adds.s (100%) rename sim/testsuite/{sim => }/h8300/addw.s (100%) rename sim/testsuite/{sim => }/h8300/addx.s (100%) rename sim/testsuite/{sim => }/h8300/allinsn.exp (100%) rename sim/testsuite/{sim => }/h8300/andb.s (100%) rename sim/testsuite/{sim => }/h8300/andl.s (100%) rename sim/testsuite/{sim => }/h8300/andw.s (100%) rename sim/testsuite/{sim => }/h8300/band.s (100%) rename sim/testsuite/{sim => }/h8300/bfld.s (100%) rename sim/testsuite/{sim => }/h8300/biand.s (100%) rename sim/testsuite/{sim => }/h8300/bra.s (100%) rename sim/testsuite/{sim => }/h8300/brabc.s (100%) rename sim/testsuite/{sim => }/h8300/bset.s (100%) rename sim/testsuite/{sim => }/h8300/cmpb.s (100%) rename sim/testsuite/{sim => }/h8300/cmpl.s (100%) rename sim/testsuite/{sim => }/h8300/cmpw.s (100%) rename sim/testsuite/{sim => }/h8300/daa.s (100%) rename sim/testsuite/{sim => }/h8300/das.s (100%) rename sim/testsuite/{sim => }/h8300/dec.s (100%) rename sim/testsuite/{sim => }/h8300/div.s (100%) rename sim/testsuite/{sim => }/h8300/extl.s (100%) rename sim/testsuite/{sim => }/h8300/extw.s (100%) rename sim/testsuite/{sim => }/h8300/inc.s (100%) rename sim/testsuite/{sim => }/h8300/jmp.s (100%) rename sim/testsuite/{sim => }/h8300/ldc.s (100%) rename sim/testsuite/{sim => }/h8300/ldm.s (100%) rename sim/testsuite/{sim => }/h8300/mac.s (100%) rename sim/testsuite/{sim => }/h8300/mova.s (100%) rename sim/testsuite/{sim => }/h8300/movb.s (100%) rename sim/testsuite/{sim => }/h8300/movl.s (100%) rename sim/testsuite/{sim => }/h8300/movmd.s (100%) rename sim/testsuite/{sim => }/h8300/movsd.s (100%) rename sim/testsuite/{sim => }/h8300/movw.s (100%) rename sim/testsuite/{sim => }/h8300/mul.s (100%) rename sim/testsuite/{sim => }/h8300/neg.s (100%) rename sim/testsuite/{sim => }/h8300/nop.s (100%) rename sim/testsuite/{sim => }/h8300/not.s (100%) rename sim/testsuite/{sim => }/h8300/orb.s (100%) rename sim/testsuite/{sim => }/h8300/orl.s (100%) rename sim/testsuite/{sim => }/h8300/orw.s (100%) rename sim/testsuite/{sim => }/h8300/rotl.s (100%) rename sim/testsuite/{sim => }/h8300/rotr.s (100%) rename sim/testsuite/{sim => }/h8300/rotxl.s (100%) rename sim/testsuite/{sim => }/h8300/rotxr.s (100%) rename sim/testsuite/{sim => }/h8300/shal.s (100%) rename sim/testsuite/{sim => }/h8300/shar.s (100%) rename sim/testsuite/{sim => }/h8300/shll.s (100%) rename sim/testsuite/{sim => }/h8300/shlr.s (100%) rename sim/testsuite/{sim => }/h8300/stack.s (100%) rename sim/testsuite/{sim => }/h8300/stc.s (100%) rename sim/testsuite/{sim => }/h8300/subb.s (100%) rename sim/testsuite/{sim => }/h8300/subl.s (100%) rename sim/testsuite/{sim => }/h8300/subs.s (100%) rename sim/testsuite/{sim => }/h8300/subw.s (100%) rename sim/testsuite/{sim => }/h8300/subx.s (100%) rename sim/testsuite/{sim => }/h8300/tas.s (100%) rename sim/testsuite/{sim => }/h8300/testutils.inc (100%) rename sim/testsuite/{sim => }/h8300/xorb.s (100%) rename sim/testsuite/{sim => }/h8300/xorl.s (100%) rename sim/testsuite/{sim => }/h8300/xorw.s (100%) rename sim/testsuite/{sim => }/iq2000/ChangeLog (100%) rename sim/testsuite/{sim => }/iq2000/allinsn.exp (100%) rename sim/testsuite/{sim => }/iq2000/pass.s (100%) rename sim/testsuite/{sim => }/iq2000/testutils.inc (100%) rename sim/testsuite/{sim => }/lm32/ChangeLog (100%) rename sim/testsuite/{sim => }/lm32/allinsn.exp (100%) rename sim/testsuite/{sim => }/lm32/pass.s (100%) rename sim/testsuite/{sim => }/lm32/testutils.inc (100%) rename sim/testsuite/{sim => }/m32c/ChangeLog (100%) rename sim/testsuite/{sim => }/m32c/allinsn.exp (100%) rename sim/testsuite/{sim => }/m32c/blinky.s (100%) rename sim/testsuite/{sim => }/m32c/fail.s (100%) rename sim/testsuite/{sim => }/m32c/gloss.s (100%) rename sim/testsuite/{sim => }/m32c/pass.s (100%) rename sim/testsuite/{sim => }/m32c/sample.ld (100%) rename sim/testsuite/{sim => }/m32c/sample.s (100%) rename sim/testsuite/{sim => }/m32c/sample2.c (100%) rename sim/testsuite/{sim => }/m32c/testutils.inc (100%) rename sim/testsuite/{sim => }/m32r/ChangeLog (100%) rename sim/testsuite/{sim => }/m32r/add.cgs (100%) rename sim/testsuite/{sim => }/m32r/add3.cgs (100%) rename sim/testsuite/{sim => }/m32r/addi.cgs (100%) rename sim/testsuite/{sim => }/m32r/addv.cgs (100%) rename sim/testsuite/{sim => }/m32r/addv3.cgs (100%) rename sim/testsuite/{sim => }/m32r/addx.cgs (100%) rename sim/testsuite/{sim => }/m32r/allinsn.exp (100%) rename sim/testsuite/{sim => }/m32r/and.cgs (100%) rename sim/testsuite/{sim => }/m32r/and3.cgs (100%) rename sim/testsuite/{sim => }/m32r/bc24.cgs (100%) rename sim/testsuite/{sim => }/m32r/bc8.cgs (100%) rename sim/testsuite/{sim => }/m32r/beq.cgs (100%) rename sim/testsuite/{sim => }/m32r/beqz.cgs (100%) rename sim/testsuite/{sim => }/m32r/bgez.cgs (100%) rename sim/testsuite/{sim => }/m32r/bgtz.cgs (100%) rename sim/testsuite/{sim => }/m32r/bl24.cgs (100%) rename sim/testsuite/{sim => }/m32r/bl8.cgs (100%) rename sim/testsuite/{sim => }/m32r/blez.cgs (100%) rename sim/testsuite/{sim => }/m32r/bltz.cgs (100%) rename sim/testsuite/{sim => }/m32r/bnc24.cgs (100%) rename sim/testsuite/{sim => }/m32r/bnc8.cgs (100%) rename sim/testsuite/{sim => }/m32r/bne.cgs (100%) rename sim/testsuite/{sim => }/m32r/bnez.cgs (100%) rename sim/testsuite/{sim => }/m32r/bra24.cgs (100%) rename sim/testsuite/{sim => }/m32r/bra8.cgs (100%) rename sim/testsuite/{sim => }/m32r/cmp.cgs (100%) rename sim/testsuite/{sim => }/m32r/cmpi.cgs (100%) rename sim/testsuite/{sim => }/m32r/cmpu.cgs (100%) rename sim/testsuite/{sim => }/m32r/cmpui.cgs (100%) rename sim/testsuite/{sim => }/m32r/div.cgs (100%) rename sim/testsuite/{sim => }/m32r/divu.cgs (100%) rename sim/testsuite/{sim => }/m32r/exit47.ms (100%) rename sim/testsuite/{sim => }/m32r/hello.ms (100%) rename sim/testsuite/{sim => }/m32r/hw-trap.ms (100%) rename sim/testsuite/{sim => }/m32r/jl.cgs (100%) rename sim/testsuite/{sim => }/m32r/jmp.cgs (100%) rename sim/testsuite/{sim => }/m32r/ld-d.cgs (100%) rename sim/testsuite/{sim => }/m32r/ld-plus.cgs (100%) rename sim/testsuite/{sim => }/m32r/ld.cgs (100%) rename sim/testsuite/{sim => }/m32r/ld24.cgs (100%) rename sim/testsuite/{sim => }/m32r/ldb-d.cgs (100%) rename sim/testsuite/{sim => }/m32r/ldb.cgs (100%) rename sim/testsuite/{sim => }/m32r/ldh-d.cgs (100%) rename sim/testsuite/{sim => }/m32r/ldh.cgs (100%) rename sim/testsuite/{sim => }/m32r/ldi16.cgs (100%) rename sim/testsuite/{sim => }/m32r/ldi8.cgs (100%) rename sim/testsuite/{sim => }/m32r/ldub-d.cgs (100%) rename sim/testsuite/{sim => }/m32r/ldub.cgs (100%) rename sim/testsuite/{sim => }/m32r/lduh-d.cgs (100%) rename sim/testsuite/{sim => }/m32r/lduh.cgs (100%) rename sim/testsuite/{sim => }/m32r/lock.cgs (100%) rename sim/testsuite/{sim => }/m32r/machi.cgs (100%) rename sim/testsuite/{sim => }/m32r/maclo.cgs (100%) rename sim/testsuite/{sim => }/m32r/macwhi.cgs (100%) rename sim/testsuite/{sim => }/m32r/macwlo.cgs (100%) rename sim/testsuite/{sim => }/m32r/misc.exp (100%) rename sim/testsuite/{sim => }/m32r/mul.cgs (100%) rename sim/testsuite/{sim => }/m32r/mulhi.cgs (100%) rename sim/testsuite/{sim => }/m32r/mullo.cgs (100%) rename sim/testsuite/{sim => }/m32r/mulwhi.cgs (100%) rename sim/testsuite/{sim => }/m32r/mulwlo.cgs (100%) rename sim/testsuite/{sim => }/m32r/mv.cgs (100%) rename sim/testsuite/{sim => }/m32r/mvfachi.cgs (100%) rename sim/testsuite/{sim => }/m32r/mvfaclo.cgs (100%) rename sim/testsuite/{sim => }/m32r/mvfacmi.cgs (100%) rename sim/testsuite/{sim => }/m32r/mvfc.cgs (100%) rename sim/testsuite/{sim => }/m32r/mvtachi.cgs (100%) rename sim/testsuite/{sim => }/m32r/mvtaclo.cgs (100%) rename sim/testsuite/{sim => }/m32r/mvtc.cgs (100%) rename sim/testsuite/{sim => }/m32r/neg.cgs (100%) rename sim/testsuite/{sim => }/m32r/nop.cgs (100%) rename sim/testsuite/{sim => }/m32r/not.cgs (100%) rename sim/testsuite/{sim => }/m32r/or.cgs (100%) rename sim/testsuite/{sim => }/m32r/or3.cgs (100%) rename sim/testsuite/{sim => }/m32r/rac.cgs (100%) rename sim/testsuite/{sim => }/m32r/rach.cgs (100%) rename sim/testsuite/{sim => }/m32r/rem.cgs (100%) rename sim/testsuite/{sim => }/m32r/remu.cgs (100%) rename sim/testsuite/{sim => }/m32r/rte.cgs (100%) rename sim/testsuite/{sim => }/m32r/seth.cgs (100%) rename sim/testsuite/{sim => }/m32r/sll.cgs (100%) rename sim/testsuite/{sim => }/m32r/sll3.cgs (100%) rename sim/testsuite/{sim => }/m32r/slli.cgs (100%) rename sim/testsuite/{sim => }/m32r/sra.cgs (100%) rename sim/testsuite/{sim => }/m32r/sra3.cgs (100%) rename sim/testsuite/{sim => }/m32r/srai.cgs (100%) rename sim/testsuite/{sim => }/m32r/srl.cgs (100%) rename sim/testsuite/{sim => }/m32r/srl3.cgs (100%) rename sim/testsuite/{sim => }/m32r/srli.cgs (100%) rename sim/testsuite/{sim => }/m32r/st-d.cgs (100%) rename sim/testsuite/{sim => }/m32r/st-minus.cgs (100%) rename sim/testsuite/{sim => }/m32r/st-plus.cgs (100%) rename sim/testsuite/{sim => }/m32r/st.cgs (100%) rename sim/testsuite/{sim => }/m32r/stb-d.cgs (100%) rename sim/testsuite/{sim => }/m32r/stb.cgs (100%) rename sim/testsuite/{sim => }/m32r/sth-d.cgs (100%) rename sim/testsuite/{sim => }/m32r/sth.cgs (100%) rename sim/testsuite/{sim => }/m32r/sub.cgs (100%) rename sim/testsuite/{sim => }/m32r/subv.cgs (100%) rename sim/testsuite/{sim => }/m32r/subx.cgs (100%) rename sim/testsuite/{sim => }/m32r/testutils.inc (100%) rename sim/testsuite/{sim => }/m32r/trap.cgs (100%) rename sim/testsuite/{sim => }/m32r/unlock.cgs (100%) rename sim/testsuite/{sim => }/m32r/uread16.ms (100%) rename sim/testsuite/{sim => }/m32r/uread32.ms (100%) rename sim/testsuite/{sim => }/m32r/uwrite16.ms (100%) rename sim/testsuite/{sim => }/m32r/uwrite32.ms (100%) rename sim/testsuite/{sim => }/m32r/xor.cgs (100%) rename sim/testsuite/{sim => }/m32r/xor3.cgs (100%) rename sim/testsuite/{sim => }/m68hc11/ChangeLog (100%) rename sim/testsuite/{sim => }/m68hc11/allinsn.exp (100%) rename sim/testsuite/{sim => }/m68hc11/pass.s (100%) rename sim/testsuite/{sim => }/m68hc11/testutils.inc (100%) rename sim/testsuite/{sim => }/mcore/ChangeLog (100%) rename sim/testsuite/{sim => }/mcore/allinsn.exp (100%) rename sim/testsuite/{sim => }/mcore/fail.s (100%) rename sim/testsuite/{sim => }/mcore/pass.s (100%) rename sim/testsuite/{sim => }/mcore/testutils.inc (100%) rename sim/testsuite/{sim => }/microblaze/ChangeLog (100%) rename sim/testsuite/{sim => }/microblaze/allinsn.exp (100%) rename sim/testsuite/{sim => }/microblaze/pass.s (100%) rename sim/testsuite/{sim => }/microblaze/testutils.inc (100%) rename sim/testsuite/{sim => }/mips/ChangeLog (100%) rename sim/testsuite/{sim => }/mips/basic.exp (100%) rename sim/testsuite/{sim => }/mips/fpu64-ps-sb1.s (100%) rename sim/testsuite/{sim => }/mips/fpu64-ps.s (100%) rename sim/testsuite/{sim => }/mips/hilo-hazard-1.s (100%) rename sim/testsuite/{sim => }/mips/hilo-hazard-2.s (100%) rename sim/testsuite/{sim => }/mips/hilo-hazard-3.s (100%) rename sim/testsuite/{sim => }/mips/hilo-hazard-4.s (100%) rename sim/testsuite/{sim => }/mips/mdmx-ob-sb1.s (100%) rename sim/testsuite/{sim => }/mips/mdmx-ob.s (100%) rename sim/testsuite/{sim => }/mips/mips32-dsp.s (100%) rename sim/testsuite/{sim => }/mips/mips32-dsp2.s (100%) rename sim/testsuite/{sim => }/mips/sanity.s (100%) rename sim/testsuite/{sim => }/mips/testutils.inc (100%) rename sim/testsuite/{sim => }/mips/utils-dsp.inc (100%) rename sim/testsuite/{sim => }/mips/utils-fpu.inc (100%) rename sim/testsuite/{sim => }/mips/utils-mdmx.inc (100%) rename sim/testsuite/{sim => }/mn10300/ChangeLog (100%) rename sim/testsuite/{sim => }/mn10300/allinsn.exp (100%) rename sim/testsuite/{sim => }/mn10300/pass.s (100%) rename sim/testsuite/{sim => }/mn10300/testutils.inc (100%) rename sim/testsuite/{sim => }/moxie/ChangeLog (100%) rename sim/testsuite/{sim => }/moxie/allinsn.exp (100%) rename sim/testsuite/{sim => }/moxie/pass.s (100%) rename sim/testsuite/{sim => }/moxie/testutils.inc (100%) rename sim/testsuite/{sim => }/msp430/ChangeLog (100%) rename sim/testsuite/{sim => }/msp430/add.s (100%) rename sim/testsuite/{sim => }/msp430/allinsn.exp (100%) rename sim/testsuite/{sim => }/msp430/mpyull_hwmult.s (100%) rename sim/testsuite/{sim => }/msp430/rrux.s (100%) rename sim/testsuite/{sim => }/msp430/testutils.inc (100%) rename sim/testsuite/{sim => }/or1k/ChangeLog (100%) rename sim/testsuite/{sim => }/or1k/add.S (100%) rename sim/testsuite/{sim => }/or1k/adrp.S (100%) rename sim/testsuite/{sim => }/or1k/alltests.exp (100%) rename sim/testsuite/{sim => }/or1k/and.S (100%) rename sim/testsuite/{sim => }/or1k/basic.S (100%) rename sim/testsuite/{sim => }/or1k/div.S (100%) rename sim/testsuite/{sim => }/or1k/ext.S (100%) rename sim/testsuite/{sim => }/or1k/find.S (100%) rename sim/testsuite/{sim => }/or1k/flag.S (100%) rename sim/testsuite/{sim => }/or1k/fpu-unordered.S (100%) rename sim/testsuite/{sim => }/or1k/fpu.S (100%) rename sim/testsuite/{sim => }/or1k/fpu64a32-unordered.S (100%) rename sim/testsuite/{sim => }/or1k/fpu64a32.S (100%) rename sim/testsuite/{sim => }/or1k/jump.S (100%) rename sim/testsuite/{sim => }/or1k/load.S (100%) rename sim/testsuite/{sim => }/or1k/mac.S (100%) rename sim/testsuite/{sim => }/or1k/mfspr.S (100%) rename sim/testsuite/{sim => }/or1k/mul.S (100%) rename sim/testsuite/{sim => }/or1k/or.S (100%) rename sim/testsuite/{sim => }/or1k/or1k-asm-test-env.h (100%) rename sim/testsuite/{sim => }/or1k/or1k-asm-test-helpers.h (100%) rename sim/testsuite/{sim => }/or1k/or1k-asm-test.h (100%) rename sim/testsuite/{sim => }/or1k/or1k-asm.h (100%) rename sim/testsuite/{sim => }/or1k/or1k-test.ld (100%) rename sim/testsuite/{sim => }/or1k/ror.S (100%) rename sim/testsuite/{sim => }/or1k/shift.S (100%) rename sim/testsuite/{sim => }/or1k/spr-defs.h (100%) rename sim/testsuite/{sim => }/or1k/sub.S (100%) rename sim/testsuite/{sim => }/or1k/xor.S (100%) rename sim/testsuite/{sim => }/pru/ChangeLog (100%) rename sim/testsuite/{sim => }/pru/add.s (100%) rename sim/testsuite/{sim => }/pru/allinsn.exp (100%) rename sim/testsuite/{sim => }/pru/dmem-zero-pass.s (100%) rename sim/testsuite/{sim => }/pru/dmem-zero-trap.s (100%) rename sim/testsuite/{sim => }/pru/dram.s (100%) rename sim/testsuite/{sim => }/pru/jmp.s (100%) rename sim/testsuite/{sim => }/pru/lmbd.s (100%) rename sim/testsuite/{sim => }/pru/loop-imm.s (100%) rename sim/testsuite/{sim => }/pru/loop-reg.s (100%) rename sim/testsuite/{sim => }/pru/mul.s (100%) rename sim/testsuite/{sim => }/pru/subreg.s (100%) rename sim/testsuite/{sim => }/pru/testutils.inc (100%) rename sim/testsuite/{sim => }/sh/ChangeLog (100%) rename sim/testsuite/{sim => }/sh/add.s (100%) rename sim/testsuite/{sim => }/sh/allinsn.exp (100%) rename sim/testsuite/{sim => }/sh/and.s (100%) rename sim/testsuite/{sim => }/sh/bandor.s (100%) rename sim/testsuite/{sim => }/sh/bandornot.s (100%) rename sim/testsuite/{sim => }/sh/bclr.s (100%) rename sim/testsuite/{sim => }/sh/bld.s (100%) rename sim/testsuite/{sim => }/sh/bldnot.s (100%) rename sim/testsuite/{sim => }/sh/bset.s (100%) rename sim/testsuite/{sim => }/sh/bst.s (100%) rename sim/testsuite/{sim => }/sh/bxor.s (100%) rename sim/testsuite/{sim => }/sh/clip.s (100%) rename sim/testsuite/{sim => }/sh/div.s (100%) rename sim/testsuite/{sim => }/sh/dmxy.s (100%) rename sim/testsuite/{sim => }/sh/fabs.s (100%) rename sim/testsuite/{sim => }/sh/fadd.s (100%) rename sim/testsuite/{sim => }/sh/fail.s (100%) rename sim/testsuite/{sim => }/sh/fcmpeq.s (100%) rename sim/testsuite/{sim => }/sh/fcmpgt.s (100%) rename sim/testsuite/{sim => }/sh/fcnvds.s (100%) rename sim/testsuite/{sim => }/sh/fcnvsd.s (100%) rename sim/testsuite/{sim => }/sh/fdiv.s (100%) rename sim/testsuite/{sim => }/sh/fipr.s (100%) rename sim/testsuite/{sim => }/sh/fldi0.s (100%) rename sim/testsuite/{sim => }/sh/fldi1.s (100%) rename sim/testsuite/{sim => }/sh/flds.s (100%) rename sim/testsuite/{sim => }/sh/float.s (100%) rename sim/testsuite/{sim => }/sh/fmac.s (100%) rename sim/testsuite/{sim => }/sh/fmov.s (100%) rename sim/testsuite/{sim => }/sh/fmul.s (100%) rename sim/testsuite/{sim => }/sh/fneg.s (100%) rename sim/testsuite/{sim => }/sh/fpchg.s (100%) rename sim/testsuite/{sim => }/sh/frchg.s (100%) rename sim/testsuite/{sim => }/sh/fsca.s (100%) rename sim/testsuite/{sim => }/sh/fschg.s (100%) rename sim/testsuite/{sim => }/sh/fsqrt.s (100%) rename sim/testsuite/{sim => }/sh/fsrra.s (100%) rename sim/testsuite/{sim => }/sh/fsub.s (100%) rename sim/testsuite/{sim => }/sh/ftrc.s (100%) rename sim/testsuite/{sim => }/sh/ldrc.s (100%) rename sim/testsuite/{sim => }/sh/loop.s (100%) rename sim/testsuite/{sim => }/sh/macl.s (100%) rename sim/testsuite/{sim => }/sh/macw.s (100%) rename sim/testsuite/{sim => }/sh/mov.s (100%) rename sim/testsuite/{sim => }/sh/movi.s (100%) rename sim/testsuite/{sim => }/sh/movli.s (100%) rename sim/testsuite/{sim => }/sh/movua.s (100%) rename sim/testsuite/{sim => }/sh/movxy.s (100%) rename sim/testsuite/{sim => }/sh/mulr.s (100%) rename sim/testsuite/{sim => }/sh/pabs.s (100%) rename sim/testsuite/{sim => }/sh/padd.s (100%) rename sim/testsuite/{sim => }/sh/paddc.s (100%) rename sim/testsuite/{sim => }/sh/pand.s (100%) rename sim/testsuite/{sim => }/sh/pass.s (100%) rename sim/testsuite/{sim => }/sh/pclr.s (100%) rename sim/testsuite/{sim => }/sh/pdec.s (100%) rename sim/testsuite/{sim => }/sh/pdmsb.s (100%) rename sim/testsuite/{sim => }/sh/pinc.s (100%) rename sim/testsuite/{sim => }/sh/pmuls.s (100%) rename sim/testsuite/{sim => }/sh/prnd.s (100%) rename sim/testsuite/{sim => }/sh/pshai.s (100%) rename sim/testsuite/{sim => }/sh/pshar.s (100%) rename sim/testsuite/{sim => }/sh/pshli.s (100%) rename sim/testsuite/{sim => }/sh/pshlr.s (100%) rename sim/testsuite/{sim => }/sh/psub.s (100%) rename sim/testsuite/{sim => }/sh/pswap.s (100%) rename sim/testsuite/{sim => }/sh/pushpop.s (100%) rename sim/testsuite/{sim => }/sh/resbank.s (100%) rename sim/testsuite/{sim => }/sh/sett.s (100%) rename sim/testsuite/{sim => }/sh/shll.s (100%) rename sim/testsuite/{sim => }/sh/shll16.s (100%) rename sim/testsuite/{sim => }/sh/shll2.s (100%) rename sim/testsuite/{sim => }/sh/shll8.s (100%) rename sim/testsuite/{sim => }/sh/shlr.s (100%) rename sim/testsuite/{sim => }/sh/shlr16.s (100%) rename sim/testsuite/{sim => }/sh/shlr2.s (100%) rename sim/testsuite/{sim => }/sh/shlr8.s (100%) rename sim/testsuite/{sim => }/sh/swap.s (100%) rename sim/testsuite/{sim => }/sh/testutils.inc (100%) rename sim/testsuite/{sim => }/v850/ChangeLog (100%) rename sim/testsuite/{sim => }/v850/allinsns.exp (100%) rename sim/testsuite/{sim => }/v850/bsh.cgs (100%) rename sim/testsuite/{sim => }/v850/div.cgs (100%) rename sim/testsuite/{sim => }/v850/divh.cgs (100%) rename sim/testsuite/{sim => }/v850/divh_3.cgs (100%) rename sim/testsuite/{sim => }/v850/divhu.cgs (100%) rename sim/testsuite/{sim => }/v850/divu.cgs (100%) rename sim/testsuite/{sim => }/v850/sar.cgs (100%) rename sim/testsuite/{sim => }/v850/satadd.cgs (100%) rename sim/testsuite/{sim => }/v850/satsub.cgs (100%) rename sim/testsuite/{sim => }/v850/satsubi.cgs (100%) rename sim/testsuite/{sim => }/v850/satsubr.cgs (100%) rename sim/testsuite/{sim => }/v850/shl.cgs (100%) rename sim/testsuite/{sim => }/v850/shr.cgs (100%) rename sim/testsuite/{sim => }/v850/testutils.cgs (100%) rename sim/testsuite/{sim => }/v850/testutils.inc (100%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-defconfig updated (de56ef90 -> 7b6684dc)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-defconfig in repository toolchain/ci/base-artifacts. discards de56ef90 0: update: binutils-gcc-linux-qemu: boot new 7b6684dc 0: update: binutils-gcc-linux-qemu: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (de56ef90) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-arm-ma [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 305 +- 02-prepare_abe/console.log | 126 +- 03-build_abe-binutils/console.log | 11712 ++++----- 04-build_abe-stage1/console.log | 20855 ++++++++------- 05-build_linux/console.log | 548 +- 06-build_abe-qemu/console.log | 6755 +++-- 07-boot_linux/console.log | 418 +- 08-check_regression/console.log | 12 +- 08-check_regression/results.regressions | 3 +- 09-update_baseline/console.log | 18 +- 09-update_baseline/results.regressions | 3 +- console.log | 40757 +++++++++++++++--------------- jenkins/manifest.sh | 20 +- results | 2 +- 14 files changed, 40811 insertions(+), 40723 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allnoconfig updated (7c79721606 -> 7cb6b97300)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allnoconfig in repository toolchain/ci/qemu. from 7c79721606 Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-t [...] adds 8cd0b410a2 target/mips: Add CP0 Config0 register definitions for MIPS3 ISA adds b4cbbb47b0 target/mips: Replace CP0_Config0 magic values by proper definitions adds 07ae8ccd0f target/mips/addr: Add translation helpers for KSEG1 adds 737cca57d3 target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment adds bf5523773e target/mips/mips-defs: Reorder CPU_MIPS5 definition adds 8b0ea9b638 target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1 adds b0586b38cb target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit() adds ce49581feb hw/mips/boston: Check 64-bit support with cpu_type_is_64bit() adds 08e2262fad target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1 adds f395cef765 target/mips/mips-defs: Use ISA_MIPS32R2 definition to check [...] adds 4d1524d2ce target/mips/mips-defs: Use ISA_MIPS32R3 definition to check [...] adds d913c3992d target/mips/mips-defs: Use ISA_MIPS32R5 definition to check [...] adds 13514fc93e target/mips/mips-defs: Use ISA_MIPS32R6 definition to check [...] adds bbd5e4a27f target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 adds 7a47bae586 target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 adds bae4b15aa4 target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 adds 5f89ce4fc2 target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 adds 2e211e0a12 target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 adds 9bcd41d41f target/mips: Inline cpu_state_reset() in mips_cpu_reset() adds 81ddae7c30 target/mips: Extract FPU helpers to 'fpu_helper.h' adds f9bd3d79f4 target/mips: Add !CONFIG_USER_ONLY comment after #endif adds 2be565f9c2 target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs adds e9927723ba target/mips: Move common helpers from helper.c to cpu.c adds 4cb213dc90 target/mips: Rename helper.c as tlb_helper.c adds ca2690e36a target/mips: Fix code style for checkpatch.pl adds f2c5b39ecd target/mips: Move mmu_init() functions to tlb_helper.c adds 0dc351ca6b target/mips: Rename translate_init.c as cpu-defs.c adds e31309365e target/mips/translate: Extract DisasContext structure adds 46c9e2b3dd target/mips/translate: Add declarations for generic code adds 11a7511856 target/mips: Replace gen_exception_err(err=0) by gen_excepti [...] adds 3a4ef3b7ee target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_ [...] adds 8758d1b8aa target/mips: Declare generic FPU / Coprocessor functions in [...] adds 57eedcf7e3 target/mips: Extract FPU specific definitions to translate.h adds 8b7322add3 target/mips: Only build TCG code when CONFIG_TCG is set adds 311edee771 target/mips/translate: Extract decode_opc_legacy() from deco [...] adds d7efb69382 target/mips/translate: Expose check_mips_64() to 32-bit mode adds 25a1362875 target/mips: Introduce ase_msa_available() helper adds 72f31f60f8 target/mips: Simplify msa_reset() adds aa314198ca target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA adds 33942f9460 target/mips: Simplify MSA TCG logic adds 7e2a619a04 target/mips: Remove now unused ASE_MSA definition adds e2665f314d target/mips: Alias MSA vector registers on FPU scalar registers adds 959c5da28e target/mips: Extract msa_translate_init() from mips_tcg_init() adds 63af5b9018 target/mips: Remove CPUMIPSState* argument from gen_msa*() methods adds 810fda17c8 target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() adds 03e4d95c91 target/mips: Move msa_reset() to msa_helper.c adds 3ef60574b6 target/mips: Extract MSA helpers from op_helper.c adds edb2384728 target/mips: Extract MSA helper definitions adds 54ccff5102 target/mips: Declare gen_msa/_branch() in 'translate.h' adds 80e64a380f target/mips: Extract MSA translation routines adds 878b87b541 target/mips: Pass TCGCond argument to MSA gen_check_zero_element() adds c7a9ef7517 target/mips: Introduce decode tree bindings for MSA ASE adds 96e5b4c758 target/mips: Use decode_ase_msa() generated from decodetree adds a685f7d075 target/mips: Extract LSA/DLSA translation generators adds 5f21f30d85 target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes adds 3f7a927847 target/mips: Introduce decodetree helpers for Release6 LSA/D [...] adds 0e9524af2d target/mips: Remove now unreachable LSA/DLSA opcodes code adds aac357ec89 target/mips: Convert Rel6 Special2 opcode to decodetree adds ddc7ef8dfe target/mips: Convert Rel6 COP1X opcode to decodetree adds 6513ca15d8 target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree adds 9a7372e354 target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree adds dd5697b2f9 target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree adds 13a839cf48 target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree adds 1ff668dde2 target/mips: Convert Rel6 LLD/SCD opcodes to decodetree adds 27ea1bc077 target/mips: Convert Rel6 LL/SC opcodes to decodetree adds 6648042afb target/mips: Remove CPU_R5900 definition adds fc63010e9b target/mips: Remove CPU_NANOMIPS32 definition adds eaca85763b target/mips: Remove vendor specific CPU definitions adds cd669e2051 docs/system: Remove deprecated 'fulong2e' machine alias adds 256af05f52 Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mip [...] adds 89fbea8737 9pfs: Fully restart unreclaim loop (CVE-2021-20181) adds a968a38005 Merge remote-tracking branch 'remotes/gkurz-gitlab/tags/9p-n [...] adds e80be993b5 ui/gtk: don't try to redefine SI prefixes adds 0431e369b0 ui/gtk: rename variable window to widget adds 3c4b8f8310 ui/gtk: limit virtual console max update interval adds 0fdc99775c ui/gtk: expose gd_monitor_update_interval adds cab82424f6 ui/gtk: update monitor interval on egl displays adds 521534df57 vnc: fix unfinalized tlscreds for VncDisplay adds 7b5fa0b583 ui: add support for remote power control to VNC server adds 5f8679fe46 vnc: Fix a memleak in vnc_display_connect() adds b3c2de9cd5 vnc: move check into vnc_cursor_define adds 9e1632ad07 vnc: move initialization to framebuffer_update_request adds 763deea7e9 vnc: add support for extended desktop resize adds 7cb6b97300 Merge remote-tracking branch 'remotes/kraxel/tags/ui-2021011 [...] No new revisions were added by this update. Summary of changes: docs/system/deprecated.rst | 5 - docs/system/removed-features.rst | 5 + hw/9pfs/9p.c | 6 +- hw/mips/boston.c | 6 +- hw/mips/fuloong2e.c | 1 - include/ui/gtk.h | 3 +- linux-user/mips/cpu_loop.c | 7 +- qemu-options.hx | 4 + target/mips/addr.c | 10 + target/mips/cp0_helper.c | 18 +- target/mips/cp0_timer.c | 4 +- .../mips/{translate_init.c.inc => cpu-defs.c.inc} | 128 +- target/mips/cpu.c | 255 +- target/mips/cpu.h | 23 +- target/mips/fpu_helper.c | 5 +- target/mips/fpu_helper.h | 59 + target/mips/gdbstub.c | 1 + target/mips/helper.h | 436 +-- target/mips/internal.h | 64 +- target/mips/kvm.c | 13 +- target/mips/machine.c | 1 + target/mips/meson.build | 21 +- target/mips/mips-defs.h | 56 +- target/mips/mips32r6.decode | 36 + target/mips/mips64r6.decode | 27 + target/mips/msa32.decode | 29 + target/mips/msa64.decode | 17 + target/mips/msa_helper.c | 430 +++ target/mips/msa_helper.h.inc | 443 +++ target/mips/msa_translate.c | 2286 +++++++++++ target/mips/op_helper.c | 396 +- target/mips/rel6_translate.c | 44 + target/mips/{helper.c => tlb_helper.c} | 266 +- target/mips/translate.c | 4034 ++++---------------- target/mips/translate.h | 177 + target/mips/translate_addr_const.c | 61 + ui/gtk-egl.c | 3 + ui/gtk.c | 25 +- ui/vnc.c | 147 +- ui/vnc.h | 15 + 40 files changed, 5016 insertions(+), 4551 deletions(-) rename target/mips/{translate_init.c.inc => cpu-defs.c.inc} (92%) create mode 100644 target/mips/fpu_helper.h create mode 100644 target/mips/mips32r6.decode create mode 100644 target/mips/mips64r6.decode create mode 100644 target/mips/msa32.decode create mode 100644 target/mips/msa64.decode create mode 100644 target/mips/msa_helper.h.inc create mode 100644 target/mips/msa_translate.c create mode 100644 target/mips/rel6_translate.c rename target/mips/{helper.c => tlb_helper.c} (87%) create mode 100644 target/mips/translate.h create mode 100644 target/mips/translate_addr_const.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allnoconfig updated (b0ccd3922f5 -> 2c356f221bb)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allnoconfig in repository toolchain/ci/gcc. from b0ccd3922f5 compiler: add support for reading embedcfg files adds c4eec1efae0 testsuite: Fix sed script errors in complex tests adds 2ea6f4a377e tree-optimization/98685 - fix placement of extern converts adds 7432f255b70 arm: Auto-vectorization for MVE: vshl adds bfab355012c arm: Auto-vectorization for MVE: vshr adds 0411ae7f08e libatomic, libgomp, libitc: Fix bootstrap [PR70454] adds cb60334b716 testsuite/96098 - remove redundant testcase adds 1a630642009 arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics adds d03f14c354a testsuite/96147 - remove scanning for ! vect_hw_misalign adds e1bd80fb706 testsuite/96147 - key scanning on vect_hw_misalign adds aa4ee5798fe testsuite/96147 - scan for vectorized load adds b36c9cd0947 testsuite/96147 - align vector access adds dc8475e3348 Pytest in tests: improve adds 446703ccc2c tree-optimization/96376 - do not check alignment for invari [...] adds f1d054017ef Revert "arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 [...] adds 63999d751df arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics adds f9a577927eb IBM Z: Fix linking to libatomic in target test cases adds 7f6cdaa9a8d rtl-ssa: Fix a silly typo adds f2cc526f47a recog: Fix insn_change_watermark destructor adds 5a783f42d77 aarch64: Add a minipass for fusing CC insns [PR88836] adds 492b90f33df c++: Fix langspecs with -fsyntax-only [PR98591] adds 1ba71fabb78 preprocessor: Make quoting : [PR 95253] adds 7d0df0aeb67 i386: Use cpp_define_formatted for __SIZEOF_FLOAT80__ definition adds d3959070aa4 [PATCH] aarch64: Implement vmlsl[_high]* intrinsics using builtins adds 50dbced2f37 openmp: Change the way of building of reduction array type adds adb520606ce c-family: Improve MEM_REF printing for diagnostics [PR98597] adds a3128bf0128 bootstrap: fix failing diagnostic selftest on Windows [PR98696] adds aaec739250b testsuite: Add testcase coverage for already fixed [PR96671] adds c0194736b47 gcc.dg/analyzer tests: use __builtin_alloca, not alloca.h adds cd09079cfd5 c++: Fix list-init of array of no-copy type [PR63707] adds ad260343385 AArch64: Add NEON, SVE and SVE2 RTL patterns for Multiply, [...] adds 424deca72b6 c++: Fix copy elision for base initialization adds d75199f7823 c++: Avoid redundant copy in {} init [PR98642] adds e63c2161d09 drop -dumpbase-ext from producer string adds 5c046034e3e match.pd: Optimize (x < 0) ^ (y < 0) to (x ^ y) < 0 etc. [PR96681] adds 0425f4c1b63 match.pd: Generalize the PR64309 simplifications [PR96669] adds e1efa6af61a preprocessor: Make quoting : [PR 95253] adds 9beb6d88eff c++: Fix qualified array-type construction [PR 98538] adds b90e4a97419 fortran: Fixes a bug in ISO_Fortran_binding.c. adds c029fcb5680 Reset force_source_line in final.c adds f1ad419ebfd rs6000, vector integer multiply/divide/modulo instructions adds 2f7f0d32e74 Daily bump. adds 2c356f221bb libstdc++-v3: Add -fcf-protection=none to -march=i486 No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 170 +++++++++ gcc/DATESTAMP | 2 +- gcc/Makefile.in | 7 + gcc/c-family/ChangeLog | 12 + gcc/c-family/c-pretty-print.c | 259 +++++++++++--- gcc/c/ChangeLog | 6 + gcc/c/c-typeck.c | 4 +- gcc/config.gcc | 2 +- gcc/config/aarch64/aarch64-cc-fusion.cc | 296 +++++++++++++++ gcc/config/aarch64/aarch64-passes.def | 1 + gcc/config/aarch64/aarch64-protos.h | 1 + gcc/config/aarch64/aarch64-simd-builtins.def | 8 + gcc/config/aarch64/aarch64-simd.md | 56 ++- gcc/config/aarch64/aarch64-sve.md | 56 +++ gcc/config/aarch64/aarch64-sve2.md | 42 +++ gcc/config/aarch64/arm_neon.h | 84 +---- gcc/config/aarch64/iterators.md | 109 +++++- gcc/config/aarch64/t-aarch64 | 6 + gcc/config/arm/arm_neon.h | 31 ++ gcc/config/arm/mve.md | 47 ++- gcc/config/arm/neon.md | 53 --- gcc/config/arm/vec-common.md | 58 +++ gcc/config/i386/i386-c.c | 9 +- gcc/config/rs6000/altivec.h | 4 + gcc/config/rs6000/altivec.md | 2 - gcc/config/rs6000/rs6000-builtin.def | 21 ++ gcc/config/rs6000/rs6000-call.c | 53 +++ gcc/config/rs6000/rs6000.md | 5 +- gcc/config/rs6000/vsx.md | 211 ++++++++--- gcc/cp/ChangeLog | 35 ++ gcc/cp/call.c | 145 ++++++-- gcc/cp/cp-tree.h | 3 +- gcc/cp/lang-specs.h | 40 ++- gcc/cp/tree.c | 18 +- gcc/cp/typeck2.c | 21 +- gcc/diagnostic.c | 12 +- gcc/doc/extend.texi | 120 +++++++ gcc/doc/install.texi | 2 +- gcc/doc/sourcebuild.texi | 4 + gcc/final.c | 1 + gcc/go/ChangeLog | 4 + gcc/match.pd | 39 +- gcc/opts.c | 1 + gcc/recog.h | 8 +- gcc/rtl-ssa/functions.h | 2 +- gcc/rtl-ssa/member-fns.inl | 2 +- gcc/testsuite/ChangeLog | 156 ++++++++ gcc/testsuite/g++.dg/cpp0x/initlist-array13.C | 16 + gcc/testsuite/g++.dg/cpp1z/elide4.C | 24 ++ gcc/testsuite/g++.dg/cpp1z/elide5.C | 15 + gcc/testsuite/g++.dg/modules/dep-1_a.C | 4 +- gcc/testsuite/g++.dg/modules/dep-1_b.C | 4 +- gcc/testsuite/g++.dg/modules/dep-2.C | 6 +- gcc/testsuite/g++.dg/modules/pr98591.H | 3 + gcc/testsuite/g++.dg/template/pr98538.C | 18 + gcc/testsuite/gcc.dg/analyzer/alloca-leak.c | 4 +- gcc/testsuite/gcc.dg/analyzer/data-model-1.c | 5 +- gcc/testsuite/gcc.dg/analyzer/malloc-1.c | 3 +- gcc/testsuite/gcc.dg/analyzer/malloc-paths-8.c | 7 +- gcc/testsuite/gcc.dg/tree-ssa/pr96669-1.c | 59 +++ gcc/testsuite/gcc.dg/tree-ssa/pr96671-1.c | 51 +++ gcc/testsuite/gcc.dg/tree-ssa/pr96671-2.c | 51 +++ gcc/testsuite/gcc.dg/tree-ssa/pr96681.c | 35 ++ gcc/testsuite/gcc.dg/uninit-38.c | 80 ++--- gcc/testsuite/gcc.dg/uninit-40.c | 50 +++ gcc/testsuite/gcc.dg/vect/bb-slp-32.c | 1 + gcc/testsuite/gcc.dg/vect/bb-slp-9.c | 2 +- gcc/testsuite/gcc.dg/vect/bb-slp-pr68892.c | 20 -- gcc/testsuite/gcc.dg/vect/bb-slp-pr98685.c | 15 + .../gcc.dg/vect/complex/complex-mla-template.c | 28 +- .../gcc.dg/vect/complex/complex-mls-template.c | 28 +- gcc/testsuite/gcc.dg/vect/slp-43.c | 4 +- gcc/testsuite/gcc.dg/vect/slp-45.c | 2 +- .../aarch64/advsimd-intrinsics/p64_p128.c | 46 ++- .../gcc.target/aarch64/sve/acle/general/ldff1_8.c | 32 ++ gcc/testsuite/gcc.target/aarch64/sve/ptest_1.c | 10 + gcc/testsuite/gcc.target/arm/simd/mve-vshl.c | 62 ++++ gcc/testsuite/gcc.target/arm/simd/mve-vshr.c | 59 +++ gcc/testsuite/gcc.target/arm/simd/vceqz_p64.c | 17 + gcc/testsuite/gcc.target/arm/simd/vceqzq_p64.c | 17 + .../gcc.target/powerpc/builtins-1-p10-runnable.c | 398 +++++++++++++++++++++ .../gcc.target/s390/md/atomic_exchange-1.c | 2 +- gcc/testsuite/gcc.target/s390/s390.exp | 4 + .../iso_fortran_binding_uint8_array.f90 | 11 + .../iso_fortran_binding_uint8_array_driver.c | 25 ++ gcc/testsuite/lib/gcov.exp | 31 +- gcc/tree-vect-slp.c | 11 +- gcc/tree-vect-stmts.c | 23 +- libatomic/ChangeLog | 9 + libatomic/configure.tgt | 56 +-- libcpp/ChangeLog | 5 + libcpp/mkdeps.c | 1 - libgfortran/ChangeLog | 6 + libgfortran/runtime/ISO_Fortran_binding.c | 3 +- libgomp/ChangeLog | 7 + libgomp/configure.tgt | 35 +- libitm/ChangeLog | 7 + libitm/configure.tgt | 37 +- .../atomic_flag/test_and_set/explicit-hle.cc | 2 +- 99 files changed, 3167 insertions(+), 512 deletions(-) create mode 100644 gcc/config/aarch64/aarch64-cc-fusion.cc create mode 100644 gcc/testsuite/g++.dg/cpp0x/initlist-array13.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/elide4.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/elide5.C create mode 100644 gcc/testsuite/g++.dg/modules/pr98591.H create mode 100644 gcc/testsuite/g++.dg/template/pr98538.C create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr96669-1.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr96671-1.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr96671-2.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr96681.c create mode 100644 gcc/testsuite/gcc.dg/uninit-40.c delete mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-pr68892.c create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-pr98685.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/ldff1_8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/ptest_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vshl.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vshr.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vceqz_p64.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vceqzq_p64.c create mode 100644 gcc/testsuite/gcc.target/powerpc/builtins-1-p10-runnable.c create mode 100644 gcc/testsuite/gfortran.dg/iso_fortran_binding_uint8_array.f90 create mode 100644 gcc/testsuite/gfortran.dg/iso_fortran_binding_uint8_array_driver.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allnoconfig updated (bb3eddb5bd -> 68b007788a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allnoconfig in repository toolchain/ci/binutils-gdb. from bb3eddb5bd sim: testsuite: delete configure script adds dcd709e056 RISC-V: Comments tidy and improvement. adds b800637e76 RISC-V: Error and warning messages tidy. adds 1942a04836 RISC-V: Indent and GNU coding standards tidy, also aligned t [...] adds 4bb5732e27 RISC-V: Fixed the indent that caused by the previous commits [...] adds 10f92414d6 [gdb/testsuite] Fix gdb.fortran/array-slices.exp with -m32 adds 5a11fff005 gdb/tui: compare pointer to nullptr, not 0 adds e403a898b5 Automatic date update in version.in adds 1368b914e9 sim: testsuite: flatten tree adds eb6e6af8c1 PR26002 undefined symbol VER_NDX_GLOBAL vs. VER_NDX_LOCAL adds ad92f33d38 Tidy inflateEnd calls adds 68b007788a ld/x86: Add -z report-relative-reloc No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 45 + bfd/compress.c | 3 +- bfd/elf-linker-x86.h | 3 + bfd/elf32-i386.c | 36 + bfd/elf64-x86-64.c | 33 + bfd/elflink.c | 2 +- bfd/elfnn-riscv.c | 319 +++-- bfd/elfxx-riscv.c | 54 +- bfd/elfxx-riscv.h | 4 +- bfd/elfxx-x86.c | 47 + bfd/elfxx-x86.h | 4 + bfd/version.h | 2 +- binutils/ChangeLog | 4 + binutils/readelf.c | 4 +- gas/ChangeLog | 23 + gas/config/tc-riscv.c | 521 ++++--- gas/config/tc-riscv.h | 6 +- gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 6 +- .../gas/riscv/priv-reg-fail-read-only-01.l | 136 +- .../gas/riscv/priv-reg-fail-read-only-02.l | 48 +- gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 130 +- .../gas/riscv/priv-reg-fail-version-1p10.l | 48 +- .../gas/riscv/priv-reg-fail-version-1p11.l | 46 +- .../gas/riscv/priv-reg-fail-version-1p9p1.l | 54 +- gdb/ChangeLog | 4 + gdb/testsuite/ChangeLog | 6 + gdb/testsuite/gdb.fortran/array-slices.exp | 2 +- gdb/tui/tui.c | 4 +- include/ChangeLog | 11 + include/elf/riscv.h | 3 +- include/opcode/riscv-opc.h | 16 +- include/opcode/riscv.h | 127 +- ld/ChangeLog | 35 + ld/NEWS | 3 + ld/emulparams/elf32_x86_64.sh | 1 + ld/emulparams/elf_i386.sh | 1 + ld/emulparams/elf_x86_64.sh | 1 + ld/emulparams/x86-report-relative.sh | 11 + ld/ld.texi | 4 + ld/testsuite/ld-elfvers/vers16.dsym | 2 +- ld/testsuite/ld-elfvers/vers6.dsym | 2 +- ld/testsuite/ld-i386/i386.exp | 1 + ld/testsuite/ld-i386/report-reloc-1.d | 10 + ld/testsuite/ld-i386/report-reloc-1.l | 2 + ld/testsuite/ld-i386/report-reloc-1.s | 12 + .../ld-riscv-elf/attr-merge-priv-spec-failed-01.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-02.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-03.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-04.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-05.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-06.d | 4 +- ld/testsuite/ld-x86-64/report-reloc-1-x32.d | 10 + ld/testsuite/ld-x86-64/report-reloc-1.d | 10 + ld/testsuite/ld-x86-64/report-reloc-1.l | 2 + ld/testsuite/ld-x86-64/report-reloc-1.s | 12 + ld/testsuite/ld-x86-64/x86-64.exp | 2 + opcodes/ChangeLog | 16 + opcodes/riscv-dis.c | 30 +- opcodes/riscv-opc.c | 1456 ++++++++++---------- sim/testsuite/ChangeLog | 5 + sim/testsuite/Makefile.in | 1 - sim/testsuite/{sim => }/aarch64/ChangeLog | 0 sim/testsuite/{sim => }/aarch64/adds.s | 0 sim/testsuite/{sim => }/aarch64/addv.s | 0 sim/testsuite/{sim => }/aarch64/allinsn.exp | 0 sim/testsuite/{sim => }/aarch64/bit.s | 0 sim/testsuite/{sim => }/aarch64/cmtst.s | 0 sim/testsuite/{sim => }/aarch64/cnt.s | 0 sim/testsuite/{sim => }/aarch64/fcmXX.s | 0 sim/testsuite/{sim => }/aarch64/fcmp.s | 0 sim/testsuite/{sim => }/aarch64/fcsel.s | 0 sim/testsuite/{sim => }/aarch64/fcvtl.s | 0 sim/testsuite/{sim => }/aarch64/fcvtz.s | 0 sim/testsuite/{sim => }/aarch64/fminnm.s | 0 sim/testsuite/{sim => }/aarch64/fstur.s | 0 sim/testsuite/{sim => }/aarch64/ldn_multiple.s | 0 sim/testsuite/{sim => }/aarch64/ldn_single.s | 0 sim/testsuite/{sim => }/aarch64/ldnr.s | 0 sim/testsuite/{sim => }/aarch64/mla.s | 0 sim/testsuite/{sim => }/aarch64/mls.s | 0 sim/testsuite/{sim => }/aarch64/mul.s | 0 sim/testsuite/{sim => }/aarch64/pass.s | 0 sim/testsuite/{sim => }/aarch64/stn_multiple.s | 0 sim/testsuite/{sim => }/aarch64/stn_single.s | 0 sim/testsuite/{sim => }/aarch64/sumov.s | 0 sim/testsuite/{sim => }/aarch64/sumulh.s | 0 sim/testsuite/{sim => }/aarch64/tbnz.s | 0 sim/testsuite/{sim => }/aarch64/testutils.inc | 0 sim/testsuite/{sim => }/aarch64/uzp.s | 0 sim/testsuite/{sim => }/aarch64/xtl.s | 0 sim/testsuite/{sim => }/aarch64/xtn.s | 0 sim/testsuite/{sim => }/arm/ChangeLog | 0 sim/testsuite/{sim => }/arm/adc.cgs | 0 sim/testsuite/{sim => }/arm/add.cgs | 0 sim/testsuite/{sim => }/arm/allinsn.exp | 0 sim/testsuite/{sim => }/arm/and.cgs | 0 sim/testsuite/{sim => }/arm/b.cgs | 0 sim/testsuite/{sim => }/arm/bic.cgs | 0 sim/testsuite/{sim => }/arm/bl.cgs | 0 sim/testsuite/{sim => }/arm/bx.cgs | 0 sim/testsuite/{sim => }/arm/cmn.cgs | 0 sim/testsuite/{sim => }/arm/cmp.cgs | 0 sim/testsuite/{sim => }/arm/eor.cgs | 0 sim/testsuite/{sim => }/arm/hello.ms | 0 sim/testsuite/{sim => }/arm/iwmmxt/iwmmxt.exp | 0 sim/testsuite/{sim => }/arm/iwmmxt/tbcst.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/testutils.inc | 0 sim/testsuite/{sim => }/arm/iwmmxt/textrm.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tinsr.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmia.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmiaph.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmiaxy.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmovmsk.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wacc.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wadd.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/waligni.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/walignr.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wand.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wandn.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wavg2.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wcmpeq.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wcmpgt.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmac.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmadd.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmax.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmin.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmov.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmul.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wor.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wpack.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wror.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsad.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wshufh.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsll.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsra.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsrl.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsub.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckeh.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckel.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckih.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckil.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wxor.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wzero.cgs | 0 sim/testsuite/{sim => }/arm/ldm.cgs | 0 sim/testsuite/{sim => }/arm/ldr.cgs | 0 sim/testsuite/{sim => }/arm/ldrb.cgs | 0 sim/testsuite/{sim => }/arm/ldrh.cgs | 0 sim/testsuite/{sim => }/arm/ldrsb.cgs | 0 sim/testsuite/{sim => }/arm/ldrsh.cgs | 0 sim/testsuite/{sim => }/arm/misaligned1.ms | 0 sim/testsuite/{sim => }/arm/misaligned2.ms | 0 sim/testsuite/{sim => }/arm/misaligned3.ms | 0 sim/testsuite/{sim => }/arm/misc.exp | 0 sim/testsuite/{sim => }/arm/mla.cgs | 0 sim/testsuite/{sim => }/arm/mov.cgs | 0 sim/testsuite/{sim => }/arm/movw-movt.ms | 0 sim/testsuite/{sim => }/arm/mrs.cgs | 0 sim/testsuite/{sim => }/arm/msr.cgs | 0 sim/testsuite/{sim => }/arm/mul.cgs | 0 sim/testsuite/{sim => }/arm/mvn.cgs | 0 sim/testsuite/{sim => }/arm/orr.cgs | 0 sim/testsuite/{sim => }/arm/rsb.cgs | 0 sim/testsuite/{sim => }/arm/rsc.cgs | 0 sim/testsuite/{sim => }/arm/sbc.cgs | 0 sim/testsuite/{sim => }/arm/smlal.cgs | 0 sim/testsuite/{sim => }/arm/smull.cgs | 0 sim/testsuite/{sim => }/arm/stm.cgs | 0 sim/testsuite/{sim => }/arm/str.cgs | 0 sim/testsuite/{sim => }/arm/strb.cgs | 0 sim/testsuite/{sim => }/arm/strh.cgs | 0 sim/testsuite/{sim => }/arm/sub.cgs | 0 sim/testsuite/{sim => }/arm/swi.cgs | 0 sim/testsuite/{sim => }/arm/swp.cgs | 0 sim/testsuite/{sim => }/arm/swpb.cgs | 0 sim/testsuite/{sim => }/arm/teq.cgs | 0 sim/testsuite/{sim => }/arm/testutils.inc | 0 sim/testsuite/{sim => }/arm/thumb/adc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add-hd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add-hd-rs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add-rd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add-sp.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add.cgs | 0 sim/testsuite/{sim => }/arm/thumb/addi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/addi8.cgs | 0 sim/testsuite/{sim => }/arm/thumb/allthumb.exp | 0 sim/testsuite/{sim => }/arm/thumb/and.cgs | 0 sim/testsuite/{sim => }/arm/thumb/asr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/b.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bcc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bcs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/beq.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bge.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bgt.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bhi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bic.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bl-hi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bl-lo.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ble.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bls.cgs | 0 sim/testsuite/{sim => }/arm/thumb/blt.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bmi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bne.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bpl.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bvc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bvs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bx-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bx-rs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmn.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmp-hd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmp-hd-rs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmp-rd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmp.cgs | 0 sim/testsuite/{sim => }/arm/thumb/eor.cgs | 0 sim/testsuite/{sim => }/arm/thumb/lda-pc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/lda-sp.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldmia.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldr-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldr-pc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldr-sprel.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldrb-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldrb.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldrh-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldrh.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldsb.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldsh.cgs | 0 sim/testsuite/{sim => }/arm/thumb/lsl.cgs | 0 sim/testsuite/{sim => }/arm/thumb/lsr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mov-hd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mov-hd-rs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mov-rd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mov.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mul.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mvn.cgs | 0 sim/testsuite/{sim => }/arm/thumb/neg.cgs | 0 sim/testsuite/{sim => }/arm/thumb/orr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/pop-pc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/pop.cgs | 0 sim/testsuite/{sim => }/arm/thumb/push-lr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/push.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ror.cgs | 0 sim/testsuite/{sim => }/arm/thumb/sbc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/stmia.cgs | 0 sim/testsuite/{sim => }/arm/thumb/str-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/str-sprel.cgs | 0 sim/testsuite/{sim => }/arm/thumb/str.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strb-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strb.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strh-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strh.cgs | 0 sim/testsuite/{sim => }/arm/thumb/sub-sp.cgs | 0 sim/testsuite/{sim => }/arm/thumb/sub.cgs | 0 sim/testsuite/{sim => }/arm/thumb/subi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/subi8.cgs | 0 sim/testsuite/{sim => }/arm/thumb/swi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/testutils.inc | 0 sim/testsuite/{sim => }/arm/thumb/tst.cgs | 0 sim/testsuite/{sim => }/arm/tst.cgs | 0 sim/testsuite/{sim => }/arm/umlal.cgs | 0 sim/testsuite/{sim => }/arm/umull.cgs | 0 sim/testsuite/{sim => }/arm/xscale/blx.cgs | 0 sim/testsuite/{sim => }/arm/xscale/mia.cgs | 0 sim/testsuite/{sim => }/arm/xscale/miaph.cgs | 0 sim/testsuite/{sim => }/arm/xscale/miaxy.cgs | 0 sim/testsuite/{sim => }/arm/xscale/mra.cgs | 0 sim/testsuite/{sim => }/arm/xscale/testutils.inc | 0 sim/testsuite/{sim => }/arm/xscale/xscale.exp | 0 sim/testsuite/{sim => }/avr/ChangeLog | 0 sim/testsuite/{sim => }/avr/allinsn.exp | 0 sim/testsuite/{sim => }/avr/pass.s | 0 sim/testsuite/{sim => }/avr/testutils.inc | 0 sim/testsuite/{sim => }/bfin/.gitignore | 0 sim/testsuite/{sim => }/bfin/10272_small.s | 0 sim/testsuite/{sim => }/bfin/10436.s | 0 sim/testsuite/{sim => }/bfin/10622.s | 0 sim/testsuite/{sim => }/bfin/10742.s | 0 sim/testsuite/{sim => }/bfin/10799.s | 0 sim/testsuite/{sim => }/bfin/11080.s | 0 sim/testsuite/{sim => }/bfin/7641.s | 0 sim/testsuite/{sim => }/bfin/ChangeLog | 0 sim/testsuite/{sim => }/bfin/PN_generator.s | 0 sim/testsuite/{sim => }/bfin/a0.s | 0 sim/testsuite/{sim => }/bfin/a0shift.S | 0 sim/testsuite/{sim => }/bfin/a1.s | 0 sim/testsuite/{sim => }/bfin/a10.s | 0 sim/testsuite/{sim => }/bfin/a11.S | 0 sim/testsuite/{sim => }/bfin/a12.s | 0 sim/testsuite/{sim => }/bfin/a2.s | 0 sim/testsuite/{sim => }/bfin/a20.S | 0 sim/testsuite/{sim => }/bfin/a21.s | 0 sim/testsuite/{sim => }/bfin/a22.s | 0 sim/testsuite/{sim => }/bfin/a23.s | 0 sim/testsuite/{sim => }/bfin/a24.s | 0 sim/testsuite/{sim => }/bfin/a25.s | 0 sim/testsuite/{sim => }/bfin/a26.s | 0 sim/testsuite/{sim => }/bfin/a3.s | 0 sim/testsuite/{sim => }/bfin/a30.s | 0 sim/testsuite/{sim => }/bfin/a4.s | 0 sim/testsuite/{sim => }/bfin/a5.s | 0 sim/testsuite/{sim => }/bfin/a6.s | 0 sim/testsuite/{sim => }/bfin/a7.s | 0 sim/testsuite/{sim => }/bfin/a8.s | 0 sim/testsuite/{sim => }/bfin/a9.s | 0 sim/testsuite/{sim => }/bfin/abs-2.S | 0 sim/testsuite/{sim => }/bfin/abs-3.S | 0 sim/testsuite/{sim => }/bfin/abs-4.S | 0 sim/testsuite/{sim => }/bfin/abs.S | 0 sim/testsuite/{sim => }/bfin/abs_acc.s | 0 sim/testsuite/{sim => }/bfin/acc-rot.s | 0 sim/testsuite/{sim => }/bfin/acp5_19.s | 0 sim/testsuite/{sim => }/bfin/acp5_4.s | 0 sim/testsuite/{sim => }/bfin/add_imm7.s | 0 sim/testsuite/{sim => }/bfin/add_shift.S | 0 sim/testsuite/{sim => }/bfin/add_sub_acc.s | 0 sim/testsuite/{sim => }/bfin/addsub_flags.S | 0 sim/testsuite/{sim => }/bfin/algnbug1.s | 0 sim/testsuite/{sim => }/bfin/algnbug2.s | 0 sim/testsuite/{sim => }/bfin/allinsn.exp | 0 sim/testsuite/{sim => }/bfin/argc.c | 0 sim/testsuite/{sim => }/bfin/ashift.s | 0 sim/testsuite/{sim => }/bfin/ashift_flags.s | 0 sim/testsuite/{sim => }/bfin/ashift_left.s | 0 sim/testsuite/{sim => }/bfin/b0.S | 0 sim/testsuite/{sim => }/bfin/b1.s | 0 sim/testsuite/{sim => }/bfin/b2.S | 0 sim/testsuite/{sim => }/bfin/brcc.s | 0 sim/testsuite/{sim => }/bfin/brevadd.s | 0 sim/testsuite/{sim => }/bfin/byteop16m.s | 0 sim/testsuite/{sim => }/bfin/byteop16p.s | 0 sim/testsuite/{sim => }/bfin/byteop1p.s | 0 sim/testsuite/{sim => }/bfin/byteop2p.s | 0 sim/testsuite/{sim => }/bfin/byteop3p.s | 0 sim/testsuite/{sim => }/bfin/byteunpack.s | 0 .../{sim => }/bfin/c_alu2op_arith_r_sft.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_b.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_h.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_mix.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_neg.s | 0 .../{sim => }/bfin/c_alu2op_conv_toggle.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_xb.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_xh.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_divq.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_divs.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_log_l_sft.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_log_r_sft.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_shadd_1.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_shadd_2.s | 0 sim/testsuite/{sim => }/bfin/c_br_preg_killed_ac.s | 0 .../{sim => }/bfin/c_br_preg_killed_ex1.s | 0 sim/testsuite/{sim => }/bfin/c_br_preg_stall_ac.s | 0 sim/testsuite/{sim => }/bfin/c_br_preg_stall_ex1.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_bp1.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_bp2.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_bp3.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_bp4.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_bp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_bp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_nbp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_fbkwd.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_nbp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brt_bp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brt_nbp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_kills_dhits.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_kills_dmiss.s | 0 sim/testsuite/{sim => }/bfin/c_cactrl_iflush_pr.s | 0 .../{sim => }/bfin/c_cactrl_iflush_pr_pp.s | 0 sim/testsuite/{sim => }/bfin/c_calla_ljump.s | 0 sim/testsuite/{sim => }/bfin/c_calla_subr.s | 0 sim/testsuite/{sim => }/bfin/c_cc2dreg.s | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_ac.S | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_an.s | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_aq.s | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av0.S | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av1.S | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_az.s | 0 .../{sim => }/bfin/c_cc_flag_ccmv_depend.S | 0 .../{sim => }/bfin/c_cc_flagdreg_mvbrsft.s | 0 .../{sim => }/bfin/c_cc_flagdreg_mvbrsft_s1.s | 0 .../{sim => }/bfin/c_cc_flagdreg_mvbrsft_sn.s | 0 .../{sim => }/bfin/c_cc_regmvlogi_mvbrsft.s | 0 .../{sim => }/bfin/c_cc_regmvlogi_mvbrsft_s1.s | 0 .../{sim => }/bfin/c_cc_regmvlogi_mvbrsft_sn.S | 0 sim/testsuite/{sim => }/bfin/c_ccflag_a0a1.S | 0 sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr_uu.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3_uu.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3_uu.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr_uu.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_cc_pr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_ncc_pr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_comp3op_dr_and_dr.s | 0 .../{sim => }/bfin/c_comp3op_dr_minus_dr.s | 0 sim/testsuite/{sim => }/bfin/c_comp3op_dr_mix.s | 0 sim/testsuite/{sim => }/bfin/c_comp3op_dr_or_dr.s | 0 .../{sim => }/bfin/c_comp3op_dr_plus_dr.s | 0 sim/testsuite/{sim => }/bfin/c_comp3op_dr_xor_dr.s | 0 .../{sim => }/bfin/c_comp3op_pr_plus_pr_sh1.s | 0 .../{sim => }/bfin/c_comp3op_pr_plus_pr_sh2.s | 0 .../{sim => }/bfin/c_compi2opd_dr_add_i7_n.s | 0 .../{sim => }/bfin/c_compi2opd_dr_add_i7_p.s | 0 .../{sim => }/bfin/c_compi2opd_dr_eq_i7_n.s | 0 .../{sim => }/bfin/c_compi2opd_dr_eq_i7_p.s | 0 sim/testsuite/{sim => }/bfin/c_compi2opd_flags.S | 0 sim/testsuite/{sim => }/bfin/c_compi2opd_flags_2.S | 0 .../{sim => }/bfin/c_compi2opp_pr_add_i7_n.s | 0 .../{sim => }/bfin/c_compi2opp_pr_add_i7_p.s | 0 .../{sim => }/bfin/c_compi2opp_pr_eq_i7_n.s | 0 .../{sim => }/bfin/c_compi2opp_pr_eq_i7_p.s | 0 .../{sim => }/bfin/c_dagmodik_lnz_imgebl.s | 0 .../{sim => }/bfin/c_dagmodik_lnz_imltbl.s | 0 .../{sim => }/bfin/c_dagmodik_lz_inc_dec.s | 0 .../{sim => }/bfin/c_dagmodim_lnz_imgebl.s | 0 .../{sim => }/bfin/c_dagmodim_lnz_imltbl.s | 0 .../{sim => }/bfin/c_dagmodim_lz_inc_dec.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_a0_pm_a1.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_a0a1s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_a_abs_a.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_a_neg_a.s | 0 .../{sim => }/bfin/c_dsp32alu_aa_absabs.s | 0 .../{sim => }/bfin/c_dsp32alu_aa_negneg.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_abs.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_absabs.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_alhwx.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_awx.s | 0 .../{sim => }/bfin/c_dsp32alu_byteop1ew.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop2.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop3.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_bytepack.s | 0 .../{sim => }/bfin/c_dsp32alu_byteunpack.s | 0 .../{sim => }/bfin/c_dsp32alu_disalnexcpt.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_max.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_maxmax.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_min.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_minmin.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_mix.s | 0 .../{sim => }/bfin/c_dsp32alu_r_lh_a0pa1.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_r_negneg.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_p.s | 0 .../{sim => }/bfin/c_dsp32alu_rh_rnd12_m.s | 0 .../{sim => }/bfin/c_dsp32alu_rh_rnd12_p.s | 0 .../{sim => }/bfin/c_dsp32alu_rh_rnd20_m.s | 0 .../{sim => }/bfin/c_dsp32alu_rh_rnd20_p.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_p.s | 0 .../{sim => }/bfin/c_dsp32alu_rl_rnd12_m.s | 0 .../{sim => }/bfin/c_dsp32alu_rl_rnd12_p.s | 0 .../{sim => }/bfin/c_dsp32alu_rl_rnd20_m.s | 0 .../{sim => }/bfin/c_dsp32alu_rl_rnd20_p.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rlh_rnd.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rm.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rmm.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rmp.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rp.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rpm.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rpp.s | 0 .../{sim => }/bfin/c_dsp32alu_rr_lph_a1a0.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm_aa.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp.s | 0 .../{sim => }/bfin/c_dsp32alu_rrpmmp_sft.s | 0 .../{sim => }/bfin/c_dsp32alu_rrpmmp_sft_x.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm.s | 0 .../{sim => }/bfin/c_dsp32alu_rrppmm_sft.s | 0 .../{sim => }/bfin/c_dsp32alu_rrppmm_sft_x.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_saa.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_sat_aa.S | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_search.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_sgn.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0.s | 0 .../{sim => }/bfin/c_dsp32mac_a1a0_iuw32.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_i.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_ih.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_is.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_iu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_t.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_tu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_i.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_ih.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_is.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_iu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_t.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_tu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0.s | 0 .../{sim => }/bfin/c_dsp32mac_dr_a1a0_iutsh.s | 0 .../{sim => }/bfin/c_dsp32mac_dr_a1a0_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_mix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a0_i.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a0_is.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a0_m.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a0_s.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a0_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1_i.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1_is.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1_m.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1_s.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1_u.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0_i.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0_is.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0_m.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0_s.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_mix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_i.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_ih.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_is.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_iu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_i.s | 0 .../{sim => }/bfin/c_dsp32mult_dr_m_iutsh.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_t.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_mix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_t.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_tu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_i.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_is.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m.s | 0 .../{sim => }/bfin/c_dsp32mult_pair_m_i.s | 0 .../{sim => }/bfin/c_dsp32mult_pair_m_is.s | 0 .../{sim => }/bfin/c_dsp32mult_pair_m_s.s | 0 .../{sim => }/bfin/c_dsp32mult_pair_m_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_a0alr.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_af.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_af_s.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_ln.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_ln_s.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_lp.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_lp_s.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_rn.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_rn_s.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_rp.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_rp_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh_s.s | 0 .../{sim => }/bfin/c_dsp32shift_align16.s | 0 .../{sim => }/bfin/c_dsp32shift_align24.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_align8.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_amix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_bitmux.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_bxor.s | 0 .../{sim => }/bfin/c_dsp32shift_expadj_h.s | 0 .../{sim => }/bfin/c_dsp32shift_expadj_l.s | 0 .../{sim => }/bfin/c_dsp32shift_expadj_r.s | 0 .../{sim => }/bfin/c_dsp32shift_expexp_r.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_fdepx.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_fextx.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_lf.s | 0 .../{sim => }/bfin/c_dsp32shift_lhalf_ln.s | 0 .../{sim => }/bfin/c_dsp32shift_lhalf_lp.s | 0 .../{sim => }/bfin/c_dsp32shift_lhalf_rn.s | 0 .../{sim => }/bfin/c_dsp32shift_lhalf_rp.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_lhh.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_lmix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_ones.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_pack.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_rot.s | 0 .../{sim => }/bfin/c_dsp32shift_rot_mix.s | 0 .../{sim => }/bfin/c_dsp32shift_signbits_r.s | 0 .../{sim => }/bfin/c_dsp32shift_signbits_rh.s | 0 .../{sim => }/bfin/c_dsp32shift_signbits_rl.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_vmax.s | 0 .../{sim => }/bfin/c_dsp32shift_vmaxvmax.s | 0 .../{sim => }/bfin/c_dsp32shiftim_a0alr.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af_s.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_ln.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_ln_s.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_lp.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_lp_s.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_rn.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_rn_s.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_rp.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_rp_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahh_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_amix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lf.s | 0 .../{sim => }/bfin/c_dsp32shiftim_lhalf_ln.s | 0 .../{sim => }/bfin/c_dsp32shiftim_lhalf_lp.s | 0 .../{sim => }/bfin/c_dsp32shiftim_lhalf_rn.s | 0 .../{sim => }/bfin/c_dsp32shiftim_lhalf_rp.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhh.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lmix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_rot.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_i.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ipp.s | 0 .../{sim => }/bfin/c_dspldst_ld_dr_ippm.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_i.s | 0 .../{sim => }/bfin/c_dspldst_ld_drhi_ipp.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_i.s | 0 .../{sim => }/bfin/c_dspldst_ld_drlo_ipp.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_i.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ipp.s | 0 .../{sim => }/bfin/c_dspldst_st_dr_ippm.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_i.s | 0 .../{sim => }/bfin/c_dspldst_st_drhi_ipp.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_i.s | 0 .../{sim => }/bfin/c_dspldst_st_drlo_ipp.s | 0 sim/testsuite/{sim => }/bfin/c_except_illopcode.S | 0 sim/testsuite/{sim => }/bfin/c_except_sys_sstep.S | 0 sim/testsuite/{sim => }/bfin/c_except_user_mode.S | 0 sim/testsuite/{sim => }/bfin/c_interr_disable.S | 0 .../{sim => }/bfin/c_interr_disable_enable.S | 0 sim/testsuite/{sim => }/bfin/c_interr_excpt.S | 0 .../{sim => }/bfin/c_interr_loopsetup_stld.S | 0 sim/testsuite/{sim => }/bfin/c_interr_nested.S | 0 sim/testsuite/{sim => }/bfin/c_interr_nmi.S | 0 sim/testsuite/{sim => }/bfin/c_interr_pending.S | 0 sim/testsuite/{sim => }/bfin/c_interr_pending_2.S | 0 sim/testsuite/{sim => }/bfin/c_interr_timer.S | 0 .../{sim => }/bfin/c_interr_timer_reload.S | 0 .../{sim => }/bfin/c_interr_timer_tcount.S | 0 .../{sim => }/bfin/c_interr_timer_tscale.S | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_drhi.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_drlo.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_ibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_ibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_ibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_dr.s | 0 .../{sim => }/bfin/c_ldimmhalf_lzhi_ibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_pibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xb.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xb.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xh.s | 0 .../{sim => }/bfin/c_ldst_ld_d_p_ppmm_hbx.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xb.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_mm.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_pp.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_p.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_mm.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_pp.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xb.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_st_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_ld_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_ld_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_st_dr_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_st_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_st_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstiifp_st_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstiifp_st_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_hi.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_lo.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_h_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_lohi.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_hi.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_lo.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_st_lohi.s | 0 sim/testsuite/{sim => }/bfin/c_linkage.s | 0 .../{sim => }/bfin/c_logi2op_alshft_mix.s | 0 .../{sim => }/bfin/c_logi2op_arith_shft.s | 0 sim/testsuite/{sim => }/bfin/c_logi2op_bitclr.s | 0 sim/testsuite/{sim => }/bfin/c_logi2op_bitset.s | 0 sim/testsuite/{sim => }/bfin/c_logi2op_bittgl.s | 0 sim/testsuite/{sim => }/bfin/c_logi2op_bittst.s | 0 .../{sim => }/bfin/c_logi2op_log_l_shft.s | 0 .../{sim => }/bfin/c_logi2op_log_l_shft_astat.S | 0 .../{sim => }/bfin/c_logi2op_log_r_shft.s | 0 .../{sim => }/bfin/c_logi2op_log_r_shft_astat.S | 0 sim/testsuite/{sim => }/bfin/c_logi2op_nbittst.s | 0 sim/testsuite/{sim => }/bfin/c_loopsetup_nested.s | 0 .../{sim => }/bfin/c_loopsetup_nested_bot.s | 0 .../{sim => }/bfin/c_loopsetup_nested_prelc.s | 0 .../{sim => }/bfin/c_loopsetup_nested_top.s | 0 sim/testsuite/{sim => }/bfin/c_loopsetup_overlap.s | 0 .../{sim => }/bfin/c_loopsetup_preg_div2_lc0.s | 0 .../{sim => }/bfin/c_loopsetup_preg_div2_lc1.s | 0 .../{sim => }/bfin/c_loopsetup_preg_lc0.s | 0 .../{sim => }/bfin/c_loopsetup_preg_lc1.s | 0 .../{sim => }/bfin/c_loopsetup_preg_stld.s | 0 sim/testsuite/{sim => }/bfin/c_loopsetup_prelc.s | 0 .../{sim => }/bfin/c_loopsetup_topbotcntr.s | 0 sim/testsuite/{sim => }/bfin/c_mmr_interr_ctl.s | 0 sim/testsuite/{sim => }/bfin/c_mmr_loop.S | 0 .../{sim => }/bfin/c_mmr_loop_user_except.S | 0 .../{sim => }/bfin/c_mmr_ppop_illegal_adr.S | 0 .../{sim => }/bfin/c_mmr_ppopm_illegal_adr.S | 0 sim/testsuite/{sim => }/bfin/c_mmr_timer.S | 0 sim/testsuite/{sim => }/bfin/c_mode_supervisor.S | 0 sim/testsuite/{sim => }/bfin/c_mode_user.S | 0 .../{sim => }/bfin/c_mode_user_superivsor.S | 0 .../{sim => }/bfin/c_multi_issue_dsp_ld_ld.s | 0 .../{sim => }/bfin/c_multi_issue_dsp_ldst_1.s | 0 .../{sim => }/bfin/c_multi_issue_dsp_ldst_2.s | 0 .../{sim => }/bfin/c_progctrl_call_pcpr.s | 0 sim/testsuite/{sim => }/bfin/c_progctrl_call_pr.s | 0 .../{sim => }/bfin/c_progctrl_clisti_interr.S | 0 .../{sim => }/bfin/c_progctrl_csync_mmr.S | 0 .../{sim => }/bfin/c_progctrl_except_rtx.S | 0 sim/testsuite/{sim => }/bfin/c_progctrl_excpt.S | 0 .../{sim => }/bfin/c_progctrl_jump_pcpr.s | 0 sim/testsuite/{sim => }/bfin/c_progctrl_jump_pr.s | 0 sim/testsuite/{sim => }/bfin/c_progctrl_nop.s | 0 .../{sim => }/bfin/c_progctrl_raise_rt_i_n.S | 0 sim/testsuite/{sim => }/bfin/c_progctrl_rts.s | 0 sim/testsuite/{sim => }/bfin/c_ptr2op_pr_neg_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ptr2op_pr_sft_2_1.s | 0 .../{sim => }/bfin/c_ptr2op_pr_shadd_1_2.s | 0 .../{sim => }/bfin/c_pushpopmultiple_dp.s | 0 .../{sim => }/bfin/c_pushpopmultiple_dp_pair.s | 0 .../{sim => }/bfin/c_pushpopmultiple_dreg.s | 0 .../{sim => }/bfin/c_pushpopmultiple_preg.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_acc_acc.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_dag_lz_dep.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_dr_acc_acc.s | 0 .../{sim => }/bfin/c_regmv_dr_dep_nostall.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_dr_dr.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_dr_imlb.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_dr_pr.s | 0 .../{sim => }/bfin/c_regmv_imlb_dep_nostall.s | 0 .../{sim => }/bfin/c_regmv_imlb_dep_stall.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_imlb_dr.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_imlb_imlb.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_imlb_pr.s | 0 .../{sim => }/bfin/c_regmv_pr_dep_nostall.s | 0 .../{sim => }/bfin/c_regmv_pr_dep_stall.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_pr_dr.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_pr_imlb.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_pr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_seq_ac_raise_mv.S | 0 .../{sim => }/bfin/c_seq_ac_raise_mv_ppop.S | 0 .../{sim => }/bfin/c_seq_ac_regmv_pushpop.S | 0 .../{sim => }/bfin/c_seq_dec_raise_pushpop.S | 0 .../{sim => }/bfin/c_seq_ex1_brcc_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex1_call_mv_pop.S | 0 sim/testsuite/{sim => }/bfin/c_seq_ex1_j_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex1_raise_brcc_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex1_raise_call_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex1_raise_j_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex2_brcc_mp_mv_pop.S | 0 sim/testsuite/{sim => }/bfin/c_seq_ex2_mmr_mvpop.S | 0 .../{sim => }/bfin/c_seq_ex2_mmrj_mvpop.S | 0 .../{sim => }/bfin/c_seq_ex2_raise_mmr_mvpop.S | 0 .../{sim => }/bfin/c_seq_ex2_raise_mmrj_mvpop.S | 0 .../{sim => }/bfin/c_seq_ex3_ls_brcc_mvp.S | 0 .../{sim => }/bfin/c_seq_ex3_ls_mmr_mvp.S | 0 .../{sim => }/bfin/c_seq_ex3_ls_mmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_cs_lsmmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_rti_lsmmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_rtn_lsmmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_rtx_lsmmrj_mvp.S | 0 sim/testsuite/{sim => }/bfin/c_ujump.s | 0 sim/testsuite/{sim => }/bfin/cc-alu.S | 0 sim/testsuite/{sim => }/bfin/cc-astat-bits.s | 0 sim/testsuite/{sim => }/bfin/cc0.s | 0 sim/testsuite/{sim => }/bfin/cc1.s | 0 sim/testsuite/{sim => }/bfin/cc5.S | 0 sim/testsuite/{sim => }/bfin/cec-exact-exception.S | 0 sim/testsuite/{sim => }/bfin/cec-ifetch.S | 0 sim/testsuite/{sim => }/bfin/cec-multi-pending.S | 0 sim/testsuite/{sim => }/bfin/cec-no-snen-reti.S | 0 .../{sim => }/bfin/cec-non-operating-env.s | 0 sim/testsuite/{sim => }/bfin/cec-raise-reti.S | 0 sim/testsuite/{sim => }/bfin/cec-snen-reti.S | 0 sim/testsuite/{sim => }/bfin/cec-syscfg-ssstep.S | 0 sim/testsuite/{sim => }/bfin/cec-system-call.S | 0 sim/testsuite/{sim => }/bfin/cir.s | 0 sim/testsuite/{sim => }/bfin/cir1.s | 0 sim/testsuite/{sim => }/bfin/cli-sti.s | 0 sim/testsuite/{sim => }/bfin/cmpacc.s | 0 sim/testsuite/{sim => }/bfin/cmpdreg.S | 0 sim/testsuite/{sim => }/bfin/compare.s | 0 sim/testsuite/{sim => }/bfin/conv_enc_gen.s | 0 sim/testsuite/{sim => }/bfin/cycles.s | 0 sim/testsuite/{sim => }/bfin/d0.s | 0 sim/testsuite/{sim => }/bfin/d1.s | 0 sim/testsuite/{sim => }/bfin/d2.s | 0 .../{sim => }/bfin/dbg_brprd_ntkn_src_kill.S | 0 .../{sim => }/bfin/dbg_brtkn_nprd_src_kill.S | 0 sim/testsuite/{sim => }/bfin/dbg_jmp_src_kill.S | 0 sim/testsuite/{sim => }/bfin/dbg_tr_basic.S | 0 sim/testsuite/{sim => }/bfin/dbg_tr_simplejp.S | 0 sim/testsuite/{sim => }/bfin/dbg_tr_tbuf0.S | 0 sim/testsuite/{sim => }/bfin/dbg_tr_umode.S | 0 .../{sim => }/bfin/disalnexcpt_implicit.S | 0 sim/testsuite/{sim => }/bfin/div0.s | 0 sim/testsuite/{sim => }/bfin/divq.s | 0 sim/testsuite/{sim => }/bfin/dotproduct.s | 0 sim/testsuite/{sim => }/bfin/dotproduct2.s | 0 sim/testsuite/{sim => }/bfin/double_prec_mult.s | 0 sim/testsuite/{sim => }/bfin/dsp_a4.s | 0 sim/testsuite/{sim => }/bfin/dsp_a7.s | 0 sim/testsuite/{sim => }/bfin/dsp_a8.s | 0 sim/testsuite/{sim => }/bfin/dsp_d0.s | 0 sim/testsuite/{sim => }/bfin/dsp_d1.s | 0 sim/testsuite/{sim => }/bfin/dsp_neg.S | 0 sim/testsuite/{sim => }/bfin/dsp_s1.s | 0 sim/testsuite/{sim => }/bfin/e0.s | 0 sim/testsuite/{sim => }/bfin/edn_snafu.s | 0 sim/testsuite/{sim => }/bfin/eu_dsp32mac_s.s | 0 sim/testsuite/{sim => }/bfin/events.s | 0 sim/testsuite/{sim => }/bfin/f221.s | 0 sim/testsuite/{sim => }/bfin/fact.s | 0 sim/testsuite/{sim => }/bfin/fir.s | 0 sim/testsuite/{sim => }/bfin/fsm.s | 0 sim/testsuite/{sim => }/bfin/greg2.s | 0 sim/testsuite/{sim => }/bfin/hwloop-bits.S | 0 sim/testsuite/{sim => }/bfin/hwloop-branch-in.s | 0 sim/testsuite/{sim => }/bfin/hwloop-branch-out.s | 0 sim/testsuite/{sim => }/bfin/hwloop-lt-bits.s | 0 sim/testsuite/{sim => }/bfin/hwloop-nested.s | 0 sim/testsuite/{sim => }/bfin/i0.s | 0 sim/testsuite/{sim => }/bfin/iir.s | 0 sim/testsuite/{sim => }/bfin/issue103.s | 0 sim/testsuite/{sim => }/bfin/issue109.s | 0 sim/testsuite/{sim => }/bfin/issue112.s | 0 sim/testsuite/{sim => }/bfin/issue113.s | 0 sim/testsuite/{sim => }/bfin/issue117.s | 0 sim/testsuite/{sim => }/bfin/issue118.s | 0 sim/testsuite/{sim => }/bfin/issue119.s | 0 sim/testsuite/{sim => }/bfin/issue121.s | 0 sim/testsuite/{sim => }/bfin/issue123.s | 0 sim/testsuite/{sim => }/bfin/issue124.s | 0 sim/testsuite/{sim => }/bfin/issue125.s | 0 sim/testsuite/{sim => }/bfin/issue126.s | 0 sim/testsuite/{sim => }/bfin/issue127.s | 0 sim/testsuite/{sim => }/bfin/issue129.s | 0 sim/testsuite/{sim => }/bfin/issue139.S | 0 sim/testsuite/{sim => }/bfin/issue140.S | 0 sim/testsuite/{sim => }/bfin/issue142.s | 0 sim/testsuite/{sim => }/bfin/issue144.s | 0 sim/testsuite/{sim => }/bfin/issue146.S | 0 sim/testsuite/{sim => }/bfin/issue175.s | 0 sim/testsuite/{sim => }/bfin/issue205.s | 0 sim/testsuite/{sim => }/bfin/issue257.s | 0 sim/testsuite/{sim => }/bfin/issue272.S | 0 sim/testsuite/{sim => }/bfin/issue83.s | 0 sim/testsuite/{sim => }/bfin/issue89.s | 0 sim/testsuite/{sim => }/bfin/l0.s | 0 sim/testsuite/{sim => }/bfin/l0shift.s | 0 sim/testsuite/{sim => }/bfin/l2_loop.s | 0 sim/testsuite/{sim => }/bfin/link-2.s | 0 sim/testsuite/{sim => }/bfin/link.s | 0 sim/testsuite/{sim => }/bfin/lmu_cplb_multiple0.S | 0 sim/testsuite/{sim => }/bfin/lmu_cplb_multiple1.S | 0 sim/testsuite/{sim => }/bfin/lmu_excpt_align.S | 0 sim/testsuite/{sim => }/bfin/lmu_excpt_default.S | 0 sim/testsuite/{sim => }/bfin/lmu_excpt_illaddr.S | 0 sim/testsuite/{sim => }/bfin/lmu_excpt_prot0.S | 0 sim/testsuite/{sim => }/bfin/lmu_excpt_prot1.S | 0 sim/testsuite/{sim => }/bfin/load.s | 0 sim/testsuite/{sim => }/bfin/logic.s | 0 sim/testsuite/{sim => }/bfin/loop_snafu.s | 0 sim/testsuite/{sim => }/bfin/loop_strncpy.s | 0 sim/testsuite/{sim => }/bfin/lp0.s | 0 sim/testsuite/{sim => }/bfin/lp1.s | 0 sim/testsuite/{sim => }/bfin/lsetup.s | 0 sim/testsuite/{sim => }/bfin/m0boundary.s | 0 sim/testsuite/{sim => }/bfin/m1.S | 0 sim/testsuite/{sim => }/bfin/m10.s | 0 sim/testsuite/{sim => }/bfin/m11.s | 0 sim/testsuite/{sim => }/bfin/m12.s | 0 sim/testsuite/{sim => }/bfin/m13.s | 0 sim/testsuite/{sim => }/bfin/m14.s | 0 sim/testsuite/{sim => }/bfin/m15.s | 0 sim/testsuite/{sim => }/bfin/m16.s | 0 sim/testsuite/{sim => }/bfin/m17.s | 0 sim/testsuite/{sim => }/bfin/m2.s | 0 sim/testsuite/{sim => }/bfin/m3.s | 0 sim/testsuite/{sim => }/bfin/m4.s | 0 sim/testsuite/{sim => }/bfin/m5.s | 0 sim/testsuite/{sim => }/bfin/m6.s | 0 sim/testsuite/{sim => }/bfin/m7.s | 0 sim/testsuite/{sim => }/bfin/m8.s | 0 sim/testsuite/{sim => }/bfin/m9.s | 0 sim/testsuite/{sim => }/bfin/mac2halfreg.S | 0 sim/testsuite/{sim => }/bfin/math.s | 0 sim/testsuite/{sim => }/bfin/max_min_flags.s | 0 sim/testsuite/{sim => }/bfin/mc_s2.s | 0 .../{sim => }/bfin/mdma-32bit-1d-neg-count.c | 0 sim/testsuite/{sim => }/bfin/mdma-32bit-1d.c | 0 .../{sim => }/bfin/mdma-8bit-1d-neg-count.c | 0 sim/testsuite/{sim => }/bfin/mdma-8bit-1d.c | 0 sim/testsuite/{sim => }/bfin/mdma-skel.h | 0 sim/testsuite/{sim => }/bfin/mem3.s | 0 sim/testsuite/{sim => }/bfin/mmr-exception.s | 0 sim/testsuite/{sim => }/bfin/move.s | 0 sim/testsuite/{sim => }/bfin/msa_acp_5.10.S | 0 sim/testsuite/{sim => }/bfin/msa_acp_5.12_1.S | 0 sim/testsuite/{sim => }/bfin/msa_acp_5.12_2.S | 0 sim/testsuite/{sim => }/bfin/msa_acp_5_10.s | 0 sim/testsuite/{sim => }/bfin/mult.s | 0 sim/testsuite/{sim => }/bfin/neg-2.S | 0 sim/testsuite/{sim => }/bfin/neg-3.S | 0 sim/testsuite/{sim => }/bfin/neg.S | 0 sim/testsuite/{sim => }/bfin/nshift.s | 0 sim/testsuite/{sim => }/bfin/pr.s | 0 sim/testsuite/{sim => }/bfin/push-pop-multiple.s | 0 sim/testsuite/{sim => }/bfin/push-pop.s | 0 sim/testsuite/{sim => }/bfin/pushpopreg_1.s | 0 sim/testsuite/{sim => }/bfin/quadaddsub.s | 0 sim/testsuite/{sim => }/bfin/random_0001.s | 0 sim/testsuite/{sim => }/bfin/random_0002.S | 0 sim/testsuite/{sim => }/bfin/random_0003.S | 0 sim/testsuite/{sim => }/bfin/random_0004.S | 0 sim/testsuite/{sim => }/bfin/random_0005.S | 0 sim/testsuite/{sim => }/bfin/random_0006.S | 0 sim/testsuite/{sim => }/bfin/random_0007.S | 0 sim/testsuite/{sim => }/bfin/random_0008.S | 0 sim/testsuite/{sim => }/bfin/random_0009.S | 0 sim/testsuite/{sim => }/bfin/random_0010.S | 0 sim/testsuite/{sim => }/bfin/random_0011.S | 0 sim/testsuite/{sim => }/bfin/random_0012.S | 0 sim/testsuite/{sim => }/bfin/random_0013.S | 0 sim/testsuite/{sim => }/bfin/random_0014.S | 0 sim/testsuite/{sim => }/bfin/random_0015.S | 0 sim/testsuite/{sim => }/bfin/random_0016.S | 0 sim/testsuite/{sim => }/bfin/random_0017.S | 0 sim/testsuite/{sim => }/bfin/random_0018.S | 0 sim/testsuite/{sim => }/bfin/random_0019.S | 0 sim/testsuite/{sim => }/bfin/random_0020.S | 0 sim/testsuite/{sim => }/bfin/random_0021.S | 0 sim/testsuite/{sim => }/bfin/random_0022.S | 0 sim/testsuite/{sim => }/bfin/random_0023.S | 0 sim/testsuite/{sim => }/bfin/random_0024.S | 0 sim/testsuite/{sim => }/bfin/random_0025.S | 0 sim/testsuite/{sim => }/bfin/random_0026.S | 0 sim/testsuite/{sim => }/bfin/random_0027.S | 0 sim/testsuite/{sim => }/bfin/random_0028.S | 0 sim/testsuite/{sim => }/bfin/random_0029.S | 0 sim/testsuite/{sim => }/bfin/random_0030.S | 0 sim/testsuite/{sim => }/bfin/random_0031.S | 0 sim/testsuite/{sim => }/bfin/random_0032.S | 0 sim/testsuite/{sim => }/bfin/random_0033.S | 0 sim/testsuite/{sim => }/bfin/random_0034.S | 0 sim/testsuite/{sim => }/bfin/random_0035.S | 0 sim/testsuite/{sim => }/bfin/random_0036.S | 0 sim/testsuite/{sim => }/bfin/random_0037.S | 0 sim/testsuite/{sim => }/bfin/run-tests.sh | 0 sim/testsuite/{sim => }/bfin/s0.s | 0 sim/testsuite/{sim => }/bfin/s1.s | 0 sim/testsuite/{sim => }/bfin/s10.s | 0 sim/testsuite/{sim => }/bfin/s11.s | 0 sim/testsuite/{sim => }/bfin/s12.s | 0 sim/testsuite/{sim => }/bfin/s13.s | 0 sim/testsuite/{sim => }/bfin/s14.s | 0 sim/testsuite/{sim => }/bfin/s15.s | 0 sim/testsuite/{sim => }/bfin/s16.s | 0 sim/testsuite/{sim => }/bfin/s17.s | 0 sim/testsuite/{sim => }/bfin/s18.s | 0 sim/testsuite/{sim => }/bfin/s19.s | 0 sim/testsuite/{sim => }/bfin/s2.s | 0 sim/testsuite/{sim => }/bfin/s20.s | 0 sim/testsuite/{sim => }/bfin/s21.s | 0 sim/testsuite/{sim => }/bfin/s3.s | 0 sim/testsuite/{sim => }/bfin/s30.s | 0 sim/testsuite/{sim => }/bfin/s4.s | 0 sim/testsuite/{sim => }/bfin/s5.s | 0 sim/testsuite/{sim => }/bfin/s6.s | 0 sim/testsuite/{sim => }/bfin/s7.s | 0 sim/testsuite/{sim => }/bfin/s8.s | 0 sim/testsuite/{sim => }/bfin/s9.s | 0 sim/testsuite/{sim => }/bfin/saatest.s | 0 sim/testsuite/{sim => }/bfin/se_all16bitopcodes.S | 0 sim/testsuite/{sim => }/bfin/se_all32bitopcodes.S | 0 .../{sim => }/bfin/se_all32bitopcodes.lds | 0 .../{sim => }/bfin/se_all64bitg0opcodes.S | 0 .../{sim => }/bfin/se_all64bitg1opcodes.S | 0 .../{sim => }/bfin/se_all64bitg2opcodes.S | 0 sim/testsuite/{sim => }/bfin/se_allopcodes.h | 0 sim/testsuite/{sim => }/bfin/se_brtarget_stall.S | 0 sim/testsuite/{sim => }/bfin/se_bug_ui.S | 0 sim/testsuite/{sim => }/bfin/se_bug_ui2.S | 0 sim/testsuite/{sim => }/bfin/se_bug_ui3.S | 0 sim/testsuite/{sim => }/bfin/se_cc2stat_haz.S | 0 sim/testsuite/{sim => }/bfin/se_cc_kill.S | 0 sim/testsuite/{sim => }/bfin/se_cof.S | 0 sim/testsuite/{sim => }/bfin/se_event_quad.S | 0 .../{sim => }/bfin/se_excpt_dagprotviol.S | 0 sim/testsuite/{sim => }/bfin/se_excpt_ifprotviol.S | 0 sim/testsuite/{sim => }/bfin/se_excpt_ssstep.S | 0 .../{sim => }/bfin/se_illegalcombination.S | 0 sim/testsuite/{sim => }/bfin/se_kill_wbbr.S | 0 sim/testsuite/{sim => }/bfin/se_kills2.S | 0 sim/testsuite/{sim => }/bfin/se_loop_disable.S | 0 sim/testsuite/{sim => }/bfin/se_loop_kill.S | 0 sim/testsuite/{sim => }/bfin/se_loop_kill_01.S | 0 sim/testsuite/{sim => }/bfin/se_loop_kill_dcr.S | 0 sim/testsuite/{sim => }/bfin/se_loop_kill_dcr_01.S | 0 sim/testsuite/{sim => }/bfin/se_loop_lr.S | 0 sim/testsuite/{sim => }/bfin/se_loop_mv2lb_stall.S | 0 sim/testsuite/{sim => }/bfin/se_loop_mv2lc.S | 0 sim/testsuite/{sim => }/bfin/se_loop_mv2lc_stall.S | 0 sim/testsuite/{sim => }/bfin/se_loop_mv2lt_stall.S | 0 sim/testsuite/{sim => }/bfin/se_loop_nest_ppm.S | 0 sim/testsuite/{sim => }/bfin/se_loop_nest_ppm_1.S | 0 sim/testsuite/{sim => }/bfin/se_loop_nest_ppm_2.S | 0 sim/testsuite/{sim => }/bfin/se_loop_ppm.S | 0 sim/testsuite/{sim => }/bfin/se_loop_ppm_1.S | 0 sim/testsuite/{sim => }/bfin/se_loop_ppm_int.S | 0 sim/testsuite/{sim => }/bfin/se_lsetup_kill.S | 0 sim/testsuite/{sim => }/bfin/se_misaligned_fetch.S | 0 sim/testsuite/{sim => }/bfin/se_more_ret_haz.S | 0 sim/testsuite/{sim => }/bfin/se_mv2lp.S | 0 sim/testsuite/{sim => }/bfin/se_oneins_zoff.S | 0 sim/testsuite/{sim => }/bfin/se_popkill.S | 0 sim/testsuite/{sim => }/bfin/se_regmv_usp_sysreg.S | 0 sim/testsuite/{sim => }/bfin/se_rets_hazard.s | 0 sim/testsuite/{sim => }/bfin/se_rts_rti.S | 0 .../{sim => }/bfin/se_ssstep_dagprotviol.S | 0 sim/testsuite/{sim => }/bfin/se_ssync.S | 0 sim/testsuite/{sim => }/bfin/se_stall_if2.S | 0 .../{sim => }/bfin/se_undefinedinstruction1.S | 0 .../{sim => }/bfin/se_undefinedinstruction2.S | 0 .../{sim => }/bfin/se_undefinedinstruction3.S | 0 .../{sim => }/bfin/se_undefinedinstruction4.S | 0 .../{sim => }/bfin/se_usermode_protviol.S | 0 sim/testsuite/{sim => }/bfin/seqstat.s | 0 sim/testsuite/{sim => }/bfin/sign.s | 0 sim/testsuite/{sim => }/bfin/simple0.s | 0 sim/testsuite/{sim => }/bfin/sri.s | 0 sim/testsuite/{sim => }/bfin/stk.s | 0 sim/testsuite/{sim => }/bfin/stk2.s | 0 sim/testsuite/{sim => }/bfin/stk3.s | 0 sim/testsuite/{sim => }/bfin/stk4.s | 0 sim/testsuite/{sim => }/bfin/stk5.s | 0 sim/testsuite/{sim => }/bfin/stk6.s | 0 sim/testsuite/{sim => }/bfin/syscfg.s | 0 sim/testsuite/{sim => }/bfin/tar10622.s | 0 sim/testsuite/{sim => }/bfin/test-dma.h | 0 sim/testsuite/{sim => }/bfin/test.h | 0 sim/testsuite/{sim => }/bfin/testset.s | 0 sim/testsuite/{sim => }/bfin/testset2.s | 0 sim/testsuite/{sim => }/bfin/testutils.inc | 0 sim/testsuite/{sim => }/bfin/unlink.S | 0 sim/testsuite/{sim => }/bfin/up0.s | 0 sim/testsuite/{sim => }/bfin/usp.S | 0 sim/testsuite/{sim => }/bfin/vec-abs-2.S | 0 sim/testsuite/{sim => }/bfin/vec-abs-3.S | 0 sim/testsuite/{sim => }/bfin/vec-abs.S | 0 sim/testsuite/{sim => }/bfin/vec-neg-2.S | 0 sim/testsuite/{sim => }/bfin/vec-neg-3.S | 0 sim/testsuite/{sim => }/bfin/vec-neg.S | 0 sim/testsuite/{sim => }/bfin/vecadd.s | 0 sim/testsuite/{sim => }/bfin/vit_max.s | 0 sim/testsuite/{sim => }/bfin/vit_max2.s | 0 sim/testsuite/{sim => }/bfin/viterbi2.s | 0 sim/testsuite/{sim => }/bfin/wtf.s | 0 sim/testsuite/{sim => }/bfin/x1.s | 0 sim/testsuite/{sim => }/bfin/zcall.s | 0 sim/testsuite/{sim => }/bfin/zeroflagrnd.s | 0 sim/testsuite/{sim => }/bpf/ChangeLog | 0 sim/testsuite/{sim => }/bpf/allinsn.exp | 0 sim/testsuite/{sim => }/bpf/alu.s | 0 sim/testsuite/{sim => }/bpf/alu32.s | 0 sim/testsuite/{sim => }/bpf/endbe.s | 0 sim/testsuite/{sim => }/bpf/endle.s | 0 sim/testsuite/{sim => }/bpf/jmp.s | 0 sim/testsuite/{sim => }/bpf/jmp32.s | 0 sim/testsuite/{sim => }/bpf/ldabs.s | 0 sim/testsuite/{sim => }/bpf/mem.s | 0 sim/testsuite/{sim => }/bpf/mov.s | 0 sim/testsuite/{sim => }/bpf/testutils.inc | 0 sim/testsuite/{sim => }/bpf/xadd.s | 0 sim/testsuite/{sim => }/cr16/ChangeLog | 0 sim/testsuite/{sim => }/cr16/addb.cgs | 0 sim/testsuite/{sim => }/cr16/addd.cgs | 0 sim/testsuite/{sim => }/cr16/addi.cgs | 0 sim/testsuite/{sim => }/cr16/addw.cgs | 0 sim/testsuite/{sim => }/cr16/allinsn.exp | 0 sim/testsuite/{sim => }/cr16/andb.cgs | 0 sim/testsuite/{sim => }/cr16/andd.cgs | 0 sim/testsuite/{sim => }/cr16/andw.cgs | 0 sim/testsuite/{sim => }/cr16/ashub.cgs | 0 sim/testsuite/{sim => }/cr16/ashub_i.cgs | 0 sim/testsuite/{sim => }/cr16/ashud.cgs | 0 sim/testsuite/{sim => }/cr16/ashud_i.cgs | 0 sim/testsuite/{sim => }/cr16/ashuw.cgs | 0 sim/testsuite/{sim => }/cr16/ashuw_i.cgs | 0 sim/testsuite/{sim => }/cr16/bal1_24.cgs | 0 sim/testsuite/{sim => }/cr16/bal2_24.cgs | 0 sim/testsuite/{sim => }/cr16/bcc.cgs | 0 sim/testsuite/{sim => }/cr16/bcs.cgs | 0 sim/testsuite/{sim => }/cr16/beq.cgs | 0 sim/testsuite/{sim => }/cr16/beq0b.cgs | 0 sim/testsuite/{sim => }/cr16/beq0w.cgs | 0 sim/testsuite/{sim => }/cr16/bge.cgs | 0 sim/testsuite/{sim => }/cr16/bgt.cgs | 0 sim/testsuite/{sim => }/cr16/bhi.cgs | 0 sim/testsuite/{sim => }/cr16/bhs.cgs | 0 sim/testsuite/{sim => }/cr16/bht.cgs | 0 sim/testsuite/{sim => }/cr16/blo.cgs | 0 sim/testsuite/{sim => }/cr16/bls.cgs | 0 sim/testsuite/{sim => }/cr16/blt.cgs | 0 sim/testsuite/{sim => }/cr16/bne.cgs | 0 sim/testsuite/{sim => }/cr16/bne0b.cgs | 0 sim/testsuite/{sim => }/cr16/bne0w.cgs | 0 sim/testsuite/{sim => }/cr16/br.cgs | 0 sim/testsuite/{sim => }/cr16/cbitb.cgs | 0 sim/testsuite/{sim => }/cr16/cbitw.cgs | 0 sim/testsuite/{sim => }/cr16/cmpb.cgs | 0 sim/testsuite/{sim => }/cr16/cmpb_i.cgs | 0 sim/testsuite/{sim => }/cr16/cmpd.cgs | 0 sim/testsuite/{sim => }/cr16/cmpd_i.cgs | 0 sim/testsuite/{sim => }/cr16/cmpi.cgs | 0 sim/testsuite/{sim => }/cr16/cmpw.cgs | 0 sim/testsuite/{sim => }/cr16/cmpw_i.cgs | 0 sim/testsuite/{sim => }/cr16/excp.cgs | 0 sim/testsuite/{sim => }/cr16/hello.ms | 0 sim/testsuite/{sim => }/cr16/hw-trap.ms | 0 sim/testsuite/{sim => }/cr16/jal.cgs | 0 sim/testsuite/{sim => }/cr16/jcc.cgs | 0 sim/testsuite/{sim => }/cr16/jcs.cgs | 0 sim/testsuite/{sim => }/cr16/jeq.cgs | 0 sim/testsuite/{sim => }/cr16/jfc.cgs | 0 sim/testsuite/{sim => }/cr16/jfs.cgs | 0 sim/testsuite/{sim => }/cr16/jge.cgs | 0 sim/testsuite/{sim => }/cr16/jgt.cgs | 0 sim/testsuite/{sim => }/cr16/jhi.cgs | 0 sim/testsuite/{sim => }/cr16/jhs.cgs | 0 sim/testsuite/{sim => }/cr16/jlo.cgs | 0 sim/testsuite/{sim => }/cr16/jls.cgs | 0 sim/testsuite/{sim => }/cr16/jlt.cgs | 0 sim/testsuite/{sim => }/cr16/jne.cgs | 0 sim/testsuite/{sim => }/cr16/jump.cgs | 0 sim/testsuite/{sim => }/cr16/loadb.cgs | 0 sim/testsuite/{sim => }/cr16/loadd.cgs | 0 sim/testsuite/{sim => }/cr16/loadm.cgs | 0 sim/testsuite/{sim => }/cr16/loadmp.cgs | 0 sim/testsuite/{sim => }/cr16/loadw.cgs | 0 sim/testsuite/{sim => }/cr16/lpr-spr.cgs | 0 sim/testsuite/{sim => }/cr16/lprd-sprd.cgs | 0 sim/testsuite/{sim => }/cr16/lshb.cgs | 0 sim/testsuite/{sim => }/cr16/lshb_i.cgs | 0 sim/testsuite/{sim => }/cr16/lshd.cgs | 0 sim/testsuite/{sim => }/cr16/lshd_i.cgs | 0 sim/testsuite/{sim => }/cr16/lshw.cgs | 0 sim/testsuite/{sim => }/cr16/lshw_i.cgs | 0 sim/testsuite/{sim => }/cr16/macqw.cgs | 0 sim/testsuite/{sim => }/cr16/macsw.cgs | 0 sim/testsuite/{sim => }/cr16/macuw.cgs | 0 sim/testsuite/{sim => }/cr16/misc.exp | 0 sim/testsuite/{sim => }/cr16/movb.cgs | 0 sim/testsuite/{sim => }/cr16/movd.cgs | 0 sim/testsuite/{sim => }/cr16/movw.cgs | 0 sim/testsuite/{sim => }/cr16/movxb.cgs | 0 sim/testsuite/{sim => }/cr16/movxw.cgs | 0 sim/testsuite/{sim => }/cr16/movzb.cgs | 0 sim/testsuite/{sim => }/cr16/movzw.cgs | 0 sim/testsuite/{sim => }/cr16/mulb.cgs | 0 sim/testsuite/{sim => }/cr16/mulsb.cgs | 0 sim/testsuite/{sim => }/cr16/mulsw.cgs | 0 sim/testsuite/{sim => }/cr16/muluw.cgs | 0 sim/testsuite/{sim => }/cr16/mulw.cgs | 0 sim/testsuite/{sim => }/cr16/nop.cgs | 0 sim/testsuite/{sim => }/cr16/orb.cgs | 0 sim/testsuite/{sim => }/cr16/ord.cgs | 0 sim/testsuite/{sim => }/cr16/orw.cgs | 0 sim/testsuite/{sim => }/cr16/pop1.cgs | 0 sim/testsuite/{sim => }/cr16/pop2.cgs | 0 sim/testsuite/{sim => }/cr16/pop3.cgs | 0 sim/testsuite/{sim => }/cr16/popret1.cgs | 0 sim/testsuite/{sim => }/cr16/popret2.cgs | 0 sim/testsuite/{sim => }/cr16/popret3.cgs | 0 sim/testsuite/{sim => }/cr16/push1.cgs | 0 sim/testsuite/{sim => }/cr16/push2.cgs | 0 sim/testsuite/{sim => }/cr16/push3.cgs | 0 sim/testsuite/{sim => }/cr16/sbitb.cgs | 0 sim/testsuite/{sim => }/cr16/sbitw.cgs | 0 sim/testsuite/{sim => }/cr16/scc.cgs | 0 sim/testsuite/{sim => }/cr16/scs.cgs | 0 sim/testsuite/{sim => }/cr16/seq.cgs | 0 sim/testsuite/{sim => }/cr16/sfc.cgs | 0 sim/testsuite/{sim => }/cr16/sfs.cgs | 0 sim/testsuite/{sim => }/cr16/sge.cgs | 0 sim/testsuite/{sim => }/cr16/sgt.cgs | 0 sim/testsuite/{sim => }/cr16/shi.cgs | 0 sim/testsuite/{sim => }/cr16/shs.cgs | 0 sim/testsuite/{sim => }/cr16/slo.cgs | 0 sim/testsuite/{sim => }/cr16/sls.cgs | 0 sim/testsuite/{sim => }/cr16/slt.cgs | 0 sim/testsuite/{sim => }/cr16/sne.cgs | 0 sim/testsuite/{sim => }/cr16/storb.cgs | 0 sim/testsuite/{sim => }/cr16/stord.cgs | 0 sim/testsuite/{sim => }/cr16/storw.cgs | 0 sim/testsuite/{sim => }/cr16/subb.cgs | 0 sim/testsuite/{sim => }/cr16/subd.cgs | 0 sim/testsuite/{sim => }/cr16/subi.cgs | 0 sim/testsuite/{sim => }/cr16/subw.cgs | 0 sim/testsuite/{sim => }/cr16/tbit.cgs | 0 sim/testsuite/{sim => }/cr16/tbitb.cgs | 0 sim/testsuite/{sim => }/cr16/tbitw.cgs | 0 sim/testsuite/{sim => }/cr16/testutils.inc | 0 sim/testsuite/{sim => }/cr16/uread16.ms | 0 sim/testsuite/{sim => }/cr16/uread32.ms | 0 sim/testsuite/{sim => }/cr16/xorb.cgs | 0 sim/testsuite/{sim => }/cr16/xord.cgs | 0 sim/testsuite/{sim => }/cr16/xorw.cgs | 0 sim/testsuite/{sim => }/cris/ChangeLog | 0 sim/testsuite/{sim => }/cris/asm/abs.ms | 0 sim/testsuite/{sim => }/cris/asm/addc.ms | 0 sim/testsuite/{sim => }/cris/asm/addcpc.ms | 0 sim/testsuite/{sim => }/cris/asm/addcv32c.ms | 0 sim/testsuite/{sim => }/cris/asm/addcv32m.ms | 0 sim/testsuite/{sim => }/cris/asm/addcv32r.ms | 0 sim/testsuite/{sim => }/cris/asm/addi.ms | 0 sim/testsuite/{sim => }/cris/asm/addiv32.ms | 0 sim/testsuite/{sim => }/cris/asm/addm.ms | 0 sim/testsuite/{sim => }/cris/asm/addoc.ms | 0 sim/testsuite/{sim => }/cris/asm/addom.ms | 0 sim/testsuite/{sim => }/cris/asm/addoq.ms | 0 sim/testsuite/{sim => }/cris/asm/addq.ms | 0 sim/testsuite/{sim => }/cris/asm/addqpc.ms | 0 sim/testsuite/{sim => }/cris/asm/addr.ms | 0 sim/testsuite/{sim => }/cris/asm/addswpc.ms | 0 sim/testsuite/{sim => }/cris/asm/addxc.ms | 0 sim/testsuite/{sim => }/cris/asm/addxm.ms | 0 sim/testsuite/{sim => }/cris/asm/addxr.ms | 0 sim/testsuite/{sim => }/cris/asm/andc.ms | 0 sim/testsuite/{sim => }/cris/asm/andm.ms | 0 sim/testsuite/{sim => }/cris/asm/andq.ms | 0 sim/testsuite/{sim => }/cris/asm/andr.ms | 0 sim/testsuite/{sim => }/cris/asm/asm.exp | 0 sim/testsuite/{sim => }/cris/asm/asr.ms | 0 sim/testsuite/{sim => }/cris/asm/ba.ms | 0 sim/testsuite/{sim => }/cris/asm/badarch1.ms | 0 sim/testsuite/{sim => }/cris/asm/bare1.ms | 0 sim/testsuite/{sim => }/cris/asm/bare2.ms | 0 sim/testsuite/{sim => }/cris/asm/bare3.ms | 0 sim/testsuite/{sim => }/cris/asm/bas.ms | 0 sim/testsuite/{sim => }/cris/asm/bccb.ms | 0 sim/testsuite/{sim => }/cris/asm/bdapc.ms | 0 sim/testsuite/{sim => }/cris/asm/bdapm.ms | 0 sim/testsuite/{sim => }/cris/asm/bdapq.ms | 0 sim/testsuite/{sim => }/cris/asm/bdapqpc.ms | 0 sim/testsuite/{sim => }/cris/asm/biap.ms | 0 sim/testsuite/{sim => }/cris/asm/boundc.ms | 0 sim/testsuite/{sim => }/cris/asm/boundm.ms | 0 sim/testsuite/{sim => }/cris/asm/boundmv32.ms | 0 sim/testsuite/{sim => }/cris/asm/boundr.ms | 0 sim/testsuite/{sim => }/cris/asm/break.ms | 0 sim/testsuite/{sim => }/cris/asm/btst.ms | 0 sim/testsuite/{sim => }/cris/asm/ccr-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/ccs-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/clearfv10.ms | 0 sim/testsuite/{sim => }/cris/asm/clearfv32.ms | 0 sim/testsuite/{sim => }/cris/asm/clrjmp1.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpc.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpm.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpq.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpr.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpxc.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpxm.ms | 0 sim/testsuite/{sim => }/cris/asm/dflags.ms | 0 sim/testsuite/{sim => }/cris/asm/dip.ms | 0 sim/testsuite/{sim => }/cris/asm/dstep.ms | 0 sim/testsuite/{sim => }/cris/asm/fidxd.ms | 0 sim/testsuite/{sim => }/cris/asm/fidxi.ms | 0 sim/testsuite/{sim => }/cris/asm/ftagd.ms | 0 sim/testsuite/{sim => }/cris/asm/ftagi.ms | 0 sim/testsuite/{sim => }/cris/asm/halt.ms | 0 sim/testsuite/{sim => }/cris/asm/io1.ms | 0 sim/testsuite/{sim => }/cris/asm/io2.ms | 0 sim/testsuite/{sim => }/cris/asm/io3.ms | 0 sim/testsuite/{sim => }/cris/asm/io4.ms | 0 sim/testsuite/{sim => }/cris/asm/io5.ms | 0 sim/testsuite/{sim => }/cris/asm/io6.ms | 0 sim/testsuite/{sim => }/cris/asm/io7.ms | 0 sim/testsuite/{sim => }/cris/asm/io8.ms | 0 sim/testsuite/{sim => }/cris/asm/io9.ms | 0 sim/testsuite/{sim => }/cris/asm/jsr.ms | 0 sim/testsuite/{sim => }/cris/asm/jsrmv10.ms | 0 sim/testsuite/{sim => }/cris/asm/jumpmp.ms | 0 sim/testsuite/{sim => }/cris/asm/jumppv32.ms | 0 sim/testsuite/{sim => }/cris/asm/lapc.ms | 0 sim/testsuite/{sim => }/cris/asm/lsl.ms | 0 sim/testsuite/{sim => }/cris/asm/lsr.ms | 0 sim/testsuite/{sim => }/cris/asm/lz.ms | 0 sim/testsuite/{sim => }/cris/asm/mcp.ms | 0 sim/testsuite/{sim => }/cris/asm/movdelsr1.ms | 0 sim/testsuite/{sim => }/cris/asm/movecpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movecr.ms | 0 sim/testsuite/{sim => }/cris/asm/movecrt10.ms | 0 sim/testsuite/{sim => }/cris/asm/movecrt32.ms | 0 sim/testsuite/{sim => }/cris/asm/movect10.ms | 0 sim/testsuite/{sim => }/cris/asm/movei.ms | 0 sim/testsuite/{sim => }/cris/asm/movempc.ms | 0 sim/testsuite/{sim => }/cris/asm/movemr.ms | 0 sim/testsuite/{sim => }/cris/asm/movemrv10.ms | 0 sim/testsuite/{sim => }/cris/asm/movemrv32.ms | 0 sim/testsuite/{sim => }/cris/asm/movepcb.ms | 0 sim/testsuite/{sim => }/cris/asm/movepcd.ms | 0 sim/testsuite/{sim => }/cris/asm/movepcw.ms | 0 sim/testsuite/{sim => }/cris/asm/moveq.ms | 0 sim/testsuite/{sim => }/cris/asm/moveqpc.ms | 0 sim/testsuite/{sim => }/cris/asm/mover.ms | 0 sim/testsuite/{sim => }/cris/asm/moverbpc.ms | 0 sim/testsuite/{sim => }/cris/asm/moverdpc.ms | 0 sim/testsuite/{sim => }/cris/asm/moverm.ms | 0 sim/testsuite/{sim => }/cris/asm/moverpcb.ms | 0 sim/testsuite/{sim => }/cris/asm/moverpcd.ms | 0 sim/testsuite/{sim => }/cris/asm/moverpcw.ms | 0 sim/testsuite/{sim => }/cris/asm/moverwpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movesmp.ms | 0 sim/testsuite/{sim => }/cris/asm/movmp.ms | 0 sim/testsuite/{sim => }/cris/asm/movmp8.ms | 0 sim/testsuite/{sim => }/cris/asm/movpmv10.ms | 0 sim/testsuite/{sim => }/cris/asm/movpmv32.ms | 0 sim/testsuite/{sim => }/cris/asm/movppc.ms | 0 sim/testsuite/{sim => }/cris/asm/movpr.ms | 0 sim/testsuite/{sim => }/cris/asm/movprv10.ms | 0 sim/testsuite/{sim => }/cris/asm/movprv32.ms | 0 sim/testsuite/{sim => }/cris/asm/movrss.ms | 0 sim/testsuite/{sim => }/cris/asm/movscpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movscr.ms | 0 sim/testsuite/{sim => }/cris/asm/movsm.ms | 0 sim/testsuite/{sim => }/cris/asm/movsmpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movsr.ms | 0 sim/testsuite/{sim => }/cris/asm/movsrpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movssr.ms | 0 sim/testsuite/{sim => }/cris/asm/movucpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movucr.ms | 0 sim/testsuite/{sim => }/cris/asm/movum.ms | 0 sim/testsuite/{sim => }/cris/asm/movumpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movur.ms | 0 sim/testsuite/{sim => }/cris/asm/movurpc.ms | 0 sim/testsuite/{sim => }/cris/asm/mstep.ms | 0 sim/testsuite/{sim => }/cris/asm/msteppc1.ms | 0 sim/testsuite/{sim => }/cris/asm/msteppc2.ms | 0 sim/testsuite/{sim => }/cris/asm/msteppc3.ms | 0 sim/testsuite/{sim => }/cris/asm/mulv10.ms | 0 sim/testsuite/{sim => }/cris/asm/mulv32.ms | 0 sim/testsuite/{sim => }/cris/asm/mulx.ms | 0 sim/testsuite/{sim => }/cris/asm/neg.ms | 0 sim/testsuite/{sim => }/cris/asm/nonvcv32.ms | 0 sim/testsuite/{sim => }/cris/asm/nopv10t.ms | 0 sim/testsuite/{sim => }/cris/asm/nopv32t.ms | 0 sim/testsuite/{sim => }/cris/asm/nopv32t2.ms | 0 sim/testsuite/{sim => }/cris/asm/nopv32t3.ms | 0 sim/testsuite/{sim => }/cris/asm/nopv32t4.ms | 0 sim/testsuite/{sim => }/cris/asm/not.ms | 0 sim/testsuite/{sim => }/cris/asm/op3.ms | 0 sim/testsuite/{sim => }/cris/asm/opterr1.ms | 0 sim/testsuite/{sim => }/cris/asm/opterr2.ms | 0 sim/testsuite/{sim => }/cris/asm/opterr3.ms | 0 sim/testsuite/{sim => }/cris/asm/opterr4.ms | 0 sim/testsuite/{sim => }/cris/asm/opterr5.ms | 0 sim/testsuite/{sim => }/cris/asm/option1.ms | 0 sim/testsuite/{sim => }/cris/asm/option2.ms | 0 sim/testsuite/{sim => }/cris/asm/option3.ms | 0 sim/testsuite/{sim => }/cris/asm/option4.ms | 0 sim/testsuite/{sim => }/cris/asm/orc.ms | 0 sim/testsuite/{sim => }/cris/asm/orm.ms | 0 sim/testsuite/{sim => }/cris/asm/orq.ms | 0 sim/testsuite/{sim => }/cris/asm/orr.ms | 0 sim/testsuite/{sim => }/cris/asm/pcplus.ms | 0 sim/testsuite/{sim => }/cris/asm/pid1.ms | 0 sim/testsuite/{sim => }/cris/asm/raw1.ms | 0 sim/testsuite/{sim => }/cris/asm/raw10.ms | 0 sim/testsuite/{sim => }/cris/asm/raw11.ms | 0 sim/testsuite/{sim => }/cris/asm/raw12.ms | 0 sim/testsuite/{sim => }/cris/asm/raw13.ms | 0 sim/testsuite/{sim => }/cris/asm/raw14.ms | 0 sim/testsuite/{sim => }/cris/asm/raw15.ms | 0 sim/testsuite/{sim => }/cris/asm/raw16.ms | 0 sim/testsuite/{sim => }/cris/asm/raw17.ms | 0 sim/testsuite/{sim => }/cris/asm/raw2.ms | 0 sim/testsuite/{sim => }/cris/asm/raw3.ms | 0 sim/testsuite/{sim => }/cris/asm/raw4.ms | 0 sim/testsuite/{sim => }/cris/asm/raw5.ms | 0 sim/testsuite/{sim => }/cris/asm/raw6.ms | 0 sim/testsuite/{sim => }/cris/asm/raw7.ms | 0 sim/testsuite/{sim => }/cris/asm/raw8.ms | 0 sim/testsuite/{sim => }/cris/asm/raw9.ms | 0 sim/testsuite/{sim => }/cris/asm/ret.ms | 0 sim/testsuite/{sim => }/cris/asm/rfe.ms | 0 sim/testsuite/{sim => }/cris/asm/rfg.ms | 0 sim/testsuite/{sim => }/cris/asm/rfn.ms | 0 sim/testsuite/{sim => }/cris/asm/sbfs.ms | 0 sim/testsuite/{sim => }/cris/asm/scc.ms | 0 sim/testsuite/{sim => }/cris/asm/sfe.ms | 0 sim/testsuite/{sim => }/cris/asm/subc.ms | 0 sim/testsuite/{sim => }/cris/asm/subm.ms | 0 sim/testsuite/{sim => }/cris/asm/subq.ms | 0 sim/testsuite/{sim => }/cris/asm/subqpc.ms | 0 sim/testsuite/{sim => }/cris/asm/subr.ms | 0 sim/testsuite/{sim => }/cris/asm/subxc.ms | 0 sim/testsuite/{sim => }/cris/asm/subxm.ms | 0 sim/testsuite/{sim => }/cris/asm/subxr.ms | 0 sim/testsuite/{sim => }/cris/asm/swap.ms | 0 sim/testsuite/{sim => }/cris/asm/tb.ms | 0 sim/testsuite/{sim => }/cris/asm/test.ms | 0 sim/testsuite/{sim => }/cris/asm/testutils.inc | 0 sim/testsuite/{sim => }/cris/asm/tjmpsrv32-2.ms | 0 sim/testsuite/{sim => }/cris/asm/tjmpsrv32.ms | 0 sim/testsuite/{sim => }/cris/asm/tjsrcv10.ms | 0 sim/testsuite/{sim => }/cris/asm/tjsrcv32.ms | 0 sim/testsuite/{sim => }/cris/asm/tmemv10.ms | 0 sim/testsuite/{sim => }/cris/asm/tmemv32.ms | 0 sim/testsuite/{sim => }/cris/asm/tmulv10.ms | 0 sim/testsuite/{sim => }/cris/asm/tmulv32.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvm1.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvm2.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvmrv10.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvmrv32.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvrmv10.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvrmv32.ms | 0 sim/testsuite/{sim => }/cris/asm/user.ms | 0 sim/testsuite/{sim => }/cris/asm/x0-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x0-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x1-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x1-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x10-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x2-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x2-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x3-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x3-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x4-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x5-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x5-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x6-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x6-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x7-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x7-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x8-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x9-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/xor.ms | 0 sim/testsuite/{sim => }/cris/c/access1.c | 0 sim/testsuite/{sim => }/cris/c/append1.c | 0 sim/testsuite/{sim => }/cris/c/badldso1.c | 0 sim/testsuite/{sim => }/cris/c/badldso2.c | 0 sim/testsuite/{sim => }/cris/c/badldso3.c | 0 sim/testsuite/{sim => }/cris/c/c.exp | 0 sim/testsuite/{sim => }/cris/c/clone1.c | 0 sim/testsuite/{sim => }/cris/c/clone2.c | 0 sim/testsuite/{sim => }/cris/c/clone3.c | 0 sim/testsuite/{sim => }/cris/c/clone4.c | 0 sim/testsuite/{sim => }/cris/c/clone5.c | 0 sim/testsuite/{sim => }/cris/c/clone6.c | 0 sim/testsuite/{sim => }/cris/c/ex1.c | 0 sim/testsuite/{sim => }/cris/c/exitg1.c | 0 sim/testsuite/{sim => }/cris/c/exitg2.c | 0 sim/testsuite/{sim => }/cris/c/fcntl1.c | 0 sim/testsuite/{sim => }/cris/c/fcntl2.c | 0 sim/testsuite/{sim => }/cris/c/fdopen1.c | 0 sim/testsuite/{sim => }/cris/c/fdopen2.c | 0 sim/testsuite/{sim => }/cris/c/freopen1.c | 0 sim/testsuite/{sim => }/cris/c/freopen2.c | 0 sim/testsuite/{sim => }/cris/c/ftruncate1.c | 0 sim/testsuite/{sim => }/cris/c/ftruncate2.c | 0 sim/testsuite/{sim => }/cris/c/getcwd1.c | 0 sim/testsuite/{sim => }/cris/c/gettod.c | 0 sim/testsuite/{sim => }/cris/c/hello.c | 0 sim/testsuite/{sim => }/cris/c/helloaout.c | 0 sim/testsuite/{sim => }/cris/c/hellodyn.c | 0 sim/testsuite/{sim => }/cris/c/hellodyn2.c | 0 sim/testsuite/{sim => }/cris/c/hellodyn3.c | 0 sim/testsuite/{sim => }/cris/c/kill1.c | 0 sim/testsuite/{sim => }/cris/c/kill2.c | 0 sim/testsuite/{sim => }/cris/c/kill3.c | 0 sim/testsuite/{sim => }/cris/c/mapbrk.c | 0 sim/testsuite/{sim => }/cris/c/mmap1.c | 0 sim/testsuite/{sim => }/cris/c/mmap2.c | 0 sim/testsuite/{sim => }/cris/c/mmap3.c | 0 sim/testsuite/{sim => }/cris/c/mmap4.c | 0 sim/testsuite/{sim => }/cris/c/mmap5.c | 0 sim/testsuite/{sim => }/cris/c/mmap6.c | 0 sim/testsuite/{sim => }/cris/c/mmap7.c | 0 sim/testsuite/{sim => }/cris/c/mmap8.c | 0 sim/testsuite/{sim => }/cris/c/mprotect1.c | 0 sim/testsuite/{sim => }/cris/c/mprotect2.c | 0 sim/testsuite/{sim => }/cris/c/mremap.c | 0 sim/testsuite/{sim => }/cris/c/openpf1.c | 0 sim/testsuite/{sim => }/cris/c/openpf2.c | 0 sim/testsuite/{sim => }/cris/c/openpf3.c | 0 sim/testsuite/{sim => }/cris/c/openpf4.c | 0 sim/testsuite/{sim => }/cris/c/openpf5.c | 0 sim/testsuite/{sim => }/cris/c/pipe1.c | 0 sim/testsuite/{sim => }/cris/c/pipe2.c | 0 sim/testsuite/{sim => }/cris/c/pipe3.c | 0 sim/testsuite/{sim => }/cris/c/pipe4.c | 0 sim/testsuite/{sim => }/cris/c/pipe5.c | 0 sim/testsuite/{sim => }/cris/c/pipe6.c | 0 sim/testsuite/{sim => }/cris/c/pipe7.c | 0 sim/testsuite/{sim => }/cris/c/readlink1.c | 0 sim/testsuite/{sim => }/cris/c/readlink10.c | 0 sim/testsuite/{sim => }/cris/c/readlink11.c | 0 sim/testsuite/{sim => }/cris/c/readlink2.c | 0 sim/testsuite/{sim => }/cris/c/readlink3.c | 0 sim/testsuite/{sim => }/cris/c/readlink4.c | 0 sim/testsuite/{sim => }/cris/c/readlink5.c | 0 sim/testsuite/{sim => }/cris/c/readlink6.c | 0 sim/testsuite/{sim => }/cris/c/readlink7.c | 0 sim/testsuite/{sim => }/cris/c/readlink8.c | 0 sim/testsuite/{sim => }/cris/c/readlink9.c | 0 sim/testsuite/{sim => }/cris/c/rename2.c | 0 sim/testsuite/{sim => }/cris/c/rtsigprocmask1.c | 0 sim/testsuite/{sim => }/cris/c/rtsigprocmask2.c | 0 sim/testsuite/{sim => }/cris/c/rtsigsuspend1.c | 0 sim/testsuite/{sim => }/cris/c/rtsigsuspend2.c | 0 sim/testsuite/{sim => }/cris/c/sched1.c | 0 sim/testsuite/{sim => }/cris/c/sched2.c | 0 sim/testsuite/{sim => }/cris/c/sched3.c | 0 sim/testsuite/{sim => }/cris/c/sched4.c | 0 sim/testsuite/{sim => }/cris/c/sched5.c | 0 sim/testsuite/{sim => }/cris/c/sched6.c | 0 sim/testsuite/{sim => }/cris/c/sched7.c | 0 sim/testsuite/{sim => }/cris/c/sched8.c | 0 sim/testsuite/{sim => }/cris/c/sched9.c | 0 sim/testsuite/{sim => }/cris/c/seek1.c | 0 sim/testsuite/{sim => }/cris/c/seek2.c | 0 sim/testsuite/{sim => }/cris/c/seek3.c | 0 sim/testsuite/{sim => }/cris/c/seek4.c | 0 sim/testsuite/{sim => }/cris/c/setrlimit1.c | 0 sim/testsuite/{sim => }/cris/c/settls1.c | 0 sim/testsuite/{sim => }/cris/c/sig1.c | 0 sim/testsuite/{sim => }/cris/c/sig10.c | 0 sim/testsuite/{sim => }/cris/c/sig11.c | 0 sim/testsuite/{sim => }/cris/c/sig12.c | 0 sim/testsuite/{sim => }/cris/c/sig13.c | 0 sim/testsuite/{sim => }/cris/c/sig2.c | 0 sim/testsuite/{sim => }/cris/c/sig3.c | 0 sim/testsuite/{sim => }/cris/c/sig4.c | 0 sim/testsuite/{sim => }/cris/c/sig5.c | 0 sim/testsuite/{sim => }/cris/c/sig6.c | 0 sim/testsuite/{sim => }/cris/c/sig7.c | 0 sim/testsuite/{sim => }/cris/c/sig8.c | 0 sim/testsuite/{sim => }/cris/c/sig9.c | 0 sim/testsuite/{sim => }/cris/c/sigreturn1.c | 0 sim/testsuite/{sim => }/cris/c/sigreturn2.c | 0 sim/testsuite/{sim => }/cris/c/sigreturn3.c | 0 sim/testsuite/{sim => }/cris/c/sigreturn4.c | 0 sim/testsuite/{sim => }/cris/c/sjlj.c | 0 sim/testsuite/{sim => }/cris/c/sock1.c | 0 sim/testsuite/{sim => }/cris/c/stat1.c | 0 sim/testsuite/{sim => }/cris/c/stat2.c | 0 sim/testsuite/{sim => }/cris/c/stat3.c | 0 sim/testsuite/{sim => }/cris/c/stat4.c | 0 sim/testsuite/{sim => }/cris/c/stat5.c | 0 sim/testsuite/{sim => }/cris/c/stat7.c | 0 sim/testsuite/{sim => }/cris/c/stat8.c | 0 sim/testsuite/{sim => }/cris/c/syscall1.c | 0 sim/testsuite/{sim => }/cris/c/syscall2.c | 0 sim/testsuite/{sim => }/cris/c/syscall3.c | 0 sim/testsuite/{sim => }/cris/c/syscall4.c | 0 sim/testsuite/{sim => }/cris/c/syscall5.c | 0 sim/testsuite/{sim => }/cris/c/syscall6.c | 0 sim/testsuite/{sim => }/cris/c/syscall7.c | 0 sim/testsuite/{sim => }/cris/c/syscall8.c | 0 sim/testsuite/{sim => }/cris/c/sysctl1.c | 0 sim/testsuite/{sim => }/cris/c/sysctl2.c | 0 sim/testsuite/{sim => }/cris/c/sysctl3.c | 0 sim/testsuite/{sim => }/cris/c/thread2.c | 0 sim/testsuite/{sim => }/cris/c/thread3.c | 0 sim/testsuite/{sim => }/cris/c/thread4.c | 0 sim/testsuite/{sim => }/cris/c/thread5.c | 0 sim/testsuite/{sim => }/cris/c/time1.c | 0 sim/testsuite/{sim => }/cris/c/time2.c | 0 sim/testsuite/{sim => }/cris/c/truncate1.c | 0 sim/testsuite/{sim => }/cris/c/truncate2.c | 0 sim/testsuite/{sim => }/cris/c/ugetrlimit1.c | 0 sim/testsuite/{sim => }/cris/c/uname1.c | 0 sim/testsuite/{sim => }/cris/c/writev1.c | 0 sim/testsuite/{sim => }/cris/c/writev2.c | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/host1.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq1.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq2.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq3.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq4.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq5.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq6.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/mbox1.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/mem1.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/mem2.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/poll1.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/quit.s | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/rvc.exp | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/std.dev | 0 .../{sim => }/cris/hw/rv-n-cris/testutils.inc | 0 .../{sim => }/cris/hw/rv-n-cris/trivial1.ms | 0 .../{sim => }/cris/hw/rv-n-cris/trivial2.ms | 0 .../{sim => }/cris/hw/rv-n-cris/trivial3.ms | 0 .../{sim => }/cris/hw/rv-n-cris/trivial4.ms | 0 .../{sim => }/cris/hw/rv-n-cris/trivial4.r | 0 .../{sim => }/cris/hw/rv-n-cris/trivial5.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/wd1.ms | 0 sim/testsuite/{sim => }/d10v/ChangeLog | 0 sim/testsuite/{sim => }/d10v/allinsn.exp | 0 sim/testsuite/{sim => }/d10v/exit47.s | 0 sim/testsuite/{sim => }/d10v/hello.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld-d.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld-i.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld-id.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld-im.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld-ip.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld2w-d.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld2w-i.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld2w-id.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld2w-im.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld2w-ip.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st-d.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st-i.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st-id.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st-im.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st-ip.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st-is.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st2w-d.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st2w-i.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st2w-id.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st2w-im.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st2w-ip.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st2w-is.s | 0 sim/testsuite/{sim => }/d10v/t-dbt.s | 0 sim/testsuite/{sim => }/d10v/t-ld-st.s | 0 sim/testsuite/{sim => }/d10v/t-mac.s | 0 sim/testsuite/{sim => }/d10v/t-macros.i | 0 sim/testsuite/{sim => }/d10v/t-mod-ld-pre.s | 0 sim/testsuite/{sim => }/d10v/t-msbu.s | 0 sim/testsuite/{sim => }/d10v/t-mulxu.s | 0 sim/testsuite/{sim => }/d10v/t-mvtac.s | 0 sim/testsuite/{sim => }/d10v/t-mvtc.s | 0 sim/testsuite/{sim => }/d10v/t-rac.s | 0 sim/testsuite/{sim => }/d10v/t-rachi.s | 0 sim/testsuite/{sim => }/d10v/t-rdt.s | 0 sim/testsuite/{sim => }/d10v/t-rep.s | 0 sim/testsuite/{sim => }/d10v/t-rie-xx.s | 0 sim/testsuite/{sim => }/d10v/t-rte.s | 0 sim/testsuite/{sim => }/d10v/t-sac.s | 0 sim/testsuite/{sim => }/d10v/t-sachi.s | 0 sim/testsuite/{sim => }/d10v/t-sadd.s | 0 sim/testsuite/{sim => }/d10v/t-slae.s | 0 sim/testsuite/{sim => }/d10v/t-sp.s | 0 sim/testsuite/{sim => }/d10v/t-sub.s | 0 sim/testsuite/{sim => }/d10v/t-sub2w.s | 0 sim/testsuite/{sim => }/d10v/t-subi.s | 0 sim/testsuite/{sim => }/d10v/t-trap.s | 0 sim/testsuite/{sim => }/frv/ChangeLog | 0 sim/testsuite/{sim => }/frv/add.cgs | 0 sim/testsuite/{sim => }/frv/add.pcgs | 0 sim/testsuite/{sim => }/frv/addcc.cgs | 0 sim/testsuite/{sim => }/frv/addi.cgs | 0 sim/testsuite/{sim => }/frv/addicc.cgs | 0 sim/testsuite/{sim => }/frv/addx.cgs | 0 sim/testsuite/{sim => }/frv/addxcc.cgs | 0 sim/testsuite/{sim => }/frv/addxi.cgs | 0 sim/testsuite/{sim => }/frv/addxicc.cgs | 0 sim/testsuite/{sim => }/frv/allinsn.exp | 0 sim/testsuite/{sim => }/frv/and.cgs | 0 sim/testsuite/{sim => }/frv/andcc.cgs | 0 sim/testsuite/{sim => }/frv/andcr.cgs | 0 sim/testsuite/{sim => }/frv/andi.cgs | 0 sim/testsuite/{sim => }/frv/andicc.cgs | 0 sim/testsuite/{sim => }/frv/andncr.cgs | 0 sim/testsuite/{sim => }/frv/bar.cgs | 0 sim/testsuite/{sim => }/frv/bc.cgs | 0 sim/testsuite/{sim => }/frv/bcclr.cgs | 0 sim/testsuite/{sim => }/frv/bceqlr.cgs | 0 sim/testsuite/{sim => }/frv/bcgelr.cgs | 0 sim/testsuite/{sim => }/frv/bcgtlr.cgs | 0 sim/testsuite/{sim => }/frv/bchilr.cgs | 0 sim/testsuite/{sim => }/frv/bclelr.cgs | 0 sim/testsuite/{sim => }/frv/bclr.cgs | 0 sim/testsuite/{sim => }/frv/bclslr.cgs | 0 sim/testsuite/{sim => }/frv/bcltlr.cgs | 0 sim/testsuite/{sim => }/frv/bcnclr.cgs | 0 sim/testsuite/{sim => }/frv/bcnelr.cgs | 0 sim/testsuite/{sim => }/frv/bcnlr.cgs | 0 sim/testsuite/{sim => }/frv/bcnolr.cgs | 0 sim/testsuite/{sim => }/frv/bcnvlr.cgs | 0 sim/testsuite/{sim => }/frv/bcplr.cgs | 0 sim/testsuite/{sim => }/frv/bcralr.cgs | 0 sim/testsuite/{sim => }/frv/bctrlr.cgs | 0 sim/testsuite/{sim => }/frv/bcvlr.cgs | 0 sim/testsuite/{sim => }/frv/beq.cgs | 0 sim/testsuite/{sim => }/frv/beqlr.cgs | 0 sim/testsuite/{sim => }/frv/bge.cgs | 0 sim/testsuite/{sim => }/frv/bgelr.cgs | 0 sim/testsuite/{sim => }/frv/bgt.cgs | 0 sim/testsuite/{sim => }/frv/bgtlr.cgs | 0 sim/testsuite/{sim => }/frv/bhi.cgs | 0 sim/testsuite/{sim => }/frv/bhilr.cgs | 0 sim/testsuite/{sim => }/frv/ble.cgs | 0 sim/testsuite/{sim => }/frv/blelr.cgs | 0 sim/testsuite/{sim => }/frv/bls.cgs | 0 sim/testsuite/{sim => }/frv/blslr.cgs | 0 sim/testsuite/{sim => }/frv/blt.cgs | 0 sim/testsuite/{sim => }/frv/bltlr.cgs | 0 sim/testsuite/{sim => }/frv/bn.cgs | 0 sim/testsuite/{sim => }/frv/bnc.cgs | 0 sim/testsuite/{sim => }/frv/bnclr.cgs | 0 sim/testsuite/{sim => }/frv/bne.cgs | 0 sim/testsuite/{sim => }/frv/bnelr.cgs | 0 sim/testsuite/{sim => }/frv/bnlr.cgs | 0 sim/testsuite/{sim => }/frv/bno.cgs | 0 sim/testsuite/{sim => }/frv/bnolr.cgs | 0 sim/testsuite/{sim => }/frv/bnv.cgs | 0 sim/testsuite/{sim => }/frv/bnvlr.cgs | 0 sim/testsuite/{sim => }/frv/bp.cgs | 0 sim/testsuite/{sim => }/frv/bplr.cgs | 0 sim/testsuite/{sim => }/frv/bra.cgs | 0 sim/testsuite/{sim => }/frv/bralr.cgs | 0 sim/testsuite/{sim => }/frv/branch.pcgs | 0 sim/testsuite/{sim => }/frv/break.cgs | 0 sim/testsuite/{sim => }/frv/bv.cgs | 0 sim/testsuite/{sim => }/frv/bvlr.cgs | 0 sim/testsuite/{sim => }/frv/cache.ms | 0 sim/testsuite/{sim => }/frv/cadd.cgs | 0 sim/testsuite/{sim => }/frv/caddcc.cgs | 0 sim/testsuite/{sim => }/frv/call.cgs | 0 sim/testsuite/{sim => }/frv/call.pcgs | 0 sim/testsuite/{sim => }/frv/callil.cgs | 0 sim/testsuite/{sim => }/frv/calll.cgs | 0 sim/testsuite/{sim => }/frv/cand.cgs | 0 sim/testsuite/{sim => }/frv/candcc.cgs | 0 sim/testsuite/{sim => }/frv/ccalll.cgs | 0 sim/testsuite/{sim => }/frv/cckc.cgs | 0 sim/testsuite/{sim => }/frv/cckeq.cgs | 0 sim/testsuite/{sim => }/frv/cckge.cgs | 0 sim/testsuite/{sim => }/frv/cckgt.cgs | 0 sim/testsuite/{sim => }/frv/cckhi.cgs | 0 sim/testsuite/{sim => }/frv/cckle.cgs | 0 sim/testsuite/{sim => }/frv/cckls.cgs | 0 sim/testsuite/{sim => }/frv/ccklt.cgs | 0 sim/testsuite/{sim => }/frv/cckn.cgs | 0 sim/testsuite/{sim => }/frv/ccknc.cgs | 0 sim/testsuite/{sim => }/frv/cckne.cgs | 0 sim/testsuite/{sim => }/frv/cckno.cgs | 0 sim/testsuite/{sim => }/frv/ccknv.cgs | 0 sim/testsuite/{sim => }/frv/cckp.cgs | 0 sim/testsuite/{sim => }/frv/cckra.cgs | 0 sim/testsuite/{sim => }/frv/cckv.cgs | 0 sim/testsuite/{sim => }/frv/ccmp.cgs | 0 sim/testsuite/{sim => }/frv/cfabss.cgs | 0 sim/testsuite/{sim => }/frv/cfadds.cgs | 0 sim/testsuite/{sim => }/frv/cfckeq.cgs | 0 sim/testsuite/{sim => }/frv/cfckge.cgs | 0 sim/testsuite/{sim => }/frv/cfckgt.cgs | 0 sim/testsuite/{sim => }/frv/cfckle.cgs | 0 sim/testsuite/{sim => }/frv/cfcklg.cgs | 0 sim/testsuite/{sim => }/frv/cfcklt.cgs | 0 sim/testsuite/{sim => }/frv/cfckne.cgs | 0 sim/testsuite/{sim => }/frv/cfckno.cgs | 0 sim/testsuite/{sim => }/frv/cfcko.cgs | 0 sim/testsuite/{sim => }/frv/cfckra.cgs | 0 sim/testsuite/{sim => }/frv/cfcku.cgs | 0 sim/testsuite/{sim => }/frv/cfckue.cgs | 0 sim/testsuite/{sim => }/frv/cfckug.cgs | 0 sim/testsuite/{sim => }/frv/cfckuge.cgs | 0 sim/testsuite/{sim => }/frv/cfckul.cgs | 0 sim/testsuite/{sim => }/frv/cfckule.cgs | 0 sim/testsuite/{sim => }/frv/cfcmps.cgs | 0 sim/testsuite/{sim => }/frv/cfdivs.cgs | 0 sim/testsuite/{sim => }/frv/cfitos.cgs | 0 sim/testsuite/{sim => }/frv/cfmadds.cgs | 0 sim/testsuite/{sim => }/frv/cfmas.cgs | 0 sim/testsuite/{sim => }/frv/cfmovs.cgs | 0 sim/testsuite/{sim => }/frv/cfmss.cgs | 0 sim/testsuite/{sim => }/frv/cfmsubs.cgs | 0 sim/testsuite/{sim => }/frv/cfmuls.cgs | 0 sim/testsuite/{sim => }/frv/cfnegs.cgs | 0 sim/testsuite/{sim => }/frv/cfsqrts.cgs | 0 sim/testsuite/{sim => }/frv/cfstoi.cgs | 0 sim/testsuite/{sim => }/frv/cfsubs.cgs | 0 sim/testsuite/{sim => }/frv/cjmpl.cgs | 0 sim/testsuite/{sim => }/frv/ckc.cgs | 0 sim/testsuite/{sim => }/frv/ckeq.cgs | 0 sim/testsuite/{sim => }/frv/ckge.cgs | 0 sim/testsuite/{sim => }/frv/ckgt.cgs | 0 sim/testsuite/{sim => }/frv/ckhi.cgs | 0 sim/testsuite/{sim => }/frv/ckle.cgs | 0 sim/testsuite/{sim => }/frv/ckls.cgs | 0 sim/testsuite/{sim => }/frv/cklt.cgs | 0 sim/testsuite/{sim => }/frv/ckn.cgs | 0 sim/testsuite/{sim => }/frv/cknc.cgs | 0 sim/testsuite/{sim => }/frv/ckne.cgs | 0 sim/testsuite/{sim => }/frv/ckno.cgs | 0 sim/testsuite/{sim => }/frv/cknv.cgs | 0 sim/testsuite/{sim => }/frv/ckp.cgs | 0 sim/testsuite/{sim => }/frv/ckra.cgs | 0 sim/testsuite/{sim => }/frv/ckv.cgs | 0 sim/testsuite/{sim => }/frv/cld.cgs | 0 sim/testsuite/{sim => }/frv/cldbf.cgs | 0 sim/testsuite/{sim => }/frv/cldbfu.cgs | 0 sim/testsuite/{sim => }/frv/cldd.cgs | 0 sim/testsuite/{sim => }/frv/clddf.cgs | 0 sim/testsuite/{sim => }/frv/clddfu.cgs | 0 sim/testsuite/{sim => }/frv/clddu.cgs | 0 sim/testsuite/{sim => }/frv/cldf.cgs | 0 sim/testsuite/{sim => }/frv/cldfu.cgs | 0 sim/testsuite/{sim => }/frv/cldhf.cgs | 0 sim/testsuite/{sim => }/frv/cldhfu.cgs | 0 sim/testsuite/{sim => }/frv/cldq.cgs | 0 sim/testsuite/{sim => }/frv/cldqu.cgs | 0 sim/testsuite/{sim => }/frv/cldsb.cgs | 0 sim/testsuite/{sim => }/frv/cldsbu.cgs | 0 sim/testsuite/{sim => }/frv/cldsh.cgs | 0 sim/testsuite/{sim => }/frv/cldshu.cgs | 0 sim/testsuite/{sim => }/frv/cldu.cgs | 0 sim/testsuite/{sim => }/frv/cldub.cgs | 0 sim/testsuite/{sim => }/frv/cldubu.cgs | 0 sim/testsuite/{sim => }/frv/clduh.cgs | 0 sim/testsuite/{sim => }/frv/clduhu.cgs | 0 sim/testsuite/{sim => }/frv/clrfa.cgs | 0 sim/testsuite/{sim => }/frv/clrfr.cgs | 0 sim/testsuite/{sim => }/frv/clrga.cgs | 0 sim/testsuite/{sim => }/frv/clrgr.cgs | 0 sim/testsuite/{sim => }/frv/cmaddhss.cgs | 0 sim/testsuite/{sim => }/frv/cmaddhus.cgs | 0 sim/testsuite/{sim => }/frv/cmand.cgs | 0 sim/testsuite/{sim => }/frv/cmbtoh.cgs | 0 sim/testsuite/{sim => }/frv/cmbtohe.cgs | 0 sim/testsuite/{sim => }/frv/cmcpxis.cgs | 0 sim/testsuite/{sim => }/frv/cmcpxiu.cgs | 0 sim/testsuite/{sim => }/frv/cmcpxrs.cgs | 0 sim/testsuite/{sim => }/frv/cmcpxru.cgs | 0 sim/testsuite/{sim => }/frv/cmexpdhd.cgs | 0 sim/testsuite/{sim => }/frv/cmexpdhw.cgs | 0 sim/testsuite/{sim => }/frv/cmhtob.cgs | 0 sim/testsuite/{sim => }/frv/cmmachs.cgs | 0 sim/testsuite/{sim => }/frv/cmmachu.cgs | 0 sim/testsuite/{sim => }/frv/cmmulhs.cgs | 0 sim/testsuite/{sim => }/frv/cmmulhu.cgs | 0 sim/testsuite/{sim => }/frv/cmnot.cgs | 0 sim/testsuite/{sim => }/frv/cmor.cgs | 0 sim/testsuite/{sim => }/frv/cmov.cgs | 0 sim/testsuite/{sim => }/frv/cmovfg.cgs | 0 sim/testsuite/{sim => }/frv/cmovfgd.cgs | 0 sim/testsuite/{sim => }/frv/cmovgf.cgs | 0 sim/testsuite/{sim => }/frv/cmovgfd.cgs | 0 sim/testsuite/{sim => }/frv/cmp.cgs | 0 sim/testsuite/{sim => }/frv/cmpb.cgs | 0 sim/testsuite/{sim => }/frv/cmpba.cgs | 0 sim/testsuite/{sim => }/frv/cmpi.cgs | 0 sim/testsuite/{sim => }/frv/cmqmachs.cgs | 0 sim/testsuite/{sim => }/frv/cmqmachu.cgs | 0 sim/testsuite/{sim => }/frv/cmqmulhs.cgs | 0 sim/testsuite/{sim => }/frv/cmqmulhu.cgs | 0 sim/testsuite/{sim => }/frv/cmsubhss.cgs | 0 sim/testsuite/{sim => }/frv/cmsubhus.cgs | 0 sim/testsuite/{sim => }/frv/cmxor.cgs | 0 sim/testsuite/{sim => }/frv/cnot.cgs | 0 sim/testsuite/{sim => }/frv/commitfa.cgs | 0 sim/testsuite/{sim => }/frv/commitfr.cgs | 0 sim/testsuite/{sim => }/frv/commitga.cgs | 0 sim/testsuite/{sim => }/frv/commitgr.cgs | 0 sim/testsuite/{sim => }/frv/cop1.cgs | 0 sim/testsuite/{sim => }/frv/cop2.cgs | 0 sim/testsuite/{sim => }/frv/cor.cgs | 0 sim/testsuite/{sim => }/frv/corcc.cgs | 0 sim/testsuite/{sim => }/frv/cscan.cgs | 0 sim/testsuite/{sim => }/frv/csdiv.cgs | 0 sim/testsuite/{sim => }/frv/csll.cgs | 0 sim/testsuite/{sim => }/frv/csllcc.cgs | 0 sim/testsuite/{sim => }/frv/csmul.cgs | 0 sim/testsuite/{sim => }/frv/csmulcc.cgs | 0 sim/testsuite/{sim => }/frv/csra.cgs | 0 sim/testsuite/{sim => }/frv/csracc.cgs | 0 sim/testsuite/{sim => }/frv/csrl.cgs | 0 sim/testsuite/{sim => }/frv/csrlcc.cgs | 0 sim/testsuite/{sim => }/frv/cst.cgs | 0 sim/testsuite/{sim => }/frv/cstb.cgs | 0 sim/testsuite/{sim => }/frv/cstbf.cgs | 0 sim/testsuite/{sim => }/frv/cstbfu.cgs | 0 sim/testsuite/{sim => }/frv/cstbu.cgs | 0 sim/testsuite/{sim => }/frv/cstd.cgs | 0 sim/testsuite/{sim => }/frv/cstdf.cgs | 0 sim/testsuite/{sim => }/frv/cstdfu.cgs | 0 sim/testsuite/{sim => }/frv/cstdu.cgs | 0 sim/testsuite/{sim => }/frv/cstf.cgs | 0 sim/testsuite/{sim => }/frv/cstfu.cgs | 0 sim/testsuite/{sim => }/frv/csth.cgs | 0 sim/testsuite/{sim => }/frv/csthf.cgs | 0 sim/testsuite/{sim => }/frv/csthfu.cgs | 0 sim/testsuite/{sim => }/frv/csthu.cgs | 0 sim/testsuite/{sim => }/frv/cstq.cgs | 0 sim/testsuite/{sim => }/frv/cstu.cgs | 0 sim/testsuite/{sim => }/frv/csub.cgs | 0 sim/testsuite/{sim => }/frv/csubcc.cgs | 0 sim/testsuite/{sim => }/frv/cswap.cgs | 0 sim/testsuite/{sim => }/frv/cudiv.cgs | 0 sim/testsuite/{sim => }/frv/cxor.cgs | 0 sim/testsuite/{sim => }/frv/cxorcc.cgs | 0 sim/testsuite/{sim => }/frv/dcef.cgs | 0 sim/testsuite/{sim => }/frv/dcei.cgs | 0 sim/testsuite/{sim => }/frv/dcf.cgs | 0 sim/testsuite/{sim => }/frv/dci.cgs | 0 sim/testsuite/{sim => }/frv/exit47.ms | 0 sim/testsuite/{sim => }/frv/fabsd.cgs | 0 sim/testsuite/{sim => }/frv/fabss.cgs | 0 sim/testsuite/{sim => }/frv/faddd.cgs | 0 sim/testsuite/{sim => }/frv/fadds.cgs | 0 sim/testsuite/{sim => }/frv/fbeq.cgs | 0 sim/testsuite/{sim => }/frv/fbeqlr.cgs | 0 sim/testsuite/{sim => }/frv/fbge.cgs | 0 sim/testsuite/{sim => }/frv/fbgelr.cgs | 0 sim/testsuite/{sim => }/frv/fbgt.cgs | 0 sim/testsuite/{sim => }/frv/fbgtlr.cgs | 0 sim/testsuite/{sim => }/frv/fble.cgs | 0 sim/testsuite/{sim => }/frv/fblelr.cgs | 0 sim/testsuite/{sim => }/frv/fblg.cgs | 0 sim/testsuite/{sim => }/frv/fblglr.cgs | 0 sim/testsuite/{sim => }/frv/fblt.cgs | 0 sim/testsuite/{sim => }/frv/fbltlr.cgs | 0 sim/testsuite/{sim => }/frv/fbne.cgs | 0 sim/testsuite/{sim => }/frv/fbnelr.cgs | 0 sim/testsuite/{sim => }/frv/fbno.cgs | 0 sim/testsuite/{sim => }/frv/fbnolr.cgs | 0 sim/testsuite/{sim => }/frv/fbo.cgs | 0 sim/testsuite/{sim => }/frv/fbolr.cgs | 0 sim/testsuite/{sim => }/frv/fbra.cgs | 0 sim/testsuite/{sim => }/frv/fbralr.cgs | 0 sim/testsuite/{sim => }/frv/fbu.cgs | 0 sim/testsuite/{sim => }/frv/fbue.cgs | 0 sim/testsuite/{sim => }/frv/fbuelr.cgs | 0 sim/testsuite/{sim => }/frv/fbug.cgs | 0 sim/testsuite/{sim => }/frv/fbuge.cgs | 0 sim/testsuite/{sim => }/frv/fbugelr.cgs | 0 sim/testsuite/{sim => }/frv/fbuglr.cgs | 0 sim/testsuite/{sim => }/frv/fbul.cgs | 0 sim/testsuite/{sim => }/frv/fbule.cgs | 0 sim/testsuite/{sim => }/frv/fbulelr.cgs | 0 sim/testsuite/{sim => }/frv/fbullr.cgs | 0 sim/testsuite/{sim => }/frv/fbulr.cgs | 0 sim/testsuite/{sim => }/frv/fcbeqlr.cgs | 0 sim/testsuite/{sim => }/frv/fcbgelr.cgs | 0 sim/testsuite/{sim => }/frv/fcbgtlr.cgs | 0 sim/testsuite/{sim => }/frv/fcblelr.cgs | 0 sim/testsuite/{sim => }/frv/fcblglr.cgs | 0 sim/testsuite/{sim => }/frv/fcbltlr.cgs | 0 sim/testsuite/{sim => }/frv/fcbnelr.cgs | 0 sim/testsuite/{sim => }/frv/fcbnolr.cgs | 0 sim/testsuite/{sim => }/frv/fcbolr.cgs | 0 sim/testsuite/{sim => }/frv/fcbralr.cgs | 0 sim/testsuite/{sim => }/frv/fcbuelr.cgs | 0 sim/testsuite/{sim => }/frv/fcbugelr.cgs | 0 sim/testsuite/{sim => }/frv/fcbuglr.cgs | 0 sim/testsuite/{sim => }/frv/fcbulelr.cgs | 0 sim/testsuite/{sim => }/frv/fcbullr.cgs | 0 sim/testsuite/{sim => }/frv/fcbulr.cgs | 0 sim/testsuite/{sim => }/frv/fckeq.cgs | 0 sim/testsuite/{sim => }/frv/fckge.cgs | 0 sim/testsuite/{sim => }/frv/fckgt.cgs | 0 sim/testsuite/{sim => }/frv/fckle.cgs | 0 sim/testsuite/{sim => }/frv/fcklg.cgs | 0 sim/testsuite/{sim => }/frv/fcklt.cgs | 0 sim/testsuite/{sim => }/frv/fckne.cgs | 0 sim/testsuite/{sim => }/frv/fckno.cgs | 0 sim/testsuite/{sim => }/frv/fcko.cgs | 0 sim/testsuite/{sim => }/frv/fckra.cgs | 0 sim/testsuite/{sim => }/frv/fcku.cgs | 0 sim/testsuite/{sim => }/frv/fckue.cgs | 0 sim/testsuite/{sim => }/frv/fckug.cgs | 0 sim/testsuite/{sim => }/frv/fckuge.cgs | 0 sim/testsuite/{sim => }/frv/fckul.cgs | 0 sim/testsuite/{sim => }/frv/fckule.cgs | 0 sim/testsuite/{sim => }/frv/fcmpd.cgs | 0 sim/testsuite/{sim => }/frv/fcmps.cgs | 0 sim/testsuite/{sim => }/frv/fdabss.cgs | 0 sim/testsuite/{sim => }/frv/fdadds.cgs | 0 sim/testsuite/{sim => }/frv/fdcmps.cgs | 0 sim/testsuite/{sim => }/frv/fddivs.cgs | 0 sim/testsuite/{sim => }/frv/fditos.cgs | 0 sim/testsuite/{sim => }/frv/fdivd.cgs | 0 sim/testsuite/{sim => }/frv/fdivs.cgs | 0 sim/testsuite/{sim => }/frv/fdmadds.cgs | 0 sim/testsuite/{sim => }/frv/fdmas.cgs | 0 sim/testsuite/{sim => }/frv/fdmovs.cgs | 0 sim/testsuite/{sim => }/frv/fdmss.cgs | 0 sim/testsuite/{sim => }/frv/fdmulcs.cgs | 0 sim/testsuite/{sim => }/frv/fdmuls.cgs | 0 sim/testsuite/{sim => }/frv/fdnegs.cgs | 0 sim/testsuite/{sim => }/frv/fdsads.cgs | 0 sim/testsuite/{sim => }/frv/fdsqrts.cgs | 0 sim/testsuite/{sim => }/frv/fdstoi.cgs | 0 sim/testsuite/{sim => }/frv/fdsubs.cgs | 0 sim/testsuite/{sim => }/frv/fdtoi.cgs | 0 sim/testsuite/{sim => }/frv/fitod.cgs | 0 sim/testsuite/{sim => }/frv/fitos.cgs | 0 sim/testsuite/{sim => }/frv/fmad.cgs | 0 sim/testsuite/{sim => }/frv/fmaddd.cgs | 0 sim/testsuite/{sim => }/frv/fmadds.cgs | 0 sim/testsuite/{sim => }/frv/fmas.cgs | 0 sim/testsuite/{sim => }/frv/fmovd.cgs | 0 sim/testsuite/{sim => }/frv/fmovs.cgs | 0 sim/testsuite/{sim => }/frv/fmsd.cgs | 0 sim/testsuite/{sim => }/frv/fmss.cgs | 0 sim/testsuite/{sim => }/frv/fmsubd.cgs | 0 sim/testsuite/{sim => }/frv/fmsubs.cgs | 0 sim/testsuite/{sim => }/frv/fmuld.cgs | 0 sim/testsuite/{sim => }/frv/fmuls.cgs | 0 sim/testsuite/{sim => }/frv/fnegd.cgs | 0 sim/testsuite/{sim => }/frv/fnegs.cgs | 0 sim/testsuite/{sim => }/frv/fnop.cgs | 0 sim/testsuite/{sim => }/frv/fr400/addss.cgs | 0 sim/testsuite/{sim => }/frv/fr400/allinsn.exp | 0 sim/testsuite/{sim => }/frv/fr400/csdiv.cgs | 0 sim/testsuite/{sim => }/frv/fr400/maddaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr400/masaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr400/maveh.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mclracc.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhdseth.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhdsets.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhsethih.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhsethis.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhsetloh.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhsetlos.cgs | 0 sim/testsuite/{sim => }/frv/fr400/movgs.cgs | 0 sim/testsuite/{sim => }/frv/fr400/movsg.cgs | 0 sim/testsuite/{sim => }/frv/fr400/msubaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr400/scutss.cgs | 0 sim/testsuite/{sim => }/frv/fr400/sdiv.cgs | 0 sim/testsuite/{sim => }/frv/fr400/sdivi.cgs | 0 sim/testsuite/{sim => }/frv/fr400/slass.cgs | 0 sim/testsuite/{sim => }/frv/fr400/smass.cgs | 0 sim/testsuite/{sim => }/frv/fr400/smsss.cgs | 0 sim/testsuite/{sim => }/frv/fr400/smu.cgs | 0 sim/testsuite/{sim => }/frv/fr400/subss.cgs | 0 sim/testsuite/{sim => }/frv/fr400/udiv.cgs | 0 sim/testsuite/{sim => }/frv/fr400/udivi.cgs | 0 sim/testsuite/{sim => }/frv/fr500/allinsn.exp | 0 sim/testsuite/{sim => }/frv/fr500/cmqaddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr500/cmqaddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr500/cmqsubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr500/cmqsubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr500/dcpl.cgs | 0 sim/testsuite/{sim => }/frv/fr500/dcul.cgs | 0 sim/testsuite/{sim => }/frv/fr500/mclracc.cgs | 0 sim/testsuite/{sim => }/frv/fr500/mqaddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr500/mqaddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr500/mqsubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr500/mqsubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/allinsn.exp | 0 sim/testsuite/{sim => }/frv/fr550/cmaddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmaddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmcpxiu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmcpxru.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmmachs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmmachu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqaddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqaddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqmachs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqmachu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqsubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqsubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmsubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmsubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/dcpl.cgs | 0 sim/testsuite/{sim => }/frv/fr550/dcul.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mabshs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/maddaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/maddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/maddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/masaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mdaddaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mdasaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mdsubaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mmachs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mmachu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mmrdhs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mmrdhu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqaddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqaddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqmachs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqmachu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqmacxhs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqsubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqsubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqxmachs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqxmacxhs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/msubaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/msubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/msubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mtrap.cgs | 0 sim/testsuite/{sim => }/frv/fr550/udiv.cgs | 0 sim/testsuite/{sim => }/frv/fr550/udivi.cgs | 0 sim/testsuite/{sim => }/frv/fsqrtd.cgs | 0 sim/testsuite/{sim => }/frv/fsqrts.cgs | 0 sim/testsuite/{sim => }/frv/fstoi.cgs | 0 sim/testsuite/{sim => }/frv/fsubd.cgs | 0 sim/testsuite/{sim => }/frv/fsubs.cgs | 0 sim/testsuite/{sim => }/frv/fteq.cgs | 0 sim/testsuite/{sim => }/frv/ftge.cgs | 0 sim/testsuite/{sim => }/frv/ftgt.cgs | 0 sim/testsuite/{sim => }/frv/ftieq.cgs | 0 sim/testsuite/{sim => }/frv/ftige.cgs | 0 sim/testsuite/{sim => }/frv/ftigt.cgs | 0 sim/testsuite/{sim => }/frv/ftile.cgs | 0 sim/testsuite/{sim => }/frv/ftilg.cgs | 0 sim/testsuite/{sim => }/frv/ftilt.cgs | 0 sim/testsuite/{sim => }/frv/ftine.cgs | 0 sim/testsuite/{sim => }/frv/ftino.cgs | 0 sim/testsuite/{sim => }/frv/ftio.cgs | 0 sim/testsuite/{sim => }/frv/ftira.cgs | 0 sim/testsuite/{sim => }/frv/ftiu.cgs | 0 sim/testsuite/{sim => }/frv/ftiue.cgs | 0 sim/testsuite/{sim => }/frv/ftiug.cgs | 0 sim/testsuite/{sim => }/frv/ftiuge.cgs | 0 sim/testsuite/{sim => }/frv/ftiul.cgs | 0 sim/testsuite/{sim => }/frv/ftle.cgs | 0 sim/testsuite/{sim => }/frv/ftlg.cgs | 0 sim/testsuite/{sim => }/frv/ftlt.cgs | 0 sim/testsuite/{sim => }/frv/ftne.cgs | 0 sim/testsuite/{sim => }/frv/ftno.cgs | 0 sim/testsuite/{sim => }/frv/fto.cgs | 0 sim/testsuite/{sim => }/frv/ftra.cgs | 0 sim/testsuite/{sim => }/frv/ftu.cgs | 0 sim/testsuite/{sim => }/frv/ftue.cgs | 0 sim/testsuite/{sim => }/frv/ftug.cgs | 0 sim/testsuite/{sim => }/frv/ftuge.cgs | 0 sim/testsuite/{sim => }/frv/ftul.cgs | 0 sim/testsuite/{sim => }/frv/ftule.cgs | 0 sim/testsuite/{sim => }/frv/grloop.ms | 0 sim/testsuite/{sim => }/frv/hello.ms | 0 sim/testsuite/{sim => }/frv/icei.cgs | 0 sim/testsuite/{sim => }/frv/ici.cgs | 0 sim/testsuite/{sim => }/frv/icpl.cgs | 0 sim/testsuite/{sim => }/frv/icul.cgs | 0 sim/testsuite/{sim => }/frv/interrupts.exp | 0 .../{sim => }/frv/interrupts/Ipipe-fr400.cgs | 0 .../{sim => }/frv/interrupts/Ipipe-fr500.cgs | 0 .../{sim => }/frv/interrupts/badalign-fr550.cgs | 0 .../{sim => }/frv/interrupts/badalign.cgs | 0 .../{sim => }/frv/interrupts/compound-fr550.cgs | 0 .../{sim => }/frv/interrupts/compound.cgs | 0 .../frv/interrupts/data_store_error-fr550.cgs | 0 .../{sim => }/frv/interrupts/data_store_error.cgs | 0 .../frv/interrupts/fp_exception-fr550.cgs | 0 .../{sim => }/frv/interrupts/fp_exception.cgs | 0 sim/testsuite/{sim => }/frv/interrupts/illinsn.cgs | 0 .../frv/interrupts/insn_access_error-fr550.cgs | 0 .../{sim => }/frv/interrupts/insn_access_error.cgs | 0 .../{sim => }/frv/interrupts/mp_exception.cgs | 0 .../frv/interrupts/privileged_instruction.cgs | 0 .../{sim => }/frv/interrupts/regalign.cgs | 0 sim/testsuite/{sim => }/frv/interrupts/reset.cgs | 0 .../{sim => }/frv/interrupts/shadow_regs.cgs | 0 sim/testsuite/{sim => }/frv/interrupts/timer.cgs | 0 sim/testsuite/{sim => }/frv/jmpil.cgs | 0 sim/testsuite/{sim => }/frv/jmpl.cgs | 0 sim/testsuite/{sim => }/frv/jmpl.pcgs | 0 sim/testsuite/{sim => }/frv/ld.cgs | 0 sim/testsuite/{sim => }/frv/ldbf.cgs | 0 sim/testsuite/{sim => }/frv/ldbfi.cgs | 0 sim/testsuite/{sim => }/frv/ldbfu.cgs | 0 sim/testsuite/{sim => }/frv/ldc.cgs | 0 sim/testsuite/{sim => }/frv/ldcu.cgs | 0 sim/testsuite/{sim => }/frv/ldd.cgs | 0 sim/testsuite/{sim => }/frv/lddc.cgs | 0 sim/testsuite/{sim => }/frv/lddcu.cgs | 0 sim/testsuite/{sim => }/frv/lddf.cgs | 0 sim/testsuite/{sim => }/frv/lddfi.cgs | 0 sim/testsuite/{sim => }/frv/lddfu.cgs | 0 sim/testsuite/{sim => }/frv/lddi.cgs | 0 sim/testsuite/{sim => }/frv/lddu.cgs | 0 sim/testsuite/{sim => }/frv/ldf.cgs | 0 sim/testsuite/{sim => }/frv/ldfi.cgs | 0 sim/testsuite/{sim => }/frv/ldfu.cgs | 0 sim/testsuite/{sim => }/frv/ldhf.cgs | 0 sim/testsuite/{sim => }/frv/ldhfi.cgs | 0 sim/testsuite/{sim => }/frv/ldhfu.cgs | 0 sim/testsuite/{sim => }/frv/ldi.cgs | 0 sim/testsuite/{sim => }/frv/ldq.cgs | 0 sim/testsuite/{sim => }/frv/ldqc.cgs | 0 sim/testsuite/{sim => }/frv/ldqcu.cgs | 0 sim/testsuite/{sim => }/frv/ldqf.cgs | 0 sim/testsuite/{sim => }/frv/ldqfi.cgs | 0 sim/testsuite/{sim => }/frv/ldqfu.cgs | 0 sim/testsuite/{sim => }/frv/ldqi.cgs | 0 sim/testsuite/{sim => }/frv/ldqu.cgs | 0 sim/testsuite/{sim => }/frv/ldsb.cgs | 0 sim/testsuite/{sim => }/frv/ldsbi.cgs | 0 sim/testsuite/{sim => }/frv/ldsbu.cgs | 0 sim/testsuite/{sim => }/frv/ldsh.cgs | 0 sim/testsuite/{sim => }/frv/ldshi.cgs | 0 sim/testsuite/{sim => }/frv/ldshu.cgs | 0 sim/testsuite/{sim => }/frv/ldu.cgs | 0 sim/testsuite/{sim => }/frv/ldub.cgs | 0 sim/testsuite/{sim => }/frv/ldubi.cgs | 0 sim/testsuite/{sim => }/frv/ldubu.cgs | 0 sim/testsuite/{sim => }/frv/lduh.cgs | 0 sim/testsuite/{sim => }/frv/lduhi.cgs | 0 sim/testsuite/{sim => }/frv/lduhu.cgs | 0 sim/testsuite/{sim => }/frv/lrbranch.pcgs | 0 sim/testsuite/{sim => }/frv/mabshs.cgs | 0 sim/testsuite/{sim => }/frv/maddhss.cgs | 0 sim/testsuite/{sim => }/frv/maddhus.cgs | 0 sim/testsuite/{sim => }/frv/mand.cgs | 0 sim/testsuite/{sim => }/frv/maveh.cgs | 0 sim/testsuite/{sim => }/frv/mbtoh.cgs | 0 sim/testsuite/{sim => }/frv/mbtohe.cgs | 0 sim/testsuite/{sim => }/frv/mclracc.cgs | 0 sim/testsuite/{sim => }/frv/mcmpsh.cgs | 0 sim/testsuite/{sim => }/frv/mcmpuh.cgs | 0 sim/testsuite/{sim => }/frv/mcop1.cgs | 0 sim/testsuite/{sim => }/frv/mcop2.cgs | 0 sim/testsuite/{sim => }/frv/mcplhi.cgs | 0 sim/testsuite/{sim => }/frv/mcpli.cgs | 0 sim/testsuite/{sim => }/frv/mcpxis.cgs | 0 sim/testsuite/{sim => }/frv/mcpxiu.cgs | 0 sim/testsuite/{sim => }/frv/mcpxrs.cgs | 0 sim/testsuite/{sim => }/frv/mcpxru.cgs | 0 sim/testsuite/{sim => }/frv/mcut.cgs | 0 sim/testsuite/{sim => }/frv/mcuti.cgs | 0 sim/testsuite/{sim => }/frv/mcutss.cgs | 0 sim/testsuite/{sim => }/frv/mcutssi.cgs | 0 sim/testsuite/{sim => }/frv/mdaddaccs.cgs | 0 sim/testsuite/{sim => }/frv/mdasaccs.cgs | 0 sim/testsuite/{sim => }/frv/mdcutssi.cgs | 0 sim/testsuite/{sim => }/frv/mdpackh.cgs | 0 sim/testsuite/{sim => }/frv/mdrotli.cgs | 0 sim/testsuite/{sim => }/frv/mdsubaccs.cgs | 0 sim/testsuite/{sim => }/frv/mdunpackh.cgs | 0 sim/testsuite/{sim => }/frv/membar.cgs | 0 sim/testsuite/{sim => }/frv/mexpdhd.cgs | 0 sim/testsuite/{sim => }/frv/mexpdhw.cgs | 0 sim/testsuite/{sim => }/frv/mhdseth.cgs | 0 sim/testsuite/{sim => }/frv/mhdsets.cgs | 0 sim/testsuite/{sim => }/frv/mhsethih.cgs | 0 sim/testsuite/{sim => }/frv/mhsethis.cgs | 0 sim/testsuite/{sim => }/frv/mhsetloh.cgs | 0 sim/testsuite/{sim => }/frv/mhsetlos.cgs | 0 sim/testsuite/{sim => }/frv/mhtob.cgs | 0 sim/testsuite/{sim => }/frv/misc.exp | 0 sim/testsuite/{sim => }/frv/mmachs.cgs | 0 sim/testsuite/{sim => }/frv/mmachu.cgs | 0 sim/testsuite/{sim => }/frv/mmrdhs.cgs | 0 sim/testsuite/{sim => }/frv/mmrdhu.cgs | 0 sim/testsuite/{sim => }/frv/mmulhs.cgs | 0 sim/testsuite/{sim => }/frv/mmulhu.cgs | 0 sim/testsuite/{sim => }/frv/mmulxhs.cgs | 0 sim/testsuite/{sim => }/frv/mmulxhu.cgs | 0 sim/testsuite/{sim => }/frv/mnop.cgs | 0 sim/testsuite/{sim => }/frv/mnot.cgs | 0 sim/testsuite/{sim => }/frv/mor.cgs | 0 sim/testsuite/{sim => }/frv/mov.cgs | 0 sim/testsuite/{sim => }/frv/movfg.cgs | 0 sim/testsuite/{sim => }/frv/movfgd.cgs | 0 sim/testsuite/{sim => }/frv/movfgq.cgs | 0 sim/testsuite/{sim => }/frv/movgf.cgs | 0 sim/testsuite/{sim => }/frv/movgfd.cgs | 0 sim/testsuite/{sim => }/frv/movgfq.cgs | 0 sim/testsuite/{sim => }/frv/movgs.cgs | 0 sim/testsuite/{sim => }/frv/movsg.cgs | 0 sim/testsuite/{sim => }/frv/mpackh.cgs | 0 sim/testsuite/{sim => }/frv/mqcpxis.cgs | 0 sim/testsuite/{sim => }/frv/mqcpxiu.cgs | 0 sim/testsuite/{sim => }/frv/mqcpxrs.cgs | 0 sim/testsuite/{sim => }/frv/mqcpxru.cgs | 0 sim/testsuite/{sim => }/frv/mqlclrhs.cgs | 0 sim/testsuite/{sim => }/frv/mqlmths.cgs | 0 sim/testsuite/{sim => }/frv/mqmachs.cgs | 0 sim/testsuite/{sim => }/frv/mqmachu.cgs | 0 sim/testsuite/{sim => }/frv/mqmacxhs.cgs | 0 sim/testsuite/{sim => }/frv/mqmulhs.cgs | 0 sim/testsuite/{sim => }/frv/mqmulhu.cgs | 0 sim/testsuite/{sim => }/frv/mqmulxhs.cgs | 0 sim/testsuite/{sim => }/frv/mqmulxhu.cgs | 0 sim/testsuite/{sim => }/frv/mqsaths.cgs | 0 sim/testsuite/{sim => }/frv/mqsllhi.cgs | 0 sim/testsuite/{sim => }/frv/mqsrahi.cgs | 0 sim/testsuite/{sim => }/frv/mqxmachs.cgs | 0 sim/testsuite/{sim => }/frv/mqxmacxhs.cgs | 0 sim/testsuite/{sim => }/frv/mrdacc.cgs | 0 sim/testsuite/{sim => }/frv/mrdaccg.cgs | 0 sim/testsuite/{sim => }/frv/mrotli.cgs | 0 sim/testsuite/{sim => }/frv/mrotri.cgs | 0 sim/testsuite/{sim => }/frv/msaths.cgs | 0 sim/testsuite/{sim => }/frv/msathu.cgs | 0 sim/testsuite/{sim => }/frv/msllhi.cgs | 0 sim/testsuite/{sim => }/frv/msrahi.cgs | 0 sim/testsuite/{sim => }/frv/msrlhi.cgs | 0 sim/testsuite/{sim => }/frv/msubhss.cgs | 0 sim/testsuite/{sim => }/frv/msubhus.cgs | 0 sim/testsuite/{sim => }/frv/mtrap.cgs | 0 sim/testsuite/{sim => }/frv/munpackh.cgs | 0 sim/testsuite/{sim => }/frv/mwcut.cgs | 0 sim/testsuite/{sim => }/frv/mwcuti.cgs | 0 sim/testsuite/{sim => }/frv/mwtacc.cgs | 0 sim/testsuite/{sim => }/frv/mwtaccg.cgs | 0 sim/testsuite/{sim => }/frv/mxor.cgs | 0 sim/testsuite/{sim => }/frv/nandcr.cgs | 0 sim/testsuite/{sim => }/frv/nandncr.cgs | 0 sim/testsuite/{sim => }/frv/nfadds.cgs | 0 sim/testsuite/{sim => }/frv/nfdadds.cgs | 0 sim/testsuite/{sim => }/frv/nfdcmps.cgs | 0 sim/testsuite/{sim => }/frv/nfddivs.cgs | 0 sim/testsuite/{sim => }/frv/nfditos.cgs | 0 sim/testsuite/{sim => }/frv/nfdivs.cgs | 0 sim/testsuite/{sim => }/frv/nfdmadds.cgs | 0 sim/testsuite/{sim => }/frv/nfdmas.cgs | 0 sim/testsuite/{sim => }/frv/nfdmss.cgs | 0 sim/testsuite/{sim => }/frv/nfdmulcs.cgs | 0 sim/testsuite/{sim => }/frv/nfdmuls.cgs | 0 sim/testsuite/{sim => }/frv/nfdsads.cgs | 0 sim/testsuite/{sim => }/frv/nfdsqrts.cgs | 0 sim/testsuite/{sim => }/frv/nfdstoi.cgs | 0 sim/testsuite/{sim => }/frv/nfdsubs.cgs | 0 sim/testsuite/{sim => }/frv/nfitos.cgs | 0 sim/testsuite/{sim => }/frv/nfmadds.cgs | 0 sim/testsuite/{sim => }/frv/nfmas.cgs | 0 sim/testsuite/{sim => }/frv/nfmss.cgs | 0 sim/testsuite/{sim => }/frv/nfmsubs.cgs | 0 sim/testsuite/{sim => }/frv/nfmuls.cgs | 0 sim/testsuite/{sim => }/frv/nfsqrts.cgs | 0 sim/testsuite/{sim => }/frv/nfstoi.cgs | 0 sim/testsuite/{sim => }/frv/nfsubs.cgs | 0 sim/testsuite/{sim => }/frv/nld.cgs | 0 sim/testsuite/{sim => }/frv/nldbf.cgs | 0 sim/testsuite/{sim => }/frv/nldbfi.cgs | 0 sim/testsuite/{sim => }/frv/nldbfu.cgs | 0 sim/testsuite/{sim => }/frv/nldd.cgs | 0 sim/testsuite/{sim => }/frv/nlddf.cgs | 0 sim/testsuite/{sim => }/frv/nlddfi.cgs | 0 sim/testsuite/{sim => }/frv/nlddfu.cgs | 0 sim/testsuite/{sim => }/frv/nlddi.cgs | 0 sim/testsuite/{sim => }/frv/nlddu.cgs | 0 sim/testsuite/{sim => }/frv/nldf.cgs | 0 sim/testsuite/{sim => }/frv/nldfi.cgs | 0 sim/testsuite/{sim => }/frv/nldfu.cgs | 0 sim/testsuite/{sim => }/frv/nldhf.cgs | 0 sim/testsuite/{sim => }/frv/nldhfi.cgs | 0 sim/testsuite/{sim => }/frv/nldhfu.cgs | 0 sim/testsuite/{sim => }/frv/nldi.cgs | 0 sim/testsuite/{sim => }/frv/nldq.cgs | 0 sim/testsuite/{sim => }/frv/nldqf.cgs | 0 sim/testsuite/{sim => }/frv/nldqfi.cgs | 0 sim/testsuite/{sim => }/frv/nldqfu.cgs | 0 sim/testsuite/{sim => }/frv/nldqu.cgs | 0 sim/testsuite/{sim => }/frv/nldsb.cgs | 0 sim/testsuite/{sim => }/frv/nldsbi.cgs | 0 sim/testsuite/{sim => }/frv/nldsbu.cgs | 0 sim/testsuite/{sim => }/frv/nldsh.cgs | 0 sim/testsuite/{sim => }/frv/nldshi.cgs | 0 sim/testsuite/{sim => }/frv/nldshu.cgs | 0 sim/testsuite/{sim => }/frv/nldu.cgs | 0 sim/testsuite/{sim => }/frv/nldub.cgs | 0 sim/testsuite/{sim => }/frv/nldubi.cgs | 0 sim/testsuite/{sim => }/frv/nldubu.cgs | 0 sim/testsuite/{sim => }/frv/nlduh.cgs | 0 sim/testsuite/{sim => }/frv/nlduhi.cgs | 0 sim/testsuite/{sim => }/frv/nlduhu.cgs | 0 sim/testsuite/{sim => }/frv/nop.cgs | 0 sim/testsuite/{sim => }/frv/norcr.cgs | 0 sim/testsuite/{sim => }/frv/norncr.cgs | 0 sim/testsuite/{sim => }/frv/not.cgs | 0 sim/testsuite/{sim => }/frv/notcr.cgs | 0 sim/testsuite/{sim => }/frv/nsdiv.cgs | 0 sim/testsuite/{sim => }/frv/nsdivi.cgs | 0 sim/testsuite/{sim => }/frv/nudiv.cgs | 0 sim/testsuite/{sim => }/frv/nudivi.cgs | 0 sim/testsuite/{sim => }/frv/or.cgs | 0 sim/testsuite/{sim => }/frv/orcc.cgs | 0 sim/testsuite/{sim => }/frv/orcr.cgs | 0 sim/testsuite/{sim => }/frv/ori.cgs | 0 sim/testsuite/{sim => }/frv/oricc.cgs | 0 sim/testsuite/{sim => }/frv/orncr.cgs | 0 sim/testsuite/{sim => }/frv/parallel.exp | 0 sim/testsuite/{sim => }/frv/ret.cgs | 0 sim/testsuite/{sim => }/frv/rett.cgs | 0 sim/testsuite/{sim => }/frv/scan.cgs | 0 sim/testsuite/{sim => }/frv/scani.cgs | 0 sim/testsuite/{sim => }/frv/sdiv.cgs | 0 sim/testsuite/{sim => }/frv/sdivi.cgs | 0 sim/testsuite/{sim => }/frv/sethi.cgs | 0 sim/testsuite/{sim => }/frv/sethilo.pcgs | 0 sim/testsuite/{sim => }/frv/setlo.cgs | 0 sim/testsuite/{sim => }/frv/setlos.cgs | 0 sim/testsuite/{sim => }/frv/sll.cgs | 0 sim/testsuite/{sim => }/frv/sllcc.cgs | 0 sim/testsuite/{sim => }/frv/slli.cgs | 0 sim/testsuite/{sim => }/frv/sllicc.cgs | 0 sim/testsuite/{sim => }/frv/smul.cgs | 0 sim/testsuite/{sim => }/frv/smulcc.cgs | 0 sim/testsuite/{sim => }/frv/smuli.cgs | 0 sim/testsuite/{sim => }/frv/smulicc.cgs | 0 sim/testsuite/{sim => }/frv/sra.cgs | 0 sim/testsuite/{sim => }/frv/sracc.cgs | 0 sim/testsuite/{sim => }/frv/srai.cgs | 0 sim/testsuite/{sim => }/frv/sraicc.cgs | 0 sim/testsuite/{sim => }/frv/srl.cgs | 0 sim/testsuite/{sim => }/frv/srlcc.cgs | 0 sim/testsuite/{sim => }/frv/srli.cgs | 0 sim/testsuite/{sim => }/frv/srlicc.cgs | 0 sim/testsuite/{sim => }/frv/st.cgs | 0 sim/testsuite/{sim => }/frv/stb.cgs | 0 sim/testsuite/{sim => }/frv/stbf.cgs | 0 sim/testsuite/{sim => }/frv/stbfi.cgs | 0 sim/testsuite/{sim => }/frv/stbfu.cgs | 0 sim/testsuite/{sim => }/frv/stbi.cgs | 0 sim/testsuite/{sim => }/frv/stbu.cgs | 0 sim/testsuite/{sim => }/frv/stc.cgs | 0 sim/testsuite/{sim => }/frv/stcu.cgs | 0 sim/testsuite/{sim => }/frv/std.cgs | 0 sim/testsuite/{sim => }/frv/std.pcgs | 0 sim/testsuite/{sim => }/frv/stdc.cgs | 0 sim/testsuite/{sim => }/frv/stdc.pcgs | 0 sim/testsuite/{sim => }/frv/stdcu.cgs | 0 sim/testsuite/{sim => }/frv/stdf.cgs | 0 sim/testsuite/{sim => }/frv/stdf.pcgs | 0 sim/testsuite/{sim => }/frv/stdfi.cgs | 0 sim/testsuite/{sim => }/frv/stdfu.cgs | 0 sim/testsuite/{sim => }/frv/stdi.cgs | 0 sim/testsuite/{sim => }/frv/stdu.cgs | 0 sim/testsuite/{sim => }/frv/stf.cgs | 0 sim/testsuite/{sim => }/frv/stfi.cgs | 0 sim/testsuite/{sim => }/frv/stfu.cgs | 0 sim/testsuite/{sim => }/frv/sth.cgs | 0 sim/testsuite/{sim => }/frv/sthf.cgs | 0 sim/testsuite/{sim => }/frv/sthfi.cgs | 0 sim/testsuite/{sim => }/frv/sthfu.cgs | 0 sim/testsuite/{sim => }/frv/sthi.cgs | 0 sim/testsuite/{sim => }/frv/sthu.cgs | 0 sim/testsuite/{sim => }/frv/sti.cgs | 0 sim/testsuite/{sim => }/frv/stq.cgs | 0 sim/testsuite/{sim => }/frv/stq.pcgs | 0 sim/testsuite/{sim => }/frv/stqc.cgs | 0 sim/testsuite/{sim => }/frv/stqc.pcgs | 0 sim/testsuite/{sim => }/frv/stqcu.cgs | 0 sim/testsuite/{sim => }/frv/stqf.cgs | 0 sim/testsuite/{sim => }/frv/stqf.pcgs | 0 sim/testsuite/{sim => }/frv/stqfi.cgs | 0 sim/testsuite/{sim => }/frv/stqfu.cgs | 0 sim/testsuite/{sim => }/frv/stqi.cgs | 0 sim/testsuite/{sim => }/frv/stqu.cgs | 0 sim/testsuite/{sim => }/frv/stu.cgs | 0 sim/testsuite/{sim => }/frv/sub.cgs | 0 sim/testsuite/{sim => }/frv/subcc.cgs | 0 sim/testsuite/{sim => }/frv/subi.cgs | 0 sim/testsuite/{sim => }/frv/subicc.cgs | 0 sim/testsuite/{sim => }/frv/subx.cgs | 0 sim/testsuite/{sim => }/frv/subxcc.cgs | 0 sim/testsuite/{sim => }/frv/subxi.cgs | 0 sim/testsuite/{sim => }/frv/subxicc.cgs | 0 sim/testsuite/{sim => }/frv/swap.cgs | 0 sim/testsuite/{sim => }/frv/swapi.cgs | 0 sim/testsuite/{sim => }/frv/tc.cgs | 0 sim/testsuite/{sim => }/frv/teq.cgs | 0 sim/testsuite/{sim => }/frv/testutils.inc | 0 sim/testsuite/{sim => }/frv/tge.cgs | 0 sim/testsuite/{sim => }/frv/tgt.cgs | 0 sim/testsuite/{sim => }/frv/thi.cgs | 0 sim/testsuite/{sim => }/frv/tic.cgs | 0 sim/testsuite/{sim => }/frv/tieq.cgs | 0 sim/testsuite/{sim => }/frv/tige.cgs | 0 sim/testsuite/{sim => }/frv/tigt.cgs | 0 sim/testsuite/{sim => }/frv/tihi.cgs | 0 sim/testsuite/{sim => }/frv/tile.cgs | 0 sim/testsuite/{sim => }/frv/tils.cgs | 0 sim/testsuite/{sim => }/frv/tilt.cgs | 0 sim/testsuite/{sim => }/frv/tin.cgs | 0 sim/testsuite/{sim => }/frv/tinc.cgs | 0 sim/testsuite/{sim => }/frv/tine.cgs | 0 sim/testsuite/{sim => }/frv/tino.cgs | 0 sim/testsuite/{sim => }/frv/tinv.cgs | 0 sim/testsuite/{sim => }/frv/tip.cgs | 0 sim/testsuite/{sim => }/frv/tira.cgs | 0 sim/testsuite/{sim => }/frv/tiv.cgs | 0 sim/testsuite/{sim => }/frv/tle.cgs | 0 sim/testsuite/{sim => }/frv/tls.cgs | 0 sim/testsuite/{sim => }/frv/tlt.cgs | 0 sim/testsuite/{sim => }/frv/tn.cgs | 0 sim/testsuite/{sim => }/frv/tnc.cgs | 0 sim/testsuite/{sim => }/frv/tne.cgs | 0 sim/testsuite/{sim => }/frv/tno.cgs | 0 sim/testsuite/{sim => }/frv/tnv.cgs | 0 sim/testsuite/{sim => }/frv/tp.cgs | 0 sim/testsuite/{sim => }/frv/tra.cgs | 0 sim/testsuite/{sim => }/frv/tv.cgs | 0 sim/testsuite/{sim => }/frv/udiv.cgs | 0 sim/testsuite/{sim => }/frv/udivi.cgs | 0 sim/testsuite/{sim => }/frv/umul.cgs | 0 sim/testsuite/{sim => }/frv/umulcc.cgs | 0 sim/testsuite/{sim => }/frv/umuli.cgs | 0 sim/testsuite/{sim => }/frv/umulicc.cgs | 0 sim/testsuite/{sim => }/frv/xor.cgs | 0 sim/testsuite/{sim => }/frv/xorcc.cgs | 0 sim/testsuite/{sim => }/frv/xorcr.cgs | 0 sim/testsuite/{sim => }/frv/xori.cgs | 0 sim/testsuite/{sim => }/frv/xoricc.cgs | 0 sim/testsuite/{sim => }/ft32/ChangeLog | 0 sim/testsuite/{sim => }/ft32/allinsn.exp | 0 sim/testsuite/{sim => }/ft32/basic.s | 0 sim/testsuite/{sim => }/ft32/testutils.inc | 0 sim/testsuite/{sim => }/h8300/ChangeLog | 0 sim/testsuite/{sim => }/h8300/addb.s | 0 sim/testsuite/{sim => }/h8300/addl.s | 0 sim/testsuite/{sim => }/h8300/adds.s | 0 sim/testsuite/{sim => }/h8300/addw.s | 0 sim/testsuite/{sim => }/h8300/addx.s | 0 sim/testsuite/{sim => }/h8300/allinsn.exp | 0 sim/testsuite/{sim => }/h8300/andb.s | 0 sim/testsuite/{sim => }/h8300/andl.s | 0 sim/testsuite/{sim => }/h8300/andw.s | 0 sim/testsuite/{sim => }/h8300/band.s | 0 sim/testsuite/{sim => }/h8300/bfld.s | 0 sim/testsuite/{sim => }/h8300/biand.s | 0 sim/testsuite/{sim => }/h8300/bra.s | 0 sim/testsuite/{sim => }/h8300/brabc.s | 0 sim/testsuite/{sim => }/h8300/bset.s | 0 sim/testsuite/{sim => }/h8300/cmpb.s | 0 sim/testsuite/{sim => }/h8300/cmpl.s | 0 sim/testsuite/{sim => }/h8300/cmpw.s | 0 sim/testsuite/{sim => }/h8300/daa.s | 0 sim/testsuite/{sim => }/h8300/das.s | 0 sim/testsuite/{sim => }/h8300/dec.s | 0 sim/testsuite/{sim => }/h8300/div.s | 0 sim/testsuite/{sim => }/h8300/extl.s | 0 sim/testsuite/{sim => }/h8300/extw.s | 0 sim/testsuite/{sim => }/h8300/inc.s | 0 sim/testsuite/{sim => }/h8300/jmp.s | 0 sim/testsuite/{sim => }/h8300/ldc.s | 0 sim/testsuite/{sim => }/h8300/ldm.s | 0 sim/testsuite/{sim => }/h8300/mac.s | 0 sim/testsuite/{sim => }/h8300/mova.s | 0 sim/testsuite/{sim => }/h8300/movb.s | 0 sim/testsuite/{sim => }/h8300/movl.s | 0 sim/testsuite/{sim => }/h8300/movmd.s | 0 sim/testsuite/{sim => }/h8300/movsd.s | 0 sim/testsuite/{sim => }/h8300/movw.s | 0 sim/testsuite/{sim => }/h8300/mul.s | 0 sim/testsuite/{sim => }/h8300/neg.s | 0 sim/testsuite/{sim => }/h8300/nop.s | 0 sim/testsuite/{sim => }/h8300/not.s | 0 sim/testsuite/{sim => }/h8300/orb.s | 0 sim/testsuite/{sim => }/h8300/orl.s | 0 sim/testsuite/{sim => }/h8300/orw.s | 0 sim/testsuite/{sim => }/h8300/rotl.s | 0 sim/testsuite/{sim => }/h8300/rotr.s | 0 sim/testsuite/{sim => }/h8300/rotxl.s | 0 sim/testsuite/{sim => }/h8300/rotxr.s | 0 sim/testsuite/{sim => }/h8300/shal.s | 0 sim/testsuite/{sim => }/h8300/shar.s | 0 sim/testsuite/{sim => }/h8300/shll.s | 0 sim/testsuite/{sim => }/h8300/shlr.s | 0 sim/testsuite/{sim => }/h8300/stack.s | 0 sim/testsuite/{sim => }/h8300/stc.s | 0 sim/testsuite/{sim => }/h8300/subb.s | 0 sim/testsuite/{sim => }/h8300/subl.s | 0 sim/testsuite/{sim => }/h8300/subs.s | 0 sim/testsuite/{sim => }/h8300/subw.s | 0 sim/testsuite/{sim => }/h8300/subx.s | 0 sim/testsuite/{sim => }/h8300/tas.s | 0 sim/testsuite/{sim => }/h8300/testutils.inc | 0 sim/testsuite/{sim => }/h8300/xorb.s | 0 sim/testsuite/{sim => }/h8300/xorl.s | 0 sim/testsuite/{sim => }/h8300/xorw.s | 0 sim/testsuite/{sim => }/iq2000/ChangeLog | 0 sim/testsuite/{sim => }/iq2000/allinsn.exp | 0 sim/testsuite/{sim => }/iq2000/pass.s | 0 sim/testsuite/{sim => }/iq2000/testutils.inc | 0 sim/testsuite/{sim => }/lm32/ChangeLog | 0 sim/testsuite/{sim => }/lm32/allinsn.exp | 0 sim/testsuite/{sim => }/lm32/pass.s | 0 sim/testsuite/{sim => }/lm32/testutils.inc | 0 sim/testsuite/{sim => }/m32c/ChangeLog | 0 sim/testsuite/{sim => }/m32c/allinsn.exp | 0 sim/testsuite/{sim => }/m32c/blinky.s | 0 sim/testsuite/{sim => }/m32c/fail.s | 0 sim/testsuite/{sim => }/m32c/gloss.s | 0 sim/testsuite/{sim => }/m32c/pass.s | 0 sim/testsuite/{sim => }/m32c/sample.ld | 0 sim/testsuite/{sim => }/m32c/sample.s | 0 sim/testsuite/{sim => }/m32c/sample2.c | 0 sim/testsuite/{sim => }/m32c/testutils.inc | 0 sim/testsuite/{sim => }/m32r/ChangeLog | 0 sim/testsuite/{sim => }/m32r/add.cgs | 0 sim/testsuite/{sim => }/m32r/add3.cgs | 0 sim/testsuite/{sim => }/m32r/addi.cgs | 0 sim/testsuite/{sim => }/m32r/addv.cgs | 0 sim/testsuite/{sim => }/m32r/addv3.cgs | 0 sim/testsuite/{sim => }/m32r/addx.cgs | 0 sim/testsuite/{sim => }/m32r/allinsn.exp | 0 sim/testsuite/{sim => }/m32r/and.cgs | 0 sim/testsuite/{sim => }/m32r/and3.cgs | 0 sim/testsuite/{sim => }/m32r/bc24.cgs | 0 sim/testsuite/{sim => }/m32r/bc8.cgs | 0 sim/testsuite/{sim => }/m32r/beq.cgs | 0 sim/testsuite/{sim => }/m32r/beqz.cgs | 0 sim/testsuite/{sim => }/m32r/bgez.cgs | 0 sim/testsuite/{sim => }/m32r/bgtz.cgs | 0 sim/testsuite/{sim => }/m32r/bl24.cgs | 0 sim/testsuite/{sim => }/m32r/bl8.cgs | 0 sim/testsuite/{sim => }/m32r/blez.cgs | 0 sim/testsuite/{sim => }/m32r/bltz.cgs | 0 sim/testsuite/{sim => }/m32r/bnc24.cgs | 0 sim/testsuite/{sim => }/m32r/bnc8.cgs | 0 sim/testsuite/{sim => }/m32r/bne.cgs | 0 sim/testsuite/{sim => }/m32r/bnez.cgs | 0 sim/testsuite/{sim => }/m32r/bra24.cgs | 0 sim/testsuite/{sim => }/m32r/bra8.cgs | 0 sim/testsuite/{sim => }/m32r/cmp.cgs | 0 sim/testsuite/{sim => }/m32r/cmpi.cgs | 0 sim/testsuite/{sim => }/m32r/cmpu.cgs | 0 sim/testsuite/{sim => }/m32r/cmpui.cgs | 0 sim/testsuite/{sim => }/m32r/div.cgs | 0 sim/testsuite/{sim => }/m32r/divu.cgs | 0 sim/testsuite/{sim => }/m32r/exit47.ms | 0 sim/testsuite/{sim => }/m32r/hello.ms | 0 sim/testsuite/{sim => }/m32r/hw-trap.ms | 0 sim/testsuite/{sim => }/m32r/jl.cgs | 0 sim/testsuite/{sim => }/m32r/jmp.cgs | 0 sim/testsuite/{sim => }/m32r/ld-d.cgs | 0 sim/testsuite/{sim => }/m32r/ld-plus.cgs | 0 sim/testsuite/{sim => }/m32r/ld.cgs | 0 sim/testsuite/{sim => }/m32r/ld24.cgs | 0 sim/testsuite/{sim => }/m32r/ldb-d.cgs | 0 sim/testsuite/{sim => }/m32r/ldb.cgs | 0 sim/testsuite/{sim => }/m32r/ldh-d.cgs | 0 sim/testsuite/{sim => }/m32r/ldh.cgs | 0 sim/testsuite/{sim => }/m32r/ldi16.cgs | 0 sim/testsuite/{sim => }/m32r/ldi8.cgs | 0 sim/testsuite/{sim => }/m32r/ldub-d.cgs | 0 sim/testsuite/{sim => }/m32r/ldub.cgs | 0 sim/testsuite/{sim => }/m32r/lduh-d.cgs | 0 sim/testsuite/{sim => }/m32r/lduh.cgs | 0 sim/testsuite/{sim => }/m32r/lock.cgs | 0 sim/testsuite/{sim => }/m32r/machi.cgs | 0 sim/testsuite/{sim => }/m32r/maclo.cgs | 0 sim/testsuite/{sim => }/m32r/macwhi.cgs | 0 sim/testsuite/{sim => }/m32r/macwlo.cgs | 0 sim/testsuite/{sim => }/m32r/misc.exp | 0 sim/testsuite/{sim => }/m32r/mul.cgs | 0 sim/testsuite/{sim => }/m32r/mulhi.cgs | 0 sim/testsuite/{sim => }/m32r/mullo.cgs | 0 sim/testsuite/{sim => }/m32r/mulwhi.cgs | 0 sim/testsuite/{sim => }/m32r/mulwlo.cgs | 0 sim/testsuite/{sim => }/m32r/mv.cgs | 0 sim/testsuite/{sim => }/m32r/mvfachi.cgs | 0 sim/testsuite/{sim => }/m32r/mvfaclo.cgs | 0 sim/testsuite/{sim => }/m32r/mvfacmi.cgs | 0 sim/testsuite/{sim => }/m32r/mvfc.cgs | 0 sim/testsuite/{sim => }/m32r/mvtachi.cgs | 0 sim/testsuite/{sim => }/m32r/mvtaclo.cgs | 0 sim/testsuite/{sim => }/m32r/mvtc.cgs | 0 sim/testsuite/{sim => }/m32r/neg.cgs | 0 sim/testsuite/{sim => }/m32r/nop.cgs | 0 sim/testsuite/{sim => }/m32r/not.cgs | 0 sim/testsuite/{sim => }/m32r/or.cgs | 0 sim/testsuite/{sim => }/m32r/or3.cgs | 0 sim/testsuite/{sim => }/m32r/rac.cgs | 0 sim/testsuite/{sim => }/m32r/rach.cgs | 0 sim/testsuite/{sim => }/m32r/rem.cgs | 0 sim/testsuite/{sim => }/m32r/remu.cgs | 0 sim/testsuite/{sim => }/m32r/rte.cgs | 0 sim/testsuite/{sim => }/m32r/seth.cgs | 0 sim/testsuite/{sim => }/m32r/sll.cgs | 0 sim/testsuite/{sim => }/m32r/sll3.cgs | 0 sim/testsuite/{sim => }/m32r/slli.cgs | 0 sim/testsuite/{sim => }/m32r/sra.cgs | 0 sim/testsuite/{sim => }/m32r/sra3.cgs | 0 sim/testsuite/{sim => }/m32r/srai.cgs | 0 sim/testsuite/{sim => }/m32r/srl.cgs | 0 sim/testsuite/{sim => }/m32r/srl3.cgs | 0 sim/testsuite/{sim => }/m32r/srli.cgs | 0 sim/testsuite/{sim => }/m32r/st-d.cgs | 0 sim/testsuite/{sim => }/m32r/st-minus.cgs | 0 sim/testsuite/{sim => }/m32r/st-plus.cgs | 0 sim/testsuite/{sim => }/m32r/st.cgs | 0 sim/testsuite/{sim => }/m32r/stb-d.cgs | 0 sim/testsuite/{sim => }/m32r/stb.cgs | 0 sim/testsuite/{sim => }/m32r/sth-d.cgs | 0 sim/testsuite/{sim => }/m32r/sth.cgs | 0 sim/testsuite/{sim => }/m32r/sub.cgs | 0 sim/testsuite/{sim => }/m32r/subv.cgs | 0 sim/testsuite/{sim => }/m32r/subx.cgs | 0 sim/testsuite/{sim => }/m32r/testutils.inc | 0 sim/testsuite/{sim => }/m32r/trap.cgs | 0 sim/testsuite/{sim => }/m32r/unlock.cgs | 0 sim/testsuite/{sim => }/m32r/uread16.ms | 0 sim/testsuite/{sim => }/m32r/uread32.ms | 0 sim/testsuite/{sim => }/m32r/uwrite16.ms | 0 sim/testsuite/{sim => }/m32r/uwrite32.ms | 0 sim/testsuite/{sim => }/m32r/xor.cgs | 0 sim/testsuite/{sim => }/m32r/xor3.cgs | 0 sim/testsuite/{sim => }/m68hc11/ChangeLog | 0 sim/testsuite/{sim => }/m68hc11/allinsn.exp | 0 sim/testsuite/{sim => }/m68hc11/pass.s | 0 sim/testsuite/{sim => }/m68hc11/testutils.inc | 0 sim/testsuite/{sim => }/mcore/ChangeLog | 0 sim/testsuite/{sim => }/mcore/allinsn.exp | 0 sim/testsuite/{sim => }/mcore/fail.s | 0 sim/testsuite/{sim => }/mcore/pass.s | 0 sim/testsuite/{sim => }/mcore/testutils.inc | 0 sim/testsuite/{sim => }/microblaze/ChangeLog | 0 sim/testsuite/{sim => }/microblaze/allinsn.exp | 0 sim/testsuite/{sim => }/microblaze/pass.s | 0 sim/testsuite/{sim => }/microblaze/testutils.inc | 0 sim/testsuite/{sim => }/mips/ChangeLog | 0 sim/testsuite/{sim => }/mips/basic.exp | 0 sim/testsuite/{sim => }/mips/fpu64-ps-sb1.s | 0 sim/testsuite/{sim => }/mips/fpu64-ps.s | 0 sim/testsuite/{sim => }/mips/hilo-hazard-1.s | 0 sim/testsuite/{sim => }/mips/hilo-hazard-2.s | 0 sim/testsuite/{sim => }/mips/hilo-hazard-3.s | 0 sim/testsuite/{sim => }/mips/hilo-hazard-4.s | 0 sim/testsuite/{sim => }/mips/mdmx-ob-sb1.s | 0 sim/testsuite/{sim => }/mips/mdmx-ob.s | 0 sim/testsuite/{sim => }/mips/mips32-dsp.s | 0 sim/testsuite/{sim => }/mips/mips32-dsp2.s | 0 sim/testsuite/{sim => }/mips/sanity.s | 0 sim/testsuite/{sim => }/mips/testutils.inc | 0 sim/testsuite/{sim => }/mips/utils-dsp.inc | 0 sim/testsuite/{sim => }/mips/utils-fpu.inc | 0 sim/testsuite/{sim => }/mips/utils-mdmx.inc | 0 sim/testsuite/{sim => }/mn10300/ChangeLog | 0 sim/testsuite/{sim => }/mn10300/allinsn.exp | 0 sim/testsuite/{sim => }/mn10300/pass.s | 0 sim/testsuite/{sim => }/mn10300/testutils.inc | 0 sim/testsuite/{sim => }/moxie/ChangeLog | 0 sim/testsuite/{sim => }/moxie/allinsn.exp | 0 sim/testsuite/{sim => }/moxie/pass.s | 0 sim/testsuite/{sim => }/moxie/testutils.inc | 0 sim/testsuite/{sim => }/msp430/ChangeLog | 0 sim/testsuite/{sim => }/msp430/add.s | 0 sim/testsuite/{sim => }/msp430/allinsn.exp | 0 sim/testsuite/{sim => }/msp430/mpyull_hwmult.s | 0 sim/testsuite/{sim => }/msp430/rrux.s | 0 sim/testsuite/{sim => }/msp430/testutils.inc | 0 sim/testsuite/{sim => }/or1k/ChangeLog | 0 sim/testsuite/{sim => }/or1k/add.S | 0 sim/testsuite/{sim => }/or1k/adrp.S | 0 sim/testsuite/{sim => }/or1k/alltests.exp | 0 sim/testsuite/{sim => }/or1k/and.S | 0 sim/testsuite/{sim => }/or1k/basic.S | 0 sim/testsuite/{sim => }/or1k/div.S | 0 sim/testsuite/{sim => }/or1k/ext.S | 0 sim/testsuite/{sim => }/or1k/find.S | 0 sim/testsuite/{sim => }/or1k/flag.S | 0 sim/testsuite/{sim => }/or1k/fpu-unordered.S | 0 sim/testsuite/{sim => }/or1k/fpu.S | 0 sim/testsuite/{sim => }/or1k/fpu64a32-unordered.S | 0 sim/testsuite/{sim => }/or1k/fpu64a32.S | 0 sim/testsuite/{sim => }/or1k/jump.S | 0 sim/testsuite/{sim => }/or1k/load.S | 0 sim/testsuite/{sim => }/or1k/mac.S | 0 sim/testsuite/{sim => }/or1k/mfspr.S | 0 sim/testsuite/{sim => }/or1k/mul.S | 0 sim/testsuite/{sim => }/or1k/or.S | 0 sim/testsuite/{sim => }/or1k/or1k-asm-test-env.h | 0 .../{sim => }/or1k/or1k-asm-test-helpers.h | 0 sim/testsuite/{sim => }/or1k/or1k-asm-test.h | 0 sim/testsuite/{sim => }/or1k/or1k-asm.h | 0 sim/testsuite/{sim => }/or1k/or1k-test.ld | 0 sim/testsuite/{sim => }/or1k/ror.S | 0 sim/testsuite/{sim => }/or1k/shift.S | 0 sim/testsuite/{sim => }/or1k/spr-defs.h | 0 sim/testsuite/{sim => }/or1k/sub.S | 0 sim/testsuite/{sim => }/or1k/xor.S | 0 sim/testsuite/{sim => }/pru/ChangeLog | 0 sim/testsuite/{sim => }/pru/add.s | 0 sim/testsuite/{sim => }/pru/allinsn.exp | 0 sim/testsuite/{sim => }/pru/dmem-zero-pass.s | 0 sim/testsuite/{sim => }/pru/dmem-zero-trap.s | 0 sim/testsuite/{sim => }/pru/dram.s | 0 sim/testsuite/{sim => }/pru/jmp.s | 0 sim/testsuite/{sim => }/pru/lmbd.s | 0 sim/testsuite/{sim => }/pru/loop-imm.s | 0 sim/testsuite/{sim => }/pru/loop-reg.s | 0 sim/testsuite/{sim => }/pru/mul.s | 0 sim/testsuite/{sim => }/pru/subreg.s | 0 sim/testsuite/{sim => }/pru/testutils.inc | 0 sim/testsuite/{sim => }/sh/ChangeLog | 0 sim/testsuite/{sim => }/sh/add.s | 0 sim/testsuite/{sim => }/sh/allinsn.exp | 0 sim/testsuite/{sim => }/sh/and.s | 0 sim/testsuite/{sim => }/sh/bandor.s | 0 sim/testsuite/{sim => }/sh/bandornot.s | 0 sim/testsuite/{sim => }/sh/bclr.s | 0 sim/testsuite/{sim => }/sh/bld.s | 0 sim/testsuite/{sim => }/sh/bldnot.s | 0 sim/testsuite/{sim => }/sh/bset.s | 0 sim/testsuite/{sim => }/sh/bst.s | 0 sim/testsuite/{sim => }/sh/bxor.s | 0 sim/testsuite/{sim => }/sh/clip.s | 0 sim/testsuite/{sim => }/sh/div.s | 0 sim/testsuite/{sim => }/sh/dmxy.s | 0 sim/testsuite/{sim => }/sh/fabs.s | 0 sim/testsuite/{sim => }/sh/fadd.s | 0 sim/testsuite/{sim => }/sh/fail.s | 0 sim/testsuite/{sim => }/sh/fcmpeq.s | 0 sim/testsuite/{sim => }/sh/fcmpgt.s | 0 sim/testsuite/{sim => }/sh/fcnvds.s | 0 sim/testsuite/{sim => }/sh/fcnvsd.s | 0 sim/testsuite/{sim => }/sh/fdiv.s | 0 sim/testsuite/{sim => }/sh/fipr.s | 0 sim/testsuite/{sim => }/sh/fldi0.s | 0 sim/testsuite/{sim => }/sh/fldi1.s | 0 sim/testsuite/{sim => }/sh/flds.s | 0 sim/testsuite/{sim => }/sh/float.s | 0 sim/testsuite/{sim => }/sh/fmac.s | 0 sim/testsuite/{sim => }/sh/fmov.s | 0 sim/testsuite/{sim => }/sh/fmul.s | 0 sim/testsuite/{sim => }/sh/fneg.s | 0 sim/testsuite/{sim => }/sh/fpchg.s | 0 sim/testsuite/{sim => }/sh/frchg.s | 0 sim/testsuite/{sim => }/sh/fsca.s | 0 sim/testsuite/{sim => }/sh/fschg.s | 0 sim/testsuite/{sim => }/sh/fsqrt.s | 0 sim/testsuite/{sim => }/sh/fsrra.s | 0 sim/testsuite/{sim => }/sh/fsub.s | 0 sim/testsuite/{sim => }/sh/ftrc.s | 0 sim/testsuite/{sim => }/sh/ldrc.s | 0 sim/testsuite/{sim => }/sh/loop.s | 0 sim/testsuite/{sim => }/sh/macl.s | 0 sim/testsuite/{sim => }/sh/macw.s | 0 sim/testsuite/{sim => }/sh/mov.s | 0 sim/testsuite/{sim => }/sh/movi.s | 0 sim/testsuite/{sim => }/sh/movli.s | 0 sim/testsuite/{sim => }/sh/movua.s | 0 sim/testsuite/{sim => }/sh/movxy.s | 0 sim/testsuite/{sim => }/sh/mulr.s | 0 sim/testsuite/{sim => }/sh/pabs.s | 0 sim/testsuite/{sim => }/sh/padd.s | 0 sim/testsuite/{sim => }/sh/paddc.s | 0 sim/testsuite/{sim => }/sh/pand.s | 0 sim/testsuite/{sim => }/sh/pass.s | 0 sim/testsuite/{sim => }/sh/pclr.s | 0 sim/testsuite/{sim => }/sh/pdec.s | 0 sim/testsuite/{sim => }/sh/pdmsb.s | 0 sim/testsuite/{sim => }/sh/pinc.s | 0 sim/testsuite/{sim => }/sh/pmuls.s | 0 sim/testsuite/{sim => }/sh/prnd.s | 0 sim/testsuite/{sim => }/sh/pshai.s | 0 sim/testsuite/{sim => }/sh/pshar.s | 0 sim/testsuite/{sim => }/sh/pshli.s | 0 sim/testsuite/{sim => }/sh/pshlr.s | 0 sim/testsuite/{sim => }/sh/psub.s | 0 sim/testsuite/{sim => }/sh/pswap.s | 0 sim/testsuite/{sim => }/sh/pushpop.s | 0 sim/testsuite/{sim => }/sh/resbank.s | 0 sim/testsuite/{sim => }/sh/sett.s | 0 sim/testsuite/{sim => }/sh/shll.s | 0 sim/testsuite/{sim => }/sh/shll16.s | 0 sim/testsuite/{sim => }/sh/shll2.s | 0 sim/testsuite/{sim => }/sh/shll8.s | 0 sim/testsuite/{sim => }/sh/shlr.s | 0 sim/testsuite/{sim => }/sh/shlr16.s | 0 sim/testsuite/{sim => }/sh/shlr2.s | 0 sim/testsuite/{sim => }/sh/shlr8.s | 0 sim/testsuite/{sim => }/sh/swap.s | 0 sim/testsuite/{sim => }/sh/testutils.inc | 0 sim/testsuite/{sim => }/v850/ChangeLog | 0 sim/testsuite/{sim => }/v850/allinsns.exp | 0 sim/testsuite/{sim => }/v850/bsh.cgs | 0 sim/testsuite/{sim => }/v850/div.cgs | 0 sim/testsuite/{sim => }/v850/divh.cgs | 0 sim/testsuite/{sim => }/v850/divh_3.cgs | 0 sim/testsuite/{sim => }/v850/divhu.cgs | 0 sim/testsuite/{sim => }/v850/divu.cgs | 0 sim/testsuite/{sim => }/v850/sar.cgs | 0 sim/testsuite/{sim => }/v850/satadd.cgs | 0 sim/testsuite/{sim => }/v850/satsub.cgs | 0 sim/testsuite/{sim => }/v850/satsubi.cgs | 0 sim/testsuite/{sim => }/v850/satsubr.cgs | 0 sim/testsuite/{sim => }/v850/shl.cgs | 0 sim/testsuite/{sim => }/v850/shr.cgs | 0 sim/testsuite/{sim => }/v850/testutils.cgs | 0 sim/testsuite/{sim => }/v850/testutils.inc | 0 2919 files changed, 1854 insertions(+), 1550 deletions(-) create mode 100644 ld/emulparams/x86-report-relative.sh create mode 100644 ld/testsuite/ld-i386/report-reloc-1.d create mode 100644 ld/testsuite/ld-i386/report-reloc-1.l create mode 100644 ld/testsuite/ld-i386/report-reloc-1.s create mode 100644 ld/testsuite/ld-x86-64/report-reloc-1-x32.d create mode 100644 ld/testsuite/ld-x86-64/report-reloc-1.d create mode 100644 ld/testsuite/ld-x86-64/report-reloc-1.l create mode 100644 ld/testsuite/ld-x86-64/report-reloc-1.s rename sim/testsuite/{sim => }/aarch64/ChangeLog (100%) rename sim/testsuite/{sim => }/aarch64/adds.s (100%) rename sim/testsuite/{sim => }/aarch64/addv.s (100%) rename sim/testsuite/{sim => }/aarch64/allinsn.exp (100%) rename sim/testsuite/{sim => }/aarch64/bit.s (100%) rename sim/testsuite/{sim => }/aarch64/cmtst.s (100%) rename sim/testsuite/{sim => }/aarch64/cnt.s (100%) rename sim/testsuite/{sim => }/aarch64/fcmXX.s (100%) rename sim/testsuite/{sim => }/aarch64/fcmp.s (100%) rename sim/testsuite/{sim => }/aarch64/fcsel.s (100%) rename sim/testsuite/{sim => }/aarch64/fcvtl.s (100%) rename sim/testsuite/{sim => }/aarch64/fcvtz.s (100%) rename sim/testsuite/{sim => }/aarch64/fminnm.s (100%) rename sim/testsuite/{sim => }/aarch64/fstur.s (100%) rename sim/testsuite/{sim => }/aarch64/ldn_multiple.s (100%) rename sim/testsuite/{sim => }/aarch64/ldn_single.s (100%) rename sim/testsuite/{sim => }/aarch64/ldnr.s (100%) rename sim/testsuite/{sim => }/aarch64/mla.s (100%) rename sim/testsuite/{sim => }/aarch64/mls.s (100%) rename sim/testsuite/{sim => }/aarch64/mul.s (100%) rename sim/testsuite/{sim => }/aarch64/pass.s (100%) rename sim/testsuite/{sim => }/aarch64/stn_multiple.s (100%) rename sim/testsuite/{sim => }/aarch64/stn_single.s (100%) rename sim/testsuite/{sim => }/aarch64/sumov.s (100%) rename sim/testsuite/{sim => }/aarch64/sumulh.s (100%) rename sim/testsuite/{sim => }/aarch64/tbnz.s (100%) rename sim/testsuite/{sim => }/aarch64/testutils.inc (100%) rename sim/testsuite/{sim => }/aarch64/uzp.s (100%) rename sim/testsuite/{sim => }/aarch64/xtl.s (100%) rename sim/testsuite/{sim => }/aarch64/xtn.s (100%) rename sim/testsuite/{sim => }/arm/ChangeLog (100%) rename sim/testsuite/{sim => }/arm/adc.cgs (100%) rename sim/testsuite/{sim => }/arm/add.cgs (100%) rename sim/testsuite/{sim => }/arm/allinsn.exp (100%) rename sim/testsuite/{sim => }/arm/and.cgs (100%) rename sim/testsuite/{sim => }/arm/b.cgs (100%) rename sim/testsuite/{sim => }/arm/bic.cgs (100%) rename sim/testsuite/{sim => }/arm/bl.cgs (100%) rename sim/testsuite/{sim => }/arm/bx.cgs (100%) rename sim/testsuite/{sim => }/arm/cmn.cgs (100%) rename sim/testsuite/{sim => }/arm/cmp.cgs (100%) rename sim/testsuite/{sim => }/arm/eor.cgs (100%) rename sim/testsuite/{sim => }/arm/hello.ms (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/iwmmxt.exp (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/tbcst.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/testutils.inc (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/textrm.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/tinsr.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/tmia.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/tmiaph.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/tmiaxy.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/tmovmsk.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wacc.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wadd.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/waligni.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/walignr.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wand.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wandn.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wavg2.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wcmpeq.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wcmpgt.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wmac.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wmadd.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wmax.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wmin.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wmov.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wmul.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wor.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wpack.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wror.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wsad.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wshufh.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wsll.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wsra.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wsrl.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wsub.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wunpckeh.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wunpckel.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wunpckih.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wunpckil.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wxor.cgs (100%) rename sim/testsuite/{sim => }/arm/iwmmxt/wzero.cgs (100%) rename sim/testsuite/{sim => }/arm/ldm.cgs (100%) rename sim/testsuite/{sim => }/arm/ldr.cgs (100%) rename sim/testsuite/{sim => }/arm/ldrb.cgs (100%) rename sim/testsuite/{sim => }/arm/ldrh.cgs (100%) rename sim/testsuite/{sim => }/arm/ldrsb.cgs (100%) rename sim/testsuite/{sim => }/arm/ldrsh.cgs (100%) rename sim/testsuite/{sim => }/arm/misaligned1.ms (100%) rename sim/testsuite/{sim => }/arm/misaligned2.ms (100%) rename sim/testsuite/{sim => }/arm/misaligned3.ms (100%) rename sim/testsuite/{sim => }/arm/misc.exp (100%) rename sim/testsuite/{sim => }/arm/mla.cgs (100%) rename sim/testsuite/{sim => }/arm/mov.cgs (100%) rename sim/testsuite/{sim => }/arm/movw-movt.ms (100%) rename sim/testsuite/{sim => }/arm/mrs.cgs (100%) rename sim/testsuite/{sim => }/arm/msr.cgs (100%) rename sim/testsuite/{sim => }/arm/mul.cgs (100%) rename sim/testsuite/{sim => }/arm/mvn.cgs (100%) rename sim/testsuite/{sim => }/arm/orr.cgs (100%) rename sim/testsuite/{sim => }/arm/rsb.cgs (100%) rename sim/testsuite/{sim => }/arm/rsc.cgs (100%) rename sim/testsuite/{sim => }/arm/sbc.cgs (100%) rename sim/testsuite/{sim => }/arm/smlal.cgs (100%) rename sim/testsuite/{sim => }/arm/smull.cgs (100%) rename sim/testsuite/{sim => }/arm/stm.cgs (100%) rename sim/testsuite/{sim => }/arm/str.cgs (100%) rename sim/testsuite/{sim => }/arm/strb.cgs (100%) rename sim/testsuite/{sim => }/arm/strh.cgs (100%) rename sim/testsuite/{sim => }/arm/sub.cgs (100%) rename sim/testsuite/{sim => }/arm/swi.cgs (100%) rename sim/testsuite/{sim => }/arm/swp.cgs (100%) rename sim/testsuite/{sim => }/arm/swpb.cgs (100%) rename sim/testsuite/{sim => }/arm/teq.cgs (100%) rename sim/testsuite/{sim => }/arm/testutils.inc (100%) rename sim/testsuite/{sim => }/arm/thumb/adc.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/add-hd-hs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/add-hd-rs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/add-rd-hs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/add-sp.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/add.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/addi.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/addi8.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/allthumb.exp (100%) rename sim/testsuite/{sim => }/arm/thumb/and.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/asr.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/b.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bcc.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bcs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/beq.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bge.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bgt.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bhi.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bic.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bl-hi.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bl-lo.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ble.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bls.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/blt.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bmi.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bne.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bpl.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bvc.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bvs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bx-hs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/bx-rs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/cmn.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/cmp-hd-hs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/cmp-hd-rs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/cmp-rd-hs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/cmp.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/eor.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/lda-pc.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/lda-sp.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldmia.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldr-imm.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldr-pc.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldr-sprel.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldr.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldrb-imm.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldrb.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldrh-imm.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldrh.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldsb.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ldsh.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/lsl.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/lsr.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/mov-hd-hs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/mov-hd-rs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/mov-rd-hs.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/mov.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/mul.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/mvn.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/neg.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/orr.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/pop-pc.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/pop.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/push-lr.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/push.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/ror.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/sbc.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/stmia.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/str-imm.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/str-sprel.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/str.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/strb-imm.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/strb.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/strh-imm.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/strh.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/sub-sp.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/sub.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/subi.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/subi8.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/swi.cgs (100%) rename sim/testsuite/{sim => }/arm/thumb/testutils.inc (100%) rename sim/testsuite/{sim => }/arm/thumb/tst.cgs (100%) rename sim/testsuite/{sim => }/arm/tst.cgs (100%) rename sim/testsuite/{sim => }/arm/umlal.cgs (100%) rename sim/testsuite/{sim => }/arm/umull.cgs (100%) rename sim/testsuite/{sim => }/arm/xscale/blx.cgs (100%) rename sim/testsuite/{sim => }/arm/xscale/mia.cgs (100%) rename sim/testsuite/{sim => }/arm/xscale/miaph.cgs (100%) rename sim/testsuite/{sim => }/arm/xscale/miaxy.cgs (100%) rename sim/testsuite/{sim => }/arm/xscale/mra.cgs (100%) rename sim/testsuite/{sim => }/arm/xscale/testutils.inc (100%) rename sim/testsuite/{sim => }/arm/xscale/xscale.exp (100%) rename sim/testsuite/{sim => }/avr/ChangeLog (100%) rename sim/testsuite/{sim => }/avr/allinsn.exp (100%) rename sim/testsuite/{sim => }/avr/pass.s (100%) rename sim/testsuite/{sim => }/avr/testutils.inc (100%) rename sim/testsuite/{sim => }/bfin/.gitignore (100%) rename sim/testsuite/{sim => }/bfin/10272_small.s (100%) rename sim/testsuite/{sim => }/bfin/10436.s (100%) rename sim/testsuite/{sim => }/bfin/10622.s (100%) rename sim/testsuite/{sim => }/bfin/10742.s (100%) rename sim/testsuite/{sim => }/bfin/10799.s (100%) rename sim/testsuite/{sim => }/bfin/11080.s (100%) rename sim/testsuite/{sim => }/bfin/7641.s (100%) rename sim/testsuite/{sim => }/bfin/ChangeLog (100%) rename sim/testsuite/{sim => }/bfin/PN_generator.s (100%) rename sim/testsuite/{sim => }/bfin/a0.s (100%) rename sim/testsuite/{sim => }/bfin/a0shift.S (100%) rename sim/testsuite/{sim => }/bfin/a1.s (100%) rename sim/testsuite/{sim => }/bfin/a10.s (100%) rename sim/testsuite/{sim => }/bfin/a11.S (100%) rename sim/testsuite/{sim => }/bfin/a12.s (100%) rename sim/testsuite/{sim => }/bfin/a2.s (100%) rename sim/testsuite/{sim => }/bfin/a20.S (100%) rename sim/testsuite/{sim => }/bfin/a21.s (100%) rename sim/testsuite/{sim => }/bfin/a22.s (100%) rename sim/testsuite/{sim => }/bfin/a23.s (100%) rename sim/testsuite/{sim => }/bfin/a24.s (100%) rename sim/testsuite/{sim => }/bfin/a25.s (100%) rename sim/testsuite/{sim => }/bfin/a26.s (100%) rename sim/testsuite/{sim => }/bfin/a3.s (100%) rename sim/testsuite/{sim => }/bfin/a30.s (100%) rename sim/testsuite/{sim => }/bfin/a4.s (100%) rename sim/testsuite/{sim => }/bfin/a5.s (100%) rename sim/testsuite/{sim => }/bfin/a6.s (100%) rename sim/testsuite/{sim => }/bfin/a7.s (100%) rename sim/testsuite/{sim => }/bfin/a8.s (100%) rename sim/testsuite/{sim => }/bfin/a9.s (100%) rename sim/testsuite/{sim => }/bfin/abs-2.S (100%) rename sim/testsuite/{sim => }/bfin/abs-3.S (100%) rename sim/testsuite/{sim => }/bfin/abs-4.S (100%) rename sim/testsuite/{sim => }/bfin/abs.S (100%) rename sim/testsuite/{sim => }/bfin/abs_acc.s (100%) rename sim/testsuite/{sim => }/bfin/acc-rot.s (100%) rename sim/testsuite/{sim => }/bfin/acp5_19.s (100%) rename sim/testsuite/{sim => }/bfin/acp5_4.s (100%) rename sim/testsuite/{sim => }/bfin/add_imm7.s (100%) rename sim/testsuite/{sim => }/bfin/add_shift.S (100%) rename sim/testsuite/{sim => }/bfin/add_sub_acc.s (100%) rename sim/testsuite/{sim => }/bfin/addsub_flags.S (100%) rename sim/testsuite/{sim => }/bfin/algnbug1.s (100%) rename sim/testsuite/{sim => }/bfin/algnbug2.s (100%) rename sim/testsuite/{sim => }/bfin/allinsn.exp (100%) rename sim/testsuite/{sim => }/bfin/argc.c (100%) rename sim/testsuite/{sim => }/bfin/ashift.s (100%) rename sim/testsuite/{sim => }/bfin/ashift_flags.s (100%) rename sim/testsuite/{sim => }/bfin/ashift_left.s (100%) rename sim/testsuite/{sim => }/bfin/b0.S (100%) rename sim/testsuite/{sim => }/bfin/b1.s (100%) rename sim/testsuite/{sim => }/bfin/b2.S (100%) rename sim/testsuite/{sim => }/bfin/brcc.s (100%) rename sim/testsuite/{sim => }/bfin/brevadd.s (100%) rename sim/testsuite/{sim => }/bfin/byteop16m.s (100%) rename sim/testsuite/{sim => }/bfin/byteop16p.s (100%) rename sim/testsuite/{sim => }/bfin/byteop1p.s (100%) rename sim/testsuite/{sim => }/bfin/byteop2p.s (100%) rename sim/testsuite/{sim => }/bfin/byteop3p.s (100%) rename sim/testsuite/{sim => }/bfin/byteunpack.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_arith_r_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_neg.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_toggle.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_divq.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_divs.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_log_l_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_log_r_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_shadd_1.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_shadd_2.s (100%) rename sim/testsuite/{sim => }/bfin/c_br_preg_killed_ac.s (100%) rename sim/testsuite/{sim => }/bfin/c_br_preg_killed_ex1.s (100%) rename sim/testsuite/{sim => }/bfin/c_br_preg_stall_ac.s (100%) rename sim/testsuite/{sim => }/bfin/c_br_preg_stall_ex1.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_bp1.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_bp2.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_bp3.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_bp4.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brf_bp.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_bp.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_nbp.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brf_fbkwd.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brf_nbp.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brt_bp.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brt_nbp.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_kills_dhits.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_kills_dmiss.s (100%) rename sim/testsuite/{sim => }/bfin/c_cactrl_iflush_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_cactrl_iflush_pr_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_calla_ljump.s (100%) rename sim/testsuite/{sim => }/bfin/c_calla_subr.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc2dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_ac.S (100%) rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_an.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_aq.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av0.S (100%) rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av1.S (100%) rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_az.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc_flag_ccmv_depend.S (100%) rename sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft_s1.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft_sn.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft_s1.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft_sn.S (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_a0a1.S (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr_uu.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3_uu.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3_uu.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr_uu.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_cc_pr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_ncc_pr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_and_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_minus_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_or_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_plus_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_xor_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_pr_plus_pr_sh1.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_pr_plus_pr_sh2.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_add_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_add_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_eq_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_eq_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_flags.S (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_flags_2.S (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_add_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_add_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_eq_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_eq_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodik_lnz_imgebl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodik_lnz_imltbl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodik_lz_inc_dec.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodim_lnz_imgebl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodim_lnz_imltbl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodim_lz_inc_dec.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a0_pm_a1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a0a1s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a_abs_a.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a_neg_a.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_aa_absabs.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_aa_negneg.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_abs.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_absabs.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_alhwx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_awx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop1ew.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop2.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop3.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_bytepack.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteunpack.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_disalnexcpt.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_max.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_maxmax.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_min.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_minmin.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_r_lh_a0pa1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_r_negneg.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd12_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd12_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd20_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd20_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd12_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd12_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd20_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd20_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rlh_rnd.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rmm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rmp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rpm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rpp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rr_lph_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm_aa.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp_sft_x.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm_sft_x.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_saa.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_sat_aa.S (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_search.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_sgn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_iuw32.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_ih.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_iu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_tu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_ih.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_iu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_tu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0_iutsh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_ih.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_iu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_iutsh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_tu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_a0alr.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_af.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_af_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align16.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align24.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align8.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_amix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bitmux.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bxor.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_l.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expexp_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fdepx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fextx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lf.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lmix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ones.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_pack.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_rot.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_rot_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_rh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_rl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_vmax.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_vmaxvmax.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_a0alr.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_ln_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_lp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rn_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_amix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lf.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lmix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_rot.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ippm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ippm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_except_illopcode.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_sys_sstep.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_user_mode.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable_enable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_excpt.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_loopsetup_stld.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nested.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nmi.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending_2.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_reload.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_tcount.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_tscale.S (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_drhi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_drlo.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_pibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_ppmm_hbx.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_st_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_st_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_st_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_hi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_lo.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_h_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_lohi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_hi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_lo.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_lohi.s (100%) rename sim/testsuite/{sim => }/bfin/c_linkage.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_alshft_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_arith_shft.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bitclr.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bitset.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bittgl.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bittst.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_l_shft.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_l_shft_astat.S (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_r_shft.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_r_shft_astat.S (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_nbittst.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_bot.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_prelc.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_top.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_overlap.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_div2_lc0.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_div2_lc1.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_lc0.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_lc1.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_stld.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_prelc.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_topbotcntr.s (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_interr_ctl.s (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_loop.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_loop_user_except.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_ppop_illegal_adr.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_ppopm_illegal_adr.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_timer.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_supervisor.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_user.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_user_superivsor.S (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ld_ld.s (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ldst_1.s (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ldst_2.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_call_pcpr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_call_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_clisti_interr.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_csync_mmr.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_except_rtx.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_excpt.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_jump_pcpr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_jump_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_nop.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_raise_rt_i_n.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_rts.s (100%) rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_neg_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_sft_2_1.s (100%) rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_shadd_1_2.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dp.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dp_pair.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_acc_acc.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dag_lz_dep.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_acc_acc.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_dep_nostall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_imlb.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dep_nostall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dep_stall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_imlb.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dep_nostall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dep_stall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_imlb.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ac_raise_mv.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ac_raise_mv_ppop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ac_regmv_pushpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_dec_raise_pushpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_brcc_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_call_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_j_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_brcc_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_call_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_j_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_brcc_mp_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_mmr_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_mmrj_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_raise_mmr_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_raise_mmrj_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_brcc_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_mmr_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_mmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_cs_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_rti_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_rtn_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_rtx_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_ujump.s (100%) rename sim/testsuite/{sim => }/bfin/cc-alu.S (100%) rename sim/testsuite/{sim => }/bfin/cc-astat-bits.s (100%) rename sim/testsuite/{sim => }/bfin/cc0.s (100%) rename sim/testsuite/{sim => }/bfin/cc1.s (100%) rename sim/testsuite/{sim => }/bfin/cc5.S (100%) rename sim/testsuite/{sim => }/bfin/cec-exact-exception.S (100%) rename sim/testsuite/{sim => }/bfin/cec-ifetch.S (100%) rename sim/testsuite/{sim => }/bfin/cec-multi-pending.S (100%) rename sim/testsuite/{sim => }/bfin/cec-no-snen-reti.S (100%) rename sim/testsuite/{sim => }/bfin/cec-non-operating-env.s (100%) rename sim/testsuite/{sim => }/bfin/cec-raise-reti.S (100%) rename sim/testsuite/{sim => }/bfin/cec-snen-reti.S (100%) rename sim/testsuite/{sim => }/bfin/cec-syscfg-ssstep.S (100%) rename sim/testsuite/{sim => }/bfin/cec-system-call.S (100%) rename sim/testsuite/{sim => }/bfin/cir.s (100%) rename sim/testsuite/{sim => }/bfin/cir1.s (100%) rename sim/testsuite/{sim => }/bfin/cli-sti.s (100%) rename sim/testsuite/{sim => }/bfin/cmpacc.s (100%) rename sim/testsuite/{sim => }/bfin/cmpdreg.S (100%) rename sim/testsuite/{sim => }/bfin/compare.s (100%) rename sim/testsuite/{sim => }/bfin/conv_enc_gen.s (100%) rename sim/testsuite/{sim => }/bfin/cycles.s (100%) rename sim/testsuite/{sim => }/bfin/d0.s (100%) rename sim/testsuite/{sim => }/bfin/d1.s (100%) rename sim/testsuite/{sim => }/bfin/d2.s (100%) rename sim/testsuite/{sim => }/bfin/dbg_brprd_ntkn_src_kill.S (100%) rename sim/testsuite/{sim => }/bfin/dbg_brtkn_nprd_src_kill.S (100%) rename sim/testsuite/{sim => }/bfin/dbg_jmp_src_kill.S (100%) rename sim/testsuite/{sim => }/bfin/dbg_tr_basic.S (100%) rename sim/testsuite/{sim => }/bfin/dbg_tr_simplejp.S (100%) rename sim/testsuite/{sim => }/bfin/dbg_tr_tbuf0.S (100%) rename sim/testsuite/{sim => }/bfin/dbg_tr_umode.S (100%) rename sim/testsuite/{sim => }/bfin/disalnexcpt_implicit.S (100%) rename sim/testsuite/{sim => }/bfin/div0.s (100%) rename sim/testsuite/{sim => }/bfin/divq.s (100%) rename sim/testsuite/{sim => }/bfin/dotproduct.s (100%) rename sim/testsuite/{sim => }/bfin/dotproduct2.s (100%) rename sim/testsuite/{sim => }/bfin/double_prec_mult.s (100%) rename sim/testsuite/{sim => }/bfin/dsp_a4.s (100%) rename sim/testsuite/{sim => }/bfin/dsp_a7.s (100%) rename sim/testsuite/{sim => }/bfin/dsp_a8.s (100%) rename sim/testsuite/{sim => }/bfin/dsp_d0.s (100%) rename sim/testsuite/{sim => }/bfin/dsp_d1.s (100%) rename sim/testsuite/{sim => }/bfin/dsp_neg.S (100%) rename sim/testsuite/{sim => }/bfin/dsp_s1.s (100%) rename sim/testsuite/{sim => }/bfin/e0.s (100%) rename sim/testsuite/{sim => }/bfin/edn_snafu.s (100%) rename sim/testsuite/{sim => }/bfin/eu_dsp32mac_s.s (100%) rename sim/testsuite/{sim => }/bfin/events.s (100%) rename sim/testsuite/{sim => }/bfin/f221.s (100%) rename sim/testsuite/{sim => }/bfin/fact.s (100%) rename sim/testsuite/{sim => }/bfin/fir.s (100%) rename sim/testsuite/{sim => }/bfin/fsm.s (100%) rename sim/testsuite/{sim => }/bfin/greg2.s (100%) rename sim/testsuite/{sim => }/bfin/hwloop-bits.S (100%) rename sim/testsuite/{sim => }/bfin/hwloop-branch-in.s (100%) rename sim/testsuite/{sim => }/bfin/hwloop-branch-out.s (100%) rename sim/testsuite/{sim => }/bfin/hwloop-lt-bits.s (100%) rename sim/testsuite/{sim => }/bfin/hwloop-nested.s (100%) rename sim/testsuite/{sim => }/bfin/i0.s (100%) rename sim/testsuite/{sim => }/bfin/iir.s (100%) rename sim/testsuite/{sim => }/bfin/issue103.s (100%) rename sim/testsuite/{sim => }/bfin/issue109.s (100%) rename sim/testsuite/{sim => }/bfin/issue112.s (100%) rename sim/testsuite/{sim => }/bfin/issue113.s (100%) rename sim/testsuite/{sim => }/bfin/issue117.s (100%) rename sim/testsuite/{sim => }/bfin/issue118.s (100%) rename sim/testsuite/{sim => }/bfin/issue119.s (100%) rename sim/testsuite/{sim => }/bfin/issue121.s (100%) rename sim/testsuite/{sim => }/bfin/issue123.s (100%) rename sim/testsuite/{sim => }/bfin/issue124.s (100%) rename sim/testsuite/{sim => }/bfin/issue125.s (100%) rename sim/testsuite/{sim => }/bfin/issue126.s (100%) rename sim/testsuite/{sim => }/bfin/issue127.s (100%) rename sim/testsuite/{sim => }/bfin/issue129.s (100%) rename sim/testsuite/{sim => }/bfin/issue139.S (100%) rename sim/testsuite/{sim => }/bfin/issue140.S (100%) rename sim/testsuite/{sim => }/bfin/issue142.s (100%) rename sim/testsuite/{sim => }/bfin/issue144.s (100%) rename sim/testsuite/{sim => }/bfin/issue146.S (100%) rename sim/testsuite/{sim => }/bfin/issue175.s (100%) rename sim/testsuite/{sim => }/bfin/issue205.s (100%) rename sim/testsuite/{sim => }/bfin/issue257.s (100%) rename sim/testsuite/{sim => }/bfin/issue272.S (100%) rename sim/testsuite/{sim => }/bfin/issue83.s (100%) rename sim/testsuite/{sim => }/bfin/issue89.s (100%) rename sim/testsuite/{sim => }/bfin/l0.s (100%) rename sim/testsuite/{sim => }/bfin/l0shift.s (100%) rename sim/testsuite/{sim => }/bfin/l2_loop.s (100%) rename sim/testsuite/{sim => }/bfin/link-2.s (100%) rename sim/testsuite/{sim => }/bfin/link.s (100%) rename sim/testsuite/{sim => }/bfin/lmu_cplb_multiple0.S (100%) rename sim/testsuite/{sim => }/bfin/lmu_cplb_multiple1.S (100%) rename sim/testsuite/{sim => }/bfin/lmu_excpt_align.S (100%) rename sim/testsuite/{sim => }/bfin/lmu_excpt_default.S (100%) rename sim/testsuite/{sim => }/bfin/lmu_excpt_illaddr.S (100%) rename sim/testsuite/{sim => }/bfin/lmu_excpt_prot0.S (100%) rename sim/testsuite/{sim => }/bfin/lmu_excpt_prot1.S (100%) rename sim/testsuite/{sim => }/bfin/load.s (100%) rename sim/testsuite/{sim => }/bfin/logic.s (100%) rename sim/testsuite/{sim => }/bfin/loop_snafu.s (100%) rename sim/testsuite/{sim => }/bfin/loop_strncpy.s (100%) rename sim/testsuite/{sim => }/bfin/lp0.s (100%) rename sim/testsuite/{sim => }/bfin/lp1.s (100%) rename sim/testsuite/{sim => }/bfin/lsetup.s (100%) rename sim/testsuite/{sim => }/bfin/m0boundary.s (100%) rename sim/testsuite/{sim => }/bfin/m1.S (100%) rename sim/testsuite/{sim => }/bfin/m10.s (100%) rename sim/testsuite/{sim => }/bfin/m11.s (100%) rename sim/testsuite/{sim => }/bfin/m12.s (100%) rename sim/testsuite/{sim => }/bfin/m13.s (100%) rename sim/testsuite/{sim => }/bfin/m14.s (100%) rename sim/testsuite/{sim => }/bfin/m15.s (100%) rename sim/testsuite/{sim => }/bfin/m16.s (100%) rename sim/testsuite/{sim => }/bfin/m17.s (100%) rename sim/testsuite/{sim => }/bfin/m2.s (100%) rename sim/testsuite/{sim => }/bfin/m3.s (100%) rename sim/testsuite/{sim => }/bfin/m4.s (100%) rename sim/testsuite/{sim => }/bfin/m5.s (100%) rename sim/testsuite/{sim => }/bfin/m6.s (100%) rename sim/testsuite/{sim => }/bfin/m7.s (100%) rename sim/testsuite/{sim => }/bfin/m8.s (100%) rename sim/testsuite/{sim => }/bfin/m9.s (100%) rename sim/testsuite/{sim => }/bfin/mac2halfreg.S (100%) rename sim/testsuite/{sim => }/bfin/math.s (100%) rename sim/testsuite/{sim => }/bfin/max_min_flags.s (100%) rename sim/testsuite/{sim => }/bfin/mc_s2.s (100%) rename sim/testsuite/{sim => }/bfin/mdma-32bit-1d-neg-count.c (100%) rename sim/testsuite/{sim => }/bfin/mdma-32bit-1d.c (100%) rename sim/testsuite/{sim => }/bfin/mdma-8bit-1d-neg-count.c (100%) rename sim/testsuite/{sim => }/bfin/mdma-8bit-1d.c (100%) rename sim/testsuite/{sim => }/bfin/mdma-skel.h (100%) rename sim/testsuite/{sim => }/bfin/mem3.s (100%) rename sim/testsuite/{sim => }/bfin/mmr-exception.s (100%) rename sim/testsuite/{sim => }/bfin/move.s (100%) rename sim/testsuite/{sim => }/bfin/msa_acp_5.10.S (100%) rename sim/testsuite/{sim => }/bfin/msa_acp_5.12_1.S (100%) rename sim/testsuite/{sim => }/bfin/msa_acp_5.12_2.S (100%) rename sim/testsuite/{sim => }/bfin/msa_acp_5_10.s (100%) rename sim/testsuite/{sim => }/bfin/mult.s (100%) rename sim/testsuite/{sim => }/bfin/neg-2.S (100%) rename sim/testsuite/{sim => }/bfin/neg-3.S (100%) rename sim/testsuite/{sim => }/bfin/neg.S (100%) rename sim/testsuite/{sim => }/bfin/nshift.s (100%) rename sim/testsuite/{sim => }/bfin/pr.s (100%) rename sim/testsuite/{sim => }/bfin/push-pop-multiple.s (100%) rename sim/testsuite/{sim => }/bfin/push-pop.s (100%) rename sim/testsuite/{sim => }/bfin/pushpopreg_1.s (100%) rename sim/testsuite/{sim => }/bfin/quadaddsub.s (100%) rename sim/testsuite/{sim => }/bfin/random_0001.s (100%) rename sim/testsuite/{sim => }/bfin/random_0002.S (100%) rename sim/testsuite/{sim => }/bfin/random_0003.S (100%) rename sim/testsuite/{sim => }/bfin/random_0004.S (100%) rename sim/testsuite/{sim => }/bfin/random_0005.S (100%) rename sim/testsuite/{sim => }/bfin/random_0006.S (100%) rename sim/testsuite/{sim => }/bfin/random_0007.S (100%) rename sim/testsuite/{sim => }/bfin/random_0008.S (100%) rename sim/testsuite/{sim => }/bfin/random_0009.S (100%) rename sim/testsuite/{sim => }/bfin/random_0010.S (100%) rename sim/testsuite/{sim => }/bfin/random_0011.S (100%) rename sim/testsuite/{sim => }/bfin/random_0012.S (100%) rename sim/testsuite/{sim => }/bfin/random_0013.S (100%) rename sim/testsuite/{sim => }/bfin/random_0014.S (100%) rename sim/testsuite/{sim => }/bfin/random_0015.S (100%) rename sim/testsuite/{sim => }/bfin/random_0016.S (100%) rename sim/testsuite/{sim => }/bfin/random_0017.S (100%) rename sim/testsuite/{sim => }/bfin/random_0018.S (100%) rename sim/testsuite/{sim => }/bfin/random_0019.S (100%) rename sim/testsuite/{sim => }/bfin/random_0020.S (100%) rename sim/testsuite/{sim => }/bfin/random_0021.S (100%) rename sim/testsuite/{sim => }/bfin/random_0022.S (100%) rename sim/testsuite/{sim => }/bfin/random_0023.S (100%) rename sim/testsuite/{sim => }/bfin/random_0024.S (100%) rename sim/testsuite/{sim => }/bfin/random_0025.S (100%) rename sim/testsuite/{sim => }/bfin/random_0026.S (100%) rename sim/testsuite/{sim => }/bfin/random_0027.S (100%) rename sim/testsuite/{sim => }/bfin/random_0028.S (100%) rename sim/testsuite/{sim => }/bfin/random_0029.S (100%) rename sim/testsuite/{sim => }/bfin/random_0030.S (100%) rename sim/testsuite/{sim => }/bfin/random_0031.S (100%) rename sim/testsuite/{sim => }/bfin/random_0032.S (100%) rename sim/testsuite/{sim => }/bfin/random_0033.S (100%) rename sim/testsuite/{sim => }/bfin/random_0034.S (100%) rename sim/testsuite/{sim => }/bfin/random_0035.S (100%) rename sim/testsuite/{sim => }/bfin/random_0036.S (100%) rename sim/testsuite/{sim => }/bfin/random_0037.S (100%) rename sim/testsuite/{sim => }/bfin/run-tests.sh (100%) rename sim/testsuite/{sim => }/bfin/s0.s (100%) rename sim/testsuite/{sim => }/bfin/s1.s (100%) rename sim/testsuite/{sim => }/bfin/s10.s (100%) rename sim/testsuite/{sim => }/bfin/s11.s (100%) rename sim/testsuite/{sim => }/bfin/s12.s (100%) rename sim/testsuite/{sim => }/bfin/s13.s (100%) rename sim/testsuite/{sim => }/bfin/s14.s (100%) rename sim/testsuite/{sim => }/bfin/s15.s (100%) rename sim/testsuite/{sim => }/bfin/s16.s (100%) rename sim/testsuite/{sim => }/bfin/s17.s (100%) rename sim/testsuite/{sim => }/bfin/s18.s (100%) rename sim/testsuite/{sim => }/bfin/s19.s (100%) rename sim/testsuite/{sim => }/bfin/s2.s (100%) rename sim/testsuite/{sim => }/bfin/s20.s (100%) rename sim/testsuite/{sim => }/bfin/s21.s (100%) rename sim/testsuite/{sim => }/bfin/s3.s (100%) rename sim/testsuite/{sim => }/bfin/s30.s (100%) rename sim/testsuite/{sim => }/bfin/s4.s (100%) rename sim/testsuite/{sim => }/bfin/s5.s (100%) rename sim/testsuite/{sim => }/bfin/s6.s (100%) rename sim/testsuite/{sim => }/bfin/s7.s (100%) rename sim/testsuite/{sim => }/bfin/s8.s (100%) rename sim/testsuite/{sim => }/bfin/s9.s (100%) rename sim/testsuite/{sim => }/bfin/saatest.s (100%) rename sim/testsuite/{sim => }/bfin/se_all16bitopcodes.S (100%) rename sim/testsuite/{sim => }/bfin/se_all32bitopcodes.S (100%) rename sim/testsuite/{sim => }/bfin/se_all32bitopcodes.lds (100%) rename sim/testsuite/{sim => }/bfin/se_all64bitg0opcodes.S (100%) rename sim/testsuite/{sim => }/bfin/se_all64bitg1opcodes.S (100%) rename sim/testsuite/{sim => }/bfin/se_all64bitg2opcodes.S (100%) rename sim/testsuite/{sim => }/bfin/se_allopcodes.h (100%) rename sim/testsuite/{sim => }/bfin/se_brtarget_stall.S (100%) rename sim/testsuite/{sim => }/bfin/se_bug_ui.S (100%) rename sim/testsuite/{sim => }/bfin/se_bug_ui2.S (100%) rename sim/testsuite/{sim => }/bfin/se_bug_ui3.S (100%) rename sim/testsuite/{sim => }/bfin/se_cc2stat_haz.S (100%) rename sim/testsuite/{sim => }/bfin/se_cc_kill.S (100%) rename sim/testsuite/{sim => }/bfin/se_cof.S (100%) rename sim/testsuite/{sim => }/bfin/se_event_quad.S (100%) rename sim/testsuite/{sim => }/bfin/se_excpt_dagprotviol.S (100%) rename sim/testsuite/{sim => }/bfin/se_excpt_ifprotviol.S (100%) rename sim/testsuite/{sim => }/bfin/se_excpt_ssstep.S (100%) rename sim/testsuite/{sim => }/bfin/se_illegalcombination.S (100%) rename sim/testsuite/{sim => }/bfin/se_kill_wbbr.S (100%) rename sim/testsuite/{sim => }/bfin/se_kills2.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_disable.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_kill.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_kill_01.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_kill_dcr.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_kill_dcr_01.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_lr.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_mv2lb_stall.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_mv2lc.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_mv2lc_stall.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_mv2lt_stall.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_nest_ppm.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_nest_ppm_1.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_nest_ppm_2.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_ppm.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_ppm_1.S (100%) rename sim/testsuite/{sim => }/bfin/se_loop_ppm_int.S (100%) rename sim/testsuite/{sim => }/bfin/se_lsetup_kill.S (100%) rename sim/testsuite/{sim => }/bfin/se_misaligned_fetch.S (100%) rename sim/testsuite/{sim => }/bfin/se_more_ret_haz.S (100%) rename sim/testsuite/{sim => }/bfin/se_mv2lp.S (100%) rename sim/testsuite/{sim => }/bfin/se_oneins_zoff.S (100%) rename sim/testsuite/{sim => }/bfin/se_popkill.S (100%) rename sim/testsuite/{sim => }/bfin/se_regmv_usp_sysreg.S (100%) rename sim/testsuite/{sim => }/bfin/se_rets_hazard.s (100%) rename sim/testsuite/{sim => }/bfin/se_rts_rti.S (100%) rename sim/testsuite/{sim => }/bfin/se_ssstep_dagprotviol.S (100%) rename sim/testsuite/{sim => }/bfin/se_ssync.S (100%) rename sim/testsuite/{sim => }/bfin/se_stall_if2.S (100%) rename sim/testsuite/{sim => }/bfin/se_undefinedinstruction1.S (100%) rename sim/testsuite/{sim => }/bfin/se_undefinedinstruction2.S (100%) rename sim/testsuite/{sim => }/bfin/se_undefinedinstruction3.S (100%) rename sim/testsuite/{sim => }/bfin/se_undefinedinstruction4.S (100%) rename sim/testsuite/{sim => }/bfin/se_usermode_protviol.S (100%) rename sim/testsuite/{sim => }/bfin/seqstat.s (100%) rename sim/testsuite/{sim => }/bfin/sign.s (100%) rename sim/testsuite/{sim => }/bfin/simple0.s (100%) rename sim/testsuite/{sim => }/bfin/sri.s (100%) rename sim/testsuite/{sim => }/bfin/stk.s (100%) rename sim/testsuite/{sim => }/bfin/stk2.s (100%) rename sim/testsuite/{sim => }/bfin/stk3.s (100%) rename sim/testsuite/{sim => }/bfin/stk4.s (100%) rename sim/testsuite/{sim => }/bfin/stk5.s (100%) rename sim/testsuite/{sim => }/bfin/stk6.s (100%) rename sim/testsuite/{sim => }/bfin/syscfg.s (100%) rename sim/testsuite/{sim => }/bfin/tar10622.s (100%) rename sim/testsuite/{sim => }/bfin/test-dma.h (100%) rename sim/testsuite/{sim => }/bfin/test.h (100%) rename sim/testsuite/{sim => }/bfin/testset.s (100%) rename sim/testsuite/{sim => }/bfin/testset2.s (100%) rename sim/testsuite/{sim => }/bfin/testutils.inc (100%) rename sim/testsuite/{sim => }/bfin/unlink.S (100%) rename sim/testsuite/{sim => }/bfin/up0.s (100%) rename sim/testsuite/{sim => }/bfin/usp.S (100%) rename sim/testsuite/{sim => }/bfin/vec-abs-2.S (100%) rename sim/testsuite/{sim => }/bfin/vec-abs-3.S (100%) rename sim/testsuite/{sim => }/bfin/vec-abs.S (100%) rename sim/testsuite/{sim => }/bfin/vec-neg-2.S (100%) rename sim/testsuite/{sim => }/bfin/vec-neg-3.S (100%) rename sim/testsuite/{sim => }/bfin/vec-neg.S (100%) rename sim/testsuite/{sim => }/bfin/vecadd.s (100%) rename sim/testsuite/{sim => }/bfin/vit_max.s (100%) rename sim/testsuite/{sim => }/bfin/vit_max2.s (100%) rename sim/testsuite/{sim => }/bfin/viterbi2.s (100%) rename sim/testsuite/{sim => }/bfin/wtf.s (100%) rename sim/testsuite/{sim => }/bfin/x1.s (100%) rename sim/testsuite/{sim => }/bfin/zcall.s (100%) rename sim/testsuite/{sim => }/bfin/zeroflagrnd.s (100%) rename sim/testsuite/{sim => }/bpf/ChangeLog (100%) rename sim/testsuite/{sim => }/bpf/allinsn.exp (100%) rename sim/testsuite/{sim => }/bpf/alu.s (100%) rename sim/testsuite/{sim => }/bpf/alu32.s (100%) rename sim/testsuite/{sim => }/bpf/endbe.s (100%) rename sim/testsuite/{sim => }/bpf/endle.s (100%) rename sim/testsuite/{sim => }/bpf/jmp.s (100%) rename sim/testsuite/{sim => }/bpf/jmp32.s (100%) rename sim/testsuite/{sim => }/bpf/ldabs.s (100%) rename sim/testsuite/{sim => }/bpf/mem.s (100%) rename sim/testsuite/{sim => }/bpf/mov.s (100%) rename sim/testsuite/{sim => }/bpf/testutils.inc (100%) rename sim/testsuite/{sim => }/bpf/xadd.s (100%) rename sim/testsuite/{sim => }/cr16/ChangeLog (100%) rename sim/testsuite/{sim => }/cr16/addb.cgs (100%) rename sim/testsuite/{sim => }/cr16/addd.cgs (100%) rename sim/testsuite/{sim => }/cr16/addi.cgs (100%) rename sim/testsuite/{sim => }/cr16/addw.cgs (100%) rename sim/testsuite/{sim => }/cr16/allinsn.exp (100%) rename sim/testsuite/{sim => }/cr16/andb.cgs (100%) rename sim/testsuite/{sim => }/cr16/andd.cgs (100%) rename sim/testsuite/{sim => }/cr16/andw.cgs (100%) rename sim/testsuite/{sim => }/cr16/ashub.cgs (100%) rename sim/testsuite/{sim => }/cr16/ashub_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/ashud.cgs (100%) rename sim/testsuite/{sim => }/cr16/ashud_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/ashuw.cgs (100%) rename sim/testsuite/{sim => }/cr16/ashuw_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/bal1_24.cgs (100%) rename sim/testsuite/{sim => }/cr16/bal2_24.cgs (100%) rename sim/testsuite/{sim => }/cr16/bcc.cgs (100%) rename sim/testsuite/{sim => }/cr16/bcs.cgs (100%) rename sim/testsuite/{sim => }/cr16/beq.cgs (100%) rename sim/testsuite/{sim => }/cr16/beq0b.cgs (100%) rename sim/testsuite/{sim => }/cr16/beq0w.cgs (100%) rename sim/testsuite/{sim => }/cr16/bge.cgs (100%) rename sim/testsuite/{sim => }/cr16/bgt.cgs (100%) rename sim/testsuite/{sim => }/cr16/bhi.cgs (100%) rename sim/testsuite/{sim => }/cr16/bhs.cgs (100%) rename sim/testsuite/{sim => }/cr16/bht.cgs (100%) rename sim/testsuite/{sim => }/cr16/blo.cgs (100%) rename sim/testsuite/{sim => }/cr16/bls.cgs (100%) rename sim/testsuite/{sim => }/cr16/blt.cgs (100%) rename sim/testsuite/{sim => }/cr16/bne.cgs (100%) rename sim/testsuite/{sim => }/cr16/bne0b.cgs (100%) rename sim/testsuite/{sim => }/cr16/bne0w.cgs (100%) rename sim/testsuite/{sim => }/cr16/br.cgs (100%) rename sim/testsuite/{sim => }/cr16/cbitb.cgs (100%) rename sim/testsuite/{sim => }/cr16/cbitw.cgs (100%) rename sim/testsuite/{sim => }/cr16/cmpb.cgs (100%) rename sim/testsuite/{sim => }/cr16/cmpb_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/cmpd.cgs (100%) rename sim/testsuite/{sim => }/cr16/cmpd_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/cmpi.cgs (100%) rename sim/testsuite/{sim => }/cr16/cmpw.cgs (100%) rename sim/testsuite/{sim => }/cr16/cmpw_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/excp.cgs (100%) rename sim/testsuite/{sim => }/cr16/hello.ms (100%) rename sim/testsuite/{sim => }/cr16/hw-trap.ms (100%) rename sim/testsuite/{sim => }/cr16/jal.cgs (100%) rename sim/testsuite/{sim => }/cr16/jcc.cgs (100%) rename sim/testsuite/{sim => }/cr16/jcs.cgs (100%) rename sim/testsuite/{sim => }/cr16/jeq.cgs (100%) rename sim/testsuite/{sim => }/cr16/jfc.cgs (100%) rename sim/testsuite/{sim => }/cr16/jfs.cgs (100%) rename sim/testsuite/{sim => }/cr16/jge.cgs (100%) rename sim/testsuite/{sim => }/cr16/jgt.cgs (100%) rename sim/testsuite/{sim => }/cr16/jhi.cgs (100%) rename sim/testsuite/{sim => }/cr16/jhs.cgs (100%) rename sim/testsuite/{sim => }/cr16/jlo.cgs (100%) rename sim/testsuite/{sim => }/cr16/jls.cgs (100%) rename sim/testsuite/{sim => }/cr16/jlt.cgs (100%) rename sim/testsuite/{sim => }/cr16/jne.cgs (100%) rename sim/testsuite/{sim => }/cr16/jump.cgs (100%) rename sim/testsuite/{sim => }/cr16/loadb.cgs (100%) rename sim/testsuite/{sim => }/cr16/loadd.cgs (100%) rename sim/testsuite/{sim => }/cr16/loadm.cgs (100%) rename sim/testsuite/{sim => }/cr16/loadmp.cgs (100%) rename sim/testsuite/{sim => }/cr16/loadw.cgs (100%) rename sim/testsuite/{sim => }/cr16/lpr-spr.cgs (100%) rename sim/testsuite/{sim => }/cr16/lprd-sprd.cgs (100%) rename sim/testsuite/{sim => }/cr16/lshb.cgs (100%) rename sim/testsuite/{sim => }/cr16/lshb_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/lshd.cgs (100%) rename sim/testsuite/{sim => }/cr16/lshd_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/lshw.cgs (100%) rename sim/testsuite/{sim => }/cr16/lshw_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/macqw.cgs (100%) rename sim/testsuite/{sim => }/cr16/macsw.cgs (100%) rename sim/testsuite/{sim => }/cr16/macuw.cgs (100%) rename sim/testsuite/{sim => }/cr16/misc.exp (100%) rename sim/testsuite/{sim => }/cr16/movb.cgs (100%) rename sim/testsuite/{sim => }/cr16/movd.cgs (100%) rename sim/testsuite/{sim => }/cr16/movw.cgs (100%) rename sim/testsuite/{sim => }/cr16/movxb.cgs (100%) rename sim/testsuite/{sim => }/cr16/movxw.cgs (100%) rename sim/testsuite/{sim => }/cr16/movzb.cgs (100%) rename sim/testsuite/{sim => }/cr16/movzw.cgs (100%) rename sim/testsuite/{sim => }/cr16/mulb.cgs (100%) rename sim/testsuite/{sim => }/cr16/mulsb.cgs (100%) rename sim/testsuite/{sim => }/cr16/mulsw.cgs (100%) rename sim/testsuite/{sim => }/cr16/muluw.cgs (100%) rename sim/testsuite/{sim => }/cr16/mulw.cgs (100%) rename sim/testsuite/{sim => }/cr16/nop.cgs (100%) rename sim/testsuite/{sim => }/cr16/orb.cgs (100%) rename sim/testsuite/{sim => }/cr16/ord.cgs (100%) rename sim/testsuite/{sim => }/cr16/orw.cgs (100%) rename sim/testsuite/{sim => }/cr16/pop1.cgs (100%) rename sim/testsuite/{sim => }/cr16/pop2.cgs (100%) rename sim/testsuite/{sim => }/cr16/pop3.cgs (100%) rename sim/testsuite/{sim => }/cr16/popret1.cgs (100%) rename sim/testsuite/{sim => }/cr16/popret2.cgs (100%) rename sim/testsuite/{sim => }/cr16/popret3.cgs (100%) rename sim/testsuite/{sim => }/cr16/push1.cgs (100%) rename sim/testsuite/{sim => }/cr16/push2.cgs (100%) rename sim/testsuite/{sim => }/cr16/push3.cgs (100%) rename sim/testsuite/{sim => }/cr16/sbitb.cgs (100%) rename sim/testsuite/{sim => }/cr16/sbitw.cgs (100%) rename sim/testsuite/{sim => }/cr16/scc.cgs (100%) rename sim/testsuite/{sim => }/cr16/scs.cgs (100%) rename sim/testsuite/{sim => }/cr16/seq.cgs (100%) rename sim/testsuite/{sim => }/cr16/sfc.cgs (100%) rename sim/testsuite/{sim => }/cr16/sfs.cgs (100%) rename sim/testsuite/{sim => }/cr16/sge.cgs (100%) rename sim/testsuite/{sim => }/cr16/sgt.cgs (100%) rename sim/testsuite/{sim => }/cr16/shi.cgs (100%) rename sim/testsuite/{sim => }/cr16/shs.cgs (100%) rename sim/testsuite/{sim => }/cr16/slo.cgs (100%) rename sim/testsuite/{sim => }/cr16/sls.cgs (100%) rename sim/testsuite/{sim => }/cr16/slt.cgs (100%) rename sim/testsuite/{sim => }/cr16/sne.cgs (100%) rename sim/testsuite/{sim => }/cr16/storb.cgs (100%) rename sim/testsuite/{sim => }/cr16/stord.cgs (100%) rename sim/testsuite/{sim => }/cr16/storw.cgs (100%) rename sim/testsuite/{sim => }/cr16/subb.cgs (100%) rename sim/testsuite/{sim => }/cr16/subd.cgs (100%) rename sim/testsuite/{sim => }/cr16/subi.cgs (100%) rename sim/testsuite/{sim => }/cr16/subw.cgs (100%) rename sim/testsuite/{sim => }/cr16/tbit.cgs (100%) rename sim/testsuite/{sim => }/cr16/tbitb.cgs (100%) rename sim/testsuite/{sim => }/cr16/tbitw.cgs (100%) rename sim/testsuite/{sim => }/cr16/testutils.inc (100%) rename sim/testsuite/{sim => }/cr16/uread16.ms (100%) rename sim/testsuite/{sim => }/cr16/uread32.ms (100%) rename sim/testsuite/{sim => }/cr16/xorb.cgs (100%) rename sim/testsuite/{sim => }/cr16/xord.cgs (100%) rename sim/testsuite/{sim => }/cr16/xorw.cgs (100%) rename sim/testsuite/{sim => }/cris/ChangeLog (100%) rename sim/testsuite/{sim => }/cris/asm/abs.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addcpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addcv32c.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addcv32m.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addcv32r.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addi.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addiv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addoc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addom.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addoq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addqpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addswpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addxc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addxm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addxr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/andc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/andm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/andq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/andr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/asm.exp (100%) rename sim/testsuite/{sim => }/cris/asm/asr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/ba.ms (100%) rename sim/testsuite/{sim => }/cris/asm/badarch1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bare1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bare2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bare3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bas.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bccb.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bdapc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bdapm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bdapq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bdapqpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/biap.ms (100%) rename sim/testsuite/{sim => }/cris/asm/boundc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/boundm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/boundmv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/boundr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/break.ms (100%) rename sim/testsuite/{sim => }/cris/asm/btst.ms (100%) rename sim/testsuite/{sim => }/cris/asm/ccr-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/ccs-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/clearfv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/clearfv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/clrjmp1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/cmpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/cmpm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/cmpq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/cmpr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/cmpxc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/cmpxm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/dflags.ms (100%) rename sim/testsuite/{sim => }/cris/asm/dip.ms (100%) rename sim/testsuite/{sim => }/cris/asm/dstep.ms (100%) rename sim/testsuite/{sim => }/cris/asm/fidxd.ms (100%) rename sim/testsuite/{sim => }/cris/asm/fidxi.ms (100%) rename sim/testsuite/{sim => }/cris/asm/ftagd.ms (100%) rename sim/testsuite/{sim => }/cris/asm/ftagi.ms (100%) rename sim/testsuite/{sim => }/cris/asm/halt.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io4.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io5.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io6.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io7.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io8.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io9.ms (100%) rename sim/testsuite/{sim => }/cris/asm/jsr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/jsrmv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/jumpmp.ms (100%) rename sim/testsuite/{sim => }/cris/asm/jumppv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/lapc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/lsl.ms (100%) rename sim/testsuite/{sim => }/cris/asm/lsr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/lz.ms (100%) rename sim/testsuite/{sim => }/cris/asm/mcp.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movdelsr1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movecpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movecr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movecrt10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movecrt32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movect10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movei.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movempc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movemr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movemrv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movemrv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movepcb.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movepcd.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movepcw.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moveq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moveqpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/mover.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverbpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverdpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverpcb.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverpcd.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverpcw.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverwpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movesmp.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movmp.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movmp8.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movpmv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movpmv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movppc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movpr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movprv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movprv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movrss.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movscpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movscr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movsm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movsmpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movsr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movsrpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movssr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movucpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movucr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movum.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movumpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movur.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movurpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/mstep.ms (100%) rename sim/testsuite/{sim => }/cris/asm/msteppc1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/msteppc2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/msteppc3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/mulv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/mulv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/mulx.ms (100%) rename sim/testsuite/{sim => }/cris/asm/neg.ms (100%) rename sim/testsuite/{sim => }/cris/asm/nonvcv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/nopv10t.ms (100%) rename sim/testsuite/{sim => }/cris/asm/nopv32t.ms (100%) rename sim/testsuite/{sim => }/cris/asm/nopv32t2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/nopv32t3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/nopv32t4.ms (100%) rename sim/testsuite/{sim => }/cris/asm/not.ms (100%) rename sim/testsuite/{sim => }/cris/asm/op3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/opterr1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/opterr2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/opterr3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/opterr4.ms (100%) rename sim/testsuite/{sim => }/cris/asm/opterr5.ms (100%) rename sim/testsuite/{sim => }/cris/asm/option1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/option2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/option3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/option4.ms (100%) rename sim/testsuite/{sim => }/cris/asm/orc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/orm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/orq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/orr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/pcplus.ms (100%) rename sim/testsuite/{sim => }/cris/asm/pid1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw11.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw12.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw13.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw14.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw15.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw16.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw17.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw4.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw5.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw6.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw7.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw8.ms (100%) rename sim/testsuite/{sim => }/cris/asm/raw9.ms (100%) rename sim/testsuite/{sim => }/cris/asm/ret.ms (100%) rename sim/testsuite/{sim => }/cris/asm/rfe.ms (100%) rename sim/testsuite/{sim => }/cris/asm/rfg.ms (100%) rename sim/testsuite/{sim => }/cris/asm/rfn.ms (100%) rename sim/testsuite/{sim => }/cris/asm/sbfs.ms (100%) rename sim/testsuite/{sim => }/cris/asm/scc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/sfe.ms (100%) rename sim/testsuite/{sim => }/cris/asm/subc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/subm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/subq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/subqpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/subr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/subxc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/subxm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/subxr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/swap.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tb.ms (100%) rename sim/testsuite/{sim => }/cris/asm/test.ms (100%) rename sim/testsuite/{sim => }/cris/asm/testutils.inc (100%) rename sim/testsuite/{sim => }/cris/asm/tjmpsrv32-2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tjmpsrv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tjsrcv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tjsrcv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmemv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmemv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmulv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmulv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmvm1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmvm2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmvmrv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmvmrv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmvrmv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/tmvrmv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/user.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x0-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x0-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x1-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x1-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x10-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x2-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x2-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x3-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x3-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x4-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x5-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x5-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x6-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x6-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x7-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x7-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x8-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/x9-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/xor.ms (100%) rename sim/testsuite/{sim => }/cris/c/access1.c (100%) rename sim/testsuite/{sim => }/cris/c/append1.c (100%) rename sim/testsuite/{sim => }/cris/c/badldso1.c (100%) rename sim/testsuite/{sim => }/cris/c/badldso2.c (100%) rename sim/testsuite/{sim => }/cris/c/badldso3.c (100%) rename sim/testsuite/{sim => }/cris/c/c.exp (100%) rename sim/testsuite/{sim => }/cris/c/clone1.c (100%) rename sim/testsuite/{sim => }/cris/c/clone2.c (100%) rename sim/testsuite/{sim => }/cris/c/clone3.c (100%) rename sim/testsuite/{sim => }/cris/c/clone4.c (100%) rename sim/testsuite/{sim => }/cris/c/clone5.c (100%) rename sim/testsuite/{sim => }/cris/c/clone6.c (100%) rename sim/testsuite/{sim => }/cris/c/ex1.c (100%) rename sim/testsuite/{sim => }/cris/c/exitg1.c (100%) rename sim/testsuite/{sim => }/cris/c/exitg2.c (100%) rename sim/testsuite/{sim => }/cris/c/fcntl1.c (100%) rename sim/testsuite/{sim => }/cris/c/fcntl2.c (100%) rename sim/testsuite/{sim => }/cris/c/fdopen1.c (100%) rename sim/testsuite/{sim => }/cris/c/fdopen2.c (100%) rename sim/testsuite/{sim => }/cris/c/freopen1.c (100%) rename sim/testsuite/{sim => }/cris/c/freopen2.c (100%) rename sim/testsuite/{sim => }/cris/c/ftruncate1.c (100%) rename sim/testsuite/{sim => }/cris/c/ftruncate2.c (100%) rename sim/testsuite/{sim => }/cris/c/getcwd1.c (100%) rename sim/testsuite/{sim => }/cris/c/gettod.c (100%) rename sim/testsuite/{sim => }/cris/c/hello.c (100%) rename sim/testsuite/{sim => }/cris/c/helloaout.c (100%) rename sim/testsuite/{sim => }/cris/c/hellodyn.c (100%) rename sim/testsuite/{sim => }/cris/c/hellodyn2.c (100%) rename sim/testsuite/{sim => }/cris/c/hellodyn3.c (100%) rename sim/testsuite/{sim => }/cris/c/kill1.c (100%) rename sim/testsuite/{sim => }/cris/c/kill2.c (100%) rename sim/testsuite/{sim => }/cris/c/kill3.c (100%) rename sim/testsuite/{sim => }/cris/c/mapbrk.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap1.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap2.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap3.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap4.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap5.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap6.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap7.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap8.c (100%) rename sim/testsuite/{sim => }/cris/c/mprotect1.c (100%) rename sim/testsuite/{sim => }/cris/c/mprotect2.c (100%) rename sim/testsuite/{sim => }/cris/c/mremap.c (100%) rename sim/testsuite/{sim => }/cris/c/openpf1.c (100%) rename sim/testsuite/{sim => }/cris/c/openpf2.c (100%) rename sim/testsuite/{sim => }/cris/c/openpf3.c (100%) rename sim/testsuite/{sim => }/cris/c/openpf4.c (100%) rename sim/testsuite/{sim => }/cris/c/openpf5.c (100%) rename sim/testsuite/{sim => }/cris/c/pipe1.c (100%) rename sim/testsuite/{sim => }/cris/c/pipe2.c (100%) rename sim/testsuite/{sim => }/cris/c/pipe3.c (100%) rename sim/testsuite/{sim => }/cris/c/pipe4.c (100%) rename sim/testsuite/{sim => }/cris/c/pipe5.c (100%) rename sim/testsuite/{sim => }/cris/c/pipe6.c (100%) rename sim/testsuite/{sim => }/cris/c/pipe7.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink1.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink10.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink11.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink2.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink3.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink4.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink5.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink6.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink7.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink8.c (100%) rename sim/testsuite/{sim => }/cris/c/readlink9.c (100%) rename sim/testsuite/{sim => }/cris/c/rename2.c (100%) rename sim/testsuite/{sim => }/cris/c/rtsigprocmask1.c (100%) rename sim/testsuite/{sim => }/cris/c/rtsigprocmask2.c (100%) rename sim/testsuite/{sim => }/cris/c/rtsigsuspend1.c (100%) rename sim/testsuite/{sim => }/cris/c/rtsigsuspend2.c (100%) rename sim/testsuite/{sim => }/cris/c/sched1.c (100%) rename sim/testsuite/{sim => }/cris/c/sched2.c (100%) rename sim/testsuite/{sim => }/cris/c/sched3.c (100%) rename sim/testsuite/{sim => }/cris/c/sched4.c (100%) rename sim/testsuite/{sim => }/cris/c/sched5.c (100%) rename sim/testsuite/{sim => }/cris/c/sched6.c (100%) rename sim/testsuite/{sim => }/cris/c/sched7.c (100%) rename sim/testsuite/{sim => }/cris/c/sched8.c (100%) rename sim/testsuite/{sim => }/cris/c/sched9.c (100%) rename sim/testsuite/{sim => }/cris/c/seek1.c (100%) rename sim/testsuite/{sim => }/cris/c/seek2.c (100%) rename sim/testsuite/{sim => }/cris/c/seek3.c (100%) rename sim/testsuite/{sim => }/cris/c/seek4.c (100%) rename sim/testsuite/{sim => }/cris/c/setrlimit1.c (100%) rename sim/testsuite/{sim => }/cris/c/settls1.c (100%) rename sim/testsuite/{sim => }/cris/c/sig1.c (100%) rename sim/testsuite/{sim => }/cris/c/sig10.c (100%) rename sim/testsuite/{sim => }/cris/c/sig11.c (100%) rename sim/testsuite/{sim => }/cris/c/sig12.c (100%) rename sim/testsuite/{sim => }/cris/c/sig13.c (100%) rename sim/testsuite/{sim => }/cris/c/sig2.c (100%) rename sim/testsuite/{sim => }/cris/c/sig3.c (100%) rename sim/testsuite/{sim => }/cris/c/sig4.c (100%) rename sim/testsuite/{sim => }/cris/c/sig5.c (100%) rename sim/testsuite/{sim => }/cris/c/sig6.c (100%) rename sim/testsuite/{sim => }/cris/c/sig7.c (100%) rename sim/testsuite/{sim => }/cris/c/sig8.c (100%) rename sim/testsuite/{sim => }/cris/c/sig9.c (100%) rename sim/testsuite/{sim => }/cris/c/sigreturn1.c (100%) rename sim/testsuite/{sim => }/cris/c/sigreturn2.c (100%) rename sim/testsuite/{sim => }/cris/c/sigreturn3.c (100%) rename sim/testsuite/{sim => }/cris/c/sigreturn4.c (100%) rename sim/testsuite/{sim => }/cris/c/sjlj.c (100%) rename sim/testsuite/{sim => }/cris/c/sock1.c (100%) rename sim/testsuite/{sim => }/cris/c/stat1.c (100%) rename sim/testsuite/{sim => }/cris/c/stat2.c (100%) rename sim/testsuite/{sim => }/cris/c/stat3.c (100%) rename sim/testsuite/{sim => }/cris/c/stat4.c (100%) rename sim/testsuite/{sim => }/cris/c/stat5.c (100%) rename sim/testsuite/{sim => }/cris/c/stat7.c (100%) rename sim/testsuite/{sim => }/cris/c/stat8.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall1.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall2.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall3.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall4.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall5.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall6.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall7.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall8.c (100%) rename sim/testsuite/{sim => }/cris/c/sysctl1.c (100%) rename sim/testsuite/{sim => }/cris/c/sysctl2.c (100%) rename sim/testsuite/{sim => }/cris/c/sysctl3.c (100%) rename sim/testsuite/{sim => }/cris/c/thread2.c (100%) rename sim/testsuite/{sim => }/cris/c/thread3.c (100%) rename sim/testsuite/{sim => }/cris/c/thread4.c (100%) rename sim/testsuite/{sim => }/cris/c/thread5.c (100%) rename sim/testsuite/{sim => }/cris/c/time1.c (100%) rename sim/testsuite/{sim => }/cris/c/time2.c (100%) rename sim/testsuite/{sim => }/cris/c/truncate1.c (100%) rename sim/testsuite/{sim => }/cris/c/truncate2.c (100%) rename sim/testsuite/{sim => }/cris/c/ugetrlimit1.c (100%) rename sim/testsuite/{sim => }/cris/c/uname1.c (100%) rename sim/testsuite/{sim => }/cris/c/writev1.c (100%) rename sim/testsuite/{sim => }/cris/c/writev2.c (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/host1.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq1.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq2.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq3.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq4.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq5.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq6.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/mbox1.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/mem1.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/mem2.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/poll1.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/quit.s (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/rvc.exp (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/std.dev (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/testutils.inc (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/trivial1.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/trivial2.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/trivial3.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/trivial4.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/trivial4.r (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/trivial5.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/wd1.ms (100%) rename sim/testsuite/{sim => }/d10v/ChangeLog (100%) rename sim/testsuite/{sim => }/d10v/allinsn.exp (100%) rename sim/testsuite/{sim => }/d10v/exit47.s (100%) rename sim/testsuite/{sim => }/d10v/hello.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-ld-d.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-ld-i.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-ld-id.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-ld-im.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-ld-ip.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-ld2w-d.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-ld2w-i.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-ld2w-id.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-ld2w-im.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-ld2w-ip.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-st-d.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-st-i.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-st-id.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-st-im.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-st-ip.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-st-is.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-st2w-d.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-st2w-i.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-st2w-id.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-st2w-im.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-st2w-ip.s (100%) rename sim/testsuite/{sim => }/d10v/t-ae-st2w-is.s (100%) rename sim/testsuite/{sim => }/d10v/t-dbt.s (100%) rename sim/testsuite/{sim => }/d10v/t-ld-st.s (100%) rename sim/testsuite/{sim => }/d10v/t-mac.s (100%) rename sim/testsuite/{sim => }/d10v/t-macros.i (100%) rename sim/testsuite/{sim => }/d10v/t-mod-ld-pre.s (100%) rename sim/testsuite/{sim => }/d10v/t-msbu.s (100%) rename sim/testsuite/{sim => }/d10v/t-mulxu.s (100%) rename sim/testsuite/{sim => }/d10v/t-mvtac.s (100%) rename sim/testsuite/{sim => }/d10v/t-mvtc.s (100%) rename sim/testsuite/{sim => }/d10v/t-rac.s (100%) rename sim/testsuite/{sim => }/d10v/t-rachi.s (100%) rename sim/testsuite/{sim => }/d10v/t-rdt.s (100%) rename sim/testsuite/{sim => }/d10v/t-rep.s (100%) rename sim/testsuite/{sim => }/d10v/t-rie-xx.s (100%) rename sim/testsuite/{sim => }/d10v/t-rte.s (100%) rename sim/testsuite/{sim => }/d10v/t-sac.s (100%) rename sim/testsuite/{sim => }/d10v/t-sachi.s (100%) rename sim/testsuite/{sim => }/d10v/t-sadd.s (100%) rename sim/testsuite/{sim => }/d10v/t-slae.s (100%) rename sim/testsuite/{sim => }/d10v/t-sp.s (100%) rename sim/testsuite/{sim => }/d10v/t-sub.s (100%) rename sim/testsuite/{sim => }/d10v/t-sub2w.s (100%) rename sim/testsuite/{sim => }/d10v/t-subi.s (100%) rename sim/testsuite/{sim => }/d10v/t-trap.s (100%) rename sim/testsuite/{sim => }/frv/ChangeLog (100%) rename sim/testsuite/{sim => }/frv/add.cgs (100%) rename sim/testsuite/{sim => }/frv/add.pcgs (100%) rename sim/testsuite/{sim => }/frv/addcc.cgs (100%) rename sim/testsuite/{sim => }/frv/addi.cgs (100%) rename sim/testsuite/{sim => }/frv/addicc.cgs (100%) rename sim/testsuite/{sim => }/frv/addx.cgs (100%) rename sim/testsuite/{sim => }/frv/addxcc.cgs (100%) rename sim/testsuite/{sim => }/frv/addxi.cgs (100%) rename sim/testsuite/{sim => }/frv/addxicc.cgs (100%) rename sim/testsuite/{sim => }/frv/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/and.cgs (100%) rename sim/testsuite/{sim => }/frv/andcc.cgs (100%) rename sim/testsuite/{sim => }/frv/andcr.cgs (100%) rename sim/testsuite/{sim => }/frv/andi.cgs (100%) rename sim/testsuite/{sim => }/frv/andicc.cgs (100%) rename sim/testsuite/{sim => }/frv/andncr.cgs (100%) rename sim/testsuite/{sim => }/frv/bar.cgs (100%) rename sim/testsuite/{sim => }/frv/bc.cgs (100%) rename sim/testsuite/{sim => }/frv/bcclr.cgs (100%) rename sim/testsuite/{sim => }/frv/bceqlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcgelr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcgtlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bchilr.cgs (100%) rename sim/testsuite/{sim => }/frv/bclelr.cgs (100%) rename sim/testsuite/{sim => }/frv/bclr.cgs (100%) rename sim/testsuite/{sim => }/frv/bclslr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcltlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcnclr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcnelr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcnlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcnolr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcnvlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcplr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcralr.cgs (100%) rename sim/testsuite/{sim => }/frv/bctrlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bcvlr.cgs (100%) rename sim/testsuite/{sim => }/frv/beq.cgs (100%) rename sim/testsuite/{sim => }/frv/beqlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bge.cgs (100%) rename sim/testsuite/{sim => }/frv/bgelr.cgs (100%) rename sim/testsuite/{sim => }/frv/bgt.cgs (100%) rename sim/testsuite/{sim => }/frv/bgtlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bhi.cgs (100%) rename sim/testsuite/{sim => }/frv/bhilr.cgs (100%) rename sim/testsuite/{sim => }/frv/ble.cgs (100%) rename sim/testsuite/{sim => }/frv/blelr.cgs (100%) rename sim/testsuite/{sim => }/frv/bls.cgs (100%) rename sim/testsuite/{sim => }/frv/blslr.cgs (100%) rename sim/testsuite/{sim => }/frv/blt.cgs (100%) rename sim/testsuite/{sim => }/frv/bltlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bn.cgs (100%) rename sim/testsuite/{sim => }/frv/bnc.cgs (100%) rename sim/testsuite/{sim => }/frv/bnclr.cgs (100%) rename sim/testsuite/{sim => }/frv/bne.cgs (100%) rename sim/testsuite/{sim => }/frv/bnelr.cgs (100%) rename sim/testsuite/{sim => }/frv/bnlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bno.cgs (100%) rename sim/testsuite/{sim => }/frv/bnolr.cgs (100%) rename sim/testsuite/{sim => }/frv/bnv.cgs (100%) rename sim/testsuite/{sim => }/frv/bnvlr.cgs (100%) rename sim/testsuite/{sim => }/frv/bp.cgs (100%) rename sim/testsuite/{sim => }/frv/bplr.cgs (100%) rename sim/testsuite/{sim => }/frv/bra.cgs (100%) rename sim/testsuite/{sim => }/frv/bralr.cgs (100%) rename sim/testsuite/{sim => }/frv/branch.pcgs (100%) rename sim/testsuite/{sim => }/frv/break.cgs (100%) rename sim/testsuite/{sim => }/frv/bv.cgs (100%) rename sim/testsuite/{sim => }/frv/bvlr.cgs (100%) rename sim/testsuite/{sim => }/frv/cache.ms (100%) rename sim/testsuite/{sim => }/frv/cadd.cgs (100%) rename sim/testsuite/{sim => }/frv/caddcc.cgs (100%) rename sim/testsuite/{sim => }/frv/call.cgs (100%) rename sim/testsuite/{sim => }/frv/call.pcgs (100%) rename sim/testsuite/{sim => }/frv/callil.cgs (100%) rename sim/testsuite/{sim => }/frv/calll.cgs (100%) rename sim/testsuite/{sim => }/frv/cand.cgs (100%) rename sim/testsuite/{sim => }/frv/candcc.cgs (100%) rename sim/testsuite/{sim => }/frv/ccalll.cgs (100%) rename sim/testsuite/{sim => }/frv/cckc.cgs (100%) rename sim/testsuite/{sim => }/frv/cckeq.cgs (100%) rename sim/testsuite/{sim => }/frv/cckge.cgs (100%) rename sim/testsuite/{sim => }/frv/cckgt.cgs (100%) rename sim/testsuite/{sim => }/frv/cckhi.cgs (100%) rename sim/testsuite/{sim => }/frv/cckle.cgs (100%) rename sim/testsuite/{sim => }/frv/cckls.cgs (100%) rename sim/testsuite/{sim => }/frv/ccklt.cgs (100%) rename sim/testsuite/{sim => }/frv/cckn.cgs (100%) rename sim/testsuite/{sim => }/frv/ccknc.cgs (100%) rename sim/testsuite/{sim => }/frv/cckne.cgs (100%) rename sim/testsuite/{sim => }/frv/cckno.cgs (100%) rename sim/testsuite/{sim => }/frv/ccknv.cgs (100%) rename sim/testsuite/{sim => }/frv/cckp.cgs (100%) rename sim/testsuite/{sim => }/frv/cckra.cgs (100%) rename sim/testsuite/{sim => }/frv/cckv.cgs (100%) rename sim/testsuite/{sim => }/frv/ccmp.cgs (100%) rename sim/testsuite/{sim => }/frv/cfabss.cgs (100%) rename sim/testsuite/{sim => }/frv/cfadds.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckeq.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckge.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckgt.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckle.cgs (100%) rename sim/testsuite/{sim => }/frv/cfcklg.cgs (100%) rename sim/testsuite/{sim => }/frv/cfcklt.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckne.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckno.cgs (100%) rename sim/testsuite/{sim => }/frv/cfcko.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckra.cgs (100%) rename sim/testsuite/{sim => }/frv/cfcku.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckue.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckug.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckuge.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckul.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckule.cgs (100%) rename sim/testsuite/{sim => }/frv/cfcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/cfdivs.cgs (100%) rename sim/testsuite/{sim => }/frv/cfitos.cgs (100%) rename sim/testsuite/{sim => }/frv/cfmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/cfmas.cgs (100%) rename sim/testsuite/{sim => }/frv/cfmovs.cgs (100%) rename sim/testsuite/{sim => }/frv/cfmss.cgs (100%) rename sim/testsuite/{sim => }/frv/cfmsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/cfmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/cfnegs.cgs (100%) rename sim/testsuite/{sim => }/frv/cfsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/cfstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/cfsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/cjmpl.cgs (100%) rename sim/testsuite/{sim => }/frv/ckc.cgs (100%) rename sim/testsuite/{sim => }/frv/ckeq.cgs (100%) rename sim/testsuite/{sim => }/frv/ckge.cgs (100%) rename sim/testsuite/{sim => }/frv/ckgt.cgs (100%) rename sim/testsuite/{sim => }/frv/ckhi.cgs (100%) rename sim/testsuite/{sim => }/frv/ckle.cgs (100%) rename sim/testsuite/{sim => }/frv/ckls.cgs (100%) rename sim/testsuite/{sim => }/frv/cklt.cgs (100%) rename sim/testsuite/{sim => }/frv/ckn.cgs (100%) rename sim/testsuite/{sim => }/frv/cknc.cgs (100%) rename sim/testsuite/{sim => }/frv/ckne.cgs (100%) rename sim/testsuite/{sim => }/frv/ckno.cgs (100%) rename sim/testsuite/{sim => }/frv/cknv.cgs (100%) rename sim/testsuite/{sim => }/frv/ckp.cgs (100%) rename sim/testsuite/{sim => }/frv/ckra.cgs (100%) rename sim/testsuite/{sim => }/frv/ckv.cgs (100%) rename sim/testsuite/{sim => }/frv/cld.cgs (100%) rename sim/testsuite/{sim => }/frv/cldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/cldbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldd.cgs (100%) rename sim/testsuite/{sim => }/frv/clddf.cgs (100%) rename sim/testsuite/{sim => }/frv/clddfu.cgs (100%) rename sim/testsuite/{sim => }/frv/clddu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldf.cgs (100%) rename sim/testsuite/{sim => }/frv/cldfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldhf.cgs (100%) rename sim/testsuite/{sim => }/frv/cldhfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldq.cgs (100%) rename sim/testsuite/{sim => }/frv/cldqu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldsb.cgs (100%) rename sim/testsuite/{sim => }/frv/cldsbu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldsh.cgs (100%) rename sim/testsuite/{sim => }/frv/cldshu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldub.cgs (100%) rename sim/testsuite/{sim => }/frv/cldubu.cgs (100%) rename sim/testsuite/{sim => }/frv/clduh.cgs (100%) rename sim/testsuite/{sim => }/frv/clduhu.cgs (100%) rename sim/testsuite/{sim => }/frv/clrfa.cgs (100%) rename sim/testsuite/{sim => }/frv/clrfr.cgs (100%) rename sim/testsuite/{sim => }/frv/clrga.cgs (100%) rename sim/testsuite/{sim => }/frv/clrgr.cgs (100%) rename sim/testsuite/{sim => }/frv/cmaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/cmaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/cmand.cgs (100%) rename sim/testsuite/{sim => }/frv/cmbtoh.cgs (100%) rename sim/testsuite/{sim => }/frv/cmbtohe.cgs (100%) rename sim/testsuite/{sim => }/frv/cmcpxis.cgs (100%) rename sim/testsuite/{sim => }/frv/cmcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmcpxrs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/cmexpdhd.cgs (100%) rename sim/testsuite/{sim => }/frv/cmexpdhw.cgs (100%) rename sim/testsuite/{sim => }/frv/cmhtob.cgs (100%) rename sim/testsuite/{sim => }/frv/cmmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmnot.cgs (100%) rename sim/testsuite/{sim => }/frv/cmor.cgs (100%) rename sim/testsuite/{sim => }/frv/cmov.cgs (100%) rename sim/testsuite/{sim => }/frv/cmovfg.cgs (100%) rename sim/testsuite/{sim => }/frv/cmovfgd.cgs (100%) rename sim/testsuite/{sim => }/frv/cmovgf.cgs (100%) rename sim/testsuite/{sim => }/frv/cmovgfd.cgs (100%) rename sim/testsuite/{sim => }/frv/cmp.cgs (100%) rename sim/testsuite/{sim => }/frv/cmpb.cgs (100%) rename sim/testsuite/{sim => }/frv/cmpba.cgs (100%) rename sim/testsuite/{sim => }/frv/cmpi.cgs (100%) rename sim/testsuite/{sim => }/frv/cmqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmqmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmqmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/cmsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/cmxor.cgs (100%) rename sim/testsuite/{sim => }/frv/cnot.cgs (100%) rename sim/testsuite/{sim => }/frv/commitfa.cgs (100%) rename sim/testsuite/{sim => }/frv/commitfr.cgs (100%) rename sim/testsuite/{sim => }/frv/commitga.cgs (100%) rename sim/testsuite/{sim => }/frv/commitgr.cgs (100%) rename sim/testsuite/{sim => }/frv/cop1.cgs (100%) rename sim/testsuite/{sim => }/frv/cop2.cgs (100%) rename sim/testsuite/{sim => }/frv/cor.cgs (100%) rename sim/testsuite/{sim => }/frv/corcc.cgs (100%) rename sim/testsuite/{sim => }/frv/cscan.cgs (100%) rename sim/testsuite/{sim => }/frv/csdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/csll.cgs (100%) rename sim/testsuite/{sim => }/frv/csllcc.cgs (100%) rename sim/testsuite/{sim => }/frv/csmul.cgs (100%) rename sim/testsuite/{sim => }/frv/csmulcc.cgs (100%) rename sim/testsuite/{sim => }/frv/csra.cgs (100%) rename sim/testsuite/{sim => }/frv/csracc.cgs (100%) rename sim/testsuite/{sim => }/frv/csrl.cgs (100%) rename sim/testsuite/{sim => }/frv/csrlcc.cgs (100%) rename sim/testsuite/{sim => }/frv/cst.cgs (100%) rename sim/testsuite/{sim => }/frv/cstb.cgs (100%) rename sim/testsuite/{sim => }/frv/cstbf.cgs (100%) rename sim/testsuite/{sim => }/frv/cstbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstbu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstd.cgs (100%) rename sim/testsuite/{sim => }/frv/cstdf.cgs (100%) rename sim/testsuite/{sim => }/frv/cstdfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstdu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstf.cgs (100%) rename sim/testsuite/{sim => }/frv/cstfu.cgs (100%) rename sim/testsuite/{sim => }/frv/csth.cgs (100%) rename sim/testsuite/{sim => }/frv/csthf.cgs (100%) rename sim/testsuite/{sim => }/frv/csthfu.cgs (100%) rename sim/testsuite/{sim => }/frv/csthu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstq.cgs (100%) rename sim/testsuite/{sim => }/frv/cstu.cgs (100%) rename sim/testsuite/{sim => }/frv/csub.cgs (100%) rename sim/testsuite/{sim => }/frv/csubcc.cgs (100%) rename sim/testsuite/{sim => }/frv/cswap.cgs (100%) rename sim/testsuite/{sim => }/frv/cudiv.cgs (100%) rename sim/testsuite/{sim => }/frv/cxor.cgs (100%) rename sim/testsuite/{sim => }/frv/cxorcc.cgs (100%) rename sim/testsuite/{sim => }/frv/dcef.cgs (100%) rename sim/testsuite/{sim => }/frv/dcei.cgs (100%) rename sim/testsuite/{sim => }/frv/dcf.cgs (100%) rename sim/testsuite/{sim => }/frv/dci.cgs (100%) rename sim/testsuite/{sim => }/frv/exit47.ms (100%) rename sim/testsuite/{sim => }/frv/fabsd.cgs (100%) rename sim/testsuite/{sim => }/frv/fabss.cgs (100%) rename sim/testsuite/{sim => }/frv/faddd.cgs (100%) rename sim/testsuite/{sim => }/frv/fadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fbeq.cgs (100%) rename sim/testsuite/{sim => }/frv/fbeqlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbge.cgs (100%) rename sim/testsuite/{sim => }/frv/fbgelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbgt.cgs (100%) rename sim/testsuite/{sim => }/frv/fbgtlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fble.cgs (100%) rename sim/testsuite/{sim => }/frv/fblelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fblg.cgs (100%) rename sim/testsuite/{sim => }/frv/fblglr.cgs (100%) rename sim/testsuite/{sim => }/frv/fblt.cgs (100%) rename sim/testsuite/{sim => }/frv/fbltlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbne.cgs (100%) rename sim/testsuite/{sim => }/frv/fbnelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbno.cgs (100%) rename sim/testsuite/{sim => }/frv/fbnolr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbo.cgs (100%) rename sim/testsuite/{sim => }/frv/fbolr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbra.cgs (100%) rename sim/testsuite/{sim => }/frv/fbralr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbu.cgs (100%) rename sim/testsuite/{sim => }/frv/fbue.cgs (100%) rename sim/testsuite/{sim => }/frv/fbuelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbug.cgs (100%) rename sim/testsuite/{sim => }/frv/fbuge.cgs (100%) rename sim/testsuite/{sim => }/frv/fbugelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbuglr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbul.cgs (100%) rename sim/testsuite/{sim => }/frv/fbule.cgs (100%) rename sim/testsuite/{sim => }/frv/fbulelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbullr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbulr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbeqlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbgelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbgtlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcblelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcblglr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbltlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbnelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbnolr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbolr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbralr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbuelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbugelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbuglr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbulelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbullr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbulr.cgs (100%) rename sim/testsuite/{sim => }/frv/fckeq.cgs (100%) rename sim/testsuite/{sim => }/frv/fckge.cgs (100%) rename sim/testsuite/{sim => }/frv/fckgt.cgs (100%) rename sim/testsuite/{sim => }/frv/fckle.cgs (100%) rename sim/testsuite/{sim => }/frv/fcklg.cgs (100%) rename sim/testsuite/{sim => }/frv/fcklt.cgs (100%) rename sim/testsuite/{sim => }/frv/fckne.cgs (100%) rename sim/testsuite/{sim => }/frv/fckno.cgs (100%) rename sim/testsuite/{sim => }/frv/fcko.cgs (100%) rename sim/testsuite/{sim => }/frv/fckra.cgs (100%) rename sim/testsuite/{sim => }/frv/fcku.cgs (100%) rename sim/testsuite/{sim => }/frv/fckue.cgs (100%) rename sim/testsuite/{sim => }/frv/fckug.cgs (100%) rename sim/testsuite/{sim => }/frv/fckuge.cgs (100%) rename sim/testsuite/{sim => }/frv/fckul.cgs (100%) rename sim/testsuite/{sim => }/frv/fckule.cgs (100%) rename sim/testsuite/{sim => }/frv/fcmpd.cgs (100%) rename sim/testsuite/{sim => }/frv/fcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/fdabss.cgs (100%) rename sim/testsuite/{sim => }/frv/fdadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fdcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/fddivs.cgs (100%) rename sim/testsuite/{sim => }/frv/fditos.cgs (100%) rename sim/testsuite/{sim => }/frv/fdivd.cgs (100%) rename sim/testsuite/{sim => }/frv/fdivs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmas.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmovs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmss.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmulcs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/fdnegs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdsads.cgs (100%) rename sim/testsuite/{sim => }/frv/fdsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/fdstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/fdsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdtoi.cgs (100%) rename sim/testsuite/{sim => }/frv/fitod.cgs (100%) rename sim/testsuite/{sim => }/frv/fitos.cgs (100%) rename sim/testsuite/{sim => }/frv/fmad.cgs (100%) rename sim/testsuite/{sim => }/frv/fmaddd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fmas.cgs (100%) rename sim/testsuite/{sim => }/frv/fmovd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmovs.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmss.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsubd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fmuld.cgs (100%) rename sim/testsuite/{sim => }/frv/fmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/fnegd.cgs (100%) rename sim/testsuite/{sim => }/frv/fnegs.cgs (100%) rename sim/testsuite/{sim => }/frv/fnop.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/addss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr400/csdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/maddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/masaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/maveh.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhdseth.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhdsets.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsethih.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsethis.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsetloh.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsetlos.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/movgs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/movsg.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/msubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/scutss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/sdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/sdivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/slass.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smass.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smsss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/subss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/udiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/udivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/dcpl.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/dcul.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr550/cmaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/dcpl.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/dcul.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mabshs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/masaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdaddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdasaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdsubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmrdhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmrdhu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqxmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqxmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/msubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/msubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/msubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mtrap.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/udiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/udivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fsqrtd.cgs (100%) rename sim/testsuite/{sim => }/frv/fsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/fstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/fsubd.cgs (100%) rename sim/testsuite/{sim => }/frv/fsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fteq.cgs (100%) rename sim/testsuite/{sim => }/frv/ftge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftgt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftieq.cgs (100%) rename sim/testsuite/{sim => }/frv/ftige.cgs (100%) rename sim/testsuite/{sim => }/frv/ftigt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftile.cgs (100%) rename sim/testsuite/{sim => }/frv/ftilg.cgs (100%) rename sim/testsuite/{sim => }/frv/ftilt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftine.cgs (100%) rename sim/testsuite/{sim => }/frv/ftino.cgs (100%) rename sim/testsuite/{sim => }/frv/ftio.cgs (100%) rename sim/testsuite/{sim => }/frv/ftira.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiu.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiue.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiug.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiuge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiul.cgs (100%) rename sim/testsuite/{sim => }/frv/ftle.cgs (100%) rename sim/testsuite/{sim => }/frv/ftlg.cgs (100%) rename sim/testsuite/{sim => }/frv/ftlt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftne.cgs (100%) rename sim/testsuite/{sim => }/frv/ftno.cgs (100%) rename sim/testsuite/{sim => }/frv/fto.cgs (100%) rename sim/testsuite/{sim => }/frv/ftra.cgs (100%) rename sim/testsuite/{sim => }/frv/ftu.cgs (100%) rename sim/testsuite/{sim => }/frv/ftue.cgs (100%) rename sim/testsuite/{sim => }/frv/ftug.cgs (100%) rename sim/testsuite/{sim => }/frv/ftuge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftul.cgs (100%) rename sim/testsuite/{sim => }/frv/ftule.cgs (100%) rename sim/testsuite/{sim => }/frv/grloop.ms (100%) rename sim/testsuite/{sim => }/frv/hello.ms (100%) rename sim/testsuite/{sim => }/frv/icei.cgs (100%) rename sim/testsuite/{sim => }/frv/ici.cgs (100%) rename sim/testsuite/{sim => }/frv/icpl.cgs (100%) rename sim/testsuite/{sim => }/frv/icul.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts.exp (100%) rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr400.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr500.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/badalign-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/badalign.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/compound-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/compound.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/data_store_error-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/data_store_error.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/fp_exception-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/fp_exception.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/illinsn.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/mp_exception.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/privileged_instruction.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/regalign.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/reset.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/shadow_regs.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/timer.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpil.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.pcgs (100%) rename sim/testsuite/{sim => }/frv/ld.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldc.cgs (100%) rename sim/testsuite/{sim => }/frv/ldcu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldd.cgs (100%) rename sim/testsuite/{sim => }/frv/lddc.cgs (100%) rename sim/testsuite/{sim => }/frv/lddcu.cgs (100%) rename sim/testsuite/{sim => }/frv/lddf.cgs (100%) rename sim/testsuite/{sim => }/frv/lddfi.cgs (100%) rename sim/testsuite/{sim => }/frv/lddfu.cgs (100%) rename sim/testsuite/{sim => }/frv/lddi.cgs (100%) rename sim/testsuite/{sim => }/frv/lddu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldq.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqc.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqcu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsb.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsbi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsbu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsh.cgs (100%) rename sim/testsuite/{sim => }/frv/ldshi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldshu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldub.cgs (100%) rename sim/testsuite/{sim => }/frv/ldubi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldubu.cgs (100%) rename sim/testsuite/{sim => }/frv/lduh.cgs (100%) rename sim/testsuite/{sim => }/frv/lduhi.cgs (100%) rename sim/testsuite/{sim => }/frv/lduhu.cgs (100%) rename sim/testsuite/{sim => }/frv/lrbranch.pcgs (100%) rename sim/testsuite/{sim => }/frv/mabshs.cgs (100%) rename sim/testsuite/{sim => }/frv/maddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/maddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/mand.cgs (100%) rename sim/testsuite/{sim => }/frv/maveh.cgs (100%) rename sim/testsuite/{sim => }/frv/mbtoh.cgs (100%) rename sim/testsuite/{sim => }/frv/mbtohe.cgs (100%) rename sim/testsuite/{sim => }/frv/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/mcmpsh.cgs (100%) rename sim/testsuite/{sim => }/frv/mcmpuh.cgs (100%) rename sim/testsuite/{sim => }/frv/mcop1.cgs (100%) rename sim/testsuite/{sim => }/frv/mcop2.cgs (100%) rename sim/testsuite/{sim => }/frv/mcplhi.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpli.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxis.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxrs.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/mcut.cgs (100%) rename sim/testsuite/{sim => }/frv/mcuti.cgs (100%) rename sim/testsuite/{sim => }/frv/mcutss.cgs (100%) rename sim/testsuite/{sim => }/frv/mcutssi.cgs (100%) rename sim/testsuite/{sim => }/frv/mdaddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdasaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdcutssi.cgs (100%) rename sim/testsuite/{sim => }/frv/mdpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mdrotli.cgs (100%) rename sim/testsuite/{sim => }/frv/mdsubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdunpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/membar.cgs (100%) rename sim/testsuite/{sim => }/frv/mexpdhd.cgs (100%) rename sim/testsuite/{sim => }/frv/mexpdhw.cgs (100%) rename sim/testsuite/{sim => }/frv/mhdseth.cgs (100%) rename sim/testsuite/{sim => }/frv/mhdsets.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsethih.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsethis.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsetloh.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsetlos.cgs (100%) rename sim/testsuite/{sim => }/frv/mhtob.cgs (100%) rename sim/testsuite/{sim => }/frv/misc.exp (100%) rename sim/testsuite/{sim => }/frv/mmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmrdhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmrdhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulxhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mnop.cgs (100%) rename sim/testsuite/{sim => }/frv/mnot.cgs (100%) rename sim/testsuite/{sim => }/frv/mor.cgs (100%) rename sim/testsuite/{sim => }/frv/mov.cgs (100%) rename sim/testsuite/{sim => }/frv/movfg.cgs (100%) rename sim/testsuite/{sim => }/frv/movfgd.cgs (100%) rename sim/testsuite/{sim => }/frv/movfgq.cgs (100%) rename sim/testsuite/{sim => }/frv/movgf.cgs (100%) rename sim/testsuite/{sim => }/frv/movgfd.cgs (100%) rename sim/testsuite/{sim => }/frv/movgfq.cgs (100%) rename sim/testsuite/{sim => }/frv/movgs.cgs (100%) rename sim/testsuite/{sim => }/frv/movsg.cgs (100%) rename sim/testsuite/{sim => }/frv/mpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxis.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxrs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/mqlclrhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqlmths.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulxhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsaths.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsllhi.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsrahi.cgs (100%) rename sim/testsuite/{sim => }/frv/mqxmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqxmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mrdacc.cgs (100%) rename sim/testsuite/{sim => }/frv/mrdaccg.cgs (100%) rename sim/testsuite/{sim => }/frv/mrotli.cgs (100%) rename sim/testsuite/{sim => }/frv/mrotri.cgs (100%) rename sim/testsuite/{sim => }/frv/msaths.cgs (100%) rename sim/testsuite/{sim => }/frv/msathu.cgs (100%) rename sim/testsuite/{sim => }/frv/msllhi.cgs (100%) rename sim/testsuite/{sim => }/frv/msrahi.cgs (100%) rename sim/testsuite/{sim => }/frv/msrlhi.cgs (100%) rename sim/testsuite/{sim => }/frv/msubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/msubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/mtrap.cgs (100%) rename sim/testsuite/{sim => }/frv/munpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mwcut.cgs (100%) rename sim/testsuite/{sim => }/frv/mwcuti.cgs (100%) rename sim/testsuite/{sim => }/frv/mwtacc.cgs (100%) rename sim/testsuite/{sim => }/frv/mwtaccg.cgs (100%) rename sim/testsuite/{sim => }/frv/mxor.cgs (100%) rename sim/testsuite/{sim => }/frv/nandcr.cgs (100%) rename sim/testsuite/{sim => }/frv/nandncr.cgs (100%) rename sim/testsuite/{sim => }/frv/nfadds.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdadds.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/nfddivs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfditos.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdivs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmas.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmss.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmulcs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdsads.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfitos.cgs (100%) rename sim/testsuite/{sim => }/frv/nfmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/nfmas.cgs (100%) rename sim/testsuite/{sim => }/frv/nfmss.cgs (100%) rename sim/testsuite/{sim => }/frv/nfmsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/nfsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/nfstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/nfsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/nld.cgs (100%) rename sim/testsuite/{sim => }/frv/nldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldbfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldd.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddf.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddi.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldhf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldhfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldhfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldq.cgs (100%) rename sim/testsuite/{sim => }/frv/nldqf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldqfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldqfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldqu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldsb.cgs (100%) rename sim/testsuite/{sim => }/frv/nldsbi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldsbu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldsh.cgs (100%) rename sim/testsuite/{sim => }/frv/nldshi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldshu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldub.cgs (100%) rename sim/testsuite/{sim => }/frv/nldubi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldubu.cgs (100%) rename sim/testsuite/{sim => }/frv/nlduh.cgs (100%) rename sim/testsuite/{sim => }/frv/nlduhi.cgs (100%) rename sim/testsuite/{sim => }/frv/nlduhu.cgs (100%) rename sim/testsuite/{sim => }/frv/nop.cgs (100%) rename sim/testsuite/{sim => }/frv/norcr.cgs (100%) rename sim/testsuite/{sim => }/frv/norncr.cgs (100%) rename sim/testsuite/{sim => }/frv/not.cgs (100%) rename sim/testsuite/{sim => }/frv/notcr.cgs (100%) rename sim/testsuite/{sim => }/frv/nsdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/nsdivi.cgs (100%) rename sim/testsuite/{sim => }/frv/nudiv.cgs (100%) rename sim/testsuite/{sim => }/frv/nudivi.cgs (100%) rename sim/testsuite/{sim => }/frv/or.cgs (100%) rename sim/testsuite/{sim => }/frv/orcc.cgs (100%) rename sim/testsuite/{sim => }/frv/orcr.cgs (100%) rename sim/testsuite/{sim => }/frv/ori.cgs (100%) rename sim/testsuite/{sim => }/frv/oricc.cgs (100%) rename sim/testsuite/{sim => }/frv/orncr.cgs (100%) rename sim/testsuite/{sim => }/frv/parallel.exp (100%) rename sim/testsuite/{sim => }/frv/ret.cgs (100%) rename sim/testsuite/{sim => }/frv/rett.cgs (100%) rename sim/testsuite/{sim => }/frv/scan.cgs (100%) rename sim/testsuite/{sim => }/frv/scani.cgs (100%) rename sim/testsuite/{sim => }/frv/sdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/sdivi.cgs (100%) rename sim/testsuite/{sim => }/frv/sethi.cgs (100%) rename sim/testsuite/{sim => }/frv/sethilo.pcgs (100%) rename sim/testsuite/{sim => }/frv/setlo.cgs (100%) rename sim/testsuite/{sim => }/frv/setlos.cgs (100%) rename sim/testsuite/{sim => }/frv/sll.cgs (100%) rename sim/testsuite/{sim => }/frv/sllcc.cgs (100%) rename sim/testsuite/{sim => }/frv/slli.cgs (100%) rename sim/testsuite/{sim => }/frv/sllicc.cgs (100%) rename sim/testsuite/{sim => }/frv/smul.cgs (100%) rename sim/testsuite/{sim => }/frv/smulcc.cgs (100%) rename sim/testsuite/{sim => }/frv/smuli.cgs (100%) rename sim/testsuite/{sim => }/frv/smulicc.cgs (100%) rename sim/testsuite/{sim => }/frv/sra.cgs (100%) rename sim/testsuite/{sim => }/frv/sracc.cgs (100%) rename sim/testsuite/{sim => }/frv/srai.cgs (100%) rename sim/testsuite/{sim => }/frv/sraicc.cgs (100%) rename sim/testsuite/{sim => }/frv/srl.cgs (100%) rename sim/testsuite/{sim => }/frv/srlcc.cgs (100%) rename sim/testsuite/{sim => }/frv/srli.cgs (100%) rename sim/testsuite/{sim => }/frv/srlicc.cgs (100%) rename sim/testsuite/{sim => }/frv/st.cgs (100%) rename sim/testsuite/{sim => }/frv/stb.cgs (100%) rename sim/testsuite/{sim => }/frv/stbf.cgs (100%) rename sim/testsuite/{sim => }/frv/stbfi.cgs (100%) rename sim/testsuite/{sim => }/frv/stbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/stbi.cgs (100%) rename sim/testsuite/{sim => }/frv/stbu.cgs (100%) rename sim/testsuite/{sim => }/frv/stc.cgs (100%) rename sim/testsuite/{sim => }/frv/stcu.cgs (100%) rename sim/testsuite/{sim => }/frv/std.cgs (100%) rename sim/testsuite/{sim => }/frv/std.pcgs (100%) rename sim/testsuite/{sim => }/frv/stdc.cgs (100%) rename sim/testsuite/{sim => }/frv/stdc.pcgs (100%) rename sim/testsuite/{sim => }/frv/stdcu.cgs (100%) rename sim/testsuite/{sim => }/frv/stdf.cgs (100%) rename sim/testsuite/{sim => }/frv/stdf.pcgs (100%) rename sim/testsuite/{sim => }/frv/stdfi.cgs (100%) rename sim/testsuite/{sim => }/frv/stdfu.cgs (100%) rename sim/testsuite/{sim => }/frv/stdi.cgs (100%) rename sim/testsuite/{sim => }/frv/stdu.cgs (100%) rename sim/testsuite/{sim => }/frv/stf.cgs (100%) rename sim/testsuite/{sim => }/frv/stfi.cgs (100%) rename sim/testsuite/{sim => }/frv/stfu.cgs (100%) rename sim/testsuite/{sim => }/frv/sth.cgs (100%) rename sim/testsuite/{sim => }/frv/sthf.cgs (100%) rename sim/testsuite/{sim => }/frv/sthfi.cgs (100%) rename sim/testsuite/{sim => }/frv/sthfu.cgs (100%) rename sim/testsuite/{sim => }/frv/sthi.cgs (100%) rename sim/testsuite/{sim => }/frv/sthu.cgs (100%) rename sim/testsuite/{sim => }/frv/sti.cgs (100%) rename sim/testsuite/{sim => }/frv/stq.cgs (100%) rename sim/testsuite/{sim => }/frv/stq.pcgs (100%) rename sim/testsuite/{sim => }/frv/stqc.cgs (100%) rename sim/testsuite/{sim => }/frv/stqc.pcgs (100%) rename sim/testsuite/{sim => }/frv/stqcu.cgs (100%) rename sim/testsuite/{sim => }/frv/stqf.cgs (100%) rename sim/testsuite/{sim => }/frv/stqf.pcgs (100%) rename sim/testsuite/{sim => }/frv/stqfi.cgs (100%) rename sim/testsuite/{sim => }/frv/stqfu.cgs (100%) rename sim/testsuite/{sim => }/frv/stqi.cgs (100%) rename sim/testsuite/{sim => }/frv/stqu.cgs (100%) rename sim/testsuite/{sim => }/frv/stu.cgs (100%) rename sim/testsuite/{sim => }/frv/sub.cgs (100%) rename sim/testsuite/{sim => }/frv/subcc.cgs (100%) rename sim/testsuite/{sim => }/frv/subi.cgs (100%) rename sim/testsuite/{sim => }/frv/subicc.cgs (100%) rename sim/testsuite/{sim => }/frv/subx.cgs (100%) rename sim/testsuite/{sim => }/frv/subxcc.cgs (100%) rename sim/testsuite/{sim => }/frv/subxi.cgs (100%) rename sim/testsuite/{sim => }/frv/subxicc.cgs (100%) rename sim/testsuite/{sim => }/frv/swap.cgs (100%) rename sim/testsuite/{sim => }/frv/swapi.cgs (100%) rename sim/testsuite/{sim => }/frv/tc.cgs (100%) rename sim/testsuite/{sim => }/frv/teq.cgs (100%) rename sim/testsuite/{sim => }/frv/testutils.inc (100%) rename sim/testsuite/{sim => }/frv/tge.cgs (100%) rename sim/testsuite/{sim => }/frv/tgt.cgs (100%) rename sim/testsuite/{sim => }/frv/thi.cgs (100%) rename sim/testsuite/{sim => }/frv/tic.cgs (100%) rename sim/testsuite/{sim => }/frv/tieq.cgs (100%) rename sim/testsuite/{sim => }/frv/tige.cgs (100%) rename sim/testsuite/{sim => }/frv/tigt.cgs (100%) rename sim/testsuite/{sim => }/frv/tihi.cgs (100%) rename sim/testsuite/{sim => }/frv/tile.cgs (100%) rename sim/testsuite/{sim => }/frv/tils.cgs (100%) rename sim/testsuite/{sim => }/frv/tilt.cgs (100%) rename sim/testsuite/{sim => }/frv/tin.cgs (100%) rename sim/testsuite/{sim => }/frv/tinc.cgs (100%) rename sim/testsuite/{sim => }/frv/tine.cgs (100%) rename sim/testsuite/{sim => }/frv/tino.cgs (100%) rename sim/testsuite/{sim => }/frv/tinv.cgs (100%) rename sim/testsuite/{sim => }/frv/tip.cgs (100%) rename sim/testsuite/{sim => }/frv/tira.cgs (100%) rename sim/testsuite/{sim => }/frv/tiv.cgs (100%) rename sim/testsuite/{sim => }/frv/tle.cgs (100%) rename sim/testsuite/{sim => }/frv/tls.cgs (100%) rename sim/testsuite/{sim => }/frv/tlt.cgs (100%) rename sim/testsuite/{sim => }/frv/tn.cgs (100%) rename sim/testsuite/{sim => }/frv/tnc.cgs (100%) rename sim/testsuite/{sim => }/frv/tne.cgs (100%) rename sim/testsuite/{sim => }/frv/tno.cgs (100%) rename sim/testsuite/{sim => }/frv/tnv.cgs (100%) rename sim/testsuite/{sim => }/frv/tp.cgs (100%) rename sim/testsuite/{sim => }/frv/tra.cgs (100%) rename sim/testsuite/{sim => }/frv/tv.cgs (100%) rename sim/testsuite/{sim => }/frv/udiv.cgs (100%) rename sim/testsuite/{sim => }/frv/udivi.cgs (100%) rename sim/testsuite/{sim => }/frv/umul.cgs (100%) rename sim/testsuite/{sim => }/frv/umulcc.cgs (100%) rename sim/testsuite/{sim => }/frv/umuli.cgs (100%) rename sim/testsuite/{sim => }/frv/umulicc.cgs (100%) rename sim/testsuite/{sim => }/frv/xor.cgs (100%) rename sim/testsuite/{sim => }/frv/xorcc.cgs (100%) rename sim/testsuite/{sim => }/frv/xorcr.cgs (100%) rename sim/testsuite/{sim => }/frv/xori.cgs (100%) rename sim/testsuite/{sim => }/frv/xoricc.cgs (100%) rename sim/testsuite/{sim => }/ft32/ChangeLog (100%) rename sim/testsuite/{sim => }/ft32/allinsn.exp (100%) rename sim/testsuite/{sim => }/ft32/basic.s (100%) rename sim/testsuite/{sim => }/ft32/testutils.inc (100%) rename sim/testsuite/{sim => }/h8300/ChangeLog (100%) rename sim/testsuite/{sim => }/h8300/addb.s (100%) rename sim/testsuite/{sim => }/h8300/addl.s (100%) rename sim/testsuite/{sim => }/h8300/adds.s (100%) rename sim/testsuite/{sim => }/h8300/addw.s (100%) rename sim/testsuite/{sim => }/h8300/addx.s (100%) rename sim/testsuite/{sim => }/h8300/allinsn.exp (100%) rename sim/testsuite/{sim => }/h8300/andb.s (100%) rename sim/testsuite/{sim => }/h8300/andl.s (100%) rename sim/testsuite/{sim => }/h8300/andw.s (100%) rename sim/testsuite/{sim => }/h8300/band.s (100%) rename sim/testsuite/{sim => }/h8300/bfld.s (100%) rename sim/testsuite/{sim => }/h8300/biand.s (100%) rename sim/testsuite/{sim => }/h8300/bra.s (100%) rename sim/testsuite/{sim => }/h8300/brabc.s (100%) rename sim/testsuite/{sim => }/h8300/bset.s (100%) rename sim/testsuite/{sim => }/h8300/cmpb.s (100%) rename sim/testsuite/{sim => }/h8300/cmpl.s (100%) rename sim/testsuite/{sim => }/h8300/cmpw.s (100%) rename sim/testsuite/{sim => }/h8300/daa.s (100%) rename sim/testsuite/{sim => }/h8300/das.s (100%) rename sim/testsuite/{sim => }/h8300/dec.s (100%) rename sim/testsuite/{sim => }/h8300/div.s (100%) rename sim/testsuite/{sim => }/h8300/extl.s (100%) rename sim/testsuite/{sim => }/h8300/extw.s (100%) rename sim/testsuite/{sim => }/h8300/inc.s (100%) rename sim/testsuite/{sim => }/h8300/jmp.s (100%) rename sim/testsuite/{sim => }/h8300/ldc.s (100%) rename sim/testsuite/{sim => }/h8300/ldm.s (100%) rename sim/testsuite/{sim => }/h8300/mac.s (100%) rename sim/testsuite/{sim => }/h8300/mova.s (100%) rename sim/testsuite/{sim => }/h8300/movb.s (100%) rename sim/testsuite/{sim => }/h8300/movl.s (100%) rename sim/testsuite/{sim => }/h8300/movmd.s (100%) rename sim/testsuite/{sim => }/h8300/movsd.s (100%) rename sim/testsuite/{sim => }/h8300/movw.s (100%) rename sim/testsuite/{sim => }/h8300/mul.s (100%) rename sim/testsuite/{sim => }/h8300/neg.s (100%) rename sim/testsuite/{sim => }/h8300/nop.s (100%) rename sim/testsuite/{sim => }/h8300/not.s (100%) rename sim/testsuite/{sim => }/h8300/orb.s (100%) rename sim/testsuite/{sim => }/h8300/orl.s (100%) rename sim/testsuite/{sim => }/h8300/orw.s (100%) rename sim/testsuite/{sim => }/h8300/rotl.s (100%) rename sim/testsuite/{sim => }/h8300/rotr.s (100%) rename sim/testsuite/{sim => }/h8300/rotxl.s (100%) rename sim/testsuite/{sim => }/h8300/rotxr.s (100%) rename sim/testsuite/{sim => }/h8300/shal.s (100%) rename sim/testsuite/{sim => }/h8300/shar.s (100%) rename sim/testsuite/{sim => }/h8300/shll.s (100%) rename sim/testsuite/{sim => }/h8300/shlr.s (100%) rename sim/testsuite/{sim => }/h8300/stack.s (100%) rename sim/testsuite/{sim => }/h8300/stc.s (100%) rename sim/testsuite/{sim => }/h8300/subb.s (100%) rename sim/testsuite/{sim => }/h8300/subl.s (100%) rename sim/testsuite/{sim => }/h8300/subs.s (100%) rename sim/testsuite/{sim => }/h8300/subw.s (100%) rename sim/testsuite/{sim => }/h8300/subx.s (100%) rename sim/testsuite/{sim => }/h8300/tas.s (100%) rename sim/testsuite/{sim => }/h8300/testutils.inc (100%) rename sim/testsuite/{sim => }/h8300/xorb.s (100%) rename sim/testsuite/{sim => }/h8300/xorl.s (100%) rename sim/testsuite/{sim => }/h8300/xorw.s (100%) rename sim/testsuite/{sim => }/iq2000/ChangeLog (100%) rename sim/testsuite/{sim => }/iq2000/allinsn.exp (100%) rename sim/testsuite/{sim => }/iq2000/pass.s (100%) rename sim/testsuite/{sim => }/iq2000/testutils.inc (100%) rename sim/testsuite/{sim => }/lm32/ChangeLog (100%) rename sim/testsuite/{sim => }/lm32/allinsn.exp (100%) rename sim/testsuite/{sim => }/lm32/pass.s (100%) rename sim/testsuite/{sim => }/lm32/testutils.inc (100%) rename sim/testsuite/{sim => }/m32c/ChangeLog (100%) rename sim/testsuite/{sim => }/m32c/allinsn.exp (100%) rename sim/testsuite/{sim => }/m32c/blinky.s (100%) rename sim/testsuite/{sim => }/m32c/fail.s (100%) rename sim/testsuite/{sim => }/m32c/gloss.s (100%) rename sim/testsuite/{sim => }/m32c/pass.s (100%) rename sim/testsuite/{sim => }/m32c/sample.ld (100%) rename sim/testsuite/{sim => }/m32c/sample.s (100%) rename sim/testsuite/{sim => }/m32c/sample2.c (100%) rename sim/testsuite/{sim => }/m32c/testutils.inc (100%) rename sim/testsuite/{sim => }/m32r/ChangeLog (100%) rename sim/testsuite/{sim => }/m32r/add.cgs (100%) rename sim/testsuite/{sim => }/m32r/add3.cgs (100%) rename sim/testsuite/{sim => }/m32r/addi.cgs (100%) rename sim/testsuite/{sim => }/m32r/addv.cgs (100%) rename sim/testsuite/{sim => }/m32r/addv3.cgs (100%) rename sim/testsuite/{sim => }/m32r/addx.cgs (100%) rename sim/testsuite/{sim => }/m32r/allinsn.exp (100%) rename sim/testsuite/{sim => }/m32r/and.cgs (100%) rename sim/testsuite/{sim => }/m32r/and3.cgs (100%) rename sim/testsuite/{sim => }/m32r/bc24.cgs (100%) rename sim/testsuite/{sim => }/m32r/bc8.cgs (100%) rename sim/testsuite/{sim => }/m32r/beq.cgs (100%) rename sim/testsuite/{sim => }/m32r/beqz.cgs (100%) rename sim/testsuite/{sim => }/m32r/bgez.cgs (100%) rename sim/testsuite/{sim => }/m32r/bgtz.cgs (100%) rename sim/testsuite/{sim => }/m32r/bl24.cgs (100%) rename sim/testsuite/{sim => }/m32r/bl8.cgs (100%) rename sim/testsuite/{sim => }/m32r/blez.cgs (100%) rename sim/testsuite/{sim => }/m32r/bltz.cgs (100%) rename sim/testsuite/{sim => }/m32r/bnc24.cgs (100%) rename sim/testsuite/{sim => }/m32r/bnc8.cgs (100%) rename sim/testsuite/{sim => }/m32r/bne.cgs (100%) rename sim/testsuite/{sim => }/m32r/bnez.cgs (100%) rename sim/testsuite/{sim => }/m32r/bra24.cgs (100%) rename sim/testsuite/{sim => }/m32r/bra8.cgs (100%) rename sim/testsuite/{sim => }/m32r/cmp.cgs (100%) rename sim/testsuite/{sim => }/m32r/cmpi.cgs (100%) rename sim/testsuite/{sim => }/m32r/cmpu.cgs (100%) rename sim/testsuite/{sim => }/m32r/cmpui.cgs (100%) rename sim/testsuite/{sim => }/m32r/div.cgs (100%) rename sim/testsuite/{sim => }/m32r/divu.cgs (100%) rename sim/testsuite/{sim => }/m32r/exit47.ms (100%) rename sim/testsuite/{sim => }/m32r/hello.ms (100%) rename sim/testsuite/{sim => }/m32r/hw-trap.ms (100%) rename sim/testsuite/{sim => }/m32r/jl.cgs (100%) rename sim/testsuite/{sim => }/m32r/jmp.cgs (100%) rename sim/testsuite/{sim => }/m32r/ld-d.cgs (100%) rename sim/testsuite/{sim => }/m32r/ld-plus.cgs (100%) rename sim/testsuite/{sim => }/m32r/ld.cgs (100%) rename sim/testsuite/{sim => }/m32r/ld24.cgs (100%) rename sim/testsuite/{sim => }/m32r/ldb-d.cgs (100%) rename sim/testsuite/{sim => }/m32r/ldb.cgs (100%) rename sim/testsuite/{sim => }/m32r/ldh-d.cgs (100%) rename sim/testsuite/{sim => }/m32r/ldh.cgs (100%) rename sim/testsuite/{sim => }/m32r/ldi16.cgs (100%) rename sim/testsuite/{sim => }/m32r/ldi8.cgs (100%) rename sim/testsuite/{sim => }/m32r/ldub-d.cgs (100%) rename sim/testsuite/{sim => }/m32r/ldub.cgs (100%) rename sim/testsuite/{sim => }/m32r/lduh-d.cgs (100%) rename sim/testsuite/{sim => }/m32r/lduh.cgs (100%) rename sim/testsuite/{sim => }/m32r/lock.cgs (100%) rename sim/testsuite/{sim => }/m32r/machi.cgs (100%) rename sim/testsuite/{sim => }/m32r/maclo.cgs (100%) rename sim/testsuite/{sim => }/m32r/macwhi.cgs (100%) rename sim/testsuite/{sim => }/m32r/macwlo.cgs (100%) rename sim/testsuite/{sim => }/m32r/misc.exp (100%) rename sim/testsuite/{sim => }/m32r/mul.cgs (100%) rename sim/testsuite/{sim => }/m32r/mulhi.cgs (100%) rename sim/testsuite/{sim => }/m32r/mullo.cgs (100%) rename sim/testsuite/{sim => }/m32r/mulwhi.cgs (100%) rename sim/testsuite/{sim => }/m32r/mulwlo.cgs (100%) rename sim/testsuite/{sim => }/m32r/mv.cgs (100%) rename sim/testsuite/{sim => }/m32r/mvfachi.cgs (100%) rename sim/testsuite/{sim => }/m32r/mvfaclo.cgs (100%) rename sim/testsuite/{sim => }/m32r/mvfacmi.cgs (100%) rename sim/testsuite/{sim => }/m32r/mvfc.cgs (100%) rename sim/testsuite/{sim => }/m32r/mvtachi.cgs (100%) rename sim/testsuite/{sim => }/m32r/mvtaclo.cgs (100%) rename sim/testsuite/{sim => }/m32r/mvtc.cgs (100%) rename sim/testsuite/{sim => }/m32r/neg.cgs (100%) rename sim/testsuite/{sim => }/m32r/nop.cgs (100%) rename sim/testsuite/{sim => }/m32r/not.cgs (100%) rename sim/testsuite/{sim => }/m32r/or.cgs (100%) rename sim/testsuite/{sim => }/m32r/or3.cgs (100%) rename sim/testsuite/{sim => }/m32r/rac.cgs (100%) rename sim/testsuite/{sim => }/m32r/rach.cgs (100%) rename sim/testsuite/{sim => }/m32r/rem.cgs (100%) rename sim/testsuite/{sim => }/m32r/remu.cgs (100%) rename sim/testsuite/{sim => }/m32r/rte.cgs (100%) rename sim/testsuite/{sim => }/m32r/seth.cgs (100%) rename sim/testsuite/{sim => }/m32r/sll.cgs (100%) rename sim/testsuite/{sim => }/m32r/sll3.cgs (100%) rename sim/testsuite/{sim => }/m32r/slli.cgs (100%) rename sim/testsuite/{sim => }/m32r/sra.cgs (100%) rename sim/testsuite/{sim => }/m32r/sra3.cgs (100%) rename sim/testsuite/{sim => }/m32r/srai.cgs (100%) rename sim/testsuite/{sim => }/m32r/srl.cgs (100%) rename sim/testsuite/{sim => }/m32r/srl3.cgs (100%) rename sim/testsuite/{sim => }/m32r/srli.cgs (100%) rename sim/testsuite/{sim => }/m32r/st-d.cgs (100%) rename sim/testsuite/{sim => }/m32r/st-minus.cgs (100%) rename sim/testsuite/{sim => }/m32r/st-plus.cgs (100%) rename sim/testsuite/{sim => }/m32r/st.cgs (100%) rename sim/testsuite/{sim => }/m32r/stb-d.cgs (100%) rename sim/testsuite/{sim => }/m32r/stb.cgs (100%) rename sim/testsuite/{sim => }/m32r/sth-d.cgs (100%) rename sim/testsuite/{sim => }/m32r/sth.cgs (100%) rename sim/testsuite/{sim => }/m32r/sub.cgs (100%) rename sim/testsuite/{sim => }/m32r/subv.cgs (100%) rename sim/testsuite/{sim => }/m32r/subx.cgs (100%) rename sim/testsuite/{sim => }/m32r/testutils.inc (100%) rename sim/testsuite/{sim => }/m32r/trap.cgs (100%) rename sim/testsuite/{sim => }/m32r/unlock.cgs (100%) rename sim/testsuite/{sim => }/m32r/uread16.ms (100%) rename sim/testsuite/{sim => }/m32r/uread32.ms (100%) rename sim/testsuite/{sim => }/m32r/uwrite16.ms (100%) rename sim/testsuite/{sim => }/m32r/uwrite32.ms (100%) rename sim/testsuite/{sim => }/m32r/xor.cgs (100%) rename sim/testsuite/{sim => }/m32r/xor3.cgs (100%) rename sim/testsuite/{sim => }/m68hc11/ChangeLog (100%) rename sim/testsuite/{sim => }/m68hc11/allinsn.exp (100%) rename sim/testsuite/{sim => }/m68hc11/pass.s (100%) rename sim/testsuite/{sim => }/m68hc11/testutils.inc (100%) rename sim/testsuite/{sim => }/mcore/ChangeLog (100%) rename sim/testsuite/{sim => }/mcore/allinsn.exp (100%) rename sim/testsuite/{sim => }/mcore/fail.s (100%) rename sim/testsuite/{sim => }/mcore/pass.s (100%) rename sim/testsuite/{sim => }/mcore/testutils.inc (100%) rename sim/testsuite/{sim => }/microblaze/ChangeLog (100%) rename sim/testsuite/{sim => }/microblaze/allinsn.exp (100%) rename sim/testsuite/{sim => }/microblaze/pass.s (100%) rename sim/testsuite/{sim => }/microblaze/testutils.inc (100%) rename sim/testsuite/{sim => }/mips/ChangeLog (100%) rename sim/testsuite/{sim => }/mips/basic.exp (100%) rename sim/testsuite/{sim => }/mips/fpu64-ps-sb1.s (100%) rename sim/testsuite/{sim => }/mips/fpu64-ps.s (100%) rename sim/testsuite/{sim => }/mips/hilo-hazard-1.s (100%) rename sim/testsuite/{sim => }/mips/hilo-hazard-2.s (100%) rename sim/testsuite/{sim => }/mips/hilo-hazard-3.s (100%) rename sim/testsuite/{sim => }/mips/hilo-hazard-4.s (100%) rename sim/testsuite/{sim => }/mips/mdmx-ob-sb1.s (100%) rename sim/testsuite/{sim => }/mips/mdmx-ob.s (100%) rename sim/testsuite/{sim => }/mips/mips32-dsp.s (100%) rename sim/testsuite/{sim => }/mips/mips32-dsp2.s (100%) rename sim/testsuite/{sim => }/mips/sanity.s (100%) rename sim/testsuite/{sim => }/mips/testutils.inc (100%) rename sim/testsuite/{sim => }/mips/utils-dsp.inc (100%) rename sim/testsuite/{sim => }/mips/utils-fpu.inc (100%) rename sim/testsuite/{sim => }/mips/utils-mdmx.inc (100%) rename sim/testsuite/{sim => }/mn10300/ChangeLog (100%) rename sim/testsuite/{sim => }/mn10300/allinsn.exp (100%) rename sim/testsuite/{sim => }/mn10300/pass.s (100%) rename sim/testsuite/{sim => }/mn10300/testutils.inc (100%) rename sim/testsuite/{sim => }/moxie/ChangeLog (100%) rename sim/testsuite/{sim => }/moxie/allinsn.exp (100%) rename sim/testsuite/{sim => }/moxie/pass.s (100%) rename sim/testsuite/{sim => }/moxie/testutils.inc (100%) rename sim/testsuite/{sim => }/msp430/ChangeLog (100%) rename sim/testsuite/{sim => }/msp430/add.s (100%) rename sim/testsuite/{sim => }/msp430/allinsn.exp (100%) rename sim/testsuite/{sim => }/msp430/mpyull_hwmult.s (100%) rename sim/testsuite/{sim => }/msp430/rrux.s (100%) rename sim/testsuite/{sim => }/msp430/testutils.inc (100%) rename sim/testsuite/{sim => }/or1k/ChangeLog (100%) rename sim/testsuite/{sim => }/or1k/add.S (100%) rename sim/testsuite/{sim => }/or1k/adrp.S (100%) rename sim/testsuite/{sim => }/or1k/alltests.exp (100%) rename sim/testsuite/{sim => }/or1k/and.S (100%) rename sim/testsuite/{sim => }/or1k/basic.S (100%) rename sim/testsuite/{sim => }/or1k/div.S (100%) rename sim/testsuite/{sim => }/or1k/ext.S (100%) rename sim/testsuite/{sim => }/or1k/find.S (100%) rename sim/testsuite/{sim => }/or1k/flag.S (100%) rename sim/testsuite/{sim => }/or1k/fpu-unordered.S (100%) rename sim/testsuite/{sim => }/or1k/fpu.S (100%) rename sim/testsuite/{sim => }/or1k/fpu64a32-unordered.S (100%) rename sim/testsuite/{sim => }/or1k/fpu64a32.S (100%) rename sim/testsuite/{sim => }/or1k/jump.S (100%) rename sim/testsuite/{sim => }/or1k/load.S (100%) rename sim/testsuite/{sim => }/or1k/mac.S (100%) rename sim/testsuite/{sim => }/or1k/mfspr.S (100%) rename sim/testsuite/{sim => }/or1k/mul.S (100%) rename sim/testsuite/{sim => }/or1k/or.S (100%) rename sim/testsuite/{sim => }/or1k/or1k-asm-test-env.h (100%) rename sim/testsuite/{sim => }/or1k/or1k-asm-test-helpers.h (100%) rename sim/testsuite/{sim => }/or1k/or1k-asm-test.h (100%) rename sim/testsuite/{sim => }/or1k/or1k-asm.h (100%) rename sim/testsuite/{sim => }/or1k/or1k-test.ld (100%) rename sim/testsuite/{sim => }/or1k/ror.S (100%) rename sim/testsuite/{sim => }/or1k/shift.S (100%) rename sim/testsuite/{sim => }/or1k/spr-defs.h (100%) rename sim/testsuite/{sim => }/or1k/sub.S (100%) rename sim/testsuite/{sim => }/or1k/xor.S (100%) rename sim/testsuite/{sim => }/pru/ChangeLog (100%) rename sim/testsuite/{sim => }/pru/add.s (100%) rename sim/testsuite/{sim => }/pru/allinsn.exp (100%) rename sim/testsuite/{sim => }/pru/dmem-zero-pass.s (100%) rename sim/testsuite/{sim => }/pru/dmem-zero-trap.s (100%) rename sim/testsuite/{sim => }/pru/dram.s (100%) rename sim/testsuite/{sim => }/pru/jmp.s (100%) rename sim/testsuite/{sim => }/pru/lmbd.s (100%) rename sim/testsuite/{sim => }/pru/loop-imm.s (100%) rename sim/testsuite/{sim => }/pru/loop-reg.s (100%) rename sim/testsuite/{sim => }/pru/mul.s (100%) rename sim/testsuite/{sim => }/pru/subreg.s (100%) rename sim/testsuite/{sim => }/pru/testutils.inc (100%) rename sim/testsuite/{sim => }/sh/ChangeLog (100%) rename sim/testsuite/{sim => }/sh/add.s (100%) rename sim/testsuite/{sim => }/sh/allinsn.exp (100%) rename sim/testsuite/{sim => }/sh/and.s (100%) rename sim/testsuite/{sim => }/sh/bandor.s (100%) rename sim/testsuite/{sim => }/sh/bandornot.s (100%) rename sim/testsuite/{sim => }/sh/bclr.s (100%) rename sim/testsuite/{sim => }/sh/bld.s (100%) rename sim/testsuite/{sim => }/sh/bldnot.s (100%) rename sim/testsuite/{sim => }/sh/bset.s (100%) rename sim/testsuite/{sim => }/sh/bst.s (100%) rename sim/testsuite/{sim => }/sh/bxor.s (100%) rename sim/testsuite/{sim => }/sh/clip.s (100%) rename sim/testsuite/{sim => }/sh/div.s (100%) rename sim/testsuite/{sim => }/sh/dmxy.s (100%) rename sim/testsuite/{sim => }/sh/fabs.s (100%) rename sim/testsuite/{sim => }/sh/fadd.s (100%) rename sim/testsuite/{sim => }/sh/fail.s (100%) rename sim/testsuite/{sim => }/sh/fcmpeq.s (100%) rename sim/testsuite/{sim => }/sh/fcmpgt.s (100%) rename sim/testsuite/{sim => }/sh/fcnvds.s (100%) rename sim/testsuite/{sim => }/sh/fcnvsd.s (100%) rename sim/testsuite/{sim => }/sh/fdiv.s (100%) rename sim/testsuite/{sim => }/sh/fipr.s (100%) rename sim/testsuite/{sim => }/sh/fldi0.s (100%) rename sim/testsuite/{sim => }/sh/fldi1.s (100%) rename sim/testsuite/{sim => }/sh/flds.s (100%) rename sim/testsuite/{sim => }/sh/float.s (100%) rename sim/testsuite/{sim => }/sh/fmac.s (100%) rename sim/testsuite/{sim => }/sh/fmov.s (100%) rename sim/testsuite/{sim => }/sh/fmul.s (100%) rename sim/testsuite/{sim => }/sh/fneg.s (100%) rename sim/testsuite/{sim => }/sh/fpchg.s (100%) rename sim/testsuite/{sim => }/sh/frchg.s (100%) rename sim/testsuite/{sim => }/sh/fsca.s (100%) rename sim/testsuite/{sim => }/sh/fschg.s (100%) rename sim/testsuite/{sim => }/sh/fsqrt.s (100%) rename sim/testsuite/{sim => }/sh/fsrra.s (100%) rename sim/testsuite/{sim => }/sh/fsub.s (100%) rename sim/testsuite/{sim => }/sh/ftrc.s (100%) rename sim/testsuite/{sim => }/sh/ldrc.s (100%) rename sim/testsuite/{sim => }/sh/loop.s (100%) rename sim/testsuite/{sim => }/sh/macl.s (100%) rename sim/testsuite/{sim => }/sh/macw.s (100%) rename sim/testsuite/{sim => }/sh/mov.s (100%) rename sim/testsuite/{sim => }/sh/movi.s (100%) rename sim/testsuite/{sim => }/sh/movli.s (100%) rename sim/testsuite/{sim => }/sh/movua.s (100%) rename sim/testsuite/{sim => }/sh/movxy.s (100%) rename sim/testsuite/{sim => }/sh/mulr.s (100%) rename sim/testsuite/{sim => }/sh/pabs.s (100%) rename sim/testsuite/{sim => }/sh/padd.s (100%) rename sim/testsuite/{sim => }/sh/paddc.s (100%) rename sim/testsuite/{sim => }/sh/pand.s (100%) rename sim/testsuite/{sim => }/sh/pass.s (100%) rename sim/testsuite/{sim => }/sh/pclr.s (100%) rename sim/testsuite/{sim => }/sh/pdec.s (100%) rename sim/testsuite/{sim => }/sh/pdmsb.s (100%) rename sim/testsuite/{sim => }/sh/pinc.s (100%) rename sim/testsuite/{sim => }/sh/pmuls.s (100%) rename sim/testsuite/{sim => }/sh/prnd.s (100%) rename sim/testsuite/{sim => }/sh/pshai.s (100%) rename sim/testsuite/{sim => }/sh/pshar.s (100%) rename sim/testsuite/{sim => }/sh/pshli.s (100%) rename sim/testsuite/{sim => }/sh/pshlr.s (100%) rename sim/testsuite/{sim => }/sh/psub.s (100%) rename sim/testsuite/{sim => }/sh/pswap.s (100%) rename sim/testsuite/{sim => }/sh/pushpop.s (100%) rename sim/testsuite/{sim => }/sh/resbank.s (100%) rename sim/testsuite/{sim => }/sh/sett.s (100%) rename sim/testsuite/{sim => }/sh/shll.s (100%) rename sim/testsuite/{sim => }/sh/shll16.s (100%) rename sim/testsuite/{sim => }/sh/shll2.s (100%) rename sim/testsuite/{sim => }/sh/shll8.s (100%) rename sim/testsuite/{sim => }/sh/shlr.s (100%) rename sim/testsuite/{sim => }/sh/shlr16.s (100%) rename sim/testsuite/{sim => }/sh/shlr2.s (100%) rename sim/testsuite/{sim => }/sh/shlr8.s (100%) rename sim/testsuite/{sim => }/sh/swap.s (100%) rename sim/testsuite/{sim => }/sh/testutils.inc (100%) rename sim/testsuite/{sim => }/v850/ChangeLog (100%) rename sim/testsuite/{sim => }/v850/allinsns.exp (100%) rename sim/testsuite/{sim => }/v850/bsh.cgs (100%) rename sim/testsuite/{sim => }/v850/div.cgs (100%) rename sim/testsuite/{sim => }/v850/divh.cgs (100%) rename sim/testsuite/{sim => }/v850/divh_3.cgs (100%) rename sim/testsuite/{sim => }/v850/divhu.cgs (100%) rename sim/testsuite/{sim => }/v850/divu.cgs (100%) rename sim/testsuite/{sim => }/v850/sar.cgs (100%) rename sim/testsuite/{sim => }/v850/satadd.cgs (100%) rename sim/testsuite/{sim => }/v850/satsub.cgs (100%) rename sim/testsuite/{sim => }/v850/satsubi.cgs (100%) rename sim/testsuite/{sim => }/v850/satsubr.cgs (100%) rename sim/testsuite/{sim => }/v850/shl.cgs (100%) rename sim/testsuite/{sim => }/v850/shr.cgs (100%) rename sim/testsuite/{sim => }/v850/testutils.cgs (100%) rename sim/testsuite/{sim => }/v850/testutils.inc (100%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allnoconfig updated (ed324553 -> 22fcc7b1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allnoconfig in repository toolchain/ci/base-artifacts. discards ed324553 0: update: binutils-gcc-linux-qemu: boot new 22fcc7b1 0: update: binutils-gcc-linux-qemu: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (ed324553) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-aarch6 [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 167 +- 02-prepare_abe/console.log | 340 +- 03-build_abe-binutils/console.log | 12179 +++++----- 04-build_abe-stage1/console.log | 16198 ++++++------- 05-build_linux/console.log | 772 +- 06-build_abe-qemu/console.log | 6844 +++--- 07-boot_linux/console.log | 4 +- 08-check_regression/console.log | 14 +- 08-check_regression/results.regressions | 3 +- 09-update_baseline/console.log | 18 +- 09-update_baseline/results.regressions | 3 +- console.log | 36536 +++++++++++++++--------------- jenkins/manifest.sh | 16 +- 13 files changed, 36588 insertions(+), 36506 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allyesconfig updated (7c79721606 -> 7cb6b97300)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allyesconfig in repository toolchain/ci/qemu. from 7c79721606 Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-t [...] adds 8cd0b410a2 target/mips: Add CP0 Config0 register definitions for MIPS3 ISA adds b4cbbb47b0 target/mips: Replace CP0_Config0 magic values by proper definitions adds 07ae8ccd0f target/mips/addr: Add translation helpers for KSEG1 adds 737cca57d3 target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment adds bf5523773e target/mips/mips-defs: Reorder CPU_MIPS5 definition adds 8b0ea9b638 target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1 adds b0586b38cb target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit() adds ce49581feb hw/mips/boston: Check 64-bit support with cpu_type_is_64bit() adds 08e2262fad target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1 adds f395cef765 target/mips/mips-defs: Use ISA_MIPS32R2 definition to check [...] adds 4d1524d2ce target/mips/mips-defs: Use ISA_MIPS32R3 definition to check [...] adds d913c3992d target/mips/mips-defs: Use ISA_MIPS32R5 definition to check [...] adds 13514fc93e target/mips/mips-defs: Use ISA_MIPS32R6 definition to check [...] adds bbd5e4a27f target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 adds 7a47bae586 target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 adds bae4b15aa4 target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 adds 5f89ce4fc2 target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 adds 2e211e0a12 target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 adds 9bcd41d41f target/mips: Inline cpu_state_reset() in mips_cpu_reset() adds 81ddae7c30 target/mips: Extract FPU helpers to 'fpu_helper.h' adds f9bd3d79f4 target/mips: Add !CONFIG_USER_ONLY comment after #endif adds 2be565f9c2 target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs adds e9927723ba target/mips: Move common helpers from helper.c to cpu.c adds 4cb213dc90 target/mips: Rename helper.c as tlb_helper.c adds ca2690e36a target/mips: Fix code style for checkpatch.pl adds f2c5b39ecd target/mips: Move mmu_init() functions to tlb_helper.c adds 0dc351ca6b target/mips: Rename translate_init.c as cpu-defs.c adds e31309365e target/mips/translate: Extract DisasContext structure adds 46c9e2b3dd target/mips/translate: Add declarations for generic code adds 11a7511856 target/mips: Replace gen_exception_err(err=0) by gen_excepti [...] adds 3a4ef3b7ee target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_ [...] adds 8758d1b8aa target/mips: Declare generic FPU / Coprocessor functions in [...] adds 57eedcf7e3 target/mips: Extract FPU specific definitions to translate.h adds 8b7322add3 target/mips: Only build TCG code when CONFIG_TCG is set adds 311edee771 target/mips/translate: Extract decode_opc_legacy() from deco [...] adds d7efb69382 target/mips/translate: Expose check_mips_64() to 32-bit mode adds 25a1362875 target/mips: Introduce ase_msa_available() helper adds 72f31f60f8 target/mips: Simplify msa_reset() adds aa314198ca target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA adds 33942f9460 target/mips: Simplify MSA TCG logic adds 7e2a619a04 target/mips: Remove now unused ASE_MSA definition adds e2665f314d target/mips: Alias MSA vector registers on FPU scalar registers adds 959c5da28e target/mips: Extract msa_translate_init() from mips_tcg_init() adds 63af5b9018 target/mips: Remove CPUMIPSState* argument from gen_msa*() methods adds 810fda17c8 target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() adds 03e4d95c91 target/mips: Move msa_reset() to msa_helper.c adds 3ef60574b6 target/mips: Extract MSA helpers from op_helper.c adds edb2384728 target/mips: Extract MSA helper definitions adds 54ccff5102 target/mips: Declare gen_msa/_branch() in 'translate.h' adds 80e64a380f target/mips: Extract MSA translation routines adds 878b87b541 target/mips: Pass TCGCond argument to MSA gen_check_zero_element() adds c7a9ef7517 target/mips: Introduce decode tree bindings for MSA ASE adds 96e5b4c758 target/mips: Use decode_ase_msa() generated from decodetree adds a685f7d075 target/mips: Extract LSA/DLSA translation generators adds 5f21f30d85 target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes adds 3f7a927847 target/mips: Introduce decodetree helpers for Release6 LSA/D [...] adds 0e9524af2d target/mips: Remove now unreachable LSA/DLSA opcodes code adds aac357ec89 target/mips: Convert Rel6 Special2 opcode to decodetree adds ddc7ef8dfe target/mips: Convert Rel6 COP1X opcode to decodetree adds 6513ca15d8 target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree adds 9a7372e354 target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree adds dd5697b2f9 target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree adds 13a839cf48 target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree adds 1ff668dde2 target/mips: Convert Rel6 LLD/SCD opcodes to decodetree adds 27ea1bc077 target/mips: Convert Rel6 LL/SC opcodes to decodetree adds 6648042afb target/mips: Remove CPU_R5900 definition adds fc63010e9b target/mips: Remove CPU_NANOMIPS32 definition adds eaca85763b target/mips: Remove vendor specific CPU definitions adds cd669e2051 docs/system: Remove deprecated 'fulong2e' machine alias adds 256af05f52 Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mip [...] adds 89fbea8737 9pfs: Fully restart unreclaim loop (CVE-2021-20181) adds a968a38005 Merge remote-tracking branch 'remotes/gkurz-gitlab/tags/9p-n [...] adds e80be993b5 ui/gtk: don't try to redefine SI prefixes adds 0431e369b0 ui/gtk: rename variable window to widget adds 3c4b8f8310 ui/gtk: limit virtual console max update interval adds 0fdc99775c ui/gtk: expose gd_monitor_update_interval adds cab82424f6 ui/gtk: update monitor interval on egl displays adds 521534df57 vnc: fix unfinalized tlscreds for VncDisplay adds 7b5fa0b583 ui: add support for remote power control to VNC server adds 5f8679fe46 vnc: Fix a memleak in vnc_display_connect() adds b3c2de9cd5 vnc: move check into vnc_cursor_define adds 9e1632ad07 vnc: move initialization to framebuffer_update_request adds 763deea7e9 vnc: add support for extended desktop resize adds 7cb6b97300 Merge remote-tracking branch 'remotes/kraxel/tags/ui-2021011 [...] No new revisions were added by this update. Summary of changes: docs/system/deprecated.rst | 5 - docs/system/removed-features.rst | 5 + hw/9pfs/9p.c | 6 +- hw/mips/boston.c | 6 +- hw/mips/fuloong2e.c | 1 - include/ui/gtk.h | 3 +- linux-user/mips/cpu_loop.c | 7 +- qemu-options.hx | 4 + target/mips/addr.c | 10 + target/mips/cp0_helper.c | 18 +- target/mips/cp0_timer.c | 4 +- .../mips/{translate_init.c.inc => cpu-defs.c.inc} | 128 +- target/mips/cpu.c | 255 +- target/mips/cpu.h | 23 +- target/mips/fpu_helper.c | 5 +- target/mips/fpu_helper.h | 59 + target/mips/gdbstub.c | 1 + target/mips/helper.h | 436 +-- target/mips/internal.h | 64 +- target/mips/kvm.c | 13 +- target/mips/machine.c | 1 + target/mips/meson.build | 21 +- target/mips/mips-defs.h | 56 +- target/mips/mips32r6.decode | 36 + target/mips/mips64r6.decode | 27 + target/mips/msa32.decode | 29 + target/mips/msa64.decode | 17 + target/mips/msa_helper.c | 430 +++ target/mips/msa_helper.h.inc | 443 +++ target/mips/msa_translate.c | 2286 +++++++++++ target/mips/op_helper.c | 396 +- target/mips/rel6_translate.c | 44 + target/mips/{helper.c => tlb_helper.c} | 266 +- target/mips/translate.c | 4034 ++++---------------- target/mips/translate.h | 177 + target/mips/translate_addr_const.c | 61 + ui/gtk-egl.c | 3 + ui/gtk.c | 25 +- ui/vnc.c | 147 +- ui/vnc.h | 15 + 40 files changed, 5016 insertions(+), 4551 deletions(-) rename target/mips/{translate_init.c.inc => cpu-defs.c.inc} (92%) create mode 100644 target/mips/fpu_helper.h create mode 100644 target/mips/mips32r6.decode create mode 100644 target/mips/mips64r6.decode create mode 100644 target/mips/msa32.decode create mode 100644 target/mips/msa64.decode create mode 100644 target/mips/msa_helper.h.inc create mode 100644 target/mips/msa_translate.c create mode 100644 target/mips/rel6_translate.c rename target/mips/{helper.c => tlb_helper.c} (87%) create mode 100644 target/mips/translate.h create mode 100644 target/mips/translate_addr_const.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allyesconfig updated (b0ccd3922f5 -> 2c356f221bb)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allyesconfig in repository toolchain/ci/gcc. from b0ccd3922f5 compiler: add support for reading embedcfg files adds c4eec1efae0 testsuite: Fix sed script errors in complex tests adds 2ea6f4a377e tree-optimization/98685 - fix placement of extern converts adds 7432f255b70 arm: Auto-vectorization for MVE: vshl adds bfab355012c arm: Auto-vectorization for MVE: vshr adds 0411ae7f08e libatomic, libgomp, libitc: Fix bootstrap [PR70454] adds cb60334b716 testsuite/96098 - remove redundant testcase adds 1a630642009 arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics adds d03f14c354a testsuite/96147 - remove scanning for ! vect_hw_misalign adds e1bd80fb706 testsuite/96147 - key scanning on vect_hw_misalign adds aa4ee5798fe testsuite/96147 - scan for vectorized load adds b36c9cd0947 testsuite/96147 - align vector access adds dc8475e3348 Pytest in tests: improve adds 446703ccc2c tree-optimization/96376 - do not check alignment for invari [...] adds f1d054017ef Revert "arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 [...] adds 63999d751df arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics adds f9a577927eb IBM Z: Fix linking to libatomic in target test cases adds 7f6cdaa9a8d rtl-ssa: Fix a silly typo adds f2cc526f47a recog: Fix insn_change_watermark destructor adds 5a783f42d77 aarch64: Add a minipass for fusing CC insns [PR88836] adds 492b90f33df c++: Fix langspecs with -fsyntax-only [PR98591] adds 1ba71fabb78 preprocessor: Make quoting : [PR 95253] adds 7d0df0aeb67 i386: Use cpp_define_formatted for __SIZEOF_FLOAT80__ definition adds d3959070aa4 [PATCH] aarch64: Implement vmlsl[_high]* intrinsics using builtins adds 50dbced2f37 openmp: Change the way of building of reduction array type adds adb520606ce c-family: Improve MEM_REF printing for diagnostics [PR98597] adds a3128bf0128 bootstrap: fix failing diagnostic selftest on Windows [PR98696] adds aaec739250b testsuite: Add testcase coverage for already fixed [PR96671] adds c0194736b47 gcc.dg/analyzer tests: use __builtin_alloca, not alloca.h adds cd09079cfd5 c++: Fix list-init of array of no-copy type [PR63707] adds ad260343385 AArch64: Add NEON, SVE and SVE2 RTL patterns for Multiply, [...] adds 424deca72b6 c++: Fix copy elision for base initialization adds d75199f7823 c++: Avoid redundant copy in {} init [PR98642] adds e63c2161d09 drop -dumpbase-ext from producer string adds 5c046034e3e match.pd: Optimize (x < 0) ^ (y < 0) to (x ^ y) < 0 etc. [PR96681] adds 0425f4c1b63 match.pd: Generalize the PR64309 simplifications [PR96669] adds e1efa6af61a preprocessor: Make quoting : [PR 95253] adds 9beb6d88eff c++: Fix qualified array-type construction [PR 98538] adds b90e4a97419 fortran: Fixes a bug in ISO_Fortran_binding.c. adds c029fcb5680 Reset force_source_line in final.c adds f1ad419ebfd rs6000, vector integer multiply/divide/modulo instructions adds 2f7f0d32e74 Daily bump. adds 2c356f221bb libstdc++-v3: Add -fcf-protection=none to -march=i486 No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 170 +++++++++ gcc/DATESTAMP | 2 +- gcc/Makefile.in | 7 + gcc/c-family/ChangeLog | 12 + gcc/c-family/c-pretty-print.c | 259 +++++++++++--- gcc/c/ChangeLog | 6 + gcc/c/c-typeck.c | 4 +- gcc/config.gcc | 2 +- gcc/config/aarch64/aarch64-cc-fusion.cc | 296 +++++++++++++++ gcc/config/aarch64/aarch64-passes.def | 1 + gcc/config/aarch64/aarch64-protos.h | 1 + gcc/config/aarch64/aarch64-simd-builtins.def | 8 + gcc/config/aarch64/aarch64-simd.md | 56 ++- gcc/config/aarch64/aarch64-sve.md | 56 +++ gcc/config/aarch64/aarch64-sve2.md | 42 +++ gcc/config/aarch64/arm_neon.h | 84 +---- gcc/config/aarch64/iterators.md | 109 +++++- gcc/config/aarch64/t-aarch64 | 6 + gcc/config/arm/arm_neon.h | 31 ++ gcc/config/arm/mve.md | 47 ++- gcc/config/arm/neon.md | 53 --- gcc/config/arm/vec-common.md | 58 +++ gcc/config/i386/i386-c.c | 9 +- gcc/config/rs6000/altivec.h | 4 + gcc/config/rs6000/altivec.md | 2 - gcc/config/rs6000/rs6000-builtin.def | 21 ++ gcc/config/rs6000/rs6000-call.c | 53 +++ gcc/config/rs6000/rs6000.md | 5 +- gcc/config/rs6000/vsx.md | 211 ++++++++--- gcc/cp/ChangeLog | 35 ++ gcc/cp/call.c | 145 ++++++-- gcc/cp/cp-tree.h | 3 +- gcc/cp/lang-specs.h | 40 ++- gcc/cp/tree.c | 18 +- gcc/cp/typeck2.c | 21 +- gcc/diagnostic.c | 12 +- gcc/doc/extend.texi | 120 +++++++ gcc/doc/install.texi | 2 +- gcc/doc/sourcebuild.texi | 4 + gcc/final.c | 1 + gcc/go/ChangeLog | 4 + gcc/match.pd | 39 +- gcc/opts.c | 1 + gcc/recog.h | 8 +- gcc/rtl-ssa/functions.h | 2 +- gcc/rtl-ssa/member-fns.inl | 2 +- gcc/testsuite/ChangeLog | 156 ++++++++ gcc/testsuite/g++.dg/cpp0x/initlist-array13.C | 16 + gcc/testsuite/g++.dg/cpp1z/elide4.C | 24 ++ gcc/testsuite/g++.dg/cpp1z/elide5.C | 15 + gcc/testsuite/g++.dg/modules/dep-1_a.C | 4 +- gcc/testsuite/g++.dg/modules/dep-1_b.C | 4 +- gcc/testsuite/g++.dg/modules/dep-2.C | 6 +- gcc/testsuite/g++.dg/modules/pr98591.H | 3 + gcc/testsuite/g++.dg/template/pr98538.C | 18 + gcc/testsuite/gcc.dg/analyzer/alloca-leak.c | 4 +- gcc/testsuite/gcc.dg/analyzer/data-model-1.c | 5 +- gcc/testsuite/gcc.dg/analyzer/malloc-1.c | 3 +- gcc/testsuite/gcc.dg/analyzer/malloc-paths-8.c | 7 +- gcc/testsuite/gcc.dg/tree-ssa/pr96669-1.c | 59 +++ gcc/testsuite/gcc.dg/tree-ssa/pr96671-1.c | 51 +++ gcc/testsuite/gcc.dg/tree-ssa/pr96671-2.c | 51 +++ gcc/testsuite/gcc.dg/tree-ssa/pr96681.c | 35 ++ gcc/testsuite/gcc.dg/uninit-38.c | 80 ++--- gcc/testsuite/gcc.dg/uninit-40.c | 50 +++ gcc/testsuite/gcc.dg/vect/bb-slp-32.c | 1 + gcc/testsuite/gcc.dg/vect/bb-slp-9.c | 2 +- gcc/testsuite/gcc.dg/vect/bb-slp-pr68892.c | 20 -- gcc/testsuite/gcc.dg/vect/bb-slp-pr98685.c | 15 + .../gcc.dg/vect/complex/complex-mla-template.c | 28 +- .../gcc.dg/vect/complex/complex-mls-template.c | 28 +- gcc/testsuite/gcc.dg/vect/slp-43.c | 4 +- gcc/testsuite/gcc.dg/vect/slp-45.c | 2 +- .../aarch64/advsimd-intrinsics/p64_p128.c | 46 ++- .../gcc.target/aarch64/sve/acle/general/ldff1_8.c | 32 ++ gcc/testsuite/gcc.target/aarch64/sve/ptest_1.c | 10 + gcc/testsuite/gcc.target/arm/simd/mve-vshl.c | 62 ++++ gcc/testsuite/gcc.target/arm/simd/mve-vshr.c | 59 +++ gcc/testsuite/gcc.target/arm/simd/vceqz_p64.c | 17 + gcc/testsuite/gcc.target/arm/simd/vceqzq_p64.c | 17 + .../gcc.target/powerpc/builtins-1-p10-runnable.c | 398 +++++++++++++++++++++ .../gcc.target/s390/md/atomic_exchange-1.c | 2 +- gcc/testsuite/gcc.target/s390/s390.exp | 4 + .../iso_fortran_binding_uint8_array.f90 | 11 + .../iso_fortran_binding_uint8_array_driver.c | 25 ++ gcc/testsuite/lib/gcov.exp | 31 +- gcc/tree-vect-slp.c | 11 +- gcc/tree-vect-stmts.c | 23 +- libatomic/ChangeLog | 9 + libatomic/configure.tgt | 56 +-- libcpp/ChangeLog | 5 + libcpp/mkdeps.c | 1 - libgfortran/ChangeLog | 6 + libgfortran/runtime/ISO_Fortran_binding.c | 3 +- libgomp/ChangeLog | 7 + libgomp/configure.tgt | 35 +- libitm/ChangeLog | 7 + libitm/configure.tgt | 37 +- .../atomic_flag/test_and_set/explicit-hle.cc | 2 +- 99 files changed, 3167 insertions(+), 512 deletions(-) create mode 100644 gcc/config/aarch64/aarch64-cc-fusion.cc create mode 100644 gcc/testsuite/g++.dg/cpp0x/initlist-array13.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/elide4.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/elide5.C create mode 100644 gcc/testsuite/g++.dg/modules/pr98591.H create mode 100644 gcc/testsuite/g++.dg/template/pr98538.C create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr96669-1.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr96671-1.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr96671-2.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr96681.c create mode 100644 gcc/testsuite/gcc.dg/uninit-40.c delete mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-pr68892.c create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-pr98685.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/ldff1_8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/ptest_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vshl.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vshr.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vceqz_p64.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vceqzq_p64.c create mode 100644 gcc/testsuite/gcc.target/powerpc/builtins-1-p10-runnable.c create mode 100644 gcc/testsuite/gfortran.dg/iso_fortran_binding_uint8_array.f90 create mode 100644 gcc/testsuite/gfortran.dg/iso_fortran_binding_uint8_array_driver.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

Tcwg-commits January 2021