Tcwg-commits December 2020

tcwg-commits@lists.linaro.org

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11568 discussions

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-stable-allyesconfig updated (d104e582838 -> 43ff75f2c3f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-stable-allyesconfig in repository toolchain/ci/llvm-project. from d104e582838 [CMake] Avoid __FakeVCSRevision.h with no git repository adds 9caca7241d4 [AArch64][GlobalISel] Use the look-through constant helper [...] adds 43ff75f2c3f [AArch64][GlobalISel] Promote scalar G_SHL constant shift a [...] No new revisions were added by this update. Summary of changes: .../Target/AArch64/GISel/AArch64LegalizerInfo.cpp | 38 +++++++++++++--------- .../AArch64/GlobalISel/legalize-merge-values.mir | 5 +-- .../GlobalISel/legalize-non-pow2-load-store.mir | 7 ++-- .../CodeGen/AArch64/GlobalISel/legalize-shift.mir | 4 +-- .../AArch64/GlobalISel/legalize-unmerge-values.mir | 5 +-- llvm/test/CodeGen/AArch64/arm64-clrsb.ll | 4 +-- 6 files changed, 35 insertions(+), 28 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-stable-allyesconfig updated (3892144d -> 9a2f148d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-stable-allyesconfig in repository toolchain/ci/base-artifacts. discards 3892144d 0: update: llvm-linux-qemu: all new 9a2f148d 0: update: llvm-linux-qemu: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (3892144d) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-aarc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 156 +- 02-prepare_abe/console.log | 442 +- 03-build_llvm/console.log | 13235 +++++++++++++------------- 04-build_linux/console.log | 900 +- 05-build_abe-qemu/console.log | 4291 +++++---- 06-boot_linux/console.log | 6 +- 07-check_regression/console.log | 12 +- 08-update_baseline/console.log | 12 +- console.log | 19054 +++++++++++++++++++------------------- jenkins/manifest.sh | 10 +- 10 files changed, 19073 insertions(+), 19045 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allmodconfig updated (75ee62ac60 -> a05f8ecd88)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allmodconfig in repository toolchain/ci/qemu. from 75ee62ac60 Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-n [...] adds 10b43754cf hw/riscv: sifive_u: Add UART1 DT node in the generated DTB adds dfc973ecc1 hw/riscv: microchip_pfsoc: add QSPI NOR flash adds b3d2a4296f hw/core/register.c: Don't use '#' flag of printf format adds c63ca4ff7f target/riscv: Fix the bug of HLVX/HLV/HSV adds 529577457c target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR adds 54a581c228 intc/ibex_plic: Clear interrupts that occur during claim process adds 617448a46b hw/riscv: Expand the is 32-bit check to support more CPUs adds c0a635f397 target/riscv: Add a TYPE_RISCV_CPU_BASE CPU adds dc4d4aaee3 riscv: spike: Remove target macro conditionals adds 09fe17125e riscv: virt: Remove target macro conditionals adds 7893677184 hw/riscv: boot: Remove compile time XLEN checks adds 9d01143063 hw/riscv: virt: Remove compile time XLEN checks adds bd62c13ea8 hw/riscv: spike: Remove compile time XLEN checks adds 2206ffa68f hw/riscv: sifive_u: Remove compile time XLEN checks adds 5b6c291b8d target/riscv: fpu_helper: Match function defs in HELPER macros adds 51ae0cabc6 target/riscv: Add a riscv_cpu_is_32bit() helper function adds 114baaca51 target/riscv: Specify the XLEN for CPUs adds 5c5a47f10c target/riscv: cpu: Remove compile time XLEN checks adds f08c7ff3dc target/riscv: cpu_helper: Remove compile time XLEN checks adds 8987cdc481 target/riscv: csr: Remove compile time XLEN checks adds 094b072c68 target/riscv: cpu: Set XLEN independently from target adds 3ed2b8ac2d hw/riscv: Use the CPU to determine if 32-bit adds d31e970a01 riscv/opentitan: Update the OpenTitan memory layout adds a05f8ecd88 Merge remote-tracking branch 'remotes/alistair/tags/pull-ris [...] No new revisions were added by this update. Summary of changes: hw/core/register.c | 16 ++-- hw/intc/ibex_plic.c | 13 ++- hw/riscv/boot.c | 70 ++++++++------- hw/riscv/microchip_pfsoc.c | 21 +++++ hw/riscv/opentitan.c | 81 ++++++++++++----- hw/riscv/sifive_u.c | 74 ++++++++++------ hw/riscv/spike.c | 52 ++++++----- hw/riscv/virt.c | 39 ++++---- include/hw/riscv/boot.h | 14 +-- include/hw/riscv/microchip_pfsoc.h | 3 + include/hw/riscv/opentitan.h | 23 +++-- include/hw/riscv/spike.h | 6 -- include/hw/riscv/virt.h | 6 -- target/riscv/cpu.c | 84 ++++++++++++------ target/riscv/cpu.h | 8 ++ target/riscv/cpu_bits.h | 8 +- target/riscv/cpu_helper.c | 15 ++-- target/riscv/csr.c | 176 +++++++++++++++++++------------------ target/riscv/fpu_helper.c | 8 -- target/riscv/helper.h | 24 ++--- 20 files changed, 434 insertions(+), 307 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allmodconfig updated (35b8d268746 -> 8b604594652)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allmodconfig in repository toolchain/ci/gcc. from 35b8d268746 arm: Add support for Cortex-A78C adds cd69e3d5cd6 Daily bump. adds 20f292863f6 c++: Diagnose unstable satisfaction adds 79f57d5cb07 c++: Diagnose self-recursive satisfaction adds 731a32b3fa7 c++: More precise tracking of potentially unstable satisfaction adds e3f0eaa2829 libstdc++: Import parts of the Ryu library adds 5033506993e libstdc++: Apply modifications to our local copy of Ryu adds 3c57e692357 libstdc++: Add floating-point std::to_chars implementation adds ddb9c661c2f libstdc++: Import MSVC floating-point std::to_chars testcases adds dc00689332f Go testsuite: handle +build lines correctly adds 11f07ef3778 c++: Fix PCH ICE with __builtin_source_location [PR98343] adds ce8dcc9105c As well as the PR this patch fixes problems in handling cla [...] adds 785b49434d2 c++: Fix windows binary files [PR 98362] adds bcac28716bb Arm: MVE: Add missing complex mul iterators adds 7ff5706fcd7 aarch64: Extend aarch64-autovec-preference==2 to 128-bit SVE adds 3af02d32cce openmp: Implicitly add 'declare target' directives for dyna [...] adds 266d7464756 libstdc++: Check FE_TONEAREST is defined before using it adds d7bab388b81 libstdc++: Fix build failure due to missing <langinfo.h> [PR98374] adds 22a7e82c200 libstdc++: Fix build failure on AArch64 ILP32 [PR98370] adds 60cecb2b83f libstdc++: Fix mistake in PR98374 change [PR98377] adds d44d47b4926 aarch64: SVE: ICE in expand_direct_optab_fn [PR98177] adds 5dc998933e7 libcc1: Fix up libcc1 configure [PR98330] new bfb37fa4dd4 openmp: Fix g++.dg/gomp/declare-target-3.C testcase when of [...] new 8b604594652 openmp: Don't optimize shared to firstprivate on task with [...] The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: ChangeLog | 4 + c++tools/ChangeLog | 21 + contrib/ChangeLog | 5 + gcc/ChangeLog | 69 + gcc/DATESTAMP | 2 +- gcc/ada/ChangeLog | 370 + gcc/config/aarch64/aarch64.c | 9 +- gcc/config/arm/iterators.md | 4 + gcc/cp/ChangeLog | 11 + gcc/cp/constraint.cc | 336 +- gcc/cp/cp-gimplify.c | 15 + gcc/cp/cp-lang.c | 32 + gcc/cp/cp-tree.h | 6 + gcc/cp/decl.c | 5 + gcc/cp/decl2.c | 7 + gcc/cp/module.cc | 23 +- gcc/cp/pt.c | 9 +- gcc/cp/typeck.c | 1 + gcc/fortran/ChangeLog | 12 + gcc/fortran/resolve.c | 2 +- gcc/fortran/trans-array.c | 448 +- gcc/fortran/trans-expr.c | 264 +- gcc/fortran/trans.c | 16 +- gcc/fortran/trans.h | 1 + gcc/gimplify.c | 12 + gcc/langhooks-def.h | 8 +- gcc/langhooks.c | 16 + gcc/langhooks.h | 10 + gcc/omp-offload.c | 11 +- gcc/testsuite/ChangeLog | 33 + gcc/testsuite/g++.dg/cpp2a/concepts-complete1.C | 18 + gcc/testsuite/g++.dg/cpp2a/concepts-complete2.C | 23 + gcc/testsuite/g++.dg/cpp2a/concepts-complete3.C | 16 + gcc/testsuite/g++.dg/cpp2a/concepts-pr88395.C | 8 +- .../g++.dg/cpp2a/concepts-recursive-sat2.C | 6 +- .../g++.dg/cpp2a/concepts-recursive-sat4.C | 13 + gcc/testsuite/g++.dg/gomp/declare-target-3.C | 31 + gcc/testsuite/g++.dg/pch/pr98343.C | 6 + gcc/testsuite/g++.dg/pch/pr98343.Hs | 18 + gcc/testsuite/g++.target/aarch64/sve/pr98177-1.C | 10 + gcc/testsuite/g++.target/aarch64/sve/pr98177-2.C | 10 + gcc/testsuite/gcc.target/aarch64/sve/pr98177-1.c | 10 + gcc/testsuite/gcc.target/aarch64/sve/pr98177-2.c | 10 + gcc/testsuite/gfortran.dg/class_allocate_25.f90 | 58 + gcc/testsuite/gfortran.dg/class_assign_4.f90 | 183 + gcc/testsuite/gfortran.dg/dependency_60.f90 | 19 + .../gfortran.dg/unlimited_polymorphic_32.f03 | 59 + gcc/testsuite/go.test/go-test.exp | 147 +- gcc/testsuite/go.test/test/fixedbugs/bug302.go | 2 +- gcc/testsuite/go.test/test/fixedbugs/bug369.go | 2 +- gcc/testsuite/go.test/test/fixedbugs/issue10607.go | 2 +- gcc/testsuite/go.test/test/fixedbugs/issue11771.go | 2 +- gcc/testsuite/go.test/test/fixedbugs/issue13268.go | 1 + gcc/testsuite/go.test/test/fixedbugs/issue14636.go | 2 +- .../go.test/test/fixedbugs/issue16037_run.go | 2 +- gcc/testsuite/go.test/test/fixedbugs/issue19658.go | 2 +- gcc/testsuite/go.test/test/fixedbugs/issue21317.go | 6 +- gcc/testsuite/go.test/test/fixedbugs/issue21576.go | 2 +- gcc/testsuite/go.test/test/fixedbugs/issue22660.go | 6 +- .../go.test/test/fixedbugs/issue33275_run.go | 2 +- gcc/testsuite/go.test/test/fixedbugs/issue33555.go | 2 +- gcc/testsuite/go.test/test/fixedbugs/issue36437.go | 2 +- gcc/testsuite/go.test/test/fixedbugs/issue9355.go | 6 +- .../go.test/test/fixedbugs/issue9862_run.go | 2 +- gcc/testsuite/go.test/test/run.go | 2 +- gcc/tree-vect-loop.c | 8 +- libcc1/configure | 2 +- libcc1/configure.ac | 2 +- libcody/ChangeLog | 10 + libgomp/testsuite/libgomp.c/task-6.c | 47 + libstdc++-v3/ChangeLog | 33 + libstdc++-v3/config/abi/pre/gnu.ver | 7 + libstdc++-v3/include/std/charconv | 24 + libstdc++-v3/src/c++17/Makefile.am | 1 + libstdc++-v3/src/c++17/Makefile.in | 3 +- libstdc++-v3/src/c++17/floating_from_chars.cc | 4 +- libstdc++-v3/src/c++17/floating_to_chars.cc | 1567 + libstdc++-v3/src/c++17/ryu/MERGE | 4 + libstdc++-v3/src/c++17/ryu/common.h | 95 + libstdc++-v3/src/c++17/ryu/d2fixed.c | 737 + libstdc++-v3/src/c++17/ryu/d2fixed_full_table.h | 4419 ++ libstdc++-v3/src/c++17/ryu/d2s.c | 485 + libstdc++-v3/src/c++17/ryu/d2s_full_table.h | 367 + libstdc++-v3/src/c++17/ryu/d2s_intrinsics.h | 354 + libstdc++-v3/src/c++17/ryu/digit_table.h | 35 + libstdc++-v3/src/c++17/ryu/f2s.c | 321 + libstdc++-v3/src/c++17/ryu/f2s_intrinsics.h | 124 + libstdc++-v3/src/c++17/ryu/generic_128.c | 305 + libstdc++-v3/src/c++17/ryu/generic_128.h | 517 + libstdc++-v3/src/c++17/ryu/ryu_generic_128.h | 70 + libstdc++-v3/testsuite/20_util/to_chars/double.cc | 57000 +++++++++++++++++++ libstdc++-v3/testsuite/20_util/to_chars/float.cc | 4142 ++ .../testsuite/20_util/to_chars/long_double.cc | 199 + 93 files changed, 72990 insertions(+), 344 deletions(-) create mode 100644 gcc/testsuite/g++.dg/cpp2a/concepts-complete1.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/concepts-complete2.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/concepts-complete3.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/concepts-recursive-sat4.C create mode 100644 gcc/testsuite/g++.dg/gomp/declare-target-3.C create mode 100644 gcc/testsuite/g++.dg/pch/pr98343.C create mode 100644 gcc/testsuite/g++.dg/pch/pr98343.Hs create mode 100644 gcc/testsuite/g++.target/aarch64/sve/pr98177-1.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/pr98177-2.C create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr98177-1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr98177-2.c create mode 100644 gcc/testsuite/gfortran.dg/class_allocate_25.f90 create mode 100644 gcc/testsuite/gfortran.dg/class_assign_4.f90 create mode 100644 gcc/testsuite/gfortran.dg/dependency_60.f90 create mode 100644 gcc/testsuite/gfortran.dg/unlimited_polymorphic_32.f03 create mode 100644 libgomp/testsuite/libgomp.c/task-6.c create mode 100644 libstdc++-v3/src/c++17/floating_to_chars.cc create mode 100644 libstdc++-v3/src/c++17/ryu/MERGE create mode 100644 libstdc++-v3/src/c++17/ryu/common.h create mode 100644 libstdc++-v3/src/c++17/ryu/d2fixed.c create mode 100644 libstdc++-v3/src/c++17/ryu/d2fixed_full_table.h create mode 100644 libstdc++-v3/src/c++17/ryu/d2s.c create mode 100644 libstdc++-v3/src/c++17/ryu/d2s_full_table.h create mode 100644 libstdc++-v3/src/c++17/ryu/d2s_intrinsics.h create mode 100644 libstdc++-v3/src/c++17/ryu/digit_table.h create mode 100644 libstdc++-v3/src/c++17/ryu/f2s.c create mode 100644 libstdc++-v3/src/c++17/ryu/f2s_intrinsics.h create mode 100644 libstdc++-v3/src/c++17/ryu/generic_128.c create mode 100644 libstdc++-v3/src/c++17/ryu/generic_128.h create mode 100644 libstdc++-v3/src/c++17/ryu/ryu_generic_128.h create mode 100644 libstdc++-v3/testsuite/20_util/to_chars/double.cc create mode 100644 libstdc++-v3/testsuite/20_util/to_chars/float.cc create mode 100644 libstdc++-v3/testsuite/20_util/to_chars/long_double.cc -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allmodconfig updated (844a65387c -> e51765f932)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allmodconfig in repository toolchain/ci/binutils-gdb. from 844a65387c Remove a use of n_spaces adds 3ece0b9527 Automatic date update in version.in adds 7f3a18cfb5 Statically initialise target common sections adds bd38246a45 Constify more arrays adds 7fbd5f4e2c Remove some static buffers adds 3fafa2e26e Assorted tidies adds 04f8967487 elf: Copy elf_gnu_osabi_retain only for relocatable link adds eba7b68cb0 ld: Build and install only unversioned libdep adds 86ef42bd73 Run fixed_points.exp with -fgnat-encodings=minimal adds a9e48095a8 gdb: define COFF file offsets with file_ptr new b3f9469bfa Fix accessing a method's fields from Python new 4aea001fd8 Add address keyword to Value.format_string new e846045952 Remove erroneous 'a' in gdb.register_window_type documentation new e51765f932 Fix name of main_type field type in pretty printer The 4 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: bfd/ChangeLog | 73 ++++++++++++++ bfd/archive.c | 4 +- bfd/coff-mcore.c | 3 +- bfd/coff-z80.c | 2 +- bfd/ecoff.c | 102 +++++--------------- bfd/elf32-csky.c | 4 +- bfd/elf32-m32c.c | 2 +- bfd/elf32-m32r.c | 20 +--- bfd/elf32-m68hc11.c | 6 +- bfd/elf32-microblaze.c | 2 - bfd/elf32-nds32.c | 2 +- bfd/elf32-ppc.c | 12 ++- bfd/elf32-rl78.c | 2 +- bfd/elf32-rx.c | 13 +-- bfd/elf32-score.c | 20 +--- bfd/elf32-score7.c | 22 ++--- bfd/elf32-tic6x.c | 20 +--- bfd/elf32-v850.c | 82 ++++++---------- bfd/elf32-z80.c | 2 +- bfd/elf64-mmix.c | 20 +--- bfd/elf64-ppc.c | 10 +- bfd/elflink.c | 4 +- bfd/elfxx-mips.c | 40 ++------ bfd/libbfd-in.h | 4 +- bfd/libbfd.h | 4 +- bfd/mach-o.c | 7 +- bfd/opncls.c | 4 +- bfd/peXXigen.c | 11 ++- bfd/som.c | 2 +- bfd/targets.c | 6 +- bfd/version.h | 2 +- bfd/vms-alpha.c | 3 +- bfd/vms-misc.c | 3 +- bfd/vms.h | 2 +- bfd/xtensa-isa.c | 4 +- gas/ChangeLog | 5 + gas/ecoff.c | 25 ++--- gdb/ChangeLog | 22 +++++ gdb/coffread.c | 30 +++--- gdb/doc/ChangeLog | 8 ++ gdb/doc/python.texi | 7 +- gdb/gdb-gdb.py.in | 2 +- gdb/python/py-type.c | 1 + gdb/python/py-value.c | 7 +- gdb/testsuite/ChangeLog | 13 +++ gdb/testsuite/gdb.ada/fixed_points.exp | 134 ++++++++++++++------------ gdb/testsuite/gdb.python/py-format-string.exp | 43 +++++++++ gdb/testsuite/gdb.python/py-type.exp | 3 + include/ChangeLog | 8 ++ include/opcode/arc-attrs.h | 2 +- include/xtensa-isa-internal.h | 3 - ld/ChangeLog | 16 +++ ld/Makefile.am | 9 +- ld/Makefile.in | 21 ++-- ld/testsuite/ld-elf/retain7.s | 5 + ld/testsuite/ld-elf/retain7a.d | 11 +++ ld/testsuite/ld-elf/retain7b.d | 10 ++ 57 files changed, 502 insertions(+), 402 deletions(-) create mode 100644 ld/testsuite/ld-elf/retain7.s create mode 100644 ld/testsuite/ld-elf/retain7a.d create mode 100644 ld/testsuite/ld-elf/retain7b.d -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allmodconfig updated (40ef39e4 -> 83db4975)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allmodconfig in repository toolchain/ci/base-artifacts. discards 40ef39e4 0: update: binutils-gcc-linux-qemu: all new 83db4975 0: update: binutils-gcc-linux-qemu: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (40ef39e4) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-aarch6 [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 143 +- 02-prepare_abe/console.log | 420 +- 03-build_abe-binutils/console.log | 11978 ++++----- 04-build_abe-stage1/console.log | 16222 ++++++------ 05-build_linux/console.log | 6400 ++--- 06-build_abe-qemu/console.log | 6513 ++--- 07-boot_linux/console.log | 2 +- 08-check_regression/console.log | 28 +- 08-check_regression/results.regressions | 2 +- 09-update_baseline/console.log | 10 +- 09-update_baseline/results.regressions | 2 +- console.log | 41716 +++++++++++++++--------------- jenkins/manifest.sh | 18 +- 13 files changed, 41727 insertions(+), 41727 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allmodconfig updated (d104e582838 -> 43ff75f2c3f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allmodconfig in repository toolchain/ci/llvm-project. from d104e582838 [CMake] Avoid __FakeVCSRevision.h with no git repository adds 9caca7241d4 [AArch64][GlobalISel] Use the look-through constant helper [...] adds 43ff75f2c3f [AArch64][GlobalISel] Promote scalar G_SHL constant shift a [...] No new revisions were added by this update. Summary of changes: .../Target/AArch64/GISel/AArch64LegalizerInfo.cpp | 38 +++++++++++++--------- .../AArch64/GlobalISel/legalize-merge-values.mir | 5 +-- .../GlobalISel/legalize-non-pow2-load-store.mir | 7 ++-- .../CodeGen/AArch64/GlobalISel/legalize-shift.mir | 4 +-- .../AArch64/GlobalISel/legalize-unmerge-values.mir | 5 +-- llvm/test/CodeGen/AArch64/arm64-clrsb.ll | 4 +-- 6 files changed, 35 insertions(+), 28 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allmodconfig updated (aabc7e7d -> e6693844)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allmodconfig in repository toolchain/ci/base-artifacts. discards aabc7e7d 0: update: llvm-linux-qemu: all new e6693844 0: update: llvm-linux-qemu: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (aabc7e7d) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-aarc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 235 +- 02-prepare_abe/console.log | 212 +- 03-build_llvm/console.log | 13241 +++++++-------- 04-build_linux/console.log | 14786 ++++++++--------- 05-build_abe-qemu/console.log | 4668 +++--- 06-boot_linux/console.log | 6 +- 07-check_regression/console.log | 34 +- 08-update_baseline/console.log | 14 +- console.log | 33196 +++++++++++++++++++------------------- jenkins/manifest.sh | 10 +- 10 files changed, 33213 insertions(+), 33189 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[gcc] branch master updated (8b604594652 -> 0e9f2b2dc8d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 8b604594652 openmp: Don't optimize shared to firstprivate on task with [...] new 0e9f2b2dc8d Re: [r11-6232 Regression] FAIL: gcc.dg/pr97750.c The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/testsuite/gcc.dg/pr97750.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig updated (75ee62ac60 -> a05f8ecd88)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig in repository toolchain/ci/qemu. from 75ee62ac60 Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-n [...] adds 10b43754cf hw/riscv: sifive_u: Add UART1 DT node in the generated DTB adds dfc973ecc1 hw/riscv: microchip_pfsoc: add QSPI NOR flash adds b3d2a4296f hw/core/register.c: Don't use '#' flag of printf format adds c63ca4ff7f target/riscv: Fix the bug of HLVX/HLV/HSV adds 529577457c target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR adds 54a581c228 intc/ibex_plic: Clear interrupts that occur during claim process adds 617448a46b hw/riscv: Expand the is 32-bit check to support more CPUs adds c0a635f397 target/riscv: Add a TYPE_RISCV_CPU_BASE CPU adds dc4d4aaee3 riscv: spike: Remove target macro conditionals adds 09fe17125e riscv: virt: Remove target macro conditionals adds 7893677184 hw/riscv: boot: Remove compile time XLEN checks adds 9d01143063 hw/riscv: virt: Remove compile time XLEN checks adds bd62c13ea8 hw/riscv: spike: Remove compile time XLEN checks adds 2206ffa68f hw/riscv: sifive_u: Remove compile time XLEN checks adds 5b6c291b8d target/riscv: fpu_helper: Match function defs in HELPER macros adds 51ae0cabc6 target/riscv: Add a riscv_cpu_is_32bit() helper function adds 114baaca51 target/riscv: Specify the XLEN for CPUs adds 5c5a47f10c target/riscv: cpu: Remove compile time XLEN checks adds f08c7ff3dc target/riscv: cpu_helper: Remove compile time XLEN checks adds 8987cdc481 target/riscv: csr: Remove compile time XLEN checks adds 094b072c68 target/riscv: cpu: Set XLEN independently from target adds 3ed2b8ac2d hw/riscv: Use the CPU to determine if 32-bit adds d31e970a01 riscv/opentitan: Update the OpenTitan memory layout adds a05f8ecd88 Merge remote-tracking branch 'remotes/alistair/tags/pull-ris [...] No new revisions were added by this update. Summary of changes: hw/core/register.c | 16 ++-- hw/intc/ibex_plic.c | 13 ++- hw/riscv/boot.c | 70 ++++++++------- hw/riscv/microchip_pfsoc.c | 21 +++++ hw/riscv/opentitan.c | 81 ++++++++++++----- hw/riscv/sifive_u.c | 74 ++++++++++------ hw/riscv/spike.c | 52 ++++++----- hw/riscv/virt.c | 39 ++++---- include/hw/riscv/boot.h | 14 +-- include/hw/riscv/microchip_pfsoc.h | 3 + include/hw/riscv/opentitan.h | 23 +++-- include/hw/riscv/spike.h | 6 -- include/hw/riscv/virt.h | 6 -- target/riscv/cpu.c | 84 ++++++++++++------ target/riscv/cpu.h | 8 ++ target/riscv/cpu_bits.h | 8 +- target/riscv/cpu_helper.c | 15 ++-- target/riscv/csr.c | 176 +++++++++++++++++++------------------ target/riscv/fpu_helper.c | 8 -- target/riscv/helper.h | 24 ++--- 20 files changed, 434 insertions(+), 307 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

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Tcwg-commits December 2020