Tcwg-commits September 2019

tcwg-commits@lists.linaro.org

5 participants
14312 discussions

[gcc] branch master updated (b33daee6bc7 -> 0f5caaa9b5f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from b33daee6bc7 [PATCH] some tree struct marking new 7da48f4c2f8 PR rtl-optimization/89435 PR rtl-optimization/89795 PR r [...] new 25f120f074c Fix libstdc++ tests for -Wvolatile warnings in C++2a mode new 0f5caaa9b5f Fix Xmethod for shared_ptr::use_count() The 3 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/testsuite/ChangeLog | 9 ++++++++ gcc/testsuite/gcc.dg/pr89435.c | 21 ++++++++++++++++++ gcc/testsuite/gcc.dg/pr89795.c | 25 ++++++++++++++++++++++ gcc/testsuite/gcc.dg/pr91720.c | 22 +++++++++++++++++++ libstdc++-v3/ChangeLog | 10 +++++++++ libstdc++-v3/python/libstdcxx/v6/xmethods.py | 2 +- .../20_util/result_of/sfinae_friendly_1.cc | 11 +++++----- .../testsuite/tr1/3_function_objects/result_of.cc | 2 ++ 8 files changed, 96 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/pr89435.c create mode 100644 gcc/testsuite/gcc.dg/pr89795.c create mode 100644 gcc/testsuite/gcc.dg/pr91720.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[gcc] branch gcc-9-branch updated (99f8fa968d7 -> f539f18a218)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch gcc-9-branch in repository gcc. from 99f8fa968d7 PR rtl-optimization/89795 * rtlanal.c (nonzero_bits1) <SU [...] new f539f18a218 Fix Xmethod for shared_ptr::use_count() The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: libstdc++-v3/ChangeLog | 5 +++++ libstdc++-v3/python/libstdcxx/v6/xmethods.py | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[gcc] branch gcc-8-branch updated (b47012f099d -> 0bd84bf0318)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch gcc-8-branch in repository gcc. from b47012f099d PR rtl-optimization/89795 * rtlanal.c (nonzero_bits1) <SU [...] new 0bd84bf0318 Fix Xmethod for shared_ptr::use_count() The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: libstdc++-v3/ChangeLog | 5 +++++ libstdc++-v3/python/libstdcxx/v6/xmethods.py | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[gcc] branch gcc-7-branch updated (4d1f8ea2c3f -> 797f5aa0e94)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch gcc-7-branch in repository gcc. from 4d1f8ea2c3f PR rtl-optimization/89795 * rtlanal.c (nonzero_bits1) <SU [...] new 797f5aa0e94 Fix Xmethod for shared_ptr::use_count() The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: libstdc++-v3/ChangeLog | 5 +++++ libstdc++-v3/python/libstdcxx/v6/xmethods.py | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[gcc] branch master updated (d7bb8e5b975 -> b33daee6bc7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from d7bb8e5b975 2019-09-11 Richard Biener <rguenther(a)suse.de> new 3e0fb9b8feb 2019-09-11 Richard Biener <rguenther(a)suse.de> new b33daee6bc7 [PATCH] some tree struct marking The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 13 ++++ gcc/cp/ChangeLog | 6 ++ gcc/cp/cp-objcp-common.c | 153 +++++++++++++++++++++++++---------------------- gcc/cp/decl.c | 16 ++--- gcc/doc/invoke.texi | 8 +++ gcc/lto-opts.c | 4 ++ gcc/lto-wrapper.c | 6 ++ gcc/tree.c | 82 +++++++++++-------------- gcc/tree.h | 4 ++ 9 files changed, 166 insertions(+), 126 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[llvm] branch master updated (8ea51586a93 -> 75f0bef6155)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 8ea51586a93 Fix -Wdocumentation warning - void function doesn't need a [...] new 68378dff20e [mips][msa] Fix infinite loop for mips.nori.b intrinsic new 75f0bef6155 [Alignment] Use llvm::Align in MachineFunction and TargetLo [...] The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: include/llvm/CodeGen/MachineFunction.h | 18 +- include/llvm/CodeGen/TargetLowering.h | 8 +- lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 2 +- lib/CodeGen/AsmPrinter/WinException.cpp | 2 +- lib/CodeGen/BranchRelaxation.cpp | 15 +- lib/CodeGen/MIRParser/MIRParser.cpp | 2 +- lib/CodeGen/MIRPrinter.cpp | 2 +- lib/CodeGen/MachineFunction.cpp | 8 +- lib/CodeGen/PatchableFunction.cpp | 2 +- lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 2 +- lib/Target/AMDGPU/R600AsmPrinter.cpp | 2 +- lib/Target/ARC/ARCMachineFunctionInfo.h | 4 +- lib/Target/ARM/ARMBasicBlockInfo.cpp | 2 +- lib/Target/ARM/ARMConstantIslandPass.cpp | 11 +- lib/Target/Mips/MipsAsmPrinter.cpp | 3 +- lib/Target/Mips/MipsConstantIslandPass.cpp | 4 +- lib/Target/Mips/MipsSEISelLowering.cpp | 1 + lib/Target/PowerPC/PPCBranchSelector.cpp | 13 +- lib/Target/SystemZ/SystemZLongBranch.cpp | 6 +- .../AArch64/GlobalISel/arm64-regbankselect.mir | 10 +- .../AArch64/GlobalISel/combine-anyext-crash.mir | 2 +- test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir | 22 +- test/CodeGen/AArch64/GlobalISel/fold-select.mir | 4 +- .../GlobalISel/fp128-legalize-crash-pr35690.mir | 2 +- test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir | 6 +- test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir | 6 +- test/CodeGen/AArch64/GlobalISel/inline-memmove.mir | 8 +- test/CodeGen/AArch64/GlobalISel/inline-memset.mir | 8 +- .../AArch64/GlobalISel/inline-small-memcpy.mir | 4 +- test/CodeGen/AArch64/GlobalISel/legalize-add.mir | 4 +- .../AArch64/GlobalISel/legalize-blockaddress.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-ceil.mir | 4 +- test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-cos.mir | 12 +- test/CodeGen/AArch64/GlobalISel/legalize-div.mir | 2 +- .../AArch64/GlobalISel/legalize-dyn-alloca.mir | 6 +- test/CodeGen/AArch64/GlobalISel/legalize-exp.mir | 12 +- test/CodeGen/AArch64/GlobalISel/legalize-ext.mir | 18 +- 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.../AArch64/GlobalISel/legalize-shuffle-vector.mir | 6 +- test/CodeGen/AArch64/GlobalISel/legalize-sin.mir | 12 +- test/CodeGen/AArch64/GlobalISel/legalize-sqrt.mir | 4 +- .../AArch64/GlobalISel/legalize-vector-icmp.mir | 128 ++-- .../legalizer-combiner-zext-trunc-crash.mir | 2 +- .../AArch64/GlobalISel/load-addressing-modes.mir | 42 +- .../GlobalISel/localizer-in-O0-pipeline.mir | 2 +- test/CodeGen/AArch64/GlobalISel/localizer.mir | 2 +- .../GlobalISel/machine-cse-mid-pipeline.mir | 2 +- .../GlobalISel/non-pow-2-extload-combine.mir | 2 +- .../AArch64/GlobalISel/observer-change-crash.mir | 2 +- .../AArch64/GlobalISel/opt-fold-compare.mir | 30 +- .../AArch64/GlobalISel/opt-shuffle-splat.mir | 12 +- .../prelegalizercombiner-extending-loads-s1.mir | 2 +- .../GlobalISel/regbank-extract-vector-elt.mir | 8 +- .../CodeGen/AArch64/GlobalISel/regbank-extract.mir | 2 +- test/CodeGen/AArch64/GlobalISel/regbank-fma.mir | 4 +- .../GlobalISel/regbank-insert-vector-elt.mir | 12 +- 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test/CodeGen/AArch64/GlobalISel/select-store.mir | 8 +- test/CodeGen/AArch64/GlobalISel/select-stx.mir | 8 +- test/CodeGen/AArch64/GlobalISel/select-trap.mir | 2 +- test/CodeGen/AArch64/GlobalISel/select-uaddo.mir | 4 +- test/CodeGen/AArch64/GlobalISel/select-unmerge.mir | 14 +- .../AArch64/GlobalISel/select-vector-icmp.mir | 160 ++--- .../AArch64/GlobalISel/select-vector-shift.mir | 8 +- .../GlobalISel/select-with-no-legality-check.mir | 304 ++++----- .../AArch64/GlobalISel/store-addressing-modes.mir | 14 +- test/CodeGen/AArch64/aarch64-mov-debug-locs.mir | 2 +- test/CodeGen/AArch64/aarch64-vector-pcs.mir | 2 +- test/CodeGen/AArch64/branch-relax-block-size.mir | 2 +- .../dont-shrink-wrap-stack-mayloadorstore.mir | 4 +- test/CodeGen/AArch64/irg-nomem.mir | 2 +- test/CodeGen/AArch64/jump-table-compress.mir | 2 +- .../AArch64/machine-outliner-inline-asm-adrp.mir | 6 +- test/CodeGen/AArch64/movimm-wzr.mir | 2 +- test/CodeGen/AArch64/reverse-csr-restore-seq.mir | 2 +- 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.../Mips/GlobalISel/instruction-select/sub.mir | 2 +- .../instruction-select/truncStore_and_aExtLoad.mir | 6 +- .../instruction-select/zextLoad_and_sextLoad.mir | 8 +- test/CodeGen/Mips/GlobalISel/legalizer/add.mir | 20 +- test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir | 56 +- test/CodeGen/Mips/GlobalISel/legalizer/branch.mir | 4 +- .../Mips/GlobalISel/legalizer/ceil_and_floor.mir | 8 +- .../Mips/GlobalISel/legalizer/constants.mir | 16 +- test/CodeGen/Mips/GlobalISel/legalizer/fabs.mir | 4 +- test/CodeGen/Mips/GlobalISel/legalizer/fcmp.mir | 4 +- test/CodeGen/Mips/GlobalISel/legalizer/fence.mir | 2 +- .../legalizer/float_arithmetic_operations.mir | 16 +- .../Mips/GlobalISel/legalizer/float_constants.mir | 4 +- .../GlobalISel/legalizer/fpext_and_fptrunc.mir | 4 +- .../GlobalISel/legalizer/fptosi_and_fptoui.mir | 32 +- test/CodeGen/Mips/GlobalISel/legalizer/fsqrt.mir | 4 +- .../Mips/GlobalISel/legalizer/global_address.mir | 2 +- test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir | 28 +- .../GlobalISel/legalizer/inttoptr_and_ptrtoint.mir | 4 +- .../GlobalISel/legalizer/jump_table_and_brjt.mir | 2 +- test/CodeGen/Mips/GlobalISel/legalizer/load.mir | 8 +- test/CodeGen/Mips/GlobalISel/legalizer/mul.mir | 22 +- test/CodeGen/Mips/GlobalISel/legalizer/phi.mir | 14 +- .../CodeGen/Mips/GlobalISel/legalizer/pointers.mir | 6 +- .../Mips/GlobalISel/legalizer/rem_and_div.mir | 32 +- test/CodeGen/Mips/GlobalISel/legalizer/select.mir | 16 +- .../GlobalISel/legalizer/sitofp_and_uitofp.mir | 32 +- .../Mips/GlobalISel/legalizer/stack_args.mir | 2 +- test/CodeGen/Mips/GlobalISel/legalizer/store.mir | 8 +- test/CodeGen/Mips/GlobalISel/legalizer/sub.mir | 18 +- test/CodeGen/Mips/GlobalISel/legalizer/trap.mir | 2 +- test/CodeGen/Mips/GlobalISel/legalizer/trunc.mir | 2 +- .../legalizer/truncStore_and_aExtLoad.mir | 12 +- .../GlobalISel/legalizer/zextLoad_and_sextLoad.mir | 20 +- .../Mips/GlobalISel/legalizer/zext_and_sext.mir | 4 +- .../truncStore_and_aExtLoad.mir | 4 +- .../mips-prelegalizer-combiner/tryCombine.mir | 2 +- .../zextLoad_and_sextLoad.mir | 20 +- .../regbankselect/TypeInfoforMF_skipCopies.mir | 4 +- test/CodeGen/Mips/GlobalISel/regbankselect/add.mir | 2 +- .../Mips/GlobalISel/regbankselect/bitwise.mir | 18 +- .../Mips/GlobalISel/regbankselect/branch.mir | 4 +- .../CodeGen/Mips/GlobalISel/regbankselect/fabs.mir | 4 +- .../CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir | 4 +- .../Mips/GlobalISel/regbankselect/fence.mir | 2 +- .../Mips/GlobalISel/regbankselect/float_args.mir | 16 +- .../regbankselect/float_arithmetic_operations.mir | 16 +- .../GlobalISel/regbankselect/float_constants.mir | 4 +- .../GlobalISel/regbankselect/fpext_and_fptrunc.mir | 4 +- .../GlobalISel/regbankselect/fptosi_and_fptoui.mir | 4 +- .../Mips/GlobalISel/regbankselect/fsqrt.mir | 4 +- .../GlobalISel/regbankselect/global_address.mir | 2 +- .../regbankselect/global_address_pic.mir | 2 +- .../CodeGen/Mips/GlobalISel/regbankselect/icmp.mir | 4 +- .../regbankselect/inttoptr_and_ptrtoint.mir | 4 +- .../regbankselect/jump_table_and_brjt.mir | 2 +- .../CodeGen/Mips/GlobalISel/regbankselect/load.mir | 12 +- .../regbankselect/long_ambiguous_chain_s32.mir | 8 +- .../regbankselect/long_ambiguous_chain_s64.mir | 8 +- test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir | 4 +- test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir | 12 +- .../Mips/GlobalISel/regbankselect/pointers.mir | 6 +- .../Mips/GlobalISel/regbankselect/rem_and_div.mir | 8 +- .../Mips/GlobalISel/regbankselect/select.mir | 14 +- .../GlobalISel/regbankselect/sitofp_and_uitofp.mir | 4 +- .../Mips/GlobalISel/regbankselect/stack_args.mir | 2 +- .../Mips/GlobalISel/regbankselect/store.mir | 8 +- test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir | 2 +- .../regbankselect/test_TypeInfoforMF.mir | 16 +- .../regbankselect/truncStore_and_aExtLoad.mir | 6 +- .../regbankselect/zextLoad_and_sextLoad.mir | 12 +- .../GlobalISel/regbankselect/zext_and_sext.mir | 4 +- test/CodeGen/Mips/cconv/vector.ll | 732 +++++++++------------ .../compact-branch-implicit-def.mir | 2 +- test/CodeGen/Mips/compactbranches/empty-block.mir | 2 +- .../indirect-jump-hazard/guards-verify-call.mir | 2 +- .../guards-verify-tailcall.mir | 2 +- test/CodeGen/Mips/instverify/dext-pos.mir | 2 +- test/CodeGen/Mips/instverify/dext-size.mir | 2 +- test/CodeGen/Mips/instverify/dextm-pos-size.mir | 2 +- test/CodeGen/Mips/instverify/dextm-pos.mir | 2 +- test/CodeGen/Mips/instverify/dextm-size.mir | 2 +- test/CodeGen/Mips/instverify/dextu-pos-size.mir | 2 +- test/CodeGen/Mips/instverify/dextu-pos.mir | 2 +- test/CodeGen/Mips/instverify/dextu-size-valid.mir | 2 +- test/CodeGen/Mips/instverify/dextu-size.mir | 2 +- test/CodeGen/Mips/instverify/dins-pos-size.mir | 2 +- test/CodeGen/Mips/instverify/dins-pos.mir | 2 +- test/CodeGen/Mips/instverify/dins-size.mir | 2 +- test/CodeGen/Mips/instverify/dinsm-pos-size.mir | 2 +- test/CodeGen/Mips/instverify/dinsm-pos.mir | 2 +- test/CodeGen/Mips/instverify/dinsm-size.mir | 2 +- test/CodeGen/Mips/instverify/dinsu-pos-size.mir | 2 +- test/CodeGen/Mips/instverify/dinsu-pos.mir | 2 +- test/CodeGen/Mips/instverify/dinsu-size.mir | 2 +- test/CodeGen/Mips/instverify/ext-pos-size.mir | 2 +- test/CodeGen/Mips/instverify/ext-pos.mir | 2 +- test/CodeGen/Mips/instverify/ext-size.mir | 2 +- test/CodeGen/Mips/instverify/ins-pos-size.mir | 2 +- test/CodeGen/Mips/instverify/ins-pos.mir | 2 +- test/CodeGen/Mips/instverify/ins-size.mir | 2 +- .../Mips/longbranch/branch-limits-fp-micromips.mir | 4 +- .../longbranch/branch-limits-fp-micromipsr6.mir | 4 +- .../Mips/longbranch/branch-limits-fp-mips.mir | 4 +- .../Mips/longbranch/branch-limits-fp-mipsr6.mir | 4 +- .../longbranch/branch-limits-int-microMIPS.mir | 16 +- .../longbranch/branch-limits-int-micromipsr6.mir | 24 +- .../Mips/longbranch/branch-limits-int-mips64.mir | 12 +- .../Mips/longbranch/branch-limits-int-mips64r6.mir | 24 +- .../Mips/longbranch/branch-limits-int-mipsr6.mir | 24 +- test/CodeGen/Mips/longbranch/branch-limits-int.mir | 12 +- test/CodeGen/Mips/longbranch/branch-limits-msa.mir | 20 +- test/CodeGen/Mips/micromips-eva.mir | 4 +- test/CodeGen/Mips/micromips-short-delay-slot.mir | 2 +- .../micromips-sizereduction/micromips-lwp-swp.mir | 8 +- .../micromips-no-lwp-swp.mir | 8 +- .../Mips/mirparser/target-flags-pic-mxgot-tls.mir | 2 +- .../Mips/mirparser/target-flags-pic-o32.mir | 2 +- test/CodeGen/Mips/mirparser/target-flags-pic.mir | 2 +- .../Mips/mirparser/target-flags-static-tls.mir | 2 +- test/CodeGen/Mips/msa/2r_vector_scalar.ll | 5 +- test/CodeGen/Mips/msa/emergency-spill.mir | 2 +- test/CodeGen/Mips/msa/nori.b.ll | 26 + test/CodeGen/Mips/sll-micromips-r6-encoding.mir | 2 +- test/CodeGen/Mips/unaligned-memops-mapping.mir | 12 +- .../PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir | 2 +- test/CodeGen/PowerPC/aantidep-def-ec.mir | 2 +- test/CodeGen/PowerPC/addisdtprelha-nonr3.mir | 2 +- test/CodeGen/PowerPC/block-placement-1.mir | 4 +- test/CodeGen/PowerPC/block-placement.mir | 2 +- test/CodeGen/PowerPC/collapse-rotates.mir | 2 +- ...convert-rr-to-ri-instrs-R0-special-handling.mir | 14 +- .../convert-rr-to-ri-instrs-out-of-range.mir | 40 +- test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir | 176 ++--- .../CodeGen/PowerPC/convert-rr-to-ri-p9-vector.mir | 6 +- test/CodeGen/PowerPC/expand-isel-1.mir | 2 +- test/CodeGen/PowerPC/expand-isel-10.mir | 2 +- test/CodeGen/PowerPC/expand-isel-2.mir | 2 +- test/CodeGen/PowerPC/expand-isel-3.mir | 2 +- test/CodeGen/PowerPC/expand-isel-4.mir | 2 +- test/CodeGen/PowerPC/expand-isel-5.mir | 2 +- test/CodeGen/PowerPC/expand-isel-6.mir | 2 +- test/CodeGen/PowerPC/expand-isel-7.mir | 2 +- test/CodeGen/PowerPC/expand-isel-8.mir | 2 +- test/CodeGen/PowerPC/expand-isel-9.mir | 2 +- test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir | 2 +- test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir | 2 +- test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir | 2 +- test/CodeGen/PowerPC/remove-implicit-use.mir | 2 +- test/CodeGen/PowerPC/remove-redundant-load-imm.mir | 28 +- test/CodeGen/PowerPC/remove-self-copies.mir | 2 +- test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir | 12 +- test/CodeGen/PowerPC/schedule-addi-load.mir | 2 +- test/CodeGen/PowerPC/setcr_bc.mir | 2 +- test/CodeGen/PowerPC/setcr_bc2.mir | 2 +- test/CodeGen/PowerPC/setcr_bc3.mir | 2 +- test/CodeGen/PowerPC/shrink-wrap.mir | 2 +- test/CodeGen/PowerPC/tls_get_addr_fence1.mir | 2 +- test/CodeGen/PowerPC/tls_get_addr_fence2.mir | 2 +- test/CodeGen/RISCV/select-optimize-multiple.mir | 4 +- test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir | 2 +- test/CodeGen/SystemZ/clear-liverange-spillreg.mir | 2 +- test/CodeGen/SystemZ/cond-move-04.mir | 2 +- test/CodeGen/SystemZ/cond-move-05.mir | 2 +- test/CodeGen/SystemZ/cond-move-08.mir | 2 +- test/CodeGen/SystemZ/cond-move-regalloc-hints.mir | 2 +- test/CodeGen/SystemZ/debuginstr-00.mir | 2 +- test/CodeGen/SystemZ/debuginstr-01.mir | 2 +- test/CodeGen/SystemZ/debuginstr-02.mir | 2 +- test/CodeGen/SystemZ/debuginstr-cgp.mir | 2 +- test/CodeGen/SystemZ/fp-conv-17.mir | 2 +- test/CodeGen/SystemZ/load-and-test-RA-hints.mir | 2 +- test/CodeGen/SystemZ/misched-readadvances.mir | 2 +- test/CodeGen/SystemZ/postra-sched-expandedops.mir | 2 +- test/CodeGen/SystemZ/regalloc-GR128-02.mir | 2 +- .../SystemZ/regalloc-fast-invalid-kill-flag.mir | 2 +- .../regcoal-undef-lane-4-rm-cp-commuting-def.mir | 2 +- test/CodeGen/SystemZ/subregliveness-06.mir | 2 +- test/CodeGen/SystemZ/subregliveness-07.mir | 2 +- test/CodeGen/Thumb/PR36658.mir | 2 +- test/CodeGen/Thumb/tbb-reuse.mir | 2 +- test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir | 2 +- .../LowOverheadLoops/end-positive-offset.mir | 2 +- test/CodeGen/Thumb2/LowOverheadLoops/massive.mir | 2 +- .../Thumb2/LowOverheadLoops/multiblock-massive.mir | 2 +- .../Thumb2/LowOverheadLoops/revert-after-call.mir | 2 +- .../Thumb2/LowOverheadLoops/revert-after-read.mir | 2 +- .../Thumb2/LowOverheadLoops/revert-after-spill.mir | 2 +- .../Thumb2/LowOverheadLoops/revert-after-write.mir | 2 +- .../Thumb2/LowOverheadLoops/revert-non-header.mir | 2 +- .../Thumb2/LowOverheadLoops/revert-non-loop.mir | 2 +- .../Thumb2/LowOverheadLoops/revert-while.mir | 2 +- .../CodeGen/Thumb2/LowOverheadLoops/size-limit.mir | 2 +- test/CodeGen/Thumb2/LowOverheadLoops/switch.mir | 2 +- .../LowOverheadLoops/while-negative-offset.mir | 2 +- test/CodeGen/Thumb2/LowOverheadLoops/while.mir | 2 +- test/CodeGen/Thumb2/m4-sched-ldr.mir | 2 +- test/CodeGen/Thumb2/mve-vpt-block.mir | 2 +- test/CodeGen/Thumb2/mve-vpt-block2.mir | 2 +- test/CodeGen/Thumb2/mve-vpt-block3.mir | 2 +- test/CodeGen/Thumb2/mve-vpt-block4.mir | 2 +- test/CodeGen/Thumb2/mve-vpt-block5.mir | 2 +- test/CodeGen/Thumb2/mve-vpt-block6.mir | 2 +- test/CodeGen/Thumb2/mve-vpt-block7.mir | 2 +- test/CodeGen/Thumb2/mve-vpt-block8.mir | 2 +- test/CodeGen/Thumb2/mve-vpt-nots.mir | 12 +- test/CodeGen/Thumb2/tbb-removeadd.mir | 2 +- .../X86/GlobalISel/avoid-matchtable-crash.mir | 2 +- test/CodeGen/X86/GlobalISel/legalize-add-v128.mir | 8 +- test/CodeGen/X86/GlobalISel/legalize-add-v256.mir | 8 +- test/CodeGen/X86/GlobalISel/legalize-add-v512.mir | 10 +- test/CodeGen/X86/GlobalISel/legalize-add.mir | 6 +- .../CodeGen/X86/GlobalISel/legalize-and-scalar.mir | 10 +- .../X86/GlobalISel/legalize-ashr-scalar.mir | 4 +- test/CodeGen/X86/GlobalISel/legalize-brcond.mir | 2 +- test/CodeGen/X86/GlobalISel/legalize-cmp.mir | 10 +- .../CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir | 24 +- test/CodeGen/X86/GlobalISel/legalize-ext.mir | 36 +- .../X86/GlobalISel/legalize-fadd-scalar.mir | 4 +- .../X86/GlobalISel/legalize-fdiv-scalar.mir | 4 +- .../X86/GlobalISel/legalize-fmul-scalar.mir | 4 +- .../X86/GlobalISel/legalize-fpext-scalar.mir | 2 +- .../X86/GlobalISel/legalize-fptrunc-scalar.mir | 2 +- .../X86/GlobalISel/legalize-fsub-scalar.mir | 4 +- .../X86/GlobalISel/legalize-insert-vec256.mir | 2 +- .../X86/GlobalISel/legalize-insert-vec512.mir | 4 +- .../X86/GlobalISel/legalize-lshr-scalar.mir | 4 +- .../X86/GlobalISel/legalize-memop-scalar-32.mir | 4 +- .../X86/GlobalISel/legalize-memop-scalar-64.mir | 4 +- .../CodeGen/X86/GlobalISel/legalize-mul-scalar.mir | 8 +- test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir | 6 +- test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir | 6 +- test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir | 6 +- test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir | 10 +- test/CodeGen/X86/GlobalISel/legalize-phi.mir | 14 +- .../CodeGen/X86/GlobalISel/legalize-shl-scalar.mir | 4 +- test/CodeGen/X86/GlobalISel/legalize-sub-v128.mir | 8 +- test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir | 8 +- test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir | 8 +- test/CodeGen/X86/GlobalISel/legalize-sub.mir | 4 +- .../CodeGen/X86/GlobalISel/legalize-xor-scalar.mir | 10 +- test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir | 10 +- .../X86/GlobalISel/regbankselect-AVX512.mir | 10 +- test/CodeGen/X86/GlobalISel/regbankselect-X32.mir | 2 +- .../X86/GlobalISel/regbankselect-X86_64.mir | 164 ++--- test/CodeGen/X86/GlobalISel/select-GV-32.mir | 4 +- test/CodeGen/X86/GlobalISel/select-GV-64.mir | 4 +- test/CodeGen/X86/GlobalISel/select-add-v128.mir | 8 +- test/CodeGen/X86/GlobalISel/select-add-v256.mir | 8 +- test/CodeGen/X86/GlobalISel/select-add-v512.mir | 8 +- test/CodeGen/X86/GlobalISel/select-add-x32.mir | 2 +- test/CodeGen/X86/GlobalISel/select-add.mir | 8 +- test/CodeGen/X86/GlobalISel/select-and-scalar.mir | 8 +- test/CodeGen/X86/GlobalISel/select-ashr-scalar.mir | 24 +- test/CodeGen/X86/GlobalISel/select-blsi.mir | 4 +- test/CodeGen/X86/GlobalISel/select-blsr.mir | 4 +- test/CodeGen/X86/GlobalISel/select-br.mir | 2 +- test/CodeGen/X86/GlobalISel/select-brcond.mir | 2 +- test/CodeGen/X86/GlobalISel/select-cmp.mir | 26 +- test/CodeGen/X86/GlobalISel/select-constant.mir | 4 +- test/CodeGen/X86/GlobalISel/select-copy.mir | 12 +- test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir | 14 +- test/CodeGen/X86/GlobalISel/select-ext.mir | 26 +- .../X86/GlobalISel/select-extract-vec256.mir | 4 +- .../X86/GlobalISel/select-extract-vec512.mir | 8 +- test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir | 4 +- test/CodeGen/X86/GlobalISel/select-fconstant.mir | 4 +- test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir | 4 +- test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir | 4 +- .../CodeGen/X86/GlobalISel/select-fpext-scalar.mir | 2 +- .../X86/GlobalISel/select-fptrunc-scalar.mir | 2 +- test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir | 4 +- test/CodeGen/X86/GlobalISel/select-gep.mir | 2 +- .../X86/GlobalISel/select-insert-vec256.mir | 8 +- .../X86/GlobalISel/select-insert-vec512.mir | 16 +- test/CodeGen/X86/GlobalISel/select-lshr-scalar.mir | 24 +- .../GlobalISel/select-memop-scalar-unordered.mir | 36 +- .../X86/GlobalISel/select-memop-scalar-x32.mir | 16 +- .../CodeGen/X86/GlobalISel/select-memop-scalar.mir | 36 +- test/CodeGen/X86/GlobalISel/select-memop-v128.mir | 8 +- test/CodeGen/X86/GlobalISel/select-memop-v256.mir | 8 +- test/CodeGen/X86/GlobalISel/select-memop-v512.mir | 8 +- .../CodeGen/X86/GlobalISel/select-merge-vec256.mir | 2 +- .../CodeGen/X86/GlobalISel/select-merge-vec512.mir | 4 +- test/CodeGen/X86/GlobalISel/select-mul-scalar.mir | 6 +- test/CodeGen/X86/GlobalISel/select-mul-vec.mir | 30 +- test/CodeGen/X86/GlobalISel/select-or-scalar.mir | 8 +- test/CodeGen/X86/GlobalISel/select-phi.mir | 12 +- test/CodeGen/X86/GlobalISel/select-shl-scalar.mir | 24 +- test/CodeGen/X86/GlobalISel/select-sub-v128.mir | 8 +- test/CodeGen/X86/GlobalISel/select-sub-v256.mir | 8 +- test/CodeGen/X86/GlobalISel/select-sub-v512.mir | 8 +- test/CodeGen/X86/GlobalISel/select-sub.mir | 4 +- test/CodeGen/X86/GlobalISel/select-trunc.mir | 12 +- test/CodeGen/X86/GlobalISel/select-undef.mir | 6 +- .../X86/GlobalISel/select-unmerge-vec256.mir | 2 +- .../X86/GlobalISel/select-unmerge-vec512.mir | 4 +- test/CodeGen/X86/GlobalISel/select-xor-scalar.mir | 8 +- test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir | 2 +- .../X86/GlobalISel/x86-legalize-inttoptr.mir | 2 +- .../X86/GlobalISel/x86-legalize-ptrtoint.mir | 8 +- test/CodeGen/X86/GlobalISel/x86-legalize-sdiv.mir | 6 +- test/CodeGen/X86/GlobalISel/x86-legalize-srem.mir | 6 +- test/CodeGen/X86/GlobalISel/x86-legalize-udiv.mir | 6 +- test/CodeGen/X86/GlobalISel/x86-legalize-urem.mir | 6 +- .../CodeGen/X86/GlobalISel/x86-select-inttoptr.mir | 2 +- .../CodeGen/X86/GlobalISel/x86-select-ptrtoint.mir | 8 +- test/CodeGen/X86/GlobalISel/x86-select-sdiv.mir | 6 +- test/CodeGen/X86/GlobalISel/x86-select-srem.mir | 6 +- test/CodeGen/X86/GlobalISel/x86-select-trap.mir | 2 +- test/CodeGen/X86/GlobalISel/x86-select-udiv.mir | 6 +- test/CodeGen/X86/GlobalISel/x86-select-urem.mir | 6 +- test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir | 2 +- .../X86/GlobalISel/x86_64-legalize-fcmp.mir | 56 +- .../X86/GlobalISel/x86_64-legalize-fptosi.mir | 16 +- .../X86/GlobalISel/x86_64-legalize-inttoptr.mir | 2 +- .../X86/GlobalISel/x86_64-legalize-ptrtoint.mir | 10 +- .../X86/GlobalISel/x86_64-legalize-sdiv.mir | 8 +- .../X86/GlobalISel/x86_64-legalize-sitofp.mir | 16 +- .../X86/GlobalISel/x86_64-legalize-srem.mir | 8 +- .../X86/GlobalISel/x86_64-legalize-udiv.mir | 8 +- .../X86/GlobalISel/x86_64-legalize-urem.mir | 8 +- .../X86/GlobalISel/x86_64-legalize-zext.mir | 20 +- test/CodeGen/X86/GlobalISel/x86_64-select-fcmp.mir | 56 +- .../X86/GlobalISel/x86_64-select-fptosi.mir | 16 +- .../X86/GlobalISel/x86_64-select-inttoptr.mir | 2 +- .../X86/GlobalISel/x86_64-select-ptrtoint.mir | 10 +- test/CodeGen/X86/GlobalISel/x86_64-select-sdiv.mir | 8 +- .../X86/GlobalISel/x86_64-select-sitofp.mir | 8 +- test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir | 8 +- test/CodeGen/X86/GlobalISel/x86_64-select-udiv.mir | 8 +- test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir | 8 +- test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir | 20 +- test/CodeGen/X86/PR37310.mir | 2 +- test/CodeGen/X86/adx-commute.mir | 8 +- test/CodeGen/X86/avoid-sfb-g-no-change.mir | 4 +- test/CodeGen/X86/avoid-sfb-g-no-change2.mir | 2 +- test/CodeGen/X86/avoid-sfb-g-no-change3.mir | 2 +- test/CodeGen/X86/avoid-sfb-kill-flags.mir | 2 +- test/CodeGen/X86/avoid-sfb-offset.mir | 2 +- test/CodeGen/X86/avx512f-256-set0.mir | 2 +- test/CodeGen/X86/bad-tls-fold.mir | 4 +- test/CodeGen/X86/block-placement.mir | 2 +- test/CodeGen/X86/conditional-tailcall-samedest.mir | 2 +- .../X86/dbg-changes-codegen-branch-folding2.mir | 2 +- test/CodeGen/X86/domain-reassignment.mir | 16 +- test/CodeGen/X86/fixup-bw-inst.mir | 10 +- test/CodeGen/X86/implicit-null-checks.mir | 54 +- test/CodeGen/X86/implicit-null-chk-reg-rewrite.mir | 2 +- test/CodeGen/X86/late-remat-update.mir | 2 +- test/CodeGen/X86/lea-opt-with-debug.mir | 2 +- test/CodeGen/X86/leaFixup32.mir | 24 +- test/CodeGen/X86/leaFixup64.mir | 50 +- test/CodeGen/X86/limit-split-cost.mir | 2 +- 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+- test/DebugInfo/MIR/ARM/split-superreg-piece.mir | 2 +- test/DebugInfo/MIR/ARM/split-superreg.mir | 2 +- test/DebugInfo/MIR/Mips/last-inst-bundled.mir | 2 +- .../MIR/Mips/live-debug-values-reg-copy.mir | 2 +- test/DebugInfo/MIR/X86/DW_OP_entry_value.mir | 2 +- .../MIR/X86/avoid-single-entry-value-location.mir | 2 +- test/DebugInfo/MIR/X86/bit-piece-dh.mir | 2 +- test/DebugInfo/MIR/X86/dbg-stack-value-range.mir | 2 +- test/DebugInfo/MIR/X86/dbginfo-entryvals.mir | 2 +- test/DebugInfo/MIR/X86/debug-loc-0.mir | 2 +- test/DebugInfo/MIR/X86/empty-inline.mir | 2 +- test/DebugInfo/MIR/X86/kill-after-spill.mir | 2 +- .../DebugInfo/MIR/X86/live-debug-values-3preds.mir | 2 +- .../MIR/X86/live-debug-values-reg-copy.mir | 2 +- .../MIR/X86/live-debug-values-restore-collide.mir | 2 +- .../MIR/X86/live-debug-values-restore.mir | 8 +- test/DebugInfo/MIR/X86/live-debug-values-spill.mir | 2 +- test/DebugInfo/MIR/X86/live-debug-values.mir | 2 +- .../X86/live-debug-vars-unused-arg-debugonly.mir | 2 +- .../MIR/X86/live-debug-vars-unused-arg.mir | 2 +- test/DebugInfo/MIR/X86/livedebugvalues-limit.mir | 4 +- .../MIR/X86/livedebugvars-crossbb-interval.mir | 2 +- test/DebugInfo/MIR/X86/mlicm-hoist.mir | 2 +- .../MIR/X86/multiple-param-dbg-value-entry.mir | 2 +- test/DebugInfo/MIR/X86/no-cfi-loc.mir | 2 +- .../MIR/X86/prolog-epilog-indirection.mir | 2 +- test/DebugInfo/MIR/X86/regcoalescer.mir | 2 +- test/DebugInfo/X86/debug-loc-asan.mir | 2 +- test/DebugInfo/X86/debug-loc-offset.mir | 10 +- test/DebugInfo/X86/dw_op_minus.mir | 2 +- test/DebugInfo/X86/live-debug-values-constprop.mir | 8 +- test/DebugInfo/X86/live-debug-vars-dse.mir | 2 +- test/DebugInfo/X86/pr19307.mir | 2 +- 653 files changed, 2914 insertions(+), 2982 deletions(-) create mode 100644 test/CodeGen/Mips/msa/nori.b.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[gcc] branch master updated (76a986c4dd6 -> d7bb8e5b975)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 76a986c4dd6 PR rtl-optimization/89795 * rtlanal.c (nonzero_bits1) <SU [...] new d7bb8e5b975 2019-09-11 Richard Biener <rguenther(a)suse.de> The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 6 ++++++ gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.dg/Warray-bounds-44.c | 23 +++++++++++++++++++++++ gcc/vr-values.c | 11 ++--------- 4 files changed, 36 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/Warray-bounds-44.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allyesconfig updated (56037cadf604 -> 3120b9a6a3f7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allyesconfig in repository toolchain/ci/linux. from 56037cadf604 Merge tag 'regulator-fix-v5.3-rc8' of git://git.kernel.org [...] adds 78e05972c5e6 ipc: fix semtimedop for generic 32-bit architectures adds fb377eb80c80 ipc: fix sparc64 ipc() wrapper adds 3120b9a6a3f7 Merge tag 'ipc-fixes' of git://git.kernel.org/pub/scm/linu [...] No new revisions were added by this update. Summary of changes: arch/sparc/kernel/sys_sparc_64.c | 33 ++++++++++++++++++--------------- include/linux/syscalls.h | 19 +++++++++++++++++++ include/uapi/asm-generic/unistd.h | 2 +- ipc/util.h | 25 ++----------------------- 4 files changed, 40 insertions(+), 39 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allyesconfig updated (c3df594ac -> 300803b35)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allyesconfig in repository toolchain/ci/base-artifacts. discards c3df594ac 0: update: llvm-linux: all new 300803b35 0: update: llvm-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (c3df594ac) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-aarc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 16 +- 02-build_llvm/console.log | 12008 ++++++++++++++++++------------------ 03-build_linux/console.log | 706 +-- 04-boot_linux/console.log | 6 +- console.log | 12736 +++++++++++++++++++-------------------- jenkins/manifest.sh | 10 +- 6 files changed, 12739 insertions(+), 12743 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-defconfig updated (e93f8076b8f -> 5f097de3a37)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-defconfig in repository toolchain/ci/gcc. from e93f8076b8f * doc/install.texi: Update and clarify requirements to bui [...] adds c566e9ccc58 2019-09-05 Richard Biener <rguenther(a)suse.de> adds 8bc9c0bbee9 [preprocessor/91639] #includes at EOF adds f742e18cbeb Implement std::span for C++20 adds 2981b5fceea [C++ PATCH] vtable decl marking adds 26d2429145d 2019-09-05 Richard Biener <rguenther(a)suse.de> adds d9743e50275 PR middle-end/91001 PR middle-end/91105 PR middle-end/91 [...] adds 8b34a2cd5a1 2019-09-05 Bernd Edlinger <bernd.edlinger(a)hotmail.de> adds 539fe734e7e Improve precondition checks for std::span adds d22747670a8 Global GCN instructions need nops too. adds d5cec9566d5 PR c++/91644 - ICE with constinit in function template. * [...] adds 414f622aff4 2019-09-05 Steven G. Kargl <kargl(a)gcc.gnu.org> adds 77f9e0f868c 2019-09-05 Harald Anlauf <anlauf(a)gmx.de> adds 995e214b491 RISC-V: Fix bad insn splits with paradoxical subregs. adds 4576da28999 Daily bump. adds d363d582274 Remove support for repo files (PR c++/91125). adds d5c58e6923b Improve documentation of for statement. adds db23acf2910 [arm] Add missing predicated-short-it variants to cmp_and a [...] adds 533c775b684 Fix GCC_LINUX_FUTEX to work with C99 compilers adds 45252ef980b [C++ PATCH] Reserve a decl_lang bit adds 924ea280583 [PATCH] Deprecate -frepo option. adds 79dd6fa74a8 [preprocessor] Popping "" file names adds f85521172f9 Define std::ssize for C++20 (P1227R2) adds 9b323eadd94 Fix testcase to not use LTO with -fvtable-verify. adds fecb4efbcf0 * g++.dg/warn/Warray-bounds-4.C: Skip AIX. [...] adds 98bd8ad6a8c * gcc.dg/torture/inf-compare-1.c: Skip AIX. [...] adds 5f2c4c2a88c * function.c (assign_parm_find_data_types): Use RECORD_OR_ [...] adds 9e947a4ac2a libgo: update to Go 1.13beta1 release adds 8715566738a PR target/91654 * config/i386/x86-tune-costs.h (skylake_c [...] adds f833076a082 rs6000: Delete UNSPEC_FRSP adds a200b916e80 rs6000: Delete UNSPEC_MV_CR_OV. adds 07f19ed925b RISC-V: Re-enable -msave-restore for shared libraries. adds 8625917444d Daily bump. adds c33c968f7e7 2019-09-07 Bernd Edlinger <bernd.edlinger(a)hotmail.de> adds bcaaaec211a add PR target/91684 to ChangeLog adds e54b76ca8cd PR tree-optimization/91665 * tree-vect-loop.c (vectorizab [...] adds b04886762de * g++.dg/cpp2a/decomp2.C: Add TLS options. [...] adds e2f9dd1f4da 2019-09-07 Bernd Edlinger <bernd.edlinger(a)hotmail.de> adds 6d529564788 Daily bump. adds c4a5a1692cf genemit: Print file+line in the "Splitting with" message adds 8024e87983d Daily bump. adds 17bc331b293 Update config.sub and config.guess. adds eab9adfb90d opt-functions.awk: fix comparison of limit, begin and end adds 6552d40b5cf testsuite: annotate c-torture/compile tests with dg-require [...] adds a111f9a0fc8 testsuite: new require effective target indirect_calls adds 3ec6f8cb4ae GCC port for eBPF adds 5dd8d3ebe3b PR target/91704 * config/i386/avxintrin.h (__v32qs): New [...] adds 668cbe0a29e PR target/87853 * config/i386/emmintrin.h (_mm_cmpeq_epi8 [...] adds a1823cbbcbd Improve constraints for std::span constructors adds a7d35751fec Minor std::to_chars optimisation for base 10 adds 983a2e1da0f Update comment of removed options. adds a4775a7b38e 2019-09-09 Barnaby Wilks <barnaby.wilks(a)arm.com> adds 57d34e71c5d Remove bt-load.c adds 32f944103ff 2019-09-09 Edward Smith-Rowland <3dw4rd(a)verizon.net> adds fe717ce74d8 Forgot Changelog from latest commit. adds 7b6485dc603 rs6000: Update rlwinm-[012].c adds 2ac0f18ef74 Simplify the implementation of HARD_REG_SET adds dfa9d60a8eb Make note_stores take an rtx_insn adds de7358edfc8 Remove COPY_HARD_REG_SET adds fb3190fc14c Remove COMPL_HARD_REG_SET adds 1ffef4f5326 Remove AND_HARD_REG_SET adds 247f191ed45 Remove IOR_HARD_REG_SET adds 9cfad81014c Remove AND_COMPL_HARD_REG_SET adds fcbb220b1d7 Remove IOR_COMPL_HARD_REG_SET adds 3a9ade4c321 Remove hard_reg_set_equal_p adds e79ff3cbaec Tweak interface to ira-build.c:ior_hard_reg_conflicts adds 65bac46108f Add "fast" conversions from arrays to bitmaps adds d48484354de Remove global REG_SETs adds 05d8579eda5 compiler: traverse types of constant expressions adds 42dd5858af0 compiler: don't use predeclared location for implicit r [...] adds 77e9a31a43f 2019-09-09 Bernd Edlinger <bernd.edlinger(a)hotmail.de> adds d44488c7785 libgo: only build x/sys/cpu/cpu_gccgo.c on x86 systems adds 7bb0cdeb0de misc/cgo/testcshared: restore gofrontend-local changes adds aa5dfff0506 Daily bump. adds 0268bb78bb7 PR c++/84374 - diagnose invalid uses of decltype(auto). * [...] adds 56021067732 compiler: permit inlining constant expressions and expr [...] adds 010217a5731 cmd/go: look for tool build ID before hashing entire file adds 12e702072d1 2019-09-09 Edward Smith-Rowland <3dw4rd(a)verizon.net> adds 367b16d1635 [ARM/FDPIC 01/24] [ARM] FDPIC: Add -mfdpic option support adds 5825655f549 Optimise std::remove_cv and use more helper aliases adds 297b1f92b15 PR libstdc++/91711 fix failing test adds 6cb819f4467 [ARM/FDPIC v6 02/24] [ARM] FDPIC: Handle arm*-*-uclinuxfdpi [...] adds 8329eec49b8 [ARM/FDPIC v6 03/24] [ARM] FDPIC: Force FDPIC related optio [...] adds 2649fa4112f [ARM/FDPIC v6 04/24] [ARM] FDPIC: Add support for FDPIC for [...] adds d52e0f059e1 [ARM/FDPIC v6 05/24] [ARM] FDPIC: Fix __do_global_dtors_aux [...] adds b5f6b83e143 [ARM/FDPIC v6 06/24] [ARM] FDPIC: Add support for c++ exceptions adds 947d9057533 [ARM/FDPIC v6 07/24] [ARM] FDPIC: Avoid saving/restoring r9 [...] adds 2ec82e4faf9 [ARM/FDPIC v6 08/24] [ARM] FDPIC: Enforce local/global bind [...] adds 859749d4a45 [ARM/FDPIC v6 09/24] [ARM] FDPIC: Add support for taking ad [...] adds cd6f4f2f6e6 [ARM/FDPIC v6 10/24] [ARM] FDPIC: Implement TLS support. adds 08ff77875e8 [ARM/FDPIC v6 11/24] [ARM] FDPIC: Add support to unwind FDP [...] adds 85fc66a7448 [ARM/FDPIC v6 12/24] [ARM] FDPIC: Restore r9 after we call [...] adds 67805ce89fe [ARM/FDPIC v6 13/24] [ARM] FDPIC: Force LSB bit for PC in C [...] adds 670a7875fc8 [ARM/FDPIC v6 14/24] [ARM][testsuite] FDPIC: Skip unsupport [...] adds 14694482176 [ARM/FDPIC v6 15/24] [ARM][testsuite] FDPIC: Adjust scan-as [...] adds 870d8516707 [ARM/FDPIC v6 16/24] [ARM][testsuite] FDPIC: Skip tests tha [...] adds b55d82d1032 [ARM/FDPIC v6 17/24] [ARM][testsuite] FDPIC: Handle *-*-uclinux* adds 1aa6db9eddf [ARM/FDPIC v6 18/24] [ARM][testsuite] FDPIC: Enable tests o [...] adds cd2be8eea01 [ARM/FDPIC v6 19/24] [ARM][testsuite] FDPIC: Adjust pr43698 [...] adds d89c07490c9 [ARM/FDPIC v6 21/24] [ARM] FDPIC: Handle stack-protector co [...] adds dff61244704 [ARM/FDPIC v6 22/24] [ARM][testsuite] FDPIC: Skip tests tha [...] adds de6995f3aee [ARM/FDPIC v6 23/24] [ARM] FDPIC: Implement libitm support. adds d8385cff92c /cp 2019-09-10 Paolo Carlini <paolo.carlini(a)oracle.com> adds 9f6c2e7c281 [ARM/FDPIC v6 24/24] [ARM] FDPIC: Handle arm*-*-uclinuxfdpi [...] adds f58c7f4de93 PR middle-end/91680 * match.pd ((A / (1 << B)) -> (A >> B [...] adds cd50420dfc2 LWG 3266. to_chars(bool) should be deleted adds d4280d8d822 * doc/install.texi: Fix syntax for html generation. adds a5c00f1f53d * gfortran.dg/default_format_1.f90: Remove XFAIL AI [...] adds 9a236ca1a68 Rename Deprecated to WarnRemoved in *.opt files. adds e98f100cc5f Make get_call_rtx_from take a const rtx_insn * adds e4c0b7eac16 Implement std::common_reference for C++20 adds 1465619d7be Move c6x REGNO_REG_CLASS out of line adds a784d7592ac Remove call_fixed_reg_set adds ea1b9aa643d Remove no_caller_save_reg_set adds b5f4ab21a9c Replace call_used_reg_set with call_used_or_fixed_regs adds 52e932b82bd Make more use of regs_invalidated_by_call adds ba77f2a8cd3 Add call_used_or_fixed_reg_p adds 9e8abc79dbc Remove redundant fixed_regs tests adds 0b944382ab7 Hide call_used_regs in target-independent code adds 0817f947478 Remove call_really_used_regs adds 9deb0dae53a go/internal/gccgoimporter: support embedded field in po [...] adds bd8c24f6216 PR go/91621 mksysinfo: change test == to test = adds ecad294dbb3 libgo: Solaris and x/sys/cpu compatibility fixes adds bf9ff334c9e PR c++/91705 - constexpr evaluation rejects ++/-- on float [...] adds dcf53eeb7d2 PR c++/91673 - ICE with noexcept in alias-declaration. * [...] adds 5f097de3a37 Daily bump. No new revisions were added by this update. Summary of changes: ChangeLog | 19 + MAINTAINERS | 2 +- config.guess | 264 +- config.sub | 50 +- config/ChangeLog | 10 + config/futex.m4 | 4 +- config/tls.m4 | 2 +- configure | 54 +- configure.ac | 54 +- contrib/ChangeLog | 4 + contrib/config-list.mk | 3 +- gcc/ChangeLog | 990 +++ gcc/DATESTAMP | 2 +- gcc/Makefile.in | 3 +- gcc/alias.c | 5 +- gcc/array-traits.h | 48 + gcc/bitmap.c | 8 +- gcc/bitmap.h | 122 +- gcc/bt-load.c | 1577 ---- gcc/c-family/ChangeLog | 19 + gcc/c-family/c-common.c | 5 - gcc/c-family/c-common.h | 5 - gcc/c-family/c-opts.c | 6 - gcc/c-family/c.opt | 138 +- gcc/caller-save.c | 75 +- gcc/calls.c | 13 +- gcc/cfgcleanup.c | 8 +- gcc/cfgloopanal.c | 2 +- gcc/collect2.c | 36 +- gcc/collect2.h | 4 +- gcc/combine.c | 15 +- gcc/common.opt | 20 +- gcc/common/config/bpf/bpf-common.c | 55 + gcc/config.gcc | 20 +- gcc/config/aarch64/aarch64.c | 6 +- gcc/config/aarch64/aarch64.opt | 2 +- gcc/config/aarch64/cortex-a57-fma-steering.c | 2 +- .../aarch64/falkor-tag-collision-avoidance.c | 2 +- gcc/config/alpha/alpha.c | 4 +- gcc/config/arc/arc.c | 4 +- gcc/config/arm/arm-c.c | 2 + gcc/config/arm/arm-protos.h | 1 + gcc/config/arm/arm.c | 537 +- gcc/config/arm/arm.h | 16 +- gcc/config/arm/arm.md | 131 +- gcc/config/arm/arm.opt | 6 +- gcc/config/arm/bpabi.h | 5 +- gcc/config/arm/linux-eabi.h | 7 +- gcc/config/arm/uclinuxfdpiceabi.h | 54 + gcc/config/arm/unspecs.md | 1 + gcc/config/avr/avr.c | 12 +- gcc/config/bfin/bfin.c | 20 +- gcc/config/bpf/bpf-helpers.def | 194 + gcc/config/bpf/bpf-helpers.h | 327 + gcc/config/bpf/bpf-opts.h | 56 + gcc/config/bpf/bpf-protos.h | 33 + gcc/config/bpf/bpf.c | 945 +++ gcc/config/bpf/bpf.h | 539 ++ gcc/config/bpf/bpf.md | 497 ++ gcc/config/bpf/bpf.opt | 123 + gcc/config/bpf/constraints.md | 32 + gcc/config/bpf/predicates.md | 64 + .../c-c++-common/empty.h => config/bpf/t-bpf} | 0 gcc/config/c6x/c6x-protos.h | 2 + gcc/config/c6x/c6x.c | 33 +- gcc/config/c6x/c6x.h | 7 +- gcc/config/cr16/cr16.c | 5 +- gcc/config/cris/cris.c | 4 +- gcc/config/csky/csky.c | 15 +- gcc/config/csky/csky.h | 28 - gcc/config/epiphany/epiphany.c | 19 +- gcc/config/epiphany/resolve-sw-modes.c | 3 +- gcc/config/fr30/fr30.c | 2 +- gcc/config/frv/frv.c | 18 +- gcc/config/ft32/ft32.c | 10 +- gcc/config/gcn/gcn.c | 30 +- gcc/config/gcn/gcn.md | 4 +- gcc/config/h8300/h8300.c | 5 +- gcc/config/i386/avx2intrin.h | 2 +- gcc/config/i386/avxintrin.h | 1 + gcc/config/i386/emmintrin.h | 2 +- gcc/config/i386/i386-expand.c | 2 +- gcc/config/i386/i386-expand.h | 2 +- gcc/config/i386/i386-options.c | 2 +- gcc/config/i386/i386.c | 29 +- gcc/config/i386/i386.opt | 13 +- gcc/config/i386/predicates.md | 2 +- gcc/config/i386/x86-tune-costs.h | 4 +- gcc/config/ia64/ia64.c | 43 +- gcc/config/ia64/ia64.h | 35 - gcc/config/ia64/ia64.opt | 4 +- gcc/config/iq2000/iq2000.h | 2 +- gcc/config/lm32/lm32.c | 2 +- gcc/config/m32c/m32c.c | 8 +- gcc/config/m32r/m32r.c | 7 +- gcc/config/m32r/m32r.h | 4 +- gcc/config/m68k/m68k.c | 6 +- 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libstdc++-v3/testsuite/23_containers/span/subspan_neg.cc create mode 100644 libstdc++-v3/testsuite/23_containers/span/tuple_element_dynamic_neg.cc create mode 100644 libstdc++-v3/testsuite/23_containers/span/tuple_element_oob_neg.cc create mode 100644 libstdc++-v3/testsuite/23_containers/span/tuple_size_neg.cc create mode 100644 libstdc++-v3/testsuite/24_iterators/range_access_cpp20.cc create mode 100644 libstdc++-v3/testsuite/25_algorithms/cpp_lib_constexpr.cc -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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Tcwg-commits September 2019