Tcwg-commits December 2019

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[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-defconfig updated (6f9b4c6826d -> 0d6ebb4f0dd)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-defconfig in repository toolchain/ci/llvm-project. from 6f9b4c6826d [SelectionDAT] Simplify SelectionDAGBuilder::visitInlineAsm adds 45acc35ac21 [ELF][PPC64] Implement IPLT code sequence for non-preemptib [...] adds fb2944bd7f8 [ELF][PPC32] Implement IPLT code sequence for non-preemptib [...] adds bb87364f26c [ELF][PPC64] Improve "call lacks nop" diagnostic and make i [...] adds 34fe8d04511 [Attributor] Use `changeUseAfterManifest` in AAValueSimplif [...] adds 65661908cb6 [NFC] Add test for load-insert-store pattern adds b47b35ff51b [Diagnostic] Add ftabstop to -Wmisleading-indentation adds 36ae255663c [opt] Fix run-twice crash and detection problem adds cd2a73a9f01 [MCP] Add stats for backward copy propagation. NFC. adds 94a24e7a401 [MIPS GlobalISel] Select bswap adds dbc136e0fe7 [MIPS GlobalISel] Select bitreverse adds 4a188fdfa79 [OpenCL] Add mipmap builtin functions adds 8232497c313 [ARM][THUMB2] Allow emitting T3 types of add and sub adds 1b6286b945a [LV][NFC] Some refactoring and renaming to facilitate next change. adds 948e745270d [LV][NFC] Keep dominator tree up to date during vectorization. adds a5a141544d0 [ARM] MVE sink ICmp test. NFC adds b4abe7afbf5 [ARM] Sink splat to ICmp adds 32cc14100e8 Revert "[MIPS GlobalISel] Select bitreverse" adds 0f0330a7870 [PowerPC] Legalize rounding nodes adds 491cfa4250d AMDGPU/GlobalISel: Account for G_PHI result bank adds 58bcf511070 AMDGPU: Generate check lines adds 9e1a2a668b9 AMDGPU: Improve llvm.round.f64 lowering for CI+ adds 9fd31fdbd30 GlobalISel: moreElementsVector for FP min/max adds 18240c3cd63 AMDGPU/GlobalISel: Add select test for fexp2 adds f33fd9648c4 [ARM][Thumb][FIX] Add unwinding information to t4 adds 987eb8e26cc [InstCombine] propagate sign argument through nested copysigns adds 1247865fe02 AMDGPU/GlobalISel: Select llvm.amdgcn.fmad.ftz adds 98f72a5107c [MIPS GlobalISel] Select bitreverse. Recommit adds ee3eebba0d3 [InstCombine] remove stale comment on test; NFC adds 03b9f0a5e19 Ignore "no-frame-pointer-elim" and "no-frame-pointer-elim-n [...] adds 48e0e68edb3 AMDGPU/GlobalISel: Re-use MRI available in selector adds 0c5bee8fdd4 [test] do not parse ls output for file size; NFCI adds 47a2fd2df4f [X86] Add X86ISD::PCMPGT to SimplifyMultipleUseDemandedBits [...] adds 94d08feaeff TableGen: Fix assert on PatFrags with predicate code adds 7fa0bfe7d58 AMDGPU/GlobalISel: Select mul24 intrinsics adds 4a7aa252a32 [X86][AsmParser] re-introduce 'offset' operator adds 000c6a5038b [OpenMP] Use the OpenMPIRBuilder for `omp cancel` adds 10fedd94b43 [OpenMP] Use the OpenMPIRBuilder for `omp parallel` adds 0bd3cc42485 [PowerPC][docs] Update Embedded PowerPC docs in Compiler Wr [...] adds bc48af8c575 [libomptarget][nfc] Change unintentional target_impl prefix [...] adds 6bd1fcd7959 [OpenMP][FIX] Generalize a test check line adds 07be32961a6 Remove a redundant `default:` on an exhaustive switch(enum). adds 8b23b2bbd96 [CodeGen] Use CreateFNeg in buildFMulAdd adds 70f8dd4cf60 [CodeGen] Use IRBuilder::CreateFNeg for __builtin_conj adds 6185dc0eb3a [X86] Add test case for PR44412. NFC adds 991f7abdfc5 [NFC] Add comments in unit test aix-xcoff-toc.ll to clarify [...] adds 831898ff8ac [SelectionDAG] Fix copy/paste mistake in comment. NFC adds 787e078f3ec [TargetLowering][AMDGPU] Make scalarizeVectorLoad return a [...] adds 0d6ebb4f0dd [mlir] Refactor operation results to use a single use list [...] No new revisions were added by this update. Summary of changes: clang/lib/CodeGen/CGBuiltin.cpp | 7 +- clang/lib/CodeGen/CGExprScalar.cpp | 15 +- clang/lib/CodeGen/CGStmtOpenMP.cpp | 95 +++ clang/lib/Parse/ParseStmt.cpp | 41 +- clang/lib/Sema/OpenCLBuiltins.td | 177 +++++ clang/lib/Sema/SemaStmtAsm.cpp | 7 +- clang/test/CodeGen/complex-builtins-2.c | 20 + clang/test/CodeGen/fp-contract-pragma.cpp | 15 + clang/test/CodeGen/ms-inline-asm-64.c | 4 +- clang/test/CodeGen/ms-inline-asm.c | 12 +- clang/test/CodeGen/ms-inline-asm.cpp | 2 +- clang/test/OpenMP/cancel_codegen.cpp | 119 ++-- clang/test/OpenMP/parallel_codegen.cpp | 117 ++-- clang/test/Parser/ms-inline-asm.c | 5 + clang/test/Parser/warn-misleading-indentation.cpp | 83 ++- lld/ELF/Arch/PPC.cpp | 12 +- lld/ELF/Arch/PPC64.cpp | 10 +- lld/ELF/InputSection.cpp | 12 +- lld/ELF/Thunks.cpp | 29 +- lld/ELF/Thunks.h | 5 + ...ptable.s => ppc32-ifunc-nonpreemptible-nopic.s} | 21 +- ...emptable.s => ppc32-ifunc-nonpreemptible-pic.s} | 36 +- lld/test/ELF/ppc64-bsymbolic-toc-restore.s | 2 +- lld/test/ELF/ppc64-error-toc-restore.s | 2 +- lld/test/ELF/ppc64-error-toc-tail-call.s | 8 +- lld/test/ELF/ppc64-ifunc.s | 95 ++- lld/test/ELF/ppc64-toc-relax-ifunc.s | 4 +- llvm/docs/CompilerWriterInfo.rst | 12 +- llvm/docs/ReleaseNotes.rst | 5 + .../llvm/CodeGen/GlobalISel/LegalizerHelper.h | 2 + llvm/include/llvm/CodeGen/TargetLowering.h | 7 +- llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h | 18 + llvm/include/llvm/Frontend/OpenMP/OMPKinds.def | 29 +- llvm/include/llvm/IR/AutoUpgrade.h | 5 + llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h | 8 +- llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h | 47 +- llvm/include/llvm/Transforms/IPO/Attributor.h | 10 + llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 1 + llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 111 ++- llvm/lib/CodeGen/MachineCopyPropagation.cpp | 6 +- .../lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 10 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 12 +- llvm/lib/CodeGen/TargetOptionsImpl.cpp | 14 +- llvm/lib/Frontend/OpenMP/OMPConstants.cpp | 2 +- llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 138 +++- llvm/lib/IR/AutoUpgrade.cpp | 20 + llvm/lib/MC/MCParser/AsmParser.cpp | 52 +- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 24 +- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 2 +- llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td | 18 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 16 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 1 + llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 36 +- llvm/lib/Target/AMDGPU/R600ISelLowering.cpp | 4 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 7 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 7 +- llvm/lib/Target/AMDGPU/VOP2Instructions.td | 4 +- llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 2 + llvm/lib/Target/ARM/ARMISelLowering.cpp | 1 + llvm/lib/Target/ARM/MVETailPredication.cpp | 4 +- llvm/lib/Target/ARM/Thumb2InstrInfo.cpp | 75 +- llvm/lib/Target/Mips/MipsLegalizerInfo.cpp | 17 + llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp | 1 + llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 15 + llvm/lib/Target/PowerPC/PPCInstrVSX.td | 37 + llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 216 +++--- llvm/lib/Target/X86/AsmParser/X86Operand.h | 20 +- llvm/lib/Target/X86/X86AsmPrinter.cpp | 8 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 7 + llvm/lib/Transforms/IPO/Attributor.cpp | 6 +- .../Transforms/InstCombine/InstCombineCalls.cpp | 10 + llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 227 +++--- llvm/lib/Transforms/Vectorize/VPlan.cpp | 10 +- llvm/lib/Transforms/Vectorize/VPlan.h | 4 +- llvm/test/Bitcode/upgrade-frame-pointer.ll | 33 + .../GlobalISel/inst-select-amdgcn.fmad.ftz.mir | 233 +++++++ .../GlobalISel/inst-select-amdgcn.mul.u24.mir | 65 ++ .../AMDGPU/GlobalISel/inst-select-fexp2.mir | 42 ++ .../AMDGPU/GlobalISel/legalize-bitreverse.mir | 21 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir | 42 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir | 42 +- .../AMDGPU/GlobalISel/regbankselect-phi-s1.mir | 96 ++- .../AMDGPU/GlobalISel/regbankselect-phi.mir | 14 +- llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll | 762 ++++++++++++++++++++- llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir | 88 +++ .../Mips/GlobalISel/instruction-select/bswap.mir | 30 + .../Mips/GlobalISel/legalizer/bitreverse.mir | 215 ++++++ .../CodeGen/Mips/GlobalISel/legalizer/bswap.mir | 101 +++ .../CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll | 184 +++++ llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bswap.ll | 68 ++ .../Mips/GlobalISel/regbankselect/bswap.mir | 28 + llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll | 10 + llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll | 2 +- llvm/test/CodeGen/PowerPC/rounding-ops.ll | 8 +- llvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll | 561 +++++++++++++++ .../PowerPC/vector-constrained-fp-intrinsics.ll | 372 +++------- .../cond-vector-reduce-mve-codegen.ll | 17 +- .../Thumb2/LowOverheadLoops/fast-fp-loops.ll | 280 ++++---- llvm/test/CodeGen/Thumb2/emit-unwinding.ll | 15 + llvm/test/CodeGen/Thumb2/large-call.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll | 615 +++++++++++++++++ llvm/test/CodeGen/Thumb2/mve-stacksplot.mir | 3 +- llvm/test/CodeGen/X86/ms-inline-asm.ll | 2 +- llvm/test/CodeGen/X86/offset-operator.ll | 15 + llvm/test/CodeGen/X86/pr44412.ll | 36 + llvm/test/CodeGen/X86/sadd_sat.ll | 4 +- llvm/test/CodeGen/X86/sadd_sat_vec.ll | 140 ++-- llvm/test/CodeGen/X86/ssub_sat.ll | 10 +- llvm/test/CodeGen/X86/ssub_sat_vec.ll | 220 +++--- llvm/test/MC/X86/pr32530.s | 13 + llvm/test/TableGen/predicate-patfags.td | 63 ++ .../ArgumentPromotion/2008-07-02-array-indexing.ll | 2 +- .../Attributor/ArgumentPromotion/control-flow.ll | 2 +- .../Attributor/ArgumentPromotion/control-flow2.ll | 4 +- .../Attributor/ArgumentPromotion/reserve-tbaa.ll | 2 +- llvm/test/Transforms/Attributor/value-simplify.ll | 2 +- llvm/test/Transforms/InstCombine/copysign.ll | 5 +- .../Transforms/InstCombine/load-insert-store.ll | 98 +++ llvm/test/tools/llvm-profdata/show-prof-size.test | 2 +- .../tools/yaml2obj/ELF/custom-null-section.yaml | 4 +- llvm/tools/opt/opt.cpp | 13 +- llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp | 120 ++++ llvm/utils/TableGen/CodeGenDAGPatterns.cpp | 26 +- mlir/include/mlir/IR/Block.h | 2 +- mlir/include/mlir/IR/Operation.h | 32 +- mlir/include/mlir/IR/UseDefLists.h | 354 +++++++--- mlir/include/mlir/IR/Value.h | 78 ++- mlir/lib/IR/Operation.cpp | 58 +- mlir/lib/IR/Value.cpp | 95 ++- mlir/lib/Transforms/ViewOpGraph.cpp | 10 +- .../deviceRTLs/amdgcn/src/target_impl.h | 4 +- .../libomptarget/deviceRTLs/common/src/libcall.cu | 4 +- .../deviceRTLs/nvptx/src/target_impl.h | 6 +- 133 files changed, 5998 insertions(+), 1620 deletions(-) create mode 100644 clang/test/CodeGen/complex-builtins-2.c copy lld/test/ELF/{ppc32-gnu-ifunc-nonpreemptable.s => ppc32-ifunc-nonpreemptible- [...] rename lld/test/ELF/{ppc32-gnu-ifunc-nonpreemptable.s => ppc32-ifunc-nonpreemptibl [...] create mode 100644 llvm/test/Bitcode/upgrade-frame-pointer.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmad.ftz.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mul.u24.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir create mode 100644 llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bswap.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitreverse.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/bswap.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bswap.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bswap.mir create mode 100644 llvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll create mode 100644 llvm/test/CodeGen/X86/offset-operator.ll create mode 100644 llvm/test/CodeGen/X86/pr44412.ll create mode 100644 llvm/test/MC/X86/pr32530.s create mode 100644 llvm/test/TableGen/predicate-patfags.td create mode 100644 llvm/test/Transforms/InstCombine/load-insert-store.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-defconfig updated (67ea57ead -> 53e3e317d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-defconfig in repository toolchain/ci/base-artifacts. discards 67ea57ead 0: update: llvm-linux: boot new 53e3e317d 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (67ea57ead) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 166 +- 02-build_llvm/console.log | 12444 +++++++++++++++---------------- 03-build_linux/console.log | 1992 +++-- 04-boot_linux/console.log | 406 +- 05-check_regression/console.log | 2 +- 06-update_baseline/console.log | 10 +- console.log | 15020 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 8 files changed, 14968 insertions(+), 15080 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-defconfig updated (6f9b4c6826d -> 0d6ebb4f0dd)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-defconfig in repository toolchain/ci/llvm-project. from 6f9b4c6826d [SelectionDAT] Simplify SelectionDAGBuilder::visitInlineAsm adds 45acc35ac21 [ELF][PPC64] Implement IPLT code sequence for non-preemptib [...] adds fb2944bd7f8 [ELF][PPC32] Implement IPLT code sequence for non-preemptib [...] adds bb87364f26c [ELF][PPC64] Improve "call lacks nop" diagnostic and make i [...] adds 34fe8d04511 [Attributor] Use `changeUseAfterManifest` in AAValueSimplif [...] adds 65661908cb6 [NFC] Add test for load-insert-store pattern adds b47b35ff51b [Diagnostic] Add ftabstop to -Wmisleading-indentation adds 36ae255663c [opt] Fix run-twice crash and detection problem adds cd2a73a9f01 [MCP] Add stats for backward copy propagation. NFC. adds 94a24e7a401 [MIPS GlobalISel] Select bswap adds dbc136e0fe7 [MIPS GlobalISel] Select bitreverse adds 4a188fdfa79 [OpenCL] Add mipmap builtin functions adds 8232497c313 [ARM][THUMB2] Allow emitting T3 types of add and sub adds 1b6286b945a [LV][NFC] Some refactoring and renaming to facilitate next change. adds 948e745270d [LV][NFC] Keep dominator tree up to date during vectorization. adds a5a141544d0 [ARM] MVE sink ICmp test. NFC adds b4abe7afbf5 [ARM] Sink splat to ICmp adds 32cc14100e8 Revert "[MIPS GlobalISel] Select bitreverse" adds 0f0330a7870 [PowerPC] Legalize rounding nodes adds 491cfa4250d AMDGPU/GlobalISel: Account for G_PHI result bank adds 58bcf511070 AMDGPU: Generate check lines adds 9e1a2a668b9 AMDGPU: Improve llvm.round.f64 lowering for CI+ adds 9fd31fdbd30 GlobalISel: moreElementsVector for FP min/max adds 18240c3cd63 AMDGPU/GlobalISel: Add select test for fexp2 adds f33fd9648c4 [ARM][Thumb][FIX] Add unwinding information to t4 adds 987eb8e26cc [InstCombine] propagate sign argument through nested copysigns adds 1247865fe02 AMDGPU/GlobalISel: Select llvm.amdgcn.fmad.ftz adds 98f72a5107c [MIPS GlobalISel] Select bitreverse. Recommit adds ee3eebba0d3 [InstCombine] remove stale comment on test; NFC adds 03b9f0a5e19 Ignore "no-frame-pointer-elim" and "no-frame-pointer-elim-n [...] adds 48e0e68edb3 AMDGPU/GlobalISel: Re-use MRI available in selector adds 0c5bee8fdd4 [test] do not parse ls output for file size; NFCI adds 47a2fd2df4f [X86] Add X86ISD::PCMPGT to SimplifyMultipleUseDemandedBits [...] adds 94d08feaeff TableGen: Fix assert on PatFrags with predicate code adds 7fa0bfe7d58 AMDGPU/GlobalISel: Select mul24 intrinsics adds 4a7aa252a32 [X86][AsmParser] re-introduce 'offset' operator adds 000c6a5038b [OpenMP] Use the OpenMPIRBuilder for `omp cancel` adds 10fedd94b43 [OpenMP] Use the OpenMPIRBuilder for `omp parallel` adds 0bd3cc42485 [PowerPC][docs] Update Embedded PowerPC docs in Compiler Wr [...] adds bc48af8c575 [libomptarget][nfc] Change unintentional target_impl prefix [...] adds 6bd1fcd7959 [OpenMP][FIX] Generalize a test check line adds 07be32961a6 Remove a redundant `default:` on an exhaustive switch(enum). adds 8b23b2bbd96 [CodeGen] Use CreateFNeg in buildFMulAdd adds 70f8dd4cf60 [CodeGen] Use IRBuilder::CreateFNeg for __builtin_conj adds 6185dc0eb3a [X86] Add test case for PR44412. NFC adds 991f7abdfc5 [NFC] Add comments in unit test aix-xcoff-toc.ll to clarify [...] adds 831898ff8ac [SelectionDAG] Fix copy/paste mistake in comment. NFC adds 787e078f3ec [TargetLowering][AMDGPU] Make scalarizeVectorLoad return a [...] new 0d6ebb4f0dd [mlir] Refactor operation results to use a single use list [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: clang/lib/CodeGen/CGBuiltin.cpp | 7 +- clang/lib/CodeGen/CGExprScalar.cpp | 15 +- clang/lib/CodeGen/CGStmtOpenMP.cpp | 95 +++ clang/lib/Parse/ParseStmt.cpp | 41 +- clang/lib/Sema/OpenCLBuiltins.td | 177 +++++ clang/lib/Sema/SemaStmtAsm.cpp | 7 +- clang/test/CodeGen/complex-builtins-2.c | 20 + clang/test/CodeGen/fp-contract-pragma.cpp | 15 + clang/test/CodeGen/ms-inline-asm-64.c | 4 +- clang/test/CodeGen/ms-inline-asm.c | 12 +- clang/test/CodeGen/ms-inline-asm.cpp | 2 +- clang/test/OpenMP/cancel_codegen.cpp | 119 ++-- clang/test/OpenMP/parallel_codegen.cpp | 117 ++-- clang/test/Parser/ms-inline-asm.c | 5 + clang/test/Parser/warn-misleading-indentation.cpp | 83 ++- lld/ELF/Arch/PPC.cpp | 12 +- lld/ELF/Arch/PPC64.cpp | 10 +- lld/ELF/InputSection.cpp | 12 +- lld/ELF/Thunks.cpp | 29 +- lld/ELF/Thunks.h | 5 + ...ptable.s => ppc32-ifunc-nonpreemptible-nopic.s} | 21 +- ...emptable.s => ppc32-ifunc-nonpreemptible-pic.s} | 36 +- lld/test/ELF/ppc64-bsymbolic-toc-restore.s | 2 +- lld/test/ELF/ppc64-error-toc-restore.s | 2 +- lld/test/ELF/ppc64-error-toc-tail-call.s | 8 +- lld/test/ELF/ppc64-ifunc.s | 95 ++- lld/test/ELF/ppc64-toc-relax-ifunc.s | 4 +- llvm/docs/CompilerWriterInfo.rst | 12 +- llvm/docs/ReleaseNotes.rst | 5 + .../llvm/CodeGen/GlobalISel/LegalizerHelper.h | 2 + llvm/include/llvm/CodeGen/TargetLowering.h | 7 +- llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h | 18 + llvm/include/llvm/Frontend/OpenMP/OMPKinds.def | 29 +- llvm/include/llvm/IR/AutoUpgrade.h | 5 + llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h | 8 +- llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h | 47 +- llvm/include/llvm/Transforms/IPO/Attributor.h | 10 + llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 1 + llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 111 ++- llvm/lib/CodeGen/MachineCopyPropagation.cpp | 6 +- .../lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 10 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 12 +- llvm/lib/CodeGen/TargetOptionsImpl.cpp | 14 +- llvm/lib/Frontend/OpenMP/OMPConstants.cpp | 2 +- llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 138 +++- llvm/lib/IR/AutoUpgrade.cpp | 20 + llvm/lib/MC/MCParser/AsmParser.cpp | 52 +- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 24 +- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 2 +- llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td | 18 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 16 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 1 + llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 36 +- llvm/lib/Target/AMDGPU/R600ISelLowering.cpp | 4 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 7 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 7 +- llvm/lib/Target/AMDGPU/VOP2Instructions.td | 4 +- llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 2 + llvm/lib/Target/ARM/ARMISelLowering.cpp | 1 + llvm/lib/Target/ARM/MVETailPredication.cpp | 4 +- llvm/lib/Target/ARM/Thumb2InstrInfo.cpp | 75 +- llvm/lib/Target/Mips/MipsLegalizerInfo.cpp | 17 + llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp | 1 + llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 15 + llvm/lib/Target/PowerPC/PPCInstrVSX.td | 37 + llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 216 +++--- llvm/lib/Target/X86/AsmParser/X86Operand.h | 20 +- llvm/lib/Target/X86/X86AsmPrinter.cpp | 8 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 7 + llvm/lib/Transforms/IPO/Attributor.cpp | 6 +- .../Transforms/InstCombine/InstCombineCalls.cpp | 10 + llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 227 +++--- llvm/lib/Transforms/Vectorize/VPlan.cpp | 10 +- llvm/lib/Transforms/Vectorize/VPlan.h | 4 +- llvm/test/Bitcode/upgrade-frame-pointer.ll | 33 + .../GlobalISel/inst-select-amdgcn.fmad.ftz.mir | 233 +++++++ .../GlobalISel/inst-select-amdgcn.mul.u24.mir | 65 ++ .../AMDGPU/GlobalISel/inst-select-fexp2.mir | 42 ++ .../AMDGPU/GlobalISel/legalize-bitreverse.mir | 21 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir | 42 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir | 42 +- .../AMDGPU/GlobalISel/regbankselect-phi-s1.mir | 96 ++- .../AMDGPU/GlobalISel/regbankselect-phi.mir | 14 +- llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll | 762 ++++++++++++++++++++- llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir | 88 +++ .../Mips/GlobalISel/instruction-select/bswap.mir | 30 + .../Mips/GlobalISel/legalizer/bitreverse.mir | 215 ++++++ .../CodeGen/Mips/GlobalISel/legalizer/bswap.mir | 101 +++ .../CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll | 184 +++++ llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bswap.ll | 68 ++ .../Mips/GlobalISel/regbankselect/bswap.mir | 28 + llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll | 10 + llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll | 2 +- llvm/test/CodeGen/PowerPC/rounding-ops.ll | 8 +- llvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll | 561 +++++++++++++++ .../PowerPC/vector-constrained-fp-intrinsics.ll | 372 +++------- .../cond-vector-reduce-mve-codegen.ll | 17 +- .../Thumb2/LowOverheadLoops/fast-fp-loops.ll | 280 ++++---- llvm/test/CodeGen/Thumb2/emit-unwinding.ll | 15 + llvm/test/CodeGen/Thumb2/large-call.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll | 615 +++++++++++++++++ llvm/test/CodeGen/Thumb2/mve-stacksplot.mir | 3 +- llvm/test/CodeGen/X86/ms-inline-asm.ll | 2 +- llvm/test/CodeGen/X86/offset-operator.ll | 15 + llvm/test/CodeGen/X86/pr44412.ll | 36 + llvm/test/CodeGen/X86/sadd_sat.ll | 4 +- llvm/test/CodeGen/X86/sadd_sat_vec.ll | 140 ++-- llvm/test/CodeGen/X86/ssub_sat.ll | 10 +- llvm/test/CodeGen/X86/ssub_sat_vec.ll | 220 +++--- llvm/test/MC/X86/pr32530.s | 13 + llvm/test/TableGen/predicate-patfags.td | 63 ++ .../ArgumentPromotion/2008-07-02-array-indexing.ll | 2 +- .../Attributor/ArgumentPromotion/control-flow.ll | 2 +- .../Attributor/ArgumentPromotion/control-flow2.ll | 4 +- .../Attributor/ArgumentPromotion/reserve-tbaa.ll | 2 +- llvm/test/Transforms/Attributor/value-simplify.ll | 2 +- llvm/test/Transforms/InstCombine/copysign.ll | 5 +- .../Transforms/InstCombine/load-insert-store.ll | 98 +++ llvm/test/tools/llvm-profdata/show-prof-size.test | 2 +- .../tools/yaml2obj/ELF/custom-null-section.yaml | 4 +- llvm/tools/opt/opt.cpp | 13 +- llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp | 120 ++++ llvm/utils/TableGen/CodeGenDAGPatterns.cpp | 26 +- mlir/include/mlir/IR/Block.h | 2 +- mlir/include/mlir/IR/Operation.h | 32 +- mlir/include/mlir/IR/UseDefLists.h | 354 +++++++--- mlir/include/mlir/IR/Value.h | 78 ++- mlir/lib/IR/Operation.cpp | 58 +- mlir/lib/IR/Value.cpp | 95 ++- mlir/lib/Transforms/ViewOpGraph.cpp | 10 +- .../deviceRTLs/amdgcn/src/target_impl.h | 4 +- .../libomptarget/deviceRTLs/common/src/libcall.cu | 4 +- .../deviceRTLs/nvptx/src/target_impl.h | 6 +- 133 files changed, 5998 insertions(+), 1620 deletions(-) create mode 100644 clang/test/CodeGen/complex-builtins-2.c copy lld/test/ELF/{ppc32-gnu-ifunc-nonpreemptable.s => ppc32-ifunc-nonpreemptible- [...] rename lld/test/ELF/{ppc32-gnu-ifunc-nonpreemptable.s => ppc32-ifunc-nonpreemptibl [...] create mode 100644 llvm/test/Bitcode/upgrade-frame-pointer.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmad.ftz.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mul.u24.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir create mode 100644 llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bswap.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitreverse.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/bswap.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bswap.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bswap.mir create mode 100644 llvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll create mode 100644 llvm/test/CodeGen/X86/offset-operator.ll create mode 100644 llvm/test/CodeGen/X86/pr44412.ll create mode 100644 llvm/test/MC/X86/pr32530.s create mode 100644 llvm/test/TableGen/predicate-patfags.td create mode 100644 llvm/test/Transforms/InstCombine/load-insert-store.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-defconfig updated (377b8a030 -> 6027f8a99)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-defconfig in repository toolchain/ci/base-artifacts. discards 377b8a030 0: update: llvm-linux: boot new 6027f8a99 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (377b8a030) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-m [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 220 +- 02-build_llvm/console.log | 12515 +++++++++++++++++----------------- 03-build_linux/console.log | 733 +- 04-boot_linux/console.log | 480 +- 05-check_regression/console.log | 10 +- 06-update_baseline/console.log | 10 +- console.log | 13968 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 8 files changed, 13922 insertions(+), 14022 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-defconfig updated (27930c060ec -> 47c4fc06d50)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-defconfig in repository toolchain/ci/gcc. from 27930c060ec Daily bump. adds c913774742e Catch division by zero errors in array sizes. adds 4af36fdd79e Remove KIND argument from INDEX so it does not mess up scal [...] adds 08edd2515e5 2019-12-30 Thomas Koenig <tkoenig(a)gcc.gnu.org> adds f6926fe5580 2019-12-30 Thomas Koenig <tkoenig(a)gcc.gnu.org> adds 7c23961a159 /gcc/cp 2019-12-30 Paolo Carlini <paolo.carlini(a)oracle.com> adds eaa18cd42c4 Remove assert in reshape_init_r. adds 9f40a2fccb6 Fix builtin functions needlessly using VIEW_CONVERT_EXPRs o [...] adds 43dd84f2c71 PR libgomp/93066 * inclhack.def (hpux_c99_inttypes3): Fix [...] adds 91c08cedf7f Fix typo in macro name guarding conditional in vxcrtstuff.c adds 09261b9be2f Fix macro reference in gthr-vxworks-tls.c adds 8ba90d1382a Improve VxWorks GTHREAD_ONCE_INIT adds bdc7738bb12 Improve recursion protection for VxWorks limits.h adds 52a91c9b12b Define STARTFILE_PREFIX_SPEC for powerpc VxWorks < 7 adds f072cb86e3b Identify sections in vx-common.h adds 12579d96252 Refine definitions for wchar_t/wint_t on VxWorks adds 489a291637f Setup TARGET_C_PREINCLUDE for VxWorks adds 600a680fb87 Simplify the compilation commands for config/vxworks.c adds c32bc16cc56 Introduce an internal API for VxWorks version checks adds 137897f3ada Setup system header wrappers for C++ on VxWorks adds f32f801247c Add missing file expected with rev 279781 adds 81312f86812 Add missing file expected with rev 279783 adds d98b8959618 Add missing files expected with rev 279784 adds 5b8261921fd * fi.po: Update. adds 2758cc57aa3 Add missing file expected with rev 279781 adds 56560d70ba6 Arrange to preinclude yvals.h ahead of stdint on VxWorks 7 adds f0b20ef201f Adapt libstdc++ os_defines for VxWorks to more recent versions adds 8beea8fd991 Guard aarch64/aapcs64 tests using abitest.S by check_weak_a [...] adds 220fd779b08 allow $ in scan-tree-dump expressions matching symbol names adds 48cc6949449 Prevent redefinition of WCHAR_MAX from testsuite/gcc.dg/cpp/ucs.c adds 20ce1da0ecc VxWorks has_nanosleep for libstdc++ enable-libstdcxx-time auto adds 043b2d62c9d undefine OFFSET in testsuite/gcc.dg/vect/tree-vect.h adds 854804d4d0b Add ChangeLog entry for rev 279797 adds 47c4fc06d50 Daily bump. No new revisions were added by this update. Summary of changes: fixincludes/ChangeLog | 8 + fixincludes/fixincl.x | 65 +- fixincludes/inclhack.def | 26 + fixincludes/tests/base/inttypes.h | 17 + gcc/ChangeLog | 170 ++++++ gcc/DATESTAMP | 2 +- gcc/config.gcc | 37 +- gcc/config/rs6000/rs6000-builtin.def | 88 ++- gcc/config/rs6000/rs6000-call.c | 523 +++++++++------- gcc/config/rs6000/vxworks.h | 7 + gcc/config/t-vxworks | 55 +- gcc/config/vx-common.h | 47 +- gcc/config/vxworks-c.c | 37 ++ gcc/config/vxworks/_vxworks-versions.h | 54 ++ gcc/config/vxworks/_yvals-wrapper.h | 44 ++ gcc/config/vxworks/_yvals.h | 45 ++ gcc/config/vxworks/complex.h | 28 + gcc/config/vxworks/inttypes.h | 28 + gcc/config/vxworks/math.h | 28 + gcc/config/vxworks/setjmp.h | 34 ++ gcc/config/vxworks/stdint.h | 28 + gcc/config/vxworks/vxworks-predef.h | 32 + gcc/cp/ChangeLog | 20 + gcc/cp/cp-tree.h | 7 +- gcc/cp/decl.c | 3 +- gcc/cp/decl2.c | 22 +- gcc/cp/init.c | 101 ++-- gcc/cp/parser.c | 3 +- gcc/cp/pt.c | 2 +- gcc/fortran/ChangeLog | 24 + gcc/fortran/arith.c | 6 + gcc/fortran/decl.c | 31 +- gcc/fortran/gfortran.h | 2 + gcc/fortran/intrinsic.c | 48 +- gcc/fortran/intrinsic.h | 3 +- gcc/fortran/iresolve.c | 25 +- gcc/fortran/trans-decl.c | 24 +- gcc/po/ChangeLog | 4 + gcc/po/fi.po | 654 +++++++++++---------- gcc/testsuite/ChangeLog | 52 ++ gcc/testsuite/c-c++-common/pr56493.c | 2 +- gcc/testsuite/g++.dg/init/delete1.C | 6 +- gcc/testsuite/g++.dg/ipa/pr85607.C | 8 +- gcc/testsuite/g++.dg/warn/Wdelete-incomplete-1.C | 7 +- .../g++.dg/warn/delete-non-virtual-dtor.C | 10 +- gcc/testsuite/g++.dg/warn/incomplete1.C | 8 +- gcc/testsuite/gcc.dg/cpp/ucs.c | 4 + gcc/testsuite/gcc.dg/tree-ssa/sra-17.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/sra-18.c | 8 +- gcc/testsuite/gcc.dg/vect/tree-vect.h | 6 + .../gcc.target/aarch64/aapcs64/aapcs64.exp | 36 +- gcc/testsuite/gcc.target/powerpc/pr92923-1.c | 453 ++++++++++++++ gcc/testsuite/gcc.target/powerpc/pr92923-2.c | 285 +++++++++ gcc/testsuite/gfortran.dg/arith_divide_2.f90 | 9 + gcc/testsuite/gfortran.dg/index_3.f90 | 8 + libcc1/ChangeLog | 5 + libcc1/libcp1plugin.cc | 3 +- libgcc/ChangeLog | 20 + libgcc/config/gthr-vxworks-tls.c | 12 +- libgcc/config/gthr-vxworks.h | 14 +- libgcc/config/vxcrtstuff.c | 4 +- libstdc++-v3/ChangeLog | 24 + libstdc++-v3/acinclude.m4 | 5 + libstdc++-v3/config/os/vxworks/os_defines.h | 67 ++- libstdc++-v3/configure | 5 + 65 files changed, 2730 insertions(+), 715 deletions(-) create mode 100644 gcc/config/vxworks-c.c create mode 100644 gcc/config/vxworks/_vxworks-versions.h create mode 100644 gcc/config/vxworks/_yvals-wrapper.h create mode 100644 gcc/config/vxworks/_yvals.h create mode 100644 gcc/config/vxworks/complex.h create mode 100644 gcc/config/vxworks/inttypes.h create mode 100644 gcc/config/vxworks/math.h create mode 100644 gcc/config/vxworks/setjmp.h create mode 100644 gcc/config/vxworks/stdint.h create mode 100644 gcc/config/vxworks/vxworks-predef.h create mode 100644 gcc/testsuite/gcc.target/powerpc/pr92923-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr92923-2.c create mode 100644 gcc/testsuite/gfortran.dg/arith_divide_2.f90 create mode 100644 gcc/testsuite/gfortran.dg/index_3.f90 -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-defconfig updated (6a89db5c95 -> 930be66764)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-defconfig in repository toolchain/ci/binutils-gdb. from 6a89db5c95 archive.c bfd_zalloc adds 37d5ab199b coff object_p memory leaks adds a7ac9aa525 vms-alpha.c object_p memory leaks adds 87d557ae1b Use "bool" in more spots in TUI adds 3d34df0aa7 Make some TUI globals "static" adds 930be66764 Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 10 ++++++++++ bfd/coffgen.c | 3 +++ bfd/version.h | 2 +- bfd/vms-alpha.c | 34 ++++++++++++++++++++++------------ gdb/ChangeLog | 22 ++++++++++++++++++++++ gdb/tui/tui-hooks.c | 12 ++++++------ gdb/tui/tui-interp.c | 6 +++--- gdb/tui/tui-win.c | 32 ++++++++++++++++---------------- gdb/tui/tui-win.h | 2 +- gdb/tui/tui.c | 8 +++----- gdb/tui/tui.h | 4 ++-- 11 files changed, 89 insertions(+), 46 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-defconfig updated (80b80bc92 -> 63cf216c1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-defconfig in repository toolchain/ci/base-artifacts. discards 80b80bc92 0: update: binutils-gcc-linux: boot new 63cf216c1 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (80b80bc92) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-arm-st [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 182 +- 02-prepare_abe/console.log | 428 +- 03-build_abe-binutils/console.log | 11328 +++++++------ 04-build_abe-stage1/console.log | 17781 ++++++++++---------- 05-build_linux/console.log | 2174 +-- 06-boot_linux/console.log | 476 +- 07-check_regression/console.log | 10 +- 08-update_baseline/console.log | 10 +- console.log | 32602 ++++++++++++++++++------------------ jenkins/manifest.sh | 12 +- 10 files changed, 32503 insertions(+), 32500 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allyesconfig updated (27930c060ec -> 47c4fc06d50)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allyesconfig in repository toolchain/ci/gcc. from 27930c060ec Daily bump. adds c913774742e Catch division by zero errors in array sizes. adds 4af36fdd79e Remove KIND argument from INDEX so it does not mess up scal [...] adds 08edd2515e5 2019-12-30 Thomas Koenig <tkoenig(a)gcc.gnu.org> adds f6926fe5580 2019-12-30 Thomas Koenig <tkoenig(a)gcc.gnu.org> adds 7c23961a159 /gcc/cp 2019-12-30 Paolo Carlini <paolo.carlini(a)oracle.com> adds eaa18cd42c4 Remove assert in reshape_init_r. adds 9f40a2fccb6 Fix builtin functions needlessly using VIEW_CONVERT_EXPRs o [...] adds 43dd84f2c71 PR libgomp/93066 * inclhack.def (hpux_c99_inttypes3): Fix [...] adds 91c08cedf7f Fix typo in macro name guarding conditional in vxcrtstuff.c adds 09261b9be2f Fix macro reference in gthr-vxworks-tls.c adds 8ba90d1382a Improve VxWorks GTHREAD_ONCE_INIT adds bdc7738bb12 Improve recursion protection for VxWorks limits.h adds 52a91c9b12b Define STARTFILE_PREFIX_SPEC for powerpc VxWorks < 7 adds f072cb86e3b Identify sections in vx-common.h adds 12579d96252 Refine definitions for wchar_t/wint_t on VxWorks adds 489a291637f Setup TARGET_C_PREINCLUDE for VxWorks adds 600a680fb87 Simplify the compilation commands for config/vxworks.c adds c32bc16cc56 Introduce an internal API for VxWorks version checks adds 137897f3ada Setup system header wrappers for C++ on VxWorks adds f32f801247c Add missing file expected with rev 279781 adds 81312f86812 Add missing file expected with rev 279783 adds d98b8959618 Add missing files expected with rev 279784 adds 5b8261921fd * fi.po: Update. adds 2758cc57aa3 Add missing file expected with rev 279781 adds 56560d70ba6 Arrange to preinclude yvals.h ahead of stdint on VxWorks 7 adds f0b20ef201f Adapt libstdc++ os_defines for VxWorks to more recent versions adds 8beea8fd991 Guard aarch64/aapcs64 tests using abitest.S by check_weak_a [...] adds 220fd779b08 allow $ in scan-tree-dump expressions matching symbol names adds 48cc6949449 Prevent redefinition of WCHAR_MAX from testsuite/gcc.dg/cpp/ucs.c adds 20ce1da0ecc VxWorks has_nanosleep for libstdc++ enable-libstdcxx-time auto adds 043b2d62c9d undefine OFFSET in testsuite/gcc.dg/vect/tree-vect.h adds 854804d4d0b Add ChangeLog entry for rev 279797 adds 47c4fc06d50 Daily bump. No new revisions were added by this update. Summary of changes: fixincludes/ChangeLog | 8 + fixincludes/fixincl.x | 65 +- fixincludes/inclhack.def | 26 + fixincludes/tests/base/inttypes.h | 17 + gcc/ChangeLog | 170 ++++++ gcc/DATESTAMP | 2 +- gcc/config.gcc | 37 +- gcc/config/rs6000/rs6000-builtin.def | 88 ++- gcc/config/rs6000/rs6000-call.c | 523 +++++++++------- gcc/config/rs6000/vxworks.h | 7 + gcc/config/t-vxworks | 55 +- gcc/config/vx-common.h | 47 +- gcc/config/vxworks-c.c | 37 ++ gcc/config/vxworks/_vxworks-versions.h | 54 ++ gcc/config/vxworks/_yvals-wrapper.h | 44 ++ gcc/config/vxworks/_yvals.h | 45 ++ gcc/config/vxworks/complex.h | 28 + gcc/config/vxworks/inttypes.h | 28 + gcc/config/vxworks/math.h | 28 + gcc/config/vxworks/setjmp.h | 34 ++ gcc/config/vxworks/stdint.h | 28 + gcc/config/vxworks/vxworks-predef.h | 32 + gcc/cp/ChangeLog | 20 + gcc/cp/cp-tree.h | 7 +- gcc/cp/decl.c | 3 +- gcc/cp/decl2.c | 22 +- gcc/cp/init.c | 101 ++-- gcc/cp/parser.c | 3 +- gcc/cp/pt.c | 2 +- gcc/fortran/ChangeLog | 24 + gcc/fortran/arith.c | 6 + gcc/fortran/decl.c | 31 +- gcc/fortran/gfortran.h | 2 + gcc/fortran/intrinsic.c | 48 +- gcc/fortran/intrinsic.h | 3 +- gcc/fortran/iresolve.c | 25 +- gcc/fortran/trans-decl.c | 24 +- gcc/po/ChangeLog | 4 + gcc/po/fi.po | 654 +++++++++++---------- gcc/testsuite/ChangeLog | 52 ++ gcc/testsuite/c-c++-common/pr56493.c | 2 +- gcc/testsuite/g++.dg/init/delete1.C | 6 +- gcc/testsuite/g++.dg/ipa/pr85607.C | 8 +- gcc/testsuite/g++.dg/warn/Wdelete-incomplete-1.C | 7 +- .../g++.dg/warn/delete-non-virtual-dtor.C | 10 +- gcc/testsuite/g++.dg/warn/incomplete1.C | 8 +- gcc/testsuite/gcc.dg/cpp/ucs.c | 4 + gcc/testsuite/gcc.dg/tree-ssa/sra-17.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/sra-18.c | 8 +- gcc/testsuite/gcc.dg/vect/tree-vect.h | 6 + .../gcc.target/aarch64/aapcs64/aapcs64.exp | 36 +- gcc/testsuite/gcc.target/powerpc/pr92923-1.c | 453 ++++++++++++++ gcc/testsuite/gcc.target/powerpc/pr92923-2.c | 285 +++++++++ gcc/testsuite/gfortran.dg/arith_divide_2.f90 | 9 + gcc/testsuite/gfortran.dg/index_3.f90 | 8 + libcc1/ChangeLog | 5 + libcc1/libcp1plugin.cc | 3 +- libgcc/ChangeLog | 20 + libgcc/config/gthr-vxworks-tls.c | 12 +- libgcc/config/gthr-vxworks.h | 14 +- libgcc/config/vxcrtstuff.c | 4 +- libstdc++-v3/ChangeLog | 24 + libstdc++-v3/acinclude.m4 | 5 + libstdc++-v3/config/os/vxworks/os_defines.h | 67 ++- libstdc++-v3/configure | 5 + 65 files changed, 2730 insertions(+), 715 deletions(-) create mode 100644 gcc/config/vxworks-c.c create mode 100644 gcc/config/vxworks/_vxworks-versions.h create mode 100644 gcc/config/vxworks/_yvals-wrapper.h create mode 100644 gcc/config/vxworks/_yvals.h create mode 100644 gcc/config/vxworks/complex.h create mode 100644 gcc/config/vxworks/inttypes.h create mode 100644 gcc/config/vxworks/math.h create mode 100644 gcc/config/vxworks/setjmp.h create mode 100644 gcc/config/vxworks/stdint.h create mode 100644 gcc/config/vxworks/vxworks-predef.h create mode 100644 gcc/testsuite/gcc.target/powerpc/pr92923-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr92923-2.c create mode 100644 gcc/testsuite/gfortran.dg/arith_divide_2.f90 create mode 100644 gcc/testsuite/gfortran.dg/index_3.f90 -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allyesconfig updated (6a89db5c95 -> 930be66764)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allyesconfig in repository toolchain/ci/binutils-gdb. from 6a89db5c95 archive.c bfd_zalloc adds 37d5ab199b coff object_p memory leaks adds a7ac9aa525 vms-alpha.c object_p memory leaks adds 87d557ae1b Use "bool" in more spots in TUI adds 3d34df0aa7 Make some TUI globals "static" adds 930be66764 Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 10 ++++++++++ bfd/coffgen.c | 3 +++ bfd/version.h | 2 +- bfd/vms-alpha.c | 34 ++++++++++++++++++++++------------ gdb/ChangeLog | 22 ++++++++++++++++++++++ gdb/tui/tui-hooks.c | 12 ++++++------ gdb/tui/tui-interp.c | 6 +++--- gdb/tui/tui-win.c | 32 ++++++++++++++++---------------- gdb/tui/tui-win.h | 2 +- gdb/tui/tui.c | 8 +++----- gdb/tui/tui.h | 4 ++-- 11 files changed, 89 insertions(+), 46 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allyesconfig updated (d809e1339 -> 0094193be)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allyesconfig in repository toolchain/ci/base-artifacts. discards d809e1339 0: update: binutils-gcc-linux: all new 0094193be 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (d809e1339) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-aarch6 [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 220 +- 02-prepare_abe/console.log | 438 +- 03-build_abe-binutils/console.log | 11814 ++++++------ 04-build_abe-stage1/console.log | 16097 +++++++++-------- 05-build_linux/console.log | 6096 +++---- 06-boot_linux/console.log | 6 +- 07-check_regression/console.log | 10 +- 08-update_baseline/console.log | 10 +- console.log | 34710 ++++++++++++++++++------------------ jenkins/manifest.sh | 12 +- 10 files changed, 34708 insertions(+), 34705 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

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Tcwg-commits December 2019