Tcwg-commits December 2019

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[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig updated (36ae255663c -> a6c59e0792e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig in repository toolchain/ci/llvm-project. from 36ae255663c [opt] Fix run-twice crash and detection problem adds cd2a73a9f01 [MCP] Add stats for backward copy propagation. NFC. adds 94a24e7a401 [MIPS GlobalISel] Select bswap adds dbc136e0fe7 [MIPS GlobalISel] Select bitreverse adds 4a188fdfa79 [OpenCL] Add mipmap builtin functions adds 8232497c313 [ARM][THUMB2] Allow emitting T3 types of add and sub adds 1b6286b945a [LV][NFC] Some refactoring and renaming to facilitate next change. adds 948e745270d [LV][NFC] Keep dominator tree up to date during vectorization. adds a5a141544d0 [ARM] MVE sink ICmp test. NFC adds b4abe7afbf5 [ARM] Sink splat to ICmp adds 32cc14100e8 Revert "[MIPS GlobalISel] Select bitreverse" adds 0f0330a7870 [PowerPC] Legalize rounding nodes adds 491cfa4250d AMDGPU/GlobalISel: Account for G_PHI result bank adds 58bcf511070 AMDGPU: Generate check lines adds 9e1a2a668b9 AMDGPU: Improve llvm.round.f64 lowering for CI+ adds 9fd31fdbd30 GlobalISel: moreElementsVector for FP min/max adds 18240c3cd63 AMDGPU/GlobalISel: Add select test for fexp2 adds f33fd9648c4 [ARM][Thumb][FIX] Add unwinding information to t4 adds 987eb8e26cc [InstCombine] propagate sign argument through nested copysigns adds 1247865fe02 AMDGPU/GlobalISel: Select llvm.amdgcn.fmad.ftz adds 98f72a5107c [MIPS GlobalISel] Select bitreverse. Recommit adds ee3eebba0d3 [InstCombine] remove stale comment on test; NFC adds 03b9f0a5e19 Ignore "no-frame-pointer-elim" and "no-frame-pointer-elim-n [...] adds 48e0e68edb3 AMDGPU/GlobalISel: Re-use MRI available in selector adds 0c5bee8fdd4 [test] do not parse ls output for file size; NFCI adds 47a2fd2df4f [X86] Add X86ISD::PCMPGT to SimplifyMultipleUseDemandedBits [...] adds 94d08feaeff TableGen: Fix assert on PatFrags with predicate code adds 7fa0bfe7d58 AMDGPU/GlobalISel: Select mul24 intrinsics adds 4a7aa252a32 [X86][AsmParser] re-introduce 'offset' operator adds 000c6a5038b [OpenMP] Use the OpenMPIRBuilder for `omp cancel` adds 10fedd94b43 [OpenMP] Use the OpenMPIRBuilder for `omp parallel` adds 0bd3cc42485 [PowerPC][docs] Update Embedded PowerPC docs in Compiler Wr [...] adds bc48af8c575 [libomptarget][nfc] Change unintentional target_impl prefix [...] adds 6bd1fcd7959 [OpenMP][FIX] Generalize a test check line adds 07be32961a6 Remove a redundant `default:` on an exhaustive switch(enum). adds 8b23b2bbd96 [CodeGen] Use CreateFNeg in buildFMulAdd adds 70f8dd4cf60 [CodeGen] Use IRBuilder::CreateFNeg for __builtin_conj adds 6185dc0eb3a [X86] Add test case for PR44412. NFC adds 991f7abdfc5 [NFC] Add comments in unit test aix-xcoff-toc.ll to clarify [...] adds 831898ff8ac [SelectionDAG] Fix copy/paste mistake in comment. NFC adds 787e078f3ec [TargetLowering][AMDGPU] Make scalarizeVectorLoad return a [...] adds 0d6ebb4f0dd [mlir] Refactor operation results to use a single use list [...] adds 5b1cbfa4232 [NFC] Style cleanup adds b350c666ab6 Revert "DebugInfo: Fix rangesBaseAddress DICompileUnit bitc [...] adds 23a6ae2b062 [NFC] Make X86MCCodeEmitter::isPCRel32Branch static adds 28880198718 [Attributor] Annotate the memory behavior of call site arguments adds b1b441d22de [Attributor] Use abstract call sites to determine associate [...] adds dada8132af6 [Attributor] Propagate known align from arguments to call s [...] adds 70771d8b9e8 [Utils] Allow update_test_checks to scrub attribute annotations new be26bd55130 [Utils] Reuse argument variable names in the body new a36a89dcdcf [NFC] Style cleanup new 4a6413cd0a8 [Utils][Fix] Minor test result change new e898ba2d151 [X86] Slightly improve our attempted error recovery for 64- [...] new 751336340da [Attributor] Function signature rewrite infrastructure new a6c59e0792e [Utils] Deal with occasionally deleted functions The 6 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: clang/lib/CodeGen/CGBuiltin.cpp | 7 +- clang/lib/CodeGen/CGExprScalar.cpp | 15 +- clang/lib/CodeGen/CGStmtOpenMP.cpp | 95 +++ clang/lib/Sema/OpenCLBuiltins.td | 177 ++++ clang/lib/Sema/SemaStmtAsm.cpp | 7 +- clang/test/CodeGen/complex-builtins-2.c | 20 + clang/test/CodeGen/fp-contract-pragma.cpp | 15 + clang/test/CodeGen/ms-inline-asm-64.c | 4 +- clang/test/CodeGen/ms-inline-asm.c | 12 +- clang/test/CodeGen/ms-inline-asm.cpp | 2 +- clang/test/OpenMP/cancel_codegen.cpp | 119 +-- clang/test/OpenMP/parallel_codegen.cpp | 117 +-- clang/test/Parser/ms-inline-asm.c | 5 + llvm/docs/CompilerWriterInfo.rst | 12 +- llvm/docs/ReleaseNotes.rst | 5 + .../llvm/CodeGen/GlobalISel/LegalizerHelper.h | 2 + llvm/include/llvm/CodeGen/TargetLowering.h | 7 +- llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h | 18 + llvm/include/llvm/Frontend/OpenMP/OMPKinds.def | 29 +- llvm/include/llvm/IR/AutoUpgrade.h | 5 + llvm/include/llvm/IR/CallSite.h | 31 +- llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h | 8 +- llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h | 47 +- llvm/include/llvm/Transforms/IPO/Attributor.h | 112 ++- llvm/lib/AsmParser/LLParser.cpp | 4 +- llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 1 + llvm/lib/Bitcode/Reader/MetadataLoader.cpp | 2 +- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 1 - llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 111 ++- llvm/lib/CodeGen/MachineCopyPropagation.cpp | 6 +- .../lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 10 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 12 +- llvm/lib/CodeGen/TargetOptionsImpl.cpp | 14 +- llvm/lib/Frontend/OpenMP/OMPConstants.cpp | 2 +- llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 138 +++- llvm/lib/IR/AbstractCallSite.cpp | 19 + llvm/lib/IR/AutoUpgrade.cpp | 20 + llvm/lib/MC/MCParser/AsmParser.cpp | 52 +- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 24 +- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 2 +- llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td | 18 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 16 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 1 + llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 36 +- llvm/lib/Target/AMDGPU/R600ISelLowering.cpp | 4 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 7 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 7 +- llvm/lib/Target/AMDGPU/VOP2Instructions.td | 4 +- llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 2 + llvm/lib/Target/ARM/ARMISelLowering.cpp | 1 + llvm/lib/Target/ARM/MVETailPredication.cpp | 4 +- llvm/lib/Target/ARM/Thumb2InstrInfo.cpp | 75 +- llvm/lib/Target/Mips/MipsLegalizerInfo.cpp | 17 + llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp | 1 + llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 15 + llvm/lib/Target/PowerPC/PPCInstrVSX.td | 37 + llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 216 +++-- llvm/lib/Target/X86/AsmParser/X86Operand.h | 20 +- .../Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 907 +++++++++++---------- llvm/lib/Target/X86/X86AsmPrinter.cpp | 8 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 17 +- llvm/lib/Transforms/IPO/Attributor.cpp | 374 ++++++++- .../Transforms/InstCombine/InstCombineCalls.cpp | 10 + llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 227 +++--- llvm/lib/Transforms/Vectorize/VPlan.cpp | 10 +- llvm/lib/Transforms/Vectorize/VPlan.h | 4 +- llvm/test/Assembler/dicompileunit.ll | 4 +- llvm/test/Bitcode/upgrade-frame-pointer.ll | 33 + .../GlobalISel/inst-select-amdgcn.fmad.ftz.mir | 233 ++++++ .../GlobalISel/inst-select-amdgcn.mul.u24.mir | 65 ++ .../AMDGPU/GlobalISel/inst-select-fexp2.mir | 42 + .../AMDGPU/GlobalISel/legalize-bitreverse.mir | 21 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir | 42 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir | 42 +- .../AMDGPU/GlobalISel/regbankselect-phi-s1.mir | 96 ++- .../AMDGPU/GlobalISel/regbankselect-phi.mir | 14 +- llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll | 762 ++++++++++++++++- llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir | 88 ++ .../Mips/GlobalISel/instruction-select/bswap.mir | 30 + .../Mips/GlobalISel/legalizer/bitreverse.mir | 215 +++++ .../CodeGen/Mips/GlobalISel/legalizer/bswap.mir | 101 +++ .../CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll | 184 +++++ llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bswap.ll | 68 ++ .../Mips/GlobalISel/regbankselect/bswap.mir | 28 + llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll | 10 + llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll | 2 +- llvm/test/CodeGen/PowerPC/rounding-ops.ll | 8 +- llvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll | 561 +++++++++++++ .../PowerPC/vector-constrained-fp-intrinsics.ll | 372 +++------ .../cond-vector-reduce-mve-codegen.ll | 17 +- .../Thumb2/LowOverheadLoops/fast-fp-loops.ll | 280 +++---- llvm/test/CodeGen/Thumb2/emit-unwinding.ll | 15 + llvm/test/CodeGen/Thumb2/large-call.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll | 615 ++++++++++++++ llvm/test/CodeGen/Thumb2/mve-stacksplot.mir | 3 +- llvm/test/CodeGen/X86/ms-inline-asm.ll | 2 +- llvm/test/CodeGen/X86/offset-operator.ll | 15 + llvm/test/CodeGen/X86/pr44412.ll | 36 + llvm/test/CodeGen/X86/sadd_sat.ll | 4 +- llvm/test/CodeGen/X86/sadd_sat_vec.ll | 140 ++-- llvm/test/CodeGen/X86/ssub_sat.ll | 10 +- llvm/test/CodeGen/X86/ssub_sat_vec.ll | 220 ++--- llvm/test/DebugInfo/X86/range_reloc.ll | 2 +- llvm/test/MC/X86/pr32530.s | 13 + llvm/test/TableGen/predicate-patfags.td | 63 ++ .../ArgumentPromotion/2008-02-01-ReturnAttrs.ll | 2 +- .../ArgumentPromotion/2008-07-02-array-indexing.ll | 2 +- .../Attributor/ArgumentPromotion/X86/attributes.ll | 4 +- .../X86/min-legal-vector-width.ll | 16 +- .../Attributor/ArgumentPromotion/attrs.ll | 2 +- .../Attributor/ArgumentPromotion/basictest.ll | 4 +- .../Attributor/ArgumentPromotion/byval-2.ll | 2 +- .../Attributor/ArgumentPromotion/byval.ll | 4 +- .../Attributor/ArgumentPromotion/chained.ll | 2 +- .../Attributor/ArgumentPromotion/control-flow.ll | 20 +- .../Attributor/ArgumentPromotion/control-flow2.ll | 4 +- .../Transforms/Attributor/ArgumentPromotion/dbg.ll | 7 +- .../Attributor/ArgumentPromotion/fp80.ll | 2 +- .../Attributor/ArgumentPromotion/inalloca.ll | 2 +- .../ArgumentPromotion/nonzero-address-spaces.ll | 5 +- .../Attributor/ArgumentPromotion/pr27568.ll | 5 +- .../Attributor/ArgumentPromotion/pr32917.ll | 2 +- .../Attributor/ArgumentPromotion/profile.ll | 2 +- .../Attributor/ArgumentPromotion/reserve-tbaa.ll | 4 +- .../Attributor/ArgumentPromotion/sret.ll | 2 +- .../Attributor/ArgumentPromotion/variadic.ll | 2 +- .../IPConstantProp/2009-09-24-byval-ptr.ll | 14 +- .../Attributor/IPConstantProp/PR26044.ll | 4 +- .../IPConstantProp/openmp_parallel_for.ll | 4 +- .../Attributor/IPConstantProp/pthreads.ll | 12 +- .../Attributor/IPConstantProp/thread_local_acs.ll | 2 +- llvm/test/Transforms/Attributor/align.ll | 38 +- llvm/test/Transforms/Attributor/callbacks.ll | 7 +- llvm/test/Transforms/Attributor/liveness.ll | 14 +- llvm/test/Transforms/Attributor/misc.ll | 18 +- llvm/test/Transforms/Attributor/noalias.ll | 22 +- llvm/test/Transforms/Attributor/nocapture-2.ll | 10 +- llvm/test/Transforms/Attributor/nonnull.ll | 14 +- llvm/test/Transforms/Attributor/value-simplify.ll | 8 +- llvm/test/Transforms/InstCombine/copysign.ll | 5 +- .../Inputs/argument_name_reuse.ll | 7 + .../Inputs/argument_name_reuse.ll.expected | 14 + .../Inputs/argument_name_reuse.ll.plain.expected | 13 + .../Inputs/basic.ll.funcsig.expected | 2 +- .../update_test_checks/Inputs/scrub_attrs.ll | 8 + .../Inputs/scrub_attrs.ll.plain.expected | 13 + .../Inputs/scrub_attrs.ll.scrub.expected | 13 + .../Inputs/sometimes_deleted_function.ll | 12 + .../Inputs/sometimes_deleted_function.ll.expected | 19 + .../update_test_checks/argument_name_reuse.test | 6 + .../update_test_checks/scrub_attrs.test | 9 + .../sometimes_deleted_function.test | 5 + llvm/test/tools/llvm-profdata/show-prof-size.test | 2 +- .../tools/yaml2obj/ELF/custom-null-section.yaml | 4 +- llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp | 120 +++ llvm/utils/TableGen/CodeGenDAGPatterns.cpp | 26 +- llvm/utils/UpdateTestChecks/common.py | 41 +- llvm/utils/update_test_checks.py | 9 + mlir/include/mlir/IR/Block.h | 2 +- mlir/include/mlir/IR/Operation.h | 32 +- mlir/include/mlir/IR/UseDefLists.h | 354 +++++--- mlir/include/mlir/IR/Value.h | 78 +- mlir/lib/IR/Operation.cpp | 58 +- mlir/lib/IR/Value.cpp | 95 ++- mlir/lib/Transforms/ViewOpGraph.cpp | 10 +- .../deviceRTLs/amdgcn/src/target_impl.h | 4 +- .../libomptarget/deviceRTLs/common/src/libcall.cu | 4 +- .../deviceRTLs/nvptx/src/target_impl.h | 6 +- 168 files changed, 6922 insertions(+), 2096 deletions(-) create mode 100644 clang/test/CodeGen/complex-builtins-2.c create mode 100644 llvm/test/Bitcode/upgrade-frame-pointer.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmad.ftz.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mul.u24.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir create mode 100644 llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bswap.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitreverse.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/bswap.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bswap.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bswap.mir create mode 100644 llvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll create mode 100644 llvm/test/CodeGen/X86/offset-operator.ll create mode 100644 llvm/test/CodeGen/X86/pr44412.ll create mode 100644 llvm/test/MC/X86/pr32530.s create mode 100644 llvm/test/TableGen/predicate-patfags.td create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/argu [...] create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/argu [...] create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/argu [...] create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/scru [...] create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/scru [...] create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/scru [...] create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/some [...] create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/some [...] create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_checks/argument_na [...] create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_checks/scrub_attrs.test create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_checks/sometimes_d [...] -- To stop receiving notification emails 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4 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig updated (b6620dfc2 -> 51080faa6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig in repository toolchain/ci/base-artifacts. discards b6620dfc2 0: update: llvm-linux: boot new 51080faa6 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (b6620dfc2) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 166 +- 02-build_llvm/console.log | 12530 +++++++++++++++++----------------- 03-build_linux/console.log | 690 +- 04-boot_linux/console.log | 442 +- 05-check_regression/console.log | 2 +- 06-update_baseline/console.log | 29 - console.log | 13859 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 8 files changed, 13832 insertions(+), 13894 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-allyesconfig updated (9577eace3e8 -> 26b996a95cc)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-allyesconfig in repository toolchain/ci/gcc. from 9577eace3e8 Daily bump. adds 8a969c076ad Catch division by zero errors in array sizes. adds 8541e44c90a 2019-12-30 Thomas Koenig <tkoenig(a)gcc.gnu.org> adds e509dbe5090 * fi.po: Update. adds 26b996a95cc Daily bump. No new revisions were added by this update. Summary of changes: gcc/DATESTAMP | 2 +- gcc/fortran/ChangeLog | 11 + gcc/fortran/arith.c | 6 + gcc/fortran/decl.c | 31 +- gcc/fortran/gfortran.h | 2 + gcc/po/ChangeLog | 4 + gcc/po/fi.po | 654 ++++++++++++++------------- gcc/testsuite/ChangeLog | 6 + gcc/testsuite/gfortran.dg/arith_divide_2.f90 | 9 + 9 files changed, 395 insertions(+), 330 deletions(-) create mode 100644 gcc/testsuite/gfortran.dg/arith_divide_2.f90 -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-allyesconfig updated (afce2016c -> 4bec0a76d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-allyesconfig in repository toolchain/ci/base-artifacts. discards afce2016c 0: update: binutils-gcc-linux: all new 4bec0a76d 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (afce2016c) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 173 +- 02-prepare_abe/console.log | 390 +- 03-build_abe-binutils/console.log | 10701 ++++++++------- 04-build_abe-stage1/console.log | 14047 +++++++++---------- 05-build_linux/console.log | 738 +- 06-boot_linux/console.log | 6 +- 07-check_regression/console.log | 10 +- 08-update_baseline/console.log | 10 +- console.log | 26079 ++++++++++++++++++------------------ jenkins/manifest.sh | 8 +- 10 files changed, 26098 insertions(+), 26064 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[gcc] branch master updated (47c4fc06d50 -> f9e233c9d08)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 47c4fc06d50 Daily bump. new f9e233c9d08 Fix SSA update when vectorisation adds a vdef to a read-only loop The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 9 ++++ gcc/testsuite/ChangeLog | 4 ++ gcc/testsuite/gcc.dg/vect/vect-epilogues-2.c | 57 ++++++++++++++++++++++++ gcc/tree-vect-loop-manip.c | 66 ++++++++++++++++++++++++++-- 4 files changed, 132 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/vect/vect-epilogues-2.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-allnoconfig updated (9577eace3e8 -> 26b996a95cc)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-allnoconfig in repository toolchain/ci/gcc. from 9577eace3e8 Daily bump. adds 8a969c076ad Catch division by zero errors in array sizes. adds 8541e44c90a 2019-12-30 Thomas Koenig <tkoenig(a)gcc.gnu.org> adds e509dbe5090 * fi.po: Update. adds 26b996a95cc Daily bump. No new revisions were added by this update. Summary of changes: gcc/DATESTAMP | 2 +- gcc/fortran/ChangeLog | 11 + gcc/fortran/arith.c | 6 + gcc/fortran/decl.c | 31 +- gcc/fortran/gfortran.h | 2 + gcc/po/ChangeLog | 4 + gcc/po/fi.po | 654 ++++++++++++++------------- gcc/testsuite/ChangeLog | 6 + gcc/testsuite/gfortran.dg/arith_divide_2.f90 | 9 + 9 files changed, 395 insertions(+), 330 deletions(-) create mode 100644 gcc/testsuite/gfortran.dg/arith_divide_2.f90 -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-allnoconfig updated (c06c4e4fe -> 6e1f526dc)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-allnoconfig in repository toolchain/ci/base-artifacts. discards c06c4e4fe 0: update: binutils-gcc-linux: boot new 6e1f526dc 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (c06c4e4fe) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 216 +- 02-prepare_abe/console.log | 438 +- 03-build_abe-binutils/console.log | 11026 +++++++-------- 04-build_abe-stage1/console.log | 14124 ++++++++++--------- 05-build_linux/console.log | 822 +- 06-boot_linux/console.log | 4 +- 07-check_regression/console.log | 10 +- 08-update_baseline/console.log | 29 - console.log | 26669 ++++++++++++++++++------------------ jenkins/manifest.sh | 8 +- 10 files changed, 26638 insertions(+), 26708 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allyesconfig updated (bb87364f26c -> 70771d8b9e8)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allyesconfig in repository toolchain/ci/llvm-project. from bb87364f26c [ELF][PPC64] Improve "call lacks nop" diagnostic and make i [...] adds 34fe8d04511 [Attributor] Use `changeUseAfterManifest` in AAValueSimplif [...] adds 65661908cb6 [NFC] Add test for load-insert-store pattern adds b47b35ff51b [Diagnostic] Add ftabstop to -Wmisleading-indentation adds 36ae255663c [opt] Fix run-twice crash and detection problem adds cd2a73a9f01 [MCP] Add stats for backward copy propagation. NFC. adds 94a24e7a401 [MIPS GlobalISel] Select bswap adds dbc136e0fe7 [MIPS GlobalISel] Select bitreverse adds 4a188fdfa79 [OpenCL] Add mipmap builtin functions adds 8232497c313 [ARM][THUMB2] Allow emitting T3 types of add and sub adds 1b6286b945a [LV][NFC] Some refactoring and renaming to facilitate next change. adds 948e745270d [LV][NFC] Keep dominator tree up to date during vectorization. adds a5a141544d0 [ARM] MVE sink ICmp test. NFC adds b4abe7afbf5 [ARM] Sink splat to ICmp adds 32cc14100e8 Revert "[MIPS GlobalISel] Select bitreverse" adds 0f0330a7870 [PowerPC] Legalize rounding nodes adds 491cfa4250d AMDGPU/GlobalISel: Account for G_PHI result bank adds 58bcf511070 AMDGPU: Generate check lines adds 9e1a2a668b9 AMDGPU: Improve llvm.round.f64 lowering for CI+ adds 9fd31fdbd30 GlobalISel: moreElementsVector for FP min/max adds 18240c3cd63 AMDGPU/GlobalISel: Add select test for fexp2 adds f33fd9648c4 [ARM][Thumb][FIX] Add unwinding information to t4 adds 987eb8e26cc [InstCombine] propagate sign argument through nested copysigns adds 1247865fe02 AMDGPU/GlobalISel: Select llvm.amdgcn.fmad.ftz adds 98f72a5107c [MIPS GlobalISel] Select bitreverse. Recommit adds ee3eebba0d3 [InstCombine] remove stale comment on test; NFC adds 03b9f0a5e19 Ignore "no-frame-pointer-elim" and "no-frame-pointer-elim-n [...] adds 48e0e68edb3 AMDGPU/GlobalISel: Re-use MRI available in selector adds 0c5bee8fdd4 [test] do not parse ls output for file size; NFCI adds 47a2fd2df4f [X86] Add X86ISD::PCMPGT to SimplifyMultipleUseDemandedBits [...] adds 94d08feaeff TableGen: Fix assert on PatFrags with predicate code adds 7fa0bfe7d58 AMDGPU/GlobalISel: Select mul24 intrinsics adds 4a7aa252a32 [X86][AsmParser] re-introduce 'offset' operator adds 000c6a5038b [OpenMP] Use the OpenMPIRBuilder for `omp cancel` adds 10fedd94b43 [OpenMP] Use the OpenMPIRBuilder for `omp parallel` adds 0bd3cc42485 [PowerPC][docs] Update Embedded PowerPC docs in Compiler Wr [...] adds bc48af8c575 [libomptarget][nfc] Change unintentional target_impl prefix [...] adds 6bd1fcd7959 [OpenMP][FIX] Generalize a test check line adds 07be32961a6 Remove a redundant `default:` on an exhaustive switch(enum). adds 8b23b2bbd96 [CodeGen] Use CreateFNeg in buildFMulAdd adds 70f8dd4cf60 [CodeGen] Use IRBuilder::CreateFNeg for __builtin_conj adds 6185dc0eb3a [X86] Add test case for PR44412. NFC adds 991f7abdfc5 [NFC] Add comments in unit test aix-xcoff-toc.ll to clarify [...] adds 831898ff8ac [SelectionDAG] Fix copy/paste mistake in comment. NFC adds 787e078f3ec [TargetLowering][AMDGPU] Make scalarizeVectorLoad return a [...] adds 0d6ebb4f0dd [mlir] Refactor operation results to use a single use list [...] adds 5b1cbfa4232 [NFC] Style cleanup adds b350c666ab6 Revert "DebugInfo: Fix rangesBaseAddress DICompileUnit bitc [...] adds 23a6ae2b062 [NFC] Make X86MCCodeEmitter::isPCRel32Branch static new 28880198718 [Attributor] Annotate the memory behavior of call site arguments new b1b441d22de [Attributor] Use abstract call sites to determine associate [...] new dada8132af6 [Attributor] Propagate known align from arguments to call s [...] new 70771d8b9e8 [Utils] Allow update_test_checks to scrub attribute annotations The 4 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: clang/lib/CodeGen/CGBuiltin.cpp | 7 +- clang/lib/CodeGen/CGExprScalar.cpp | 15 +- clang/lib/CodeGen/CGStmtOpenMP.cpp | 95 +++ clang/lib/Parse/ParseStmt.cpp | 41 +- clang/lib/Sema/OpenCLBuiltins.td | 177 +++++ clang/lib/Sema/SemaStmtAsm.cpp | 7 +- clang/test/CodeGen/complex-builtins-2.c | 20 + clang/test/CodeGen/fp-contract-pragma.cpp | 15 + clang/test/CodeGen/ms-inline-asm-64.c | 4 +- clang/test/CodeGen/ms-inline-asm.c | 12 +- clang/test/CodeGen/ms-inline-asm.cpp | 2 +- clang/test/OpenMP/cancel_codegen.cpp | 119 +-- clang/test/OpenMP/parallel_codegen.cpp | 117 +-- clang/test/Parser/ms-inline-asm.c | 5 + clang/test/Parser/warn-misleading-indentation.cpp | 83 +- llvm/docs/CompilerWriterInfo.rst | 12 +- llvm/docs/ReleaseNotes.rst | 5 + .../llvm/CodeGen/GlobalISel/LegalizerHelper.h | 2 + llvm/include/llvm/CodeGen/TargetLowering.h | 7 +- llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h | 18 + llvm/include/llvm/Frontend/OpenMP/OMPKinds.def | 29 +- llvm/include/llvm/IR/AutoUpgrade.h | 5 + llvm/include/llvm/IR/CallSite.h | 31 +- llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h | 8 +- llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h | 47 +- llvm/include/llvm/Transforms/IPO/Attributor.h | 22 +- llvm/lib/AsmParser/LLParser.cpp | 4 +- llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 1 + llvm/lib/Bitcode/Reader/MetadataLoader.cpp | 2 +- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 1 - llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 111 ++- llvm/lib/CodeGen/MachineCopyPropagation.cpp | 6 +- .../lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 10 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 12 +- llvm/lib/CodeGen/TargetOptionsImpl.cpp | 14 +- llvm/lib/Frontend/OpenMP/OMPConstants.cpp | 2 +- llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 138 +++- llvm/lib/IR/AbstractCallSite.cpp | 19 + llvm/lib/IR/AutoUpgrade.cpp | 20 + llvm/lib/MC/MCParser/AsmParser.cpp | 52 +- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 24 +- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 2 +- llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td | 18 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 16 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 1 + llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 36 +- llvm/lib/Target/AMDGPU/R600ISelLowering.cpp | 4 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 7 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 7 +- llvm/lib/Target/AMDGPU/VOP2Instructions.td | 4 +- llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 2 + llvm/lib/Target/ARM/ARMISelLowering.cpp | 1 + llvm/lib/Target/ARM/MVETailPredication.cpp | 4 +- llvm/lib/Target/ARM/Thumb2InstrInfo.cpp | 75 +- llvm/lib/Target/Mips/MipsLegalizerInfo.cpp | 17 + llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp | 1 + llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 15 + llvm/lib/Target/PowerPC/PPCInstrVSX.td | 37 + llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 216 +++-- llvm/lib/Target/X86/AsmParser/X86Operand.h | 20 +- .../Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 872 ++++++++++++--------- llvm/lib/Target/X86/X86AsmPrinter.cpp | 8 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 7 + llvm/lib/Transforms/IPO/Attributor.cpp | 121 ++- .../Transforms/InstCombine/InstCombineCalls.cpp | 10 + llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 227 +++--- llvm/lib/Transforms/Vectorize/VPlan.cpp | 10 +- llvm/lib/Transforms/Vectorize/VPlan.h | 4 +- llvm/test/Assembler/dicompileunit.ll | 4 +- llvm/test/Bitcode/upgrade-frame-pointer.ll | 33 + .../GlobalISel/inst-select-amdgcn.fmad.ftz.mir | 233 ++++++ .../GlobalISel/inst-select-amdgcn.mul.u24.mir | 65 ++ .../AMDGPU/GlobalISel/inst-select-fexp2.mir | 42 + .../AMDGPU/GlobalISel/legalize-bitreverse.mir | 21 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir | 42 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir | 42 +- .../AMDGPU/GlobalISel/regbankselect-phi-s1.mir | 96 ++- .../AMDGPU/GlobalISel/regbankselect-phi.mir | 14 +- llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll | 762 +++++++++++++++++- llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir | 88 +++ .../Mips/GlobalISel/instruction-select/bswap.mir | 30 + .../Mips/GlobalISel/legalizer/bitreverse.mir | 215 +++++ .../CodeGen/Mips/GlobalISel/legalizer/bswap.mir | 101 +++ .../CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll | 184 +++++ llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bswap.ll | 68 ++ .../Mips/GlobalISel/regbankselect/bswap.mir | 28 + llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll | 10 + llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll | 2 +- llvm/test/CodeGen/PowerPC/rounding-ops.ll | 8 +- llvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll | 561 +++++++++++++ .../PowerPC/vector-constrained-fp-intrinsics.ll | 372 +++------ .../cond-vector-reduce-mve-codegen.ll | 17 +- .../Thumb2/LowOverheadLoops/fast-fp-loops.ll | 280 +++---- llvm/test/CodeGen/Thumb2/emit-unwinding.ll | 15 + llvm/test/CodeGen/Thumb2/large-call.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll | 615 +++++++++++++++ llvm/test/CodeGen/Thumb2/mve-stacksplot.mir | 3 +- llvm/test/CodeGen/X86/ms-inline-asm.ll | 2 +- llvm/test/CodeGen/X86/offset-operator.ll | 15 + llvm/test/CodeGen/X86/pr44412.ll | 36 + llvm/test/CodeGen/X86/sadd_sat.ll | 4 +- llvm/test/CodeGen/X86/sadd_sat_vec.ll | 140 ++-- llvm/test/CodeGen/X86/ssub_sat.ll | 10 +- llvm/test/CodeGen/X86/ssub_sat_vec.ll | 220 +++--- llvm/test/DebugInfo/X86/range_reloc.ll | 2 +- llvm/test/MC/X86/pr32530.s | 13 + llvm/test/TableGen/predicate-patfags.td | 63 ++ .../ArgumentPromotion/2008-02-01-ReturnAttrs.ll | 2 +- .../ArgumentPromotion/2008-07-02-array-indexing.ll | 4 +- .../Attributor/ArgumentPromotion/X86/attributes.ll | 4 +- .../X86/min-legal-vector-width.ll | 16 +- .../Attributor/ArgumentPromotion/attrs.ll | 2 +- .../Attributor/ArgumentPromotion/basictest.ll | 4 +- .../Attributor/ArgumentPromotion/byval-2.ll | 2 +- .../Attributor/ArgumentPromotion/byval.ll | 4 +- .../Attributor/ArgumentPromotion/chained.ll | 2 +- .../Attributor/ArgumentPromotion/control-flow.ll | 4 +- .../Attributor/ArgumentPromotion/control-flow2.ll | 4 +- .../Transforms/Attributor/ArgumentPromotion/dbg.ll | 2 +- .../Attributor/ArgumentPromotion/fp80.ll | 2 +- .../Attributor/ArgumentPromotion/inalloca.ll | 2 +- .../ArgumentPromotion/nonzero-address-spaces.ll | 2 +- .../Attributor/ArgumentPromotion/pr27568.ll | 2 +- .../Attributor/ArgumentPromotion/pr32917.ll | 2 +- .../Attributor/ArgumentPromotion/profile.ll | 2 +- .../Attributor/ArgumentPromotion/reserve-tbaa.ll | 4 +- .../Attributor/ArgumentPromotion/sret.ll | 2 +- .../Attributor/ArgumentPromotion/variadic.ll | 2 +- .../IPConstantProp/2009-09-24-byval-ptr.ll | 14 +- .../Attributor/IPConstantProp/PR26044.ll | 4 +- .../IPConstantProp/openmp_parallel_for.ll | 4 +- .../Attributor/IPConstantProp/pthreads.ll | 12 +- .../Attributor/IPConstantProp/thread_local_acs.ll | 2 +- llvm/test/Transforms/Attributor/align.ll | 38 +- llvm/test/Transforms/Attributor/callbacks.ll | 7 +- llvm/test/Transforms/Attributor/liveness.ll | 4 +- llvm/test/Transforms/Attributor/misc.ll | 18 +- llvm/test/Transforms/Attributor/nocapture-2.ll | 10 +- llvm/test/Transforms/Attributor/nonnull.ll | 10 +- llvm/test/Transforms/Attributor/value-simplify.ll | 10 +- llvm/test/Transforms/InstCombine/copysign.ll | 5 +- .../Transforms/InstCombine/load-insert-store.ll | 98 +++ .../update_test_checks/Inputs/scrub_attrs.ll | 8 + .../Inputs/scrub_attrs.ll.plain.expected | 13 + .../Inputs/scrub_attrs.ll.scrub.expected | 13 + .../update_test_checks/scrub_attrs.test | 9 + llvm/test/tools/llvm-profdata/show-prof-size.test | 2 +- .../tools/yaml2obj/ELF/custom-null-section.yaml | 4 +- llvm/tools/opt/opt.cpp | 13 +- llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp | 120 +++ llvm/utils/TableGen/CodeGenDAGPatterns.cpp | 26 +- llvm/utils/UpdateTestChecks/common.py | 4 +- llvm/utils/update_test_checks.py | 9 + mlir/include/mlir/IR/Block.h | 2 +- mlir/include/mlir/IR/Operation.h | 32 +- mlir/include/mlir/IR/UseDefLists.h | 354 ++++++--- mlir/include/mlir/IR/Value.h | 78 +- mlir/lib/IR/Operation.cpp | 58 +- mlir/lib/IR/Value.cpp | 95 ++- mlir/lib/Transforms/ViewOpGraph.cpp | 10 +- .../deviceRTLs/amdgcn/src/target_impl.h | 4 +- .../libomptarget/deviceRTLs/common/src/libcall.cu | 4 +- .../deviceRTLs/nvptx/src/target_impl.h | 6 +- 163 files changed, 6630 insertions(+), 2061 deletions(-) create mode 100644 clang/test/CodeGen/complex-builtins-2.c create mode 100644 llvm/test/Bitcode/upgrade-frame-pointer.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmad.ftz.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mul.u24.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir create mode 100644 llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bswap.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitreverse.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/bswap.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bswap.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bswap.mir create mode 100644 llvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll create mode 100644 llvm/test/CodeGen/X86/offset-operator.ll create mode 100644 llvm/test/CodeGen/X86/pr44412.ll create mode 100644 llvm/test/MC/X86/pr32530.s create mode 100644 llvm/test/TableGen/predicate-patfags.td create mode 100644 llvm/test/Transforms/InstCombine/load-insert-store.ll create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/scru [...] create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/scru [...] create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/scru [...] create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_checks/scrub_attrs.test -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allyesconfig updated (b0b9710a5 -> 3cea3246c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allyesconfig in repository toolchain/ci/base-artifacts. discards b0b9710a5 0: update: llvm-linux: all new 3cea3246c 0: update: llvm-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (b0b9710a5) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 182 +- 02-build_llvm/console.log | 12574 ++++++++++++++-------------- 03-build_linux/console.log | 4018 +++++---- 04-boot_linux/console.log | 6 +- 05-check_regression/console.log | 10 +- 06-update_baseline/console.log | 29 - console.log | 16819 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 8 files changed, 16596 insertions(+), 17050 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allmodconfig updated (bb87364f26c -> 23a6ae2b062)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allmodconfig in repository toolchain/ci/llvm-project. from bb87364f26c [ELF][PPC64] Improve "call lacks nop" diagnostic and make i [...] adds 34fe8d04511 [Attributor] Use `changeUseAfterManifest` in AAValueSimplif [...] adds 65661908cb6 [NFC] Add test for load-insert-store pattern adds b47b35ff51b [Diagnostic] Add ftabstop to -Wmisleading-indentation adds 36ae255663c [opt] Fix run-twice crash and detection problem adds cd2a73a9f01 [MCP] Add stats for backward copy propagation. NFC. adds 94a24e7a401 [MIPS GlobalISel] Select bswap adds dbc136e0fe7 [MIPS GlobalISel] Select bitreverse adds 4a188fdfa79 [OpenCL] Add mipmap builtin functions adds 8232497c313 [ARM][THUMB2] Allow emitting T3 types of add and sub adds 1b6286b945a [LV][NFC] Some refactoring and renaming to facilitate next change. adds 948e745270d [LV][NFC] Keep dominator tree up to date during vectorization. adds a5a141544d0 [ARM] MVE sink ICmp test. NFC adds b4abe7afbf5 [ARM] Sink splat to ICmp adds 32cc14100e8 Revert "[MIPS GlobalISel] Select bitreverse" adds 0f0330a7870 [PowerPC] Legalize rounding nodes adds 491cfa4250d AMDGPU/GlobalISel: Account for G_PHI result bank adds 58bcf511070 AMDGPU: Generate check lines adds 9e1a2a668b9 AMDGPU: Improve llvm.round.f64 lowering for CI+ adds 9fd31fdbd30 GlobalISel: moreElementsVector for FP min/max adds 18240c3cd63 AMDGPU/GlobalISel: Add select test for fexp2 adds f33fd9648c4 [ARM][Thumb][FIX] Add unwinding information to t4 adds 987eb8e26cc [InstCombine] propagate sign argument through nested copysigns adds 1247865fe02 AMDGPU/GlobalISel: Select llvm.amdgcn.fmad.ftz adds 98f72a5107c [MIPS GlobalISel] Select bitreverse. Recommit adds ee3eebba0d3 [InstCombine] remove stale comment on test; NFC adds 03b9f0a5e19 Ignore "no-frame-pointer-elim" and "no-frame-pointer-elim-n [...] adds 48e0e68edb3 AMDGPU/GlobalISel: Re-use MRI available in selector adds 0c5bee8fdd4 [test] do not parse ls output for file size; NFCI adds 47a2fd2df4f [X86] Add X86ISD::PCMPGT to SimplifyMultipleUseDemandedBits [...] adds 94d08feaeff TableGen: Fix assert on PatFrags with predicate code adds 7fa0bfe7d58 AMDGPU/GlobalISel: Select mul24 intrinsics adds 4a7aa252a32 [X86][AsmParser] re-introduce 'offset' operator adds 000c6a5038b [OpenMP] Use the OpenMPIRBuilder for `omp cancel` adds 10fedd94b43 [OpenMP] Use the OpenMPIRBuilder for `omp parallel` adds 0bd3cc42485 [PowerPC][docs] Update Embedded PowerPC docs in Compiler Wr [...] adds bc48af8c575 [libomptarget][nfc] Change unintentional target_impl prefix [...] adds 6bd1fcd7959 [OpenMP][FIX] Generalize a test check line adds 07be32961a6 Remove a redundant `default:` on an exhaustive switch(enum). adds 8b23b2bbd96 [CodeGen] Use CreateFNeg in buildFMulAdd adds 70f8dd4cf60 [CodeGen] Use IRBuilder::CreateFNeg for __builtin_conj adds 6185dc0eb3a [X86] Add test case for PR44412. NFC adds 991f7abdfc5 [NFC] Add comments in unit test aix-xcoff-toc.ll to clarify [...] adds 831898ff8ac [SelectionDAG] Fix copy/paste mistake in comment. NFC adds 787e078f3ec [TargetLowering][AMDGPU] Make scalarizeVectorLoad return a [...] adds 0d6ebb4f0dd [mlir] Refactor operation results to use a single use list [...] adds 5b1cbfa4232 [NFC] Style cleanup adds b350c666ab6 Revert "DebugInfo: Fix rangesBaseAddress DICompileUnit bitc [...] new 23a6ae2b062 [NFC] Make X86MCCodeEmitter::isPCRel32Branch static The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: clang/lib/CodeGen/CGBuiltin.cpp | 7 +- clang/lib/CodeGen/CGExprScalar.cpp | 15 +- clang/lib/CodeGen/CGStmtOpenMP.cpp | 95 +++ clang/lib/Parse/ParseStmt.cpp | 41 +- clang/lib/Sema/OpenCLBuiltins.td | 177 +++++ clang/lib/Sema/SemaStmtAsm.cpp | 7 +- clang/test/CodeGen/complex-builtins-2.c | 20 + clang/test/CodeGen/fp-contract-pragma.cpp | 15 + clang/test/CodeGen/ms-inline-asm-64.c | 4 +- clang/test/CodeGen/ms-inline-asm.c | 12 +- clang/test/CodeGen/ms-inline-asm.cpp | 2 +- clang/test/OpenMP/cancel_codegen.cpp | 119 +-- clang/test/OpenMP/parallel_codegen.cpp | 117 +-- clang/test/Parser/ms-inline-asm.c | 5 + clang/test/Parser/warn-misleading-indentation.cpp | 83 +- llvm/docs/CompilerWriterInfo.rst | 12 +- llvm/docs/ReleaseNotes.rst | 5 + .../llvm/CodeGen/GlobalISel/LegalizerHelper.h | 2 + llvm/include/llvm/CodeGen/TargetLowering.h | 7 +- llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h | 18 + llvm/include/llvm/Frontend/OpenMP/OMPKinds.def | 29 +- llvm/include/llvm/IR/AutoUpgrade.h | 5 + llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h | 8 +- llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h | 47 +- llvm/include/llvm/Transforms/IPO/Attributor.h | 10 + llvm/lib/AsmParser/LLParser.cpp | 4 +- llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 1 + llvm/lib/Bitcode/Reader/MetadataLoader.cpp | 2 +- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 1 - llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 111 ++- llvm/lib/CodeGen/MachineCopyPropagation.cpp | 6 +- .../lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 10 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 12 +- llvm/lib/CodeGen/TargetOptionsImpl.cpp | 14 +- llvm/lib/Frontend/OpenMP/OMPConstants.cpp | 2 +- llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 138 +++- llvm/lib/IR/AutoUpgrade.cpp | 20 + llvm/lib/MC/MCParser/AsmParser.cpp | 52 +- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 24 +- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 2 +- llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td | 18 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 16 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 1 + llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 36 +- llvm/lib/Target/AMDGPU/R600ISelLowering.cpp | 4 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 7 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 7 +- llvm/lib/Target/AMDGPU/VOP2Instructions.td | 4 +- llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 2 + llvm/lib/Target/ARM/ARMISelLowering.cpp | 1 + llvm/lib/Target/ARM/MVETailPredication.cpp | 4 +- llvm/lib/Target/ARM/Thumb2InstrInfo.cpp | 75 +- llvm/lib/Target/Mips/MipsLegalizerInfo.cpp | 17 + llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp | 1 + llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 15 + llvm/lib/Target/PowerPC/PPCInstrVSX.td | 37 + llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 216 +++-- llvm/lib/Target/X86/AsmParser/X86Operand.h | 20 +- .../Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 872 ++++++++++++--------- llvm/lib/Target/X86/X86AsmPrinter.cpp | 8 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 7 + llvm/lib/Transforms/IPO/Attributor.cpp | 6 +- .../Transforms/InstCombine/InstCombineCalls.cpp | 10 + llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 227 +++--- llvm/lib/Transforms/Vectorize/VPlan.cpp | 10 +- llvm/lib/Transforms/Vectorize/VPlan.h | 4 +- llvm/test/Assembler/dicompileunit.ll | 4 +- llvm/test/Bitcode/upgrade-frame-pointer.ll | 33 + .../GlobalISel/inst-select-amdgcn.fmad.ftz.mir | 233 ++++++ .../GlobalISel/inst-select-amdgcn.mul.u24.mir | 65 ++ .../AMDGPU/GlobalISel/inst-select-fexp2.mir | 42 + .../AMDGPU/GlobalISel/legalize-bitreverse.mir | 21 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir | 42 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir | 42 +- .../AMDGPU/GlobalISel/regbankselect-phi-s1.mir | 96 ++- .../AMDGPU/GlobalISel/regbankselect-phi.mir | 14 +- llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll | 762 +++++++++++++++++- llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir | 88 +++ .../Mips/GlobalISel/instruction-select/bswap.mir | 30 + .../Mips/GlobalISel/legalizer/bitreverse.mir | 215 +++++ .../CodeGen/Mips/GlobalISel/legalizer/bswap.mir | 101 +++ .../CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll | 184 +++++ llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bswap.ll | 68 ++ .../Mips/GlobalISel/regbankselect/bswap.mir | 28 + llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll | 10 + llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll | 2 +- llvm/test/CodeGen/PowerPC/rounding-ops.ll | 8 +- llvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll | 561 +++++++++++++ .../PowerPC/vector-constrained-fp-intrinsics.ll | 372 +++------ .../cond-vector-reduce-mve-codegen.ll | 17 +- .../Thumb2/LowOverheadLoops/fast-fp-loops.ll | 280 +++---- llvm/test/CodeGen/Thumb2/emit-unwinding.ll | 15 + llvm/test/CodeGen/Thumb2/large-call.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll | 615 +++++++++++++++ llvm/test/CodeGen/Thumb2/mve-stacksplot.mir | 3 +- llvm/test/CodeGen/X86/ms-inline-asm.ll | 2 +- llvm/test/CodeGen/X86/offset-operator.ll | 15 + llvm/test/CodeGen/X86/pr44412.ll | 36 + llvm/test/CodeGen/X86/sadd_sat.ll | 4 +- llvm/test/CodeGen/X86/sadd_sat_vec.ll | 140 ++-- llvm/test/CodeGen/X86/ssub_sat.ll | 10 +- llvm/test/CodeGen/X86/ssub_sat_vec.ll | 220 +++--- llvm/test/DebugInfo/X86/range_reloc.ll | 2 +- llvm/test/MC/X86/pr32530.s | 13 + llvm/test/TableGen/predicate-patfags.td | 63 ++ .../ArgumentPromotion/2008-07-02-array-indexing.ll | 2 +- .../Attributor/ArgumentPromotion/control-flow.ll | 2 +- .../Attributor/ArgumentPromotion/control-flow2.ll | 4 +- .../Attributor/ArgumentPromotion/reserve-tbaa.ll | 2 +- llvm/test/Transforms/Attributor/value-simplify.ll | 2 +- llvm/test/Transforms/InstCombine/copysign.ll | 5 +- .../Transforms/InstCombine/load-insert-store.ll | 98 +++ llvm/test/tools/llvm-profdata/show-prof-size.test | 2 +- .../tools/yaml2obj/ELF/custom-null-section.yaml | 4 +- llvm/tools/opt/opt.cpp | 13 +- llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp | 120 +++ llvm/utils/TableGen/CodeGenDAGPatterns.cpp | 26 +- mlir/include/mlir/IR/Block.h | 2 +- mlir/include/mlir/IR/Operation.h | 32 +- mlir/include/mlir/IR/UseDefLists.h | 354 ++++++--- mlir/include/mlir/IR/Value.h | 78 +- mlir/lib/IR/Operation.cpp | 58 +- mlir/lib/IR/Value.cpp | 95 ++- mlir/lib/Transforms/ViewOpGraph.cpp | 10 +- .../deviceRTLs/amdgcn/src/target_impl.h | 4 +- .../libomptarget/deviceRTLs/common/src/libcall.cu | 4 +- .../deviceRTLs/nvptx/src/target_impl.h | 6 +- 127 files changed, 6328 insertions(+), 1939 deletions(-) create mode 100644 clang/test/CodeGen/complex-builtins-2.c create mode 100644 llvm/test/Bitcode/upgrade-frame-pointer.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmad.ftz.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mul.u24.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir create mode 100644 llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bswap.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitreverse.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/bswap.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bswap.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bswap.mir create mode 100644 llvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll create mode 100644 llvm/test/CodeGen/X86/offset-operator.ll create mode 100644 llvm/test/CodeGen/X86/pr44412.ll create mode 100644 llvm/test/MC/X86/pr32530.s create mode 100644 llvm/test/TableGen/predicate-patfags.td create mode 100644 llvm/test/Transforms/InstCombine/load-insert-store.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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Tcwg-commits December 2019