Tcwg-commits October 2019

tcwg-commits@lists.linaro.org

6 participants
13959 discussions

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-defconfig updated (105db24 -> 83441e4)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-defconfig in repository toolchain/ci/base-artifacts. discards 105db24 0: update: binutils-gcc-linux: boot new 83441e4 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (105db24) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 128 +- 02-prepare_abe/console.log | 349 +- 03-build_abe-binutils/console.log | 10702 ++++++++-------- 04-build_abe-stage1/console.log | 12625 +++++++++--------- 05-build_linux/console.log | 666 +- 06-boot_linux/console.log | 406 +- console.log | 24937 ++++++++++++++++++------------------ jenkins/manifest.sh | 8 +- 8 files changed, 24908 insertions(+), 24913 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 8 months

[gcc] branch gcc-9-branch updated (b553943b346 -> 6d913d0b879)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch gcc-9-branch in repository gcc. from b553943b346 Daily bump. new 6d913d0b879 2019-10-23 Richard Biener <rguenther(a)suse.de> The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 9 +++++++++ gcc/dwarf2out.c | 23 +++++++++++------------ gcc/testsuite/ChangeLog | 8 ++++++++ gcc/testsuite/g++.dg/debug/dwarf2/pr91887.C | 12 ++++++++++++ 4 files changed, 40 insertions(+), 12 deletions(-) create mode 100644 gcc/testsuite/g++.dg/debug/dwarf2/pr91887.C -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 8 months

[gcc] branch master updated (e04a052b62e -> 121edf5c829)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from e04a052b62e Do not ICE in IPA inliner. new 9e9f7790df6 2019-10-23 Richard Biener <rguenther(a)suse.de> new 121edf5c829 [AArch64] Don't apply mode_for_int_vector to scalars The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 13 ++++++++++++ gcc/config/aarch64/aarch64.c | 4 +++- gcc/tree-vect-stmts.c | 49 ++++++++++++++++++++++++++------------------ 3 files changed, 45 insertions(+), 21 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 8 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allyesconfig updated (7d194c2100ad -> 3b7c59a1950c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allyesconfig in repository toolchain/ci/linux. from 7d194c2100ad Linux 5.4-rc4 adds 20504fa1d2ff pinctrl: armada-37xx: fix control of pins 32 and up adds f876dbff857b pinctrl: bcm-iproc: Use SPDX header adds 39b65fbb8130 pinctrl: ns2: Fix off by one bugs in ns2_pinmux_enable() adds 48659227e0a1 pinctrl: iproc: allow for error from platform_get_irq() adds 2fd215b8fdbe pinctrl: stmfx: fix null pointer on remove adds b835d6953009 pinctrl: armada-37xx: swap polarity on LED group adds 57ff2df1b952 pinctrl: intel: Allocate IRQ chip dynamic adds 260996c30f4f pinctrl: cherryview: restore Strago DMI workaround for all [...] adds d2fe76dddaac Merge tag 'intel-pinctrl-fixes-v5.4' of git://git.kernel.o [...] adds 8f1c9dffe30b pinctrl: berlin: as370: fix a typo s/spififib/spdifib adds 9091a0698be2 dt-bindings: pinctrl: aspeed-g6: Rework SD3 function and groups adds 377dfcdcc046 pinctrl: aspeed-g6: Sort pins for sanity adds b178f91f449c pinctrl: aspeed-g6: Fix I2C14 SDA description adds 9979346f5560 pinctrl: aspeed-g6: Fix I3C3/I3C4 pinmux configuration adds c136d4c71f75 pinctrl: aspeed-g6: Make SIG_DESC_CLEAR() behave intuitively adds 155058343253 pinctrl: aspeed-g6: Fix UART13 group pinmux adds d6e7a1a5119c pinctrl: aspeed-g6: Rename SD3 to EMMC and rework pin groups adds 3b7c59a1950c Merge tag 'pinctrl-v5.4-2' of git://git.kernel.org/pub/scm [...] No new revisions were added by this update. Summary of changes: .../bindings/pinctrl/aspeed,ast2600-pinctrl.yaml | 86 +++++++------- drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 124 +++++++++------------ drivers/pinctrl/aspeed/pinmux-aspeed.h | 3 +- drivers/pinctrl/bcm/pinctrl-iproc-gpio.c | 12 +- drivers/pinctrl/bcm/pinctrl-ns2-mux.c | 4 +- drivers/pinctrl/berlin/pinctrl-as370.c | 2 +- drivers/pinctrl/intel/pinctrl-cherryview.c | 4 - drivers/pinctrl/intel/pinctrl-intel.c | 27 ++--- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 26 ++--- drivers/pinctrl/pinctrl-stmfx.c | 2 +- 10 files changed, 131 insertions(+), 159 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 8 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allyesconfig updated (b0f2012 -> a295d71)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allyesconfig in repository toolchain/ci/base-artifacts. discards b0f2012 0: update: llvm-linux: all new a295d71 0: update: llvm-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (b0f2012) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-aarc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 220 +- 02-build_llvm/console.log | 12002 +++++++++++++++++------------------ 03-build_linux/console.log | 670 +- 04-boot_linux/console.log | 6 +- 05-check_regression/console.log | 8 +- 06-update_baseline/console.log | 25 - console.log | 12931 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 8 files changed, 12910 insertions(+), 12960 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 8 months

[linux] branch master updated (3b7c59a1950c -> 13b86bc4cd64)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository linux. from 3b7c59a1950c Merge tag 'pinctrl-v5.4-2' of git://git.kernel.org/pub/scm [...] new 44db1216efe3 Btrfs: add missing extents release on file extent cluster [...] new 4b654acdae85 btrfs: block-group: Fix a memory leak due to missing btrfs [...] new 80ed4548d071 btrfs: don't needlessly create extent-refs kernel thread new 8702ba9396bf btrfs: qgroup: Always free PREALLOC META reserve in btrfs_ [...] new fd2b007eaec8 btrfs: tracepoints: Fix wrong parameter order for qgroup events new 1b2442b4ae0f btrfs: tracepoints: Fix bad entry members of qgroup events new c7967fc1499b Btrfs: fix qgroup double free after failure to reserve met [...] new ba0b084ac309 Btrfs: check for the full sync flag while holding the inod [...] new 54955e3bfde5 Merge tag 'for-5.4-rc4-tag' of git://git.kernel.org/pub/sc [...] new 1e72e673b9d1 EDAC/ghes: Fix Use after free in ghes_edac remove path new e969c860d563 Merge tag 'edac_urgent_for_5.4' of git://git.kernel.org/pu [...] new 67e15fa5b487 ARM: mm: fix alignment handler faults under memory pressure new 1bb9fb0a147f ARM: mm: alignment: use "u32" for 32-bit instructions new 851140ab0d08 ARM: 8908/1: add __always_inline to functions called from [...] new 4c0742f65b4e ARM: 8914/1: NOMMU: Fix exc_ret for XIP new 2ecb287998a4 ARM: 8926/1: v7m: remove register save to stack before svc new e963408e8ff4 drivers/amba: fix reset control error handling new 39f4d4410484 Merge branch 'misc' into fixes new 13b86bc4cd64 Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm The 19 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: arch/arm/include/asm/domain.h | 8 ++--- arch/arm/include/asm/uaccess.h | 4 +-- arch/arm/kernel/head-common.S | 5 +-- arch/arm/kernel/head-nommu.S | 2 ++ arch/arm/mm/alignment.c | 70 +++++++++++++++++++++++++++++------------- arch/arm/mm/proc-v7m.S | 6 ++-- drivers/amba/bus.c | 14 +++++++-- drivers/edac/ghes_edac.c | 4 +++ fs/btrfs/block-group.c | 1 + fs/btrfs/ctree.h | 5 +-- fs/btrfs/delalloc-space.c | 7 ++--- fs/btrfs/disk-io.c | 6 ---- fs/btrfs/file.c | 43 ++++++++++++-------------- fs/btrfs/inode-map.c | 4 +-- fs/btrfs/inode.c | 12 ++++---- fs/btrfs/ioctl.c | 6 ++-- fs/btrfs/qgroup.c | 4 +-- fs/btrfs/relocation.c | 9 +++--- include/trace/events/btrfs.h | 3 +- 19 files changed, 120 insertions(+), 93 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 8 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allmodconfig updated (0f4186779e0 -> 64df708400a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allmodconfig in repository toolchain/ci/llvm-project. from 0f4186779e0 [ThinLTO] Don't internalize during promotion adds 17f5d2b1a5c [Alignment][NFC] Attributes use Align/MaybeAlign adds 8e050e41a4b [Alignment][NFC] Use MaybeAlign in AttrBuilder adds f2c8f3b181e [PowerPC] Turn on CR-Logical reducer pass adds 734c74ba14b [Alignment][NFC] Convert LoadInst to MaybeAlign adds 5b99c189b3b [Alignment][NFC] Convert StoreInst to MaybeAlign adds e5dd30f77e1 [ThinLTO] Add code comment. NFC adds e4af9de36ca [MIPS GlobalISel] Select MSA vector generic and builtin add adds 95290827d7d [MIParser] Set RegClassOrRegBank during instruction parsing adds 3ef017d0669 [InstCombine] Signed saturation tests. NFC adds 40c47680eb2 [libcxx] Remove shared_ptr::make_shared adds 186155b89c2 [InstCombine] Signed saturation patterns adds 3bf7fddeb05 Update git-llvm script to push to GitHub adds 0bff9bd26e3 [lldb] Adjust for the new class_rw_t layout. adds 19ca80ef057 gn build: make sync build work with git revs now that svn is gone adds 48f57138be5 [AMDGPU] Allow tied operand subreg folding adds 8be5827f856 Test commit - add clarification to README regarding Darwin. adds a7cebfe9c03 Relax assertions when there's really no entries. [NFC] adds f9b1dc5553c [AMDGPU] Updated fold-vgpr-copy.mir test. NFC. adds 9b1419a9e50 [NFC][LVI][CVP] Tests where pre-specified `add` no-wrap fla [...] adds 4334892e7b0 [DAGCombine][ARM] x ==/!= c -> (x - c) ==/!= 0 iff '-c' [...] adds 68f5ca4e19c [HIP] Add option -fgpu-allow-device-init adds aed9d6d64a3 [RISCV] Add support for -ffixed-xX flags adds e0e7d06df3e fix a few typos to test git committing adds 70316d3174d Revert "Fix lld detection in standalone compiler-rt." adds 1c98ff49a30 Fix name of warn_ignored_hip_only_option adds 4c539e8da1b Revert r374202"[ObjC generics] Fix not inheriting type boun [...] adds f86dc64bad4 typo fix test commit adds cf57be9d349 [PowerPC][NFC] Remove deprecated Function Attrs comments adds efd7caaa4ec Fix broken sphinx link in CMake.rst. adds 31d3c1d8b70 [PowerPC][NFC] Remove deprecated Function Attrs comments #2 adds 19e95ab4210 [NFC] Strip trailing whitespace in test to test Github committing adds 437e0e5191c [libcxx][test][NFC] Fix comment typos. adds d052a578de5 [c++2a] Allow comparison functions to be explicitly defaulted. adds 20bf0cf2f02 [TargetLowering] optimizeSetCCToComparisonWithZero(): add e [...] adds c46d24f5c31 [MIPS GlobalISel] Select MSA vector generic and builtin sub adds d1815dacb00 [MIPS GlobalISel] Select MSA vector generic and builtin mul adds 64df708400a [lib/ObjectYAML] - Add a full stop to the comment. NFC. No new revisions were added by this update. Summary of changes: clang/include/clang/AST/Decl.h | 7 + clang/include/clang/AST/Type.h | 2 +- clang/include/clang/Basic/DiagnosticCommonKinds.td | 8 +- clang/include/clang/Basic/DiagnosticGroups.td | 4 + clang/include/clang/Basic/DiagnosticSemaKinds.td | 25 + clang/include/clang/Basic/LangOptions.def | 1 + clang/include/clang/Driver/Options.td | 9 +- clang/include/clang/Sema/Sema.h | 73 ++- clang/lib/AST/Decl.cpp | 23 +- clang/lib/AST/Type.cpp | 4 - clang/lib/CodeGen/CGDeclCXX.cpp | 7 +- clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 64 +++ clang/lib/Driver/ToolChains/HIP.cpp | 4 + clang/lib/Frontend/CompilerInvocation.cpp | 7 + clang/lib/Parse/ParseDecl.cpp | 3 +- clang/lib/Parse/ParseDeclCXX.cpp | 3 +- clang/lib/Sema/SemaCUDA.cpp | 2 + clang/lib/Sema/SemaDecl.cpp | 22 - clang/lib/Sema/SemaDeclCXX.cpp | 285 ++++++++++-- clang/lib/Sema/SemaTemplateInstantiateDecl.cpp | 9 +- .../class.compare/class.compare.default/p1.cpp | 46 ++ clang/test/CXX/class/class.compare/class.eq/p1.cpp | 25 + .../test/CXX/class/class.compare/class.rel/p1.cpp | 25 + .../dcl.fct.def/dcl.fct.def.default/p1.cpp | 26 +- clang/test/CodeGenCUDA/device-init-fun.cu | 19 + clang/test/Driver/riscv-fixed-x-register.c | 341 ++++++++++++++ clang/test/Frontend/warn-device-init-fun.cu | 8 + clang/test/Parser/cxx0x-decl.cpp | 2 +- clang/test/SemaCXX/cxx0x-defaulted-functions.cpp | 2 +- clang/test/SemaCXX/cxx17-compat.cpp | 33 ++ clang/test/SemaObjC/parameterized_classes_subst.m | 14 - compiler-rt/CMakeLists.txt | 2 +- compiler-rt/cmake/config-ix.cmake | 1 - libcxx/include/memory | 45 +- .../memory/aligned_allocation_macro.pass.cpp | 2 +- .../array/array.cons/initializer_list.pass.cpp | 2 +- .../lexically_relative_and_proximate.pass.cpp | 2 +- .../fs.op.funcs/fs.op.relative/relative.pass.cpp | 2 +- .../weakly_canonical.pass.cpp | 2 +- .../fpos/fpos.operations/difference.pass.cpp | 2 +- .../fpos/fpos.operations/subtraction.pass.cpp | 2 +- libcxx/test/std/numerics/c.math/abs.pass.cpp | 4 +- .../string_compare/size_size_string_view.pass.cpp | 2 +- .../opge.string_view.pointer.pass.cpp | 4 +- .../opgt.string_view.pointer.pass.cpp | 4 +- .../ople.string_view.pointer.pass.cpp | 4 +- .../oplt.string_view.pointer.pass.cpp | 4 +- .../meta.const.eval/is_constant_evaluated.pass.cpp | 2 +- .../meta/meta.rel/is_convertible.pass.cpp | 2 +- .../optional/optional.specalg/swap.pass.cpp | 2 +- .../unique.ptr.asgn/move_convert.pass.cpp | 2 +- .../unique.ptr.class/unique.ptr.ctor/move.pass.cpp | 4 +- .../unique.ptr.ctor/move_convert.pass.cpp | 2 +- .../unique.ptr.ctor/nullptr.pass.cpp | 2 +- .../unique.ptr.ctor/pointer.pass.cpp | 2 +- .../time.cal.weekday.members/ok.pass.cpp | 2 +- .../tuple.tuple/tuple.assign/convert_copy.pass.cpp | 2 +- .../tuple.tuple/tuple.assign/convert_move.pass.cpp | 2 +- lld/include/lld/Core/Error.h | 4 +- lld/include/lld/Core/UndefinedAtom.h | 2 +- .../AppleObjCClassDescriptorV2.cpp | 12 + llvm/docs/CMake.rst | 2 +- llvm/include/llvm/CodeGen/TargetLowering.h | 7 + llvm/include/llvm/IR/Attributes.h | 40 +- llvm/include/llvm/IR/Function.h | 9 +- llvm/include/llvm/IR/InstrTypes.h | 10 +- llvm/include/llvm/IR/Instructions.h | 32 +- llvm/lib/AsmParser/LLParser.cpp | 43 +- llvm/lib/AsmParser/LLParser.h | 4 +- llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 12 +- llvm/lib/CodeGen/MIRParser/MIParser.cpp | 2 + llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 65 +++ llvm/lib/IR/AttributeImpl.h | 4 +- llvm/lib/IR/Attributes.cpp | 51 +-- llvm/lib/IR/Instructions.cpp | 59 ++- llvm/lib/ObjectYAML/ELFEmitter.cpp | 2 +- llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 12 - llvm/lib/Target/Mips/MipsInstructionSelector.cpp | 4 +- llvm/lib/Target/Mips/MipsLegalizerInfo.cpp | 74 ++- llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp | 10 +- llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp | 18 +- llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp | 9 +- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp | 2 +- llvm/lib/Target/PowerPC/README.txt | 3 + llvm/lib/Target/RISCV/RISCV.td | 5 + llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 11 + llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 38 ++ llvm/lib/Target/RISCV/RISCVISelLowering.h | 6 + llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 11 + llvm/lib/Target/RISCV/RISCVRegisterInfo.h | 2 + llvm/lib/Target/RISCV/RISCVSubtarget.cpp | 1 + llvm/lib/Target/RISCV/RISCVSubtarget.h | 5 + llvm/lib/Transforms/IPO/FunctionImport.cpp | 3 + llvm/lib/Transforms/IPO/GlobalOpt.cpp | 16 +- .../Transforms/InstCombine/InstCombineCalls.cpp | 7 +- .../Transforms/InstCombine/InstCombineInternal.h | 1 + .../InstCombine/InstCombineLoadStoreAlloca.cpp | 4 +- llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp | 6 +- .../Transforms/InstCombine/InstCombineSelect.cpp | 67 +++ .../lib/Transforms/Scalar/DeadStoreElimination.cpp | 5 +- llvm/lib/Transforms/Scalar/GVN.cpp | 8 +- llvm/lib/Transforms/Scalar/JumpThreading.cpp | 2 +- llvm/lib/Transforms/Scalar/LoopLoadElimination.cpp | 3 +- llvm/test/CodeGen/AMDGPU/fold-vgpr-copy.mir | 35 +- llvm/test/CodeGen/ARM/addsubcarry-promotion.ll | 62 +-- llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.ll | 27 ++ .../test/CodeGen/MIR/Mips/setRegClassOrRegBank.mir | 39 ++ .../Mips/GlobalISel/instruction-select/add_vec.mir | 130 ++++++ .../Mips/GlobalISel/instruction-select/mul_vec.mir | 130 ++++++ .../Mips/GlobalISel/instruction-select/sub_vec.mir | 130 ++++++ .../CodeGen/Mips/GlobalISel/legalizer/add_vec.mir | 122 +++++ .../Mips/GlobalISel/legalizer/add_vec_builtin.mir | 237 ++++++++++ .../CodeGen/Mips/GlobalISel/legalizer/mul_vec.mir | 122 +++++ .../Mips/GlobalISel/legalizer/mul_vec_builtin.mir | 129 ++++++ .../GlobalISel/legalizer/sitofp_and_uitofp.mir | 20 +- .../CodeGen/Mips/GlobalISel/legalizer/sub_vec.mir | 122 +++++ .../Mips/GlobalISel/legalizer/sub_vec_builtin.mir | 237 ++++++++++ .../CodeGen/Mips/GlobalISel/llvm-ir/add_vec.ll | 70 +++ .../Mips/GlobalISel/llvm-ir/add_vec_builtin.ll | 138 ++++++ .../CodeGen/Mips/GlobalISel/llvm-ir/mul_vec.ll | 70 +++ .../Mips/GlobalISel/llvm-ir/mul_vec_builtin.ll | 74 +++ .../CodeGen/Mips/GlobalISel/llvm-ir/sub_vec.ll | 70 +++ .../Mips/GlobalISel/llvm-ir/sub_vec_builtin.ll | 138 ++++++ .../Mips/GlobalISel/regbankselect/add_vec.mir | 126 +++++ .../Mips/GlobalISel/regbankselect/mul_vec.mir | 126 +++++ .../Mips/GlobalISel/regbankselect/sub_vec.mir | 126 +++++ llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll | 39 +- llvm/test/CodeGen/PowerPC/brcond.ll | 6 +- llvm/test/CodeGen/PowerPC/build-vector-tests.ll | 131 +----- llvm/test/CodeGen/PowerPC/pr42492.ll | 14 +- llvm/test/CodeGen/PowerPC/sms-simple.ll | 6 +- llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll | 15 +- llvm/test/CodeGen/PowerPC/vec-min-max.ll | 23 +- llvm/test/CodeGen/RISCV/reserved-reg-errors.ll | 36 ++ llvm/test/CodeGen/RISCV/reserved-regs.ll | 130 ++++++ llvm/test/CodeGen/X86/pr43769.ll | 54 +++ .../Transforms/CorrelatedValuePropagation/icmp.ll | 136 ++++++ llvm/test/Transforms/InstCombine/sadd_sat.ll | 503 ++++++++++++++++++++ llvm/unittests/IR/AttributesTest.cpp | 8 +- llvm/utils/TableGen/SequenceToOffsetTable.h | 4 +- llvm/utils/git-svn/git-llvm | 510 ++++----------------- .../utils/gn/build/sync_source_lists_from_cmake.py | 24 +- 142 files changed, 4967 insertions(+), 1056 deletions(-) create mode 100644 clang/test/CXX/class/class.compare/class.compare.default/p1.cpp create mode 100644 clang/test/CXX/class/class.compare/class.eq/p1.cpp create mode 100644 clang/test/CXX/class/class.compare/class.rel/p1.cpp create mode 100644 clang/test/CodeGenCUDA/device-init-fun.cu create mode 100644 clang/test/Driver/riscv-fixed-x-register.c create mode 100644 clang/test/Frontend/warn-device-init-fun.cu create mode 100644 llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.ll create mode 100644 llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add_vec.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul_vec.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub_vec.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec_builtin.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub_vec.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub_vec_builtin.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec_builtin.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul_vec.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul_vec_builtin.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub_vec.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub_vec_builtin.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul_vec.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub_vec.mir create mode 100644 llvm/test/CodeGen/RISCV/reserved-reg-errors.ll create mode 100644 llvm/test/CodeGen/RISCV/reserved-regs.ll create mode 100644 llvm/test/CodeGen/X86/pr43769.ll create mode 100644 llvm/test/Transforms/InstCombine/sadd_sat.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 8 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allmodconfig updated (506d48e -> dd291da)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allmodconfig in repository toolchain/ci/base-artifacts. discards 506d48e 0: update: llvm-linux: all new dd291da 0: update: llvm-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (506d48e) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 110 +- 02-build_llvm/console.log | 12857 ++++++++++++++-------------- 03-build_linux/console.log | 5032 +++++------ 04-boot_linux/console.log | 2 +- 06-update_baseline/console.log | 8 +- console.log | 18009 ++++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 7 files changed, 18366 insertions(+), 17660 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 8 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-allnoconfig updated (7d194c2100ad -> 3b7c59a1950c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-allnoconfig in repository toolchain/ci/linux. from 7d194c2100ad Linux 5.4-rc4 adds 20504fa1d2ff pinctrl: armada-37xx: fix control of pins 32 and up adds f876dbff857b pinctrl: bcm-iproc: Use SPDX header adds 39b65fbb8130 pinctrl: ns2: Fix off by one bugs in ns2_pinmux_enable() adds 48659227e0a1 pinctrl: iproc: allow for error from platform_get_irq() adds 2fd215b8fdbe pinctrl: stmfx: fix null pointer on remove adds b835d6953009 pinctrl: armada-37xx: swap polarity on LED group adds 57ff2df1b952 pinctrl: intel: Allocate IRQ chip dynamic adds 260996c30f4f pinctrl: cherryview: restore Strago DMI workaround for all [...] adds d2fe76dddaac Merge tag 'intel-pinctrl-fixes-v5.4' of git://git.kernel.o [...] adds 8f1c9dffe30b pinctrl: berlin: as370: fix a typo s/spififib/spdifib adds 9091a0698be2 dt-bindings: pinctrl: aspeed-g6: Rework SD3 function and groups adds 377dfcdcc046 pinctrl: aspeed-g6: Sort pins for sanity adds b178f91f449c pinctrl: aspeed-g6: Fix I2C14 SDA description adds 9979346f5560 pinctrl: aspeed-g6: Fix I3C3/I3C4 pinmux configuration adds c136d4c71f75 pinctrl: aspeed-g6: Make SIG_DESC_CLEAR() behave intuitively adds 155058343253 pinctrl: aspeed-g6: Fix UART13 group pinmux adds d6e7a1a5119c pinctrl: aspeed-g6: Rename SD3 to EMMC and rework pin groups adds 3b7c59a1950c Merge tag 'pinctrl-v5.4-2' of git://git.kernel.org/pub/scm [...] No new revisions were added by this update. Summary of changes: .../bindings/pinctrl/aspeed,ast2600-pinctrl.yaml | 86 +++++++------- drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 124 +++++++++------------ drivers/pinctrl/aspeed/pinmux-aspeed.h | 3 +- drivers/pinctrl/bcm/pinctrl-iproc-gpio.c | 12 +- drivers/pinctrl/bcm/pinctrl-ns2-mux.c | 4 +- drivers/pinctrl/berlin/pinctrl-as370.c | 2 +- drivers/pinctrl/intel/pinctrl-cherryview.c | 4 - drivers/pinctrl/intel/pinctrl-intel.c | 27 ++--- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 26 ++--- drivers/pinctrl/pinctrl-stmfx.c | 2 +- 10 files changed, 131 insertions(+), 159 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 8 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-allnoconfig updated (4593553 -> 89044ae)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-allnoconfig in repository toolchain/ci/base-artifacts. discards 4593553 0: update: llvm-linux: all new 89044ae 0: update: llvm-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (4593553) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-arm- [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 166 +- 02-build_llvm/console.log | 11948 ++++++++++++++++++------------------ 03-build_linux/console.log | 620 +- 04-boot_linux/console.log | 2 +- console.log | 12761 ++++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 6 files changed, 12765 insertions(+), 12740 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 8 months

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Tcwg-commits October 2019