Tcwg-commits September 2017

tcwg-commits@lists.linaro.org

6 participants
3137 discussions

[gcc] branch rsandifo/sve-rebase updated (177960d125f -> ef23a3d42dc)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch rsandifo/sve-rebase in repository gcc. discards 177960d125f Work around PR81082 discards 786b4eb1b04 Use conditional internal functions in if-conversion discards eb54cd0e094 Implement SLP of internal functions discards c548ba751f0 Handle vector boolean types when calculating the SLP unroll factor discards aced0fe83d2 Remove unnecessary temporary in tree-if-conv.c discards adaacac36e5 Don't require an integer mode for PARALLELs discards 8610e671bd4 Add early rematerialisation pass discards 560665e67be Record equivalences for spill registers discards acb3c9d2491 Support fused multiply-adds in fully-masked reductions discards 3737b05aac9 Replace FMA_EXPR with one internal fn per optab discards ec18574a642 Use single-iteration epilogues when peeling for gaps discards ff96746a4ae Allow single-element interleaving for non-power-of-2 strides discards 90b2d2609ed Add support for first-faulting loads discards 98d4366f61d Add support for speculative loads discards c092fdb9932 Support for aliasing with variable strides discards d448846d7fe Fix for big field stores discards 29eed380e44 Avoid pessimistic check for overlapping groups discards ae378521a8f Add support for gather loads and scatter stores discards af2db18adca Add support for FADDA discards f0051cd19e5 Add support for CLASTB discards 0296146662f Add support for BRKA and LASTB discards 4445deeba8e Allow capped vectorisation factors discards 80a0901f868 Reuse results of vect_create_addr_base_for_vector_ref discards 26ef82e3618 Add an empty_mask_is_expensive hook discards 732eff2973c Predicated arithmetic folds discards d1e4c744bdc Predicated comparison folds discards 3bf65415228 Allow combine to reorder statements discards 2c10c5cf870 Rework the legitimize_address_displacement hook discards bd601cf2e43 Improve ivopts handling of offset multiples discards 3d7e31b4d78 Handle peeling for alignment with masking discards 361cbf2997a Allow the number of iterations to be smaller than VF discards 233d390c4ea Make ivopts handle calls to internal functions discards b0c750f8609 Improve VIEW_CONVERT_EXPR for vector booleans discards 249248d3c14 Add support for fully-predicated loops discards b016ee14732 Protect against min_profitable_iters going negative discards f07d2565c2c SLP reductions with variable-length vectors discards 64d6df9984a Handle more SLP constant and extern definitions for variable VF discards 6fec6d2fc57 Add optabs for common types of permutation discards 10515c3259e Add support for bitwise reductions discards 82192d164f4 Add support for masked load/store_lanes discards 5554c972348 [AArch64] SVE load/store_lanes support discards af3dd6f0977 Fix folding of vector mask EQ/NE expressions discards aac737bc8e7 [AArch64] Testsuite markup for SVE discards b9adb798350 [AArch64] Add SVE support discards 7e72ebf292e Revert DECL_USER_ALIGN patch discards 85fcfe5d34a vect_masked_store discards 6f971bbe077 vect_align_stack_vars discards aa29cef42ba vect_variable_length discards 8ddb3912127 target_vect_unaligned_possible discards 7035c33e90b vect_element_align_preferred discards 5c18a9963db vect_permN discards 3498dd0a23f available_vector_sizes discards 4a8ac7dabb2 Add VECTOR_BITS to tree-vect.h discards 8755c781353 Use asm volatile ("" ::: "memory") discards 513424be113 Use extract_bit_field_as_subreg for vectors discards 188ec7f09c4 Improve spilling for variable-width slots discards 4d118127687 Improve canonicalisation of TARGET_MEM_REFs discards 07261597c2f Improve ivopts handling of forced scales discards 54dedce8a8b Improve vector mask pattern handling discards eebfd6df60c [AArch64] Generate permute patterns using rtx builders discards d67d491a144 [AArch64] Rewrite aarch64_simd_valid_immediate discards 7e005720e80 [AArch64] Add const_offset field to aarch64_address_info discards 5a620fd09d3 [AArch64] Rename the internal "Upl" constraint discards a3a1ca1ae4a [AArch64] Set NUM_POLY_INT_COEFFS to 2 discards 1bc7d6dfcc1 [AArch64] Rework interface to add constant/offset routines discards be1e3304cf5 [AArch64] Move code around discards 83089a07ac0 Allow the target to set MAX_BITSIZE_MODE_ANY_MODE discards b8ac46e7f92 Add support for adjusting the number of units in a mode discards 1fb9fb3b984 Add support for MODE_VECTOR_BOOL discards 4f1910420bc Don't query the frontend for unsupported types discards 7b2f08e3d5d Make more use of simplify_gen_binary discards 24664896c77 Use poly_int rtx accessors instead of hwi accessors discards 82fe36e7800 Use poly_int tree accessors instead of hwi accessors discards 22dabb2b12b poly_int: GET_MODE_SIZE discards 10e5bdfb39b poly_int: GET_MODE_BITSIZE discards fae46ebbc9c poly_int: GET_MODE_PRECISION discards dd08b0b7036 poly_int: TYPE_VECTOR_SUBPARTS discards 1fe09a2e1f0 poly_int: GET_MODE_NUNITS discards 0768d9b6e29 poly_int: vect_no_alias_p discards 51aa7b4399c poly_int: current_vector_size and TARGET_AUTOVECTORIZE_VECT [...] discards 07563fd1d57 poly_int: get_mask_mode discards 021d5f1ae69 poly_int: omp_max_vf discards db3cc4dfe08 poly_int: vectoriser vf and uf discards 59f590bb86f poly_int: prune_runtime_alias_test_list discards 3ee5e177725 poly_int: loop versioning threshold discards 0765dd04818 poly_int: tree-ssa-loop-ivopts.c:iv_use discards 0c6a894e099 poly_int: get_binfo_at_offset discards 08d62f1e048 poly_int: build_ref_for_offset discards 6b604621ecf poly_int: MEM_REF offsets discards 1ae2823cbef poly_int: bit_field_size/offset discards 22f2a96cdba poly_int: int_size_in_bytes discards 02db4c3a54c poly_int: emit_group_load/store discards 52fcd2915b8 poly_int: reload<->ira interface discards ad656ce43b4 poly_int: emit_inc discards afc02c6d8da poly_int: cfgexpand stack variables discards 3528764f40d poly_int: argument sizes discards cc55f1093fd poly_int: REG_ARGS_SIZE discards bad4a90b13d poly_int: push_block/emit_push_insn discards 31c50b594f3 poly_int: frame allocations discards c60c26faf6f poly_int: reload1.c discards 0400e0369d3 poly_int: reload.c discards 8e1c9917897 poly_int: get_inner_reference & co. discards a4f2ec57a88 poly_int: get_inner_reference_aff discards a627dff5b0b poly_int: pointer_may_wrap_p discards 96ccc0ffde3 poly_int: symbolic_number discards 2696aaa247c poly_int: aff_tree discards 972d6dbed61 poly_int: get_addr_unit_base_and_extent discards eb88485cf1d poly_int: get_ref_base_and_extent discards ddb62024e1d poly_int: ipa_parm_adjustment discards ca33f391fdb poly_int: DWARF CFA offsets discards bfc2efc8796 poly_int: operand_subword discards e602dfb02e2 poly_int: SUBREG_BYTE discards 53bed29190e poly_int: store_field & co discards ea07cbac225 poly_int: C++ bitfield regions discards 7d1ea3340c5 poly_int: extract_bit_field bitrange discards 24531eec59a poly_int: store_bit_field bitrange discards eead231a701 poly_int: create_integer_operand discards d8edd0edb2e poly_int: lra frame offsets discards 13dc3386576 poly_int: MEM_OFFSET and MEM_SIZE discards e88b3cfa10c poly_int: rtx_addr_can_trap_p_1 discards 2bd2c0a8e7c poly_int: dse.c discards b9deb0f5dc6 poly_int: ao_ref and vn_reference_op_t discards 320afa842b8 poly_int: same_addr_size_stores_p discards 16b1d69d3e1 poly_int: fold_ctor_reference discards 6797ae2afa2 Add DWARF support for polynomial offsets discards 29db1015377 Make REG_OFFSET a poly_int64 discards 8c6c56c3a66 poly_int: compute_data_ref_aligment discards 339cf948e6e Add poly_int dump routines discards bba059dbdc8 Add polynomial tree constants discards 08b8a21beff Add polynomial rtx constants discards c2c764b0399 Make mode query functions accept poly_ints discards 694c680b812 Treat VEC_{DUPLICATE,SERIES}_EXPR as gimple constants discards fc20343bcf9 Add VEC_SERIES_EXPR and associated optab discards de5955c4af3 Add a VEC_DUPLICATE_EXPR tree code and associated optab discards dc76ed88892 Add a VEC_SERIES rtl code discards 3ca5d1f5ad5 Allow vector CONSTs discards 33c1600d9f1 Add rtx const vec_duplicate helpers discards 80201e16a7d Factor out the mode handling in lower-subreg.c discards f31ea06145b [AArch64] Add an endian_lane_rtx helper routine discards 5dd12a15f9b Add copy_rtx call to RTL loop unroller discards 276fb73f2c3 SUBREG_PROMOTED_VAR_P handling in expand_direct_optab_fn discards e78c3a2aa3f Prevent invalid register mode changes in combine discards 92d9215eb6b Fix infinite loop in simplify_operand_subreg discards c1b2c238ebe Fix for match.pd handling of three-constant bitops discards cfc4094aab6 Fix unguarded uses of tree_to_uhwi discards 2cf39d91827 Tighten tree-ssa-ccp.c:get_value_for_expr condition discards ee1b69e160a Add missing int_cst_rangeN checks to tree-vrp.c discards 93cd489261e compare_values use in extract_range_from_multiplicative_op_1 discards 81b2ab128ea Base subreg rules on REGMODE_NATURAL_SIZE rather than UNITS [...] discards b0f02b546cf Let the target choose a vectorisation alignment discards a6c2f2a7a86 Fix a failure in the Fortran matmul* tests discards eaedcf87d32 Include phis in SLP unrolling calculation discards 35dd7922338 mask load/store for external masks discards c0561923e33 Fix type of bitstart in vectorizable_live_operation discards b8fc0a07e4e Fix vectorizable_live_operation handling of vector booleans discards 44a4cd0dd1d Invoke vectorizable_live_operation in a consistent way discards 6583bdb69c5 Move computation of SLP_TREE_NUMBER_OF_VEC_STMTS discards 9ebff4f2cdb Add LOOP_VINFO_MAX_VECT_FACTOR discards e55ad216cb8 Add a vect_get_dr_size helper function discards 2038ad5f588 Add a vect_worthwhile_without_simd_p helper routine discards cd2e62112ca Add a vect_get_num_copies helper routine discards 0757fe4c9d3 Make more use of gimple-fold.h discards 0110e13d3dd Add gimple_build_vector* helpers discards 2c7df4e1757 Pass number of elements alongside tree* when constructing vectors discards 168eac7f21b Store VECTOR_CST_NELTS directly in tree node discards 419f7649cae Use MACRO_MODE for FUNCTION_ARG_OFFSET discards 0a767b4c079 Use MACRO_MODE for TRULY_NOOP_TRUNCATION_MODES_P discards 6a0d1227461 Use MACRO_MODE for CANNOT_CHANGE_MODE_CLASS discards df7bab4c6d2 Use MACRO_MODE for SECONDARY_MEMORY_NEEDED discards 325b37cfe7c Use MACRO_MODE for SECONDARY_MEMORY_NEEDED_MODE discards 5a217e3558d Use MACRO_MODE for HARD_REGNO_NREGS discards d29991acf7f Turn SLOW_UNALIGNED_ACCESS into a target hook discards 098af172e36 Use MACRO_MODE for targhooks.c and address.h wrappers discards 495850961d6 Add helpers for shift count modes discards 8e4585a3480 Use scalar_mode in expand_shift_1 discards 0d54be45f8f Widening optab cleanup discards 7ad76b3d087 Add a fixed_size_mode_pod class discards b7148037b50 Add a fixed_size_mode class discards b5309864e05 Add a mem_alias_size helper class discards 18904d1bb86 [AArch64] Fix address check in SIMD mov expander discards f0355833340 Test failures discards 7fe064fdc8b Remove DOS file formatting discards be756a82c4d Revert r251538 discards f6e9bb53488 TARGET_C_FILE discards f46128ff363 Add poly-int.h new 4979f3ebbed Add poly-int.h new e29587874bd TARGET_C_FILE new eff8f2a5045 Revert r251538 new 1bcd36cd056 Remove DOS file formatting new 1aeaad25057 Test failures new d6293f8bfb7 [AArch64] Fix address check in SIMD mov expander new b43836fd50c Add a mem_alias_size helper class new 6b33cdf3616 Add a fixed_size_mode class new 975b1b89641 Add a fixed_size_mode_pod class new 10379376ef8 Widening optab cleanup new 195a8561cab Use scalar_mode in expand_shift_1 new b68ee9e8e23 Add helpers for shift count modes new af3a447c267 Use MACRO_MODE for targhooks.c and address.h wrappers new 644ddf5b469 Turn SLOW_UNALIGNED_ACCESS into a target hook new 7192b40b153 Use MACRO_MODE for HARD_REGNO_NREGS new eb845e7427e Use MACRO_MODE for SECONDARY_MEMORY_NEEDED_MODE new 04d0418956b Use MACRO_MODE for SECONDARY_MEMORY_NEEDED new 40eef5b52b0 Use MACRO_MODE for CANNOT_CHANGE_MODE_CLASS new 0d1697a591a Use MACRO_MODE for TRULY_NOOP_TRUNCATION_MODES_P new 63d0bcaa52b Use MACRO_MODE for FUNCTION_ARG_OFFSET new f0ce84151f3 Store VECTOR_CST_NELTS directly in tree node new 68267c798b0 Pass number of elements alongside tree* when constructing vectors new 71b428acebe Add gimple_build_vector* helpers new 9815bec4d69 Make more use of gimple-fold.h new 4db84a0df3b Add a vect_get_num_copies helper routine new eeac0dc9338 Add a vect_worthwhile_without_simd_p helper routine new b3fdcb47aba Add a vect_get_dr_size helper function new a7e6f56353b Add LOOP_VINFO_MAX_VECT_FACTOR new b897a0f6f38 Move computation of SLP_TREE_NUMBER_OF_VEC_STMTS new 71970d913d5 Invoke vectorizable_live_operation in a consistent way new 2c3e914f0fa Fix vectorizable_live_operation handling of vector booleans new dfb17348147 Fix type of bitstart in vectorizable_live_operation new f587a5a1d0c mask load/store for external masks new 96c585ce9fd Include phis in SLP unrolling calculation new 3d76fcf1044 Fix a failure in the Fortran matmul* tests new 7e509ee0f1e Let the target choose a vectorisation alignment new 325e9a946c1 Base subreg rules on REGMODE_NATURAL_SIZE rather than UNITS [...] new 7cdb8b7309b compare_values use in extract_range_from_multiplicative_op_1 new 47215b3cbb6 Add missing int_cst_rangeN checks to tree-vrp.c new f5c9064742d Tighten tree-ssa-ccp.c:get_value_for_expr condition new 05c0544d42a Fix unguarded uses of tree_to_uhwi new 38668eeb2cb Fix for match.pd handling of three-constant bitops new ba7b48a74cc Fix infinite loop in simplify_operand_subreg new 6396f0786d0 Prevent invalid register mode changes in combine new 67efee0bd3b SUBREG_PROMOTED_VAR_P handling in expand_direct_optab_fn new d5ed46320e7 Add copy_rtx call to RTL loop unroller new d687f50abab [AArch64] Add an endian_lane_rtx helper routine new 0eb1616928b Factor out the mode handling in lower-subreg.c new 768337e5021 Add rtx const vec_duplicate helpers new fc6dd8c0a21 Allow vector CONSTs new 323fc841f19 Add a VEC_SERIES rtl code new ca8c55dfd36 Add a VEC_DUPLICATE_EXPR tree code and associated optab new f52a830bd92 Add VEC_SERIES_EXPR and associated optab new 0d2c707aa75 Treat VEC_{DUPLICATE,SERIES}_EXPR as gimple constants new 497fdc12029 Make mode query functions accept poly_ints new c09d96cd276 Add polynomial rtx constants new 098010573fd Add polynomial tree constants new 3428e0313f7 Add poly_int dump routines new fe54201c7b4 poly_int: compute_data_ref_aligment new e284f4d7ac1 Make REG_OFFSET a poly_int64 new c94de5d7af9 Add DWARF support for polynomial offsets new 39c37e95c66 poly_int: fold_ctor_reference new 46bbf96bc86 poly_int: same_addr_size_stores_p new 134a5a1b293 poly_int: ao_ref and vn_reference_op_t new ec2205d0f00 poly_int: dse.c new a4bce1992f0 poly_int: rtx_addr_can_trap_p_1 new a46dfd261b0 poly_int: MEM_OFFSET and MEM_SIZE new 679da64eae1 poly_int: lra frame offsets new 0ff9a3c7f7b poly_int: create_integer_operand new 0869d4aa03d poly_int: store_bit_field bitrange new 83f23b1bf62 poly_int: extract_bit_field bitrange new d43866d81de poly_int: C++ bitfield regions new 6dbd434a473 poly_int: store_field & co new 0240825ba7f poly_int: SUBREG_BYTE new 347f8cfe435 poly_int: operand_subword new a3b2c26e60d poly_int: DWARF CFA offsets new 5cb2cd1212e poly_int: ipa_parm_adjustment new b585947aca0 poly_int: get_ref_base_and_extent new a6d8c584896 poly_int: get_addr_unit_base_and_extent new accb36db085 poly_int: aff_tree new 44a0e328e76 poly_int: symbolic_number new ce951bf5734 poly_int: pointer_may_wrap_p new 429dec91073 poly_int: get_inner_reference_aff new d084e8a47a6 poly_int: get_inner_reference & co. new 17a1d2f57a4 poly_int: reload.c new 47afd892561 poly_int: reload1.c new 5b1abd05029 poly_int: frame allocations new 8e35dd88f6c poly_int: push_block/emit_push_insn new c112c3c982e poly_int: REG_ARGS_SIZE new 4c9983b59ae poly_int: argument sizes new cf1accbdaa1 poly_int: cfgexpand stack variables new c106818a499 poly_int: emit_inc new a8341c8a6ab poly_int: reload<->ira interface new 37e245cf582 poly_int: emit_group_load/store new 1c36a9c29b3 poly_int: int_size_in_bytes new 5b945e39570 poly_int: bit_field_size/offset new 13ffe07b87a poly_int: MEM_REF offsets new 5ee9cfad677 poly_int: build_ref_for_offset new 82143ff2d9a poly_int: get_binfo_at_offset new 076dda82086 poly_int: tree-ssa-loop-ivopts.c:iv_use new 92534464a9a poly_int: loop versioning threshold new b5e4185edda poly_int: prune_runtime_alias_test_list new f22d18692d2 poly_int: vectoriser vf and uf new 546f64ab92d poly_int: omp_max_vf new f44e39029b9 poly_int: get_mask_mode new 6f0fd33e0a0 poly_int: current_vector_size and TARGET_AUTOVECTORIZE_VECT [...] new 443110a20b3 poly_int: vect_no_alias_p new 74efce9fdf7 poly_int: GET_MODE_NUNITS new f7d5b045032 poly_int: TYPE_VECTOR_SUBPARTS new 0dd83283638 poly_int: GET_MODE_PRECISION new 6c6516e46f0 poly_int: GET_MODE_BITSIZE new 30c49300190 poly_int: GET_MODE_SIZE new 9d03c8a2f73 Use poly_int tree accessors instead of hwi accessors new 5f179c01600 Use poly_int rtx accessors instead of hwi accessors new 860f2109ee2 Make more use of simplify_gen_binary new ed5d814407a Don't query the frontend for unsupported types new 5e4372e4fcd Add support for MODE_VECTOR_BOOL new 07dbe6e81de Add support for adjusting the number of units in a mode new bf3c1d651cd Allow the target to set MAX_BITSIZE_MODE_ANY_MODE new 154254e320c [AArch64] Move code around new 8125ecac4d1 [AArch64] Rework interface to add constant/offset routines new d2d3e8dd028 [AArch64] Set NUM_POLY_INT_COEFFS to 2 new 14434d14309 [AArch64] Rename the internal "Upl" constraint new 8488b0770e2 [AArch64] Add const_offset field to aarch64_address_info new b73e062deba [AArch64] Rewrite aarch64_simd_valid_immediate new 7e9cfdc77b2 [AArch64] Generate permute patterns using rtx builders new 060323a4e07 Improve vector mask pattern handling new b041addd770 Improve ivopts handling of forced scales new fcba0cf5368 Improve canonicalisation of TARGET_MEM_REFs new 713ae3c6eac Improve spilling for variable-width slots new 562bfba3cb5 Use extract_bit_field_as_subreg for vectors new 524d0b2d555 Use asm volatile ("" ::: "memory") new 7dc6dad1eb6 Add VECTOR_BITS to tree-vect.h new 0f36a6237ed available_vector_sizes new 4e183354130 vect_permN new e546e2fe66a vect_element_align_preferred new eb0e6b0bf0b target_vect_unaligned_possible new 96611c6ab7e vect_variable_length new 202668f9422 vect_align_stack_vars new dc76b394260 vect_masked_store new 70d6c814ee0 Revert DECL_USER_ALIGN patch new ab555c062a2 [AArch64] Add SVE support new 19dc776e2d2 [AArch64] Testsuite markup for SVE new b6fa41549e9 Fix folding of vector mask EQ/NE expressions new 859dc22ab5f [AArch64] SVE load/store_lanes support new 7fa0f8dfb29 Add support for masked load/store_lanes new 5554ffcc8b5 Add support for bitwise reductions new 7c8091164ef Add optabs for common types of permutation new 41d077ba312 Handle more SLP constant and extern definitions for variable VF new 90fa8e5f46d SLP reductions with variable-length vectors new 9abe4ff73c6 Protect against min_profitable_iters going negative new 5dc9f385272 Add support for fully-predicated loops new 962da392212 Improve VIEW_CONVERT_EXPR for vector booleans new 27ebf97012e Make ivopts handle calls to internal functions new d8fdd895898 Allow the number of iterations to be smaller than VF new 956d1b26525 Handle peeling for alignment with masking new 852caeccc50 Improve ivopts handling of offset multiples new f6de01bbcd7 Rework the legitimize_address_displacement hook new 5e22e6b63b3 Allow combine to reorder statements new 5933a35a958 Predicated comparison folds new c3ab6547bfd Predicated arithmetic folds new 55886d6377f Add an empty_mask_is_expensive hook new 12817db72cb Reuse results of vect_create_addr_base_for_vector_ref new d8507fa239e Allow capped vectorisation factors new 67c604dd01b Add support for BRKA and LASTB new 6919370e899 Add support for CLASTB new e7f699c127e Add support for FADDA new 8c36f2080eb Add support for gather loads and scatter stores new cb3a665669c Avoid pessimistic check for overlapping groups new f9dcc26026b Fix for big field stores new 8e42b98a366 Support for aliasing with variable strides new 4f30c15223d Add support for speculative loads new 70c2d758d7f Add support for first-faulting loads new 887f1706126 Allow single-element interleaving for non-power-of-2 strides new 61a12d37d19 Use single-iteration epilogues when peeling for gaps new 30c7c314a65 Replace FMA_EXPR with one internal fn per optab new de4ba95a75f Support fused multiply-adds in fully-masked reductions new 1f5d6a553e1 Record equivalences for spill registers new 43a7245c949 Add early rematerialisation pass new 7ed6633274b Don't require an integer mode for PARALLELs new 63f1a796987 Remove unnecessary temporary in tree-if-conv.c new 05178016359 Handle vector boolean types when calculating the SLP unroll factor new 93fd9167de0 Implement SLP of internal functions new 1fbc954b2b9 Use conditional internal functions in if-conversion new ef23a3d42dc Work around PR81082 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (177960d125f) \ N -- N -- N refs/heads/rsandifo/sve-rebase (ef23a3d42dc) You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 185 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/doc/poly-int.texi | 52 ++++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 41 insertions(+), 11 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 2 months

[gcc] branch linaro-dev/sve updated (ece93ae7fd5 -> c1c77dc5441)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch linaro-dev/sve in repository gcc. from ece93ae7fd5 Merge trunk into sve new c1c77dc5441 Tweak poly-int.texi, and add menus for older texinfo The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/doc/poly-int.texi | 52 ++++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 41 insertions(+), 11 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 2 months

[binutils-gdb] annotated tag gdb-8.0.1-release created (now 140b38cfbc)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to annotated tag gdb-8.0.1-release in repository binutils-gdb. at 140b38cfbc (tag) tagging 2dcf9205c32aa69c102640962ff03746d04c02cc (commit) replaces gdb-8.0-release tagged by Joel Brobecker on Thu Sep 7 07:29:43 2017 -0700 - Log ----------------------------------------------------------------- GDB 8.0.1 Release. -----BEGIN PGP SIGNATURE----- iF0EABECAB0FAlmxV9cWHGJyb2JlY2tlckBhZGFjb3JlLmNvbQAKCRCS7bBL/zJc 87EYAJ40JtCE1jBXBbAUt7qZfFrfbq+fWQCgkwzaBJzlDDBD08l2Slzvz0m4VDg= =kKnq -----END PGP SIGNATURE----- ----------------------------------------------------------------------- No new revisions were added by this update. -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 2 months

[gcc] branch master updated (71abcdeeec6 -> accd2c538b6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 71abcdeeec6 PR target/81979 * output.h (switch_to_other_text_partitio [...] new accd2c538b6 * sancov.c: Include tm_p.h. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 4 ++++ gcc/sancov.c | 1 + 2 files changed, 5 insertions(+) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 2 months

[clang] branch master updated (4c51de1ebe -> 824f38dfa3)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository clang. from 4c51de1ebe [clang-format] Fix documentation for AllowAllParametersOfDec [...] new 824f38dfa3 [clang-format] Add support for C++17 structured bindings. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Format/FormatToken.h | 1 + lib/Format/TokenAnnotator.cpp | 25 ++++++++++++++++++++----- unittests/Format/FormatTest.cpp | 25 +++++++++++++++++++++++++ 3 files changed, 46 insertions(+), 5 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 2 months

[glibc] branch master updated (7c9c5be96f -> 5c23ee6eb8)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository glibc. from 7c9c5be96f Use ASCII in LC_TIME of om_ET for better readability new 05f0011fb0 Add SOL_TLS definition from Linux 4.13. new 5c23ee6eb8 Update netinet/tcp.h from Linux 4.13. The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: ChangeLog | 10 ++++++++++ sysdeps/gnu/netinet/tcp.h | 10 ++++++++-- sysdeps/unix/sysv/linux/bits/socket.h | 1 + 3 files changed, 19 insertions(+), 2 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 2 months

[binutils-gdb] branch master updated (6999821f8b -> 63c99141de)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from 6999821f8b x86: Remove _bfd_{i386,x86_64}_elf_convert_load new 63c99141de remove QStartupWithShell entry from NEWS::Changes in GDB 7.11 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gdb/ChangeLog | 4 ++++ gdb/NEWS | 3 --- 2 files changed, 4 insertions(+), 3 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 2 months

[binutils-gdb] branch gdb-8.0-branch updated (cc08efc331 -> 2dcf9205c3)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch gdb-8.0-branch in repository binutils-gdb. from cc08efc331 Automatic date update in version.in new 2dcf9205c3 Set GDB version number to 8.0.1. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gdb/ChangeLog | 5 +++++ gdb/PROBLEMS | 2 +- gdb/version.in | 2 +- 3 files changed, 7 insertions(+), 2 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 2 months

[llvm] branch master updated (7465dfa4567 -> 563f2fdd927)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 7465dfa4567 [mips] Use RegisterMCAsmBackend to register all MIPS asm ba [...] new 563f2fdd927 [X86][LLVM]Expanding Supports lowerInterleavedLoad() in X86 [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/X86/X86InterleavedAccess.cpp | 213 +++++++++++-- test/CodeGen/X86/x86-interleaved-access.ll | 328 ++++++--------------- .../InterleavedAccess/X86/interleavedLoad.ll | 63 +++- 3 files changed, 341 insertions(+), 263 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 2 months

[clang] branch master updated (cb7a513bac -> 4c51de1ebe)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository clang. from cb7a513bac Add an usage example of BreakBeforeBraces new 4c51de1ebe [clang-format] Fix documentation for AllowAllParametersOfDec [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: docs/ClangFormatStyleOptions.rst | 17 ++++++++++++----- include/clang/Format/Format.h | 17 ++++++++++++----- 2 files changed, 24 insertions(+), 10 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 2 months

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

Tcwg-commits September 2017