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from 3e3d015f524 AMDGPU: Fix multi-use shl/add combine
new 0207b2e66b7 [X86] Regenerate fold-load-unops.ll and add and avx512f com [...]
new 44ff104a6ca [X86] Add tests for full vector loads to fold-load-unops.ll.
new 986f1e6c444 [X86] Fix SQRTSS/SQRTSD/RCPSS/RCPSD intrinsics to use sse_l [...]
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lib/Target/X86/X86InstrAVX512.td | 7 ++--
lib/Target/X86/X86InstrSSE.td | 16 +++++---
test/CodeGen/X86/fold-load-unops.ll | 77 +++++++++++++++++++++++++++++++++----
3 files changed, 82 insertions(+), 18 deletions(-)
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from d024fd1406d [X86] Attempt to fix signed and unsigned comparison warning.
new 3e3d015f524 AMDGPU: Fix multi-use shl/add combine
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lib/Target/AMDGPU/SIISelLowering.cpp | 45 ++-----
lib/Target/AMDGPU/SIISelLowering.h | 1 +
test/CodeGen/AMDGPU/shl_add_ptr.ll | 242 +++++++++++++++++++++++++----------
3 files changed, 188 insertions(+), 100 deletions(-)
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from edd7e051d Implement P0550R2: Transformation Trait remove_cvref
new 928f2866e Put the status in the wrong column
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www/cxx2a_status.html | 2 +-
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from 7513814cb Two more papers from Albuquerque
new edd7e051d Implement P0550R2: Transformation Trait remove_cvref
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include/type_traits | 14 ++++++
.../meta.trans.other/remove_cvref.pass.cpp | 52 ++++++++++++++++++++++
www/cxx2a_status.html | 2 +-
3 files changed, 67 insertions(+), 1 deletion(-)
create mode 100644 test/std/utilities/meta/meta.trans/meta.trans.other/remove_cvre [...]
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discards d680a8325f ld: Create a new LOAD segment for text-only LOAD segment
new b7efc5daf4 ld: Create a new LOAD segment for text-only LOAD segment
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from 5f9380c9267 [X86] Use sse_load_f32/f64 in patterns for the memory forms [...]
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from 1cedae7c8d0 Fix some misc. -enable-var-scope violations
new fa371074cbd [X86] Split VRNDSCALE/VREDUCE/VGETMANT/VRANGE ISD nodes int [...]
new e6cdd204029 [X86] Use EVEX encoded VRNDSCALE instructions to implement [...]
new 5f9380c9267 [X86] Use sse_load_f32/f64 in patterns for the memory forms [...]
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lib/Target/X86/X86ISelLowering.cpp | 73 +++++++++++++++++++++++---
lib/Target/X86/X86ISelLowering.h | 10 ++--
lib/Target/X86/X86InstrAVX512.td | 89 ++++++++++++++++---------------
lib/Target/X86/X86InstrFragmentsSIMD.td | 31 ++++++++---
lib/Target/X86/X86InstrSSE.td | 55 +++++++++----------
lib/Target/X86/X86IntrinsicsInfo.h | 85 ++++++++++++++++--------------
test/CodeGen/X86/avx-intrinsics-x86.ll | 26 ++++++---
test/CodeGen/X86/avx-schedule.ll | 8 +--
test/CodeGen/X86/sse41-intrinsics-x86.ll | 68 ++++++++++++++++--------
test/CodeGen/X86/sse41-schedule.ll | 16 +++---
test/CodeGen/X86/vec_ss_load_fold.ll | 90 ++++++++++++++++++++++----------
11 files changed, 352 insertions(+), 199 deletions(-)
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from d8f8d0c326f AMDGPU: Select d16 loads into low component of register
new 1cedae7c8d0 Fix some misc. -enable-var-scope violations
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test/CodeGen/AArch64/arm64-atomic.ll | 10 ++---
.../AArch64/arm64-codegen-prepare-extload.ll | 16 +++----
test/CodeGen/AArch64/arm64-fp128.ll | 6 +--
test/CodeGen/AArch64/arm64-scvt.ll | 16 +++----
.../Transforms/CodeGenPrepare/AArch64/free-zext.ll | 24 +++++------
.../InstCombine/cast-call-combine-prof.ll | 8 ++--
test/Transforms/InstCombine/convergent.ll | 10 ++---
test/Transforms/InstCombine/ctpop.ll | 4 +-
test/Transforms/InstCombine/err-rep-cold.ll | 12 +++---
test/Transforms/InstCombine/getelementptr.ll | 4 +-
test/Transforms/InstCombine/intrinsics.ll | 8 ++--
test/Transforms/InstCombine/phi-select-constant.ll | 8 ++--
test/Transforms/InstCombine/pow-1.ll | 10 ++---
test/Transforms/InstCombine/printf-1.ll | 4 +-
test/Transforms/InstCombine/rem.ll | 6 +--
test/Transforms/InstCombine/select.ll | 2 +-
test/Transforms/InstCombine/select_meta.ll | 50 +++++++++++-----------
test/Transforms/JumpThreading/basic.ll | 36 ++++++++--------
test/Transforms/MemCpyOpt/memcpy.ll | 12 +++---
.../SimplifyCFG/PowerPC/cttz-ctlz-spec.ll | 4 +-
test/Transforms/SimplifyCFG/inline-asm-sink.ll | 8 ++--
test/Transforms/SimplifyCFG/sink-common-code.ll | 6 +--
.../SimplifyCFG/switch-on-const-select.ll | 10 ++---
23 files changed, 137 insertions(+), 137 deletions(-)
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unknown user pushed a change to branch users/hjl/pr22393
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discards 8689a6b7b5 ld: Create a new LOAD segment for text-only LOAD segment
discards 555eb3fe4e ld: Add TEXT_SEGMENT_ALIGN/TEXT_SEGMENT_{RELRO_}END
discards 95078c08fc ld: Add "-z textonly" option to ELF linker
discards 24c80251ad ld: Add ldlang_check_relro_region/update lang_find_relro_sections_1
discards 6748ad3962 ld: Add lang_size_relro_segment
discards c0745d6aa8 ld: Add fold_segment_align/fold_segment_relro_end/fold_segment_end
discards e30c6d38be ld: Update phase_enum/relro_enum and add seg_align_type
adds 0f99513f2a ld: Update phase_enum/relro_enum and add seg_align_type
adds d7475e036f ld: Add fold_segment_align/fold_segment_relro_end/fold_segment_end
adds cba6246d3a ld: Add lang_size_relro_segment
adds f4d18a5466 cl
adds ed1794ee7a ld: Add ldlang_check_relro_region/update lang_find_relro_sections_1
new 33e061633f ld: Add "-z textonly" option to ELF linker
new ec3d9464d3 ld: Add TEXT_SEGMENT_ALIGN/TEXT_SEGMENT_{RELRO_}END
new d680a8325f ld: Create a new LOAD segment for text-only LOAD segment
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ld/ChangeLog | 45 +++++++++++++++++++++++++++++++++++++++++++++
ld/ldlang.c | 27 ++++++++++++---------------
2 files changed, 57 insertions(+), 15 deletions(-)
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new cba6246d3a ld: Add lang_size_relro_segment
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ld/ChangeLog | 26 +++++++
ld/ldexp.c | 194 +++++++++++++++++++++++++++-----------------------
ld/ldlang.c | 229 ++++++++++++++++++++++++++++++++++++-----------------------
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