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from 04d07cd0d0 [analyzer] Document the issue hash debugging facility
new 5ae0ef1c7f Change // CHECK: shufflevector <8 x double> %0, <8 x double> [...]
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test/CodeGen/avx512f-builtins.c | 6 +++---
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from ed1794ee7a ld: Add ldlang_check_relro_region/update lang_find_relro_sections_1
new 2abc2bec4d x86-64/Intel: issue diagnostic for out of range displacement
new 1187cf29b1 x86/Intel: don't mistake riz/eiz as base register
new 897e603cb9 x86: {f,}xsave64 / {f,}xrstor64 / xsaveopt64 should not allo [...]
new b76bc5d54e x86: don't default variable shift count insns to 8-bit operand size
new 5be87c8fa7 PE: don't corrupt section flags when linking from ELF objects
new 6465780617 gas/ia64: fix testsuite failures
new 5b2b928e83 gas/arm64: don't emit stack pointer symbol table entries
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bfd/ChangeLog | 8 ++++++
bfd/coff-tic80.c | 2 ++
bfd/coffcode.h | 25 +++++++++++------
gas/ChangeLog | 37 ++++++++++++++++++++++++
gas/config/tc-aarch64.c | 11 ++++----
gas/config/tc-i386-intel.c | 53 ++++++++++++++++++-----------------
gas/config/tc-i386.c | 25 +++++++++++++----
gas/testsuite/gas/i386/intel.d | 3 ++
gas/testsuite/gas/i386/intel.s | 6 ++++
gas/testsuite/gas/i386/inval.l | 7 +++++
gas/testsuite/gas/i386/inval.s | 4 +++
gas/testsuite/gas/i386/x86-64-inval.l | 2 ++
gas/testsuite/gas/i386/x86-64-inval.s | 1 +
gas/testsuite/gas/ia64/group-1.d | 2 +-
gas/testsuite/gas/ia64/group-2.d | 19 +++++++------
gas/testsuite/gas/ia64/xdata.d | 2 +-
include/ChangeLog | 6 ++++
include/coff/pe.h | 5 +++-
opcodes/ChangeLog | 6 ++++
opcodes/i386-opc.tbl | 10 +++----
opcodes/i386-tbl.h | 10 +++----
21 files changed, 178 insertions(+), 66 deletions(-)
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from c614faa912 [x86][AVX512] Lowering shuffle i/f intrinsics to LLVM IR
new 04d07cd0d0 [analyzer] Document the issue hash debugging facility
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docs/analyzer/DebugChecks.rst | 13 +++++++++++++
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from 0e6bdca6ccb [PartialInliner] Inline vararg functions that forward varargs.
new 0b4ce86d631 [CodeExtractor] Add missing AllowVarArgs initialization.
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lib/Transforms/Utils/CodeExtractor.cpp | 5 +++--
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from 4aa7ca82da7 Test commit
new 0e6bdca6ccb [PartialInliner] Inline vararg functions that forward varargs.
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include/llvm/Transforms/Utils/Cloning.h | 8 ++-
include/llvm/Transforms/Utils/CodeExtractor.h | 17 +++--
lib/Transforms/IPO/PartialInlining.cpp | 12 +++-
lib/Transforms/Utils/CodeExtractor.cpp | 57 +++++++++++----
lib/Transforms/Utils/InlineFunction.cpp | 28 ++++++--
.../CodeExtractor/PartialInlineVarArg.ll | 83 ++++++++++++++++++++++
6 files changed, 176 insertions(+), 29 deletions(-)
create mode 100644 test/Transforms/CodeExtractor/PartialInlineVarArg.ll
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from 7ea14e0563d GCOV: remove typedef of coverage_t.
new 9deedf62e20 PR tree-optimization/78821 * gimple-ssa-store-merging.c ( [...]
new 4194a7134b6 [Documentation] Fix latency in pipeline description example
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gcc/ChangeLog | 17 +++++
gcc/doc/md.texi | 4 +-
gcc/gimple-ssa-store-merging.c | 122 +++++++++++++++++++++++++++-----
gcc/testsuite/ChangeLog | 3 +
gcc/testsuite/gcc.dg/store_merging_15.c | 56 +++++++++++++++
5 files changed, 182 insertions(+), 20 deletions(-)
create mode 100644 gcc/testsuite/gcc.dg/store_merging_15.c
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from 99449d9e381 [x86][AVX512] Lowering shuffle i/f intrinsics to LLVM IR
new 4aa7ca82da7 Test commit
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lib/Target/AArch64/SVEInstrFormats.td | 2 +-
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from 181fe5d2e cygwin: pread: Remove incorrect comment
new b1a388799 newlib/.../getreent.c: Allow to be provided by host and do so [...]
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newlib/configure.host | 4 ++--
newlib/libc/reent/getreent.c | 8 ++++++++
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from 950ddbd7c12 PR tree-optimization/82954 * gimple-ssa-store-merging.c [...]
new 457c9288ec3 GCOV: introduce global vector of functions
new d93799f5b09 GCOV: simplify usage of function_info::artificial.
new 67da56f6703 GCOV: introduce vector for function_info::counts.
new 98888fd6d90 GCOV: remove typedef for function_t
new 6f93d61e9f5 GCOV: remove typedef for arc_t
new 07f3f54d1e4 GCOV: remove typedef for block_t
new 7ea14e0563d GCOV: remove typedef of coverage_t.
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gcc/ChangeLog | 86 ++++++++++++++
gcc/gcov.c | 367 ++++++++++++++++++++++++++++------------------------------
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from d0b10f16275 [X86][SKX] Adding scheduling info of non-intrinsic + commut [...]
new 99449d9e381 [x86][AVX512] Lowering shuffle i/f intrinsics to LLVM IR
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include/llvm/IR/IntrinsicsX86.td | 47 -----
lib/IR/AutoUpgrade.cpp | 26 ++-
lib/Target/X86/X86IntrinsicsInfo.h | 16 --
test/CodeGen/X86/avx512-intrinsics-fast-isel.ll | 225 +++++++++++++++++++++
test/CodeGen/X86/avx512-intrinsics-upgrade.ll | 70 +++++++
test/CodeGen/X86/avx512-intrinsics.ll | 69 -------
test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll | 229 ++++++++++++++++++++++
test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll | 84 +++++++-
test/CodeGen/X86/avx512vl-intrinsics.ll | 82 --------
9 files changed, 629 insertions(+), 219 deletions(-)
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