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yvan.roux pushed a commit to branch ryanarn/reduced_parallel
in repository toolchain/abe.
The following commit(s) were added to refs/heads/ryanarn/reduced_parallel by this push:
new 5ac561c Reduce one level of verbosity and fix debug option
5ac561c is described below
commit 5ac561ceaa227597544c0fb08aa6ae9c5ba770ad
Author: Yvan Roux <yvan.roux(a)linaro.org>
Date: Tue Aug 18 21:53:18 2015 +0200
Reduce one level of verbosity and fix debug option
Change-Id: Iaad997597dc7c8f9ad3811f30429dd76d7f35a13
---
jenkins.sh | 2 +-
lib/make.sh | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/jenkins.sh b/jenkins.sh
index e7aee89..f786528 100755
--- a/jenkins.sh
+++ b/jenkins.sh
@@ -343,7 +343,7 @@ fi
(cd $user_snapshots/gcc.git; git fetch origin '+refs/changes/*:refs/remotes/gerrit [...]
# Turn on extra verbose dejagnu logging
-export RUNTESTFLAGS="-v -v -v -v -d"
+export RUNTESTFLAGS="-v -v -v --debug"
# Now we build the cross compiler, for a native compiler this becomes
# the stage2 bootstrap build.
diff --git a/lib/make.sh b/lib/make.sh
index 7cf2885..eda3a7b 100755
--- a/lib/make.sh
+++ b/lib/make.sh
@@ -731,7 +731,7 @@ make_check()
fi
if test x"${override_runtestflags}" != x; then
- local make_flags="${make_flags} RUNTESTFLAGS=\"${override_runtestflags} -v [...]
+ local make_flags="${make_flags} RUNTESTFLAGS=\"${override_runtestflags} -v [...]
fi
if test x"${parallel}" = x"yes"; then
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from bf62f7a PR c++/67216 * testsuite/tr1/2_general_utilities/shared_ptr [...]
new 1abbc4f gcc/ PR rtl-optimization/67218 * simplify-rtx.c (exact_int_ [...]
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Summary of changes:
gcc/ChangeLog | 6 ++++
gcc/simplify-rtx.c | 38 ++++++++++++++++------
gcc/testsuite/ChangeLog | 13 ++++++++
gcc/testsuite/gcc.c-torture/execute/ieee/pr67218.c | 15 +++++++++
.../gcc.target/aarch64/fcvt_int_float_double1.c | 10 ++++++
.../gcc.target/aarch64/fcvt_int_float_double2.c | 11 +++++++
.../gcc.target/aarch64/fcvt_int_float_double3.c | 10 ++++++
.../gcc.target/aarch64/fcvt_int_float_double4.c | 11 +++++++
.../gcc.target/aarch64/fcvt_uint_float_double1.c | 10 ++++++
.../gcc.target/aarch64/fcvt_uint_float_double2.c | 11 +++++++
.../gcc.target/aarch64/fcvt_uint_float_double3.c | 10 ++++++
.../gcc.target/aarch64/fcvt_uint_float_double4.c | 11 +++++++
12 files changed, 146 insertions(+), 10 deletions(-)
create mode 100644 gcc/testsuite/gcc.c-torture/execute/ieee/pr67218.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/fcvt_int_float_double1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/fcvt_int_float_double2.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/fcvt_int_float_double3.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/fcvt_int_float_double4.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/fcvt_uint_float_double1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/fcvt_uint_float_double2.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/fcvt_uint_float_double3.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/fcvt_uint_float_double4.c
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from 6e5ffd4 * gcc.target/aarch64/atomic-comp-swap-release-acquire.c: Adj [...]
new 1dae3b7 PR libstdc++/67066 * doc/xml/manual/configure.xml (manual.i [...]
new 5ed72ca * include/bits/ptr_traits.h: Include <bits/move.h> for addressof.
new bf62f7a PR c++/67216 * testsuite/tr1/2_general_utilities/shared_ptr [...]
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libstdc++-v3/ChangeLog | 18 ++++++++++++++++++
libstdc++-v3/doc/html/manual/concept_checking.html | 5 +++--
libstdc++-v3/doc/html/manual/configure.html | 8 +++++---
libstdc++-v3/doc/html/manual/status.html | 2 +-
libstdc++-v3/doc/xml/manual/configure.xml | 8 +++++---
libstdc++-v3/doc/xml/manual/diagnostics.xml | 5 +++--
libstdc++-v3/include/bits/ptr_traits.h | 2 +-
libstdc++-v3/include/bits/stl_deque.h | 2 ++
libstdc++-v3/include/bits/stl_stack.h | 2 ++
libstdc++-v3/include/bits/stl_vector.h | 2 ++
.../shared_ptr/observers/bool_conv.cc | 4 ++--
11 files changed, 44 insertions(+), 14 deletions(-)
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unknown user pushed a commit to branch aoliva/pr64164
in repository gcc.
commit 311424833d5b7060c8381a6460030b2f38b30158
Author: Alexandre Oliva <aoliva(a)redhat.com>
Date: Tue Aug 18 01:20:14 2015 -0300
incremental fixes for m68k and armeb
---
gcc/cfgexpand.c | 44 +++++++++++++++++++++++++++++++++----------
gcc/cfgexpand.h | 2 +-
gcc/function.c | 50 +++++++++++++++++++++++++++++++++++++++----------
gcc/tree-ssa-coalesce.c | 4 ++--
4 files changed, 77 insertions(+), 23 deletions(-)
diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c
index 0bc20f6..d567a87 100644
--- a/gcc/cfgexpand.c
+++ b/gcc/cfgexpand.c
@@ -172,17 +172,23 @@ leader_merge (tree cur, tree next)
return cur;
}
-/* Return true if VAR is a PARM_DECL or a RESULT_DECL of type BLKmode.
+/* Return true if VAR is a PARM_DECL or a RESULT_DECL that ought to be
+ assigned to a stack slot. We can't have expand_one_ssa_partition
+ choose their address: the pseudo holding the address would be set
+ up too late for assign_params to copy the parameter if needed.
+
Such parameters are likely passed as a pointer to the value, rather
than as a value, and so we must not coalesce them, nor allocate
stack space for them before determining the calling conventions for
- them. For their SSA_NAMEs, expand_one_ssa_partition emits RTL as
- MEMs with pc_rtx as the address, and then it replaces the pc_rtx
- with NULL so as to make sure the MEM is not used before it is
- adjusted in assign_parm_setup_reg. */
+ them.
+
+ For their SSA_NAMEs, expand_one_ssa_partition emits RTL as MEMs
+ with pc_rtx as the address, and then it replaces the pc_rtx with
+ NULL so as to make sure the MEM is not used before it is adjusted
+ in assign_parm_setup_reg. */
bool
-parm_maybe_byref_p (tree var)
+parm_in_stack_slot_p (tree var)
{
if (!var || VAR_P (var))
return false;
@@ -190,7 +196,7 @@ parm_maybe_byref_p (tree var)
gcc_assert (TREE_CODE (var) == PARM_DECL
|| TREE_CODE (var) == RESULT_DECL);
- return TYPE_MODE (TREE_TYPE (var)) == BLKmode;
+ return !use_register_for_decl (var);
}
/* Return the partition of the default SSA_DEF for decl VAR. */
@@ -1343,17 +1349,35 @@ expand_one_ssa_partition (tree var)
if (!use_register_for_decl (var))
{
- if (parm_maybe_byref_p (SSA_NAME_VAR (var))
- && ssa_default_def_partition (SSA_NAME_VAR (var)) == part)
+ /* We can't risk having the parm assigned to a MEM location
+ whose address references a pseudo, for the pseudo will only
+ be set up after arguments are copied to the stack slot.
+
+ If the parm doesn't have a default def (e.g., because its
+ incoming value is unused), then we want to let assign_params
+ do the allocation, too. In this case we want to make sure
+ SSA_NAMEs associated with the parm don't get assigned to more
+ than one partition, lest we'd create two unassigned stac
+ slots for the same parm, thus the assert at the end of the
+ block. */
+ if (parm_in_stack_slot_p (SSA_NAME_VAR (var))
+ && (ssa_default_def_partition (SSA_NAME_VAR (var)) == part
+ || !ssa_default_def (cfun, SSA_NAME_VAR (var))))
{
expand_one_stack_var_at (var, pc_rtx, 0, 0);
rtx x = SA.partition_to_pseudo[part];
gcc_assert (GET_CODE (x) == MEM);
- gcc_assert (GET_MODE (x) == BLKmode);
gcc_assert (XEXP (x, 0) == pc_rtx);
/* Reset the address, so that any attempt to use it will
ICE. It will be adjusted in assign_parm_setup_reg. */
XEXP (x, 0) = NULL_RTX;
+ /* If the RTL associated with the parm is not what we have
+ just created, the parm has been split over multiple
+ partitions. In order for this to work, we must have a
+ default def for the parm, otherwise assign_params won't
+ know what to do. */
+ gcc_assert (DECL_RTL_IF_SET (SSA_NAME_VAR (var)) == x
+ || ssa_default_def (cfun, SSA_NAME_VAR (var)));
}
else if (defer_stack_allocation (var, true))
add_stack_var (var);
diff --git a/gcc/cfgexpand.h b/gcc/cfgexpand.h
index 987cf356..d168672 100644
--- a/gcc/cfgexpand.h
+++ b/gcc/cfgexpand.h
@@ -22,7 +22,7 @@ along with GCC; see the file COPYING3. If not see
extern tree gimple_assign_rhs_to_tree (gimple);
extern HOST_WIDE_INT estimated_stack_frame_size (struct cgraph_node *);
-extern bool parm_maybe_byref_p (tree);
+extern bool parm_in_stack_slot_p (tree);
extern rtx get_rtl_for_parm_ssa_default_def (tree var);
diff --git a/gcc/function.c b/gcc/function.c
index 715c19f..147dc33 100644
--- a/gcc/function.c
+++ b/gcc/function.c
@@ -2934,6 +2934,21 @@ assign_parm_setup_block_p (struct assign_parm_data_one *data)
return false;
}
+/* Return true if FROM_EXPAND is a MEM with an address to be filled in
+ by assign_params. This should be the case if, and only if,
+ parm_in_stack_slot_p holds for the parm DECL that expanded to
+ FROM_EXPAND, so we check that, too. */
+
+static bool
+parm_in_unassigned_mem_p (tree decl, rtx from_expand)
+{
+ bool result = MEM_P (from_expand) && !XEXP (from_expand, 0);
+
+ gcc_assert (result == parm_in_stack_slot_p (decl));
+
+ return result;
+}
+
/* A subroutine of assign_parms. Arrange for the parameter to be
present and valid in DATA->STACK_RTL. */
@@ -2956,8 +2971,7 @@ assign_parm_setup_block (struct assign_parm_data_all *all,
{
DECL_ALIGN (parm) = MAX (DECL_ALIGN (parm), BITS_PER_WORD);
rtx from_expand = rtl_for_parm (all, parm);
- if (from_expand && (!parm_maybe_byref_p (parm)
- || XEXP (from_expand, 0) != NULL_RTX))
+ if (from_expand && !parm_in_unassigned_mem_p (parm, from_expand))
stack_parm = copy_rtx (from_expand);
else
{
@@ -2968,8 +2982,7 @@ assign_parm_setup_block (struct assign_parm_data_all *all,
if (from_expand)
{
gcc_assert (GET_CODE (stack_parm) == MEM);
- gcc_assert (GET_CODE (from_expand) == MEM);
- gcc_assert (XEXP (from_expand, 0) == NULL_RTX);
+ gcc_assert (parm_in_unassigned_mem_p (parm, from_expand));
XEXP (from_expand, 0) = XEXP (stack_parm, 0);
PUT_MODE (from_expand, GET_MODE (stack_parm));
stack_parm = copy_rtx (from_expand);
@@ -3017,6 +3030,11 @@ assign_parm_setup_block (struct assign_parm_data_all *all,
else if (size == 0)
;
+ /* MEM may be a REG if coalescing assigns the param's partition
+ to a pseudo. */
+ else if (REG_P (mem))
+ emit_move_insn (mem, entry_parm);
+
/* If SIZE is that of a mode no bigger than a word, just use
that mode's store operation. */
else if (size <= UNITS_PER_WORD)
@@ -3121,7 +3139,7 @@ assign_parm_setup_reg (struct assign_parm_data_all *all, tree parm,
if (GET_MODE (parmreg) != promoted_nominal_mode)
parmreg = gen_lowpart (promoted_nominal_mode, parmreg);
}
- else if (!from_expand || parm_maybe_byref_p (parm))
+ else if (!from_expand || parm_in_unassigned_mem_p (parm, from_expand))
{
parmreg = gen_reg_rtx (promoted_nominal_mode);
if (!DECL_ARTIFICIAL (parm))
@@ -3349,7 +3367,7 @@ assign_parm_setup_reg (struct assign_parm_data_all *all, tree parm,
did_conversion = true;
}
else if (GET_MODE (parmreg) == BLKmode)
- gcc_assert (parm_maybe_byref_p (parm));
+ gcc_assert (parm_in_stack_slot_p (parm));
else
emit_move_insn (parmreg, src);
@@ -3455,12 +3473,15 @@ assign_parm_setup_stack (struct assign_parm_data_all *all, [...]
if (data->entry_parm != data->stack_parm)
{
rtx src, dest;
+ rtx from_expand = NULL_RTX;
if (data->stack_parm == 0)
{
- rtx x = data->stack_parm = rtl_for_parm (all, parm);
- if (x)
- gcc_assert (GET_MODE (x) == GET_MODE (data->entry_parm));
+ from_expand = rtl_for_parm (all, parm);
+ if (from_expand)
+ gcc_assert (GET_MODE (from_expand) == GET_MODE (data->entry_parm));
+ if (from_expand && !parm_in_unassigned_mem_p (parm, from_expand))
+ data->stack_parm = from_expand;
}
if (data->stack_parm == 0)
@@ -3472,7 +3493,16 @@ assign_parm_setup_stack (struct assign_parm_data_all *all, t [...]
= assign_stack_local (GET_MODE (data->entry_parm),
GET_MODE_SIZE (GET_MODE (data->entry_parm)),
align);
- set_mem_attributes (data->stack_parm, parm, 1);
+ if (!from_expand)
+ set_mem_attributes (data->stack_parm, parm, 1);
+ else
+ {
+ gcc_assert (GET_CODE (data->stack_parm) == MEM);
+ gcc_assert (parm_in_unassigned_mem_p (parm, from_expand));
+ XEXP (from_expand, 0) = XEXP (data->stack_parm, 0);
+ PUT_MODE (from_expand, GET_MODE (data->stack_parm));
+ data->stack_parm = copy_rtx (from_expand);
+ }
}
dest = validize_mem (copy_rtx (data->stack_parm));
diff --git a/gcc/tree-ssa-coalesce.c b/gcc/tree-ssa-coalesce.c
index 08ce72c..6468012 100644
--- a/gcc/tree-ssa-coalesce.c
+++ b/gcc/tree-ssa-coalesce.c
@@ -1386,8 +1386,8 @@ gimple_can_coalesce_p (tree name1, tree name2)
because it may be passed by reference. */
return ((!var1 || VAR_P (var1)) && (!var2 || VAR_P (var2)))
|| (/* The case var1 == var2 is already covered above. */
- !parm_maybe_byref_p (var1)
- && !parm_maybe_byref_p (var2)
+ !parm_in_stack_slot_p (var1)
+ && !parm_in_stack_slot_p (var2)
&& promote_ssa_mode (name1, NULL) == promote_ssa_mode (name2, NULL));
}
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unknown user pushed a change to branch aoliva/pr64164
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discards 78360e9 incremental fixes for m68k and armeb
new 3114248 incremental fixes for m68k and armeb
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gcc/cfgexpand.c | 20 ++++++++++++++++++--
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from a03a71a c-family/ 2015-08-18 Paolo Carlini <paolo.carlini(a)oracle.com>
new 6e5ffd4 * gcc.target/aarch64/atomic-comp-swap-release-acquire.c: Adj [...]
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gcc/testsuite/ChangeLog | 20 ++++++++++++++++++++
.../aarch64/atomic-comp-swap-release-acquire.c | 2 +-
gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c | 2 +-
gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c | 2 +-
gcc/testsuite/gcc.target/aarch64/atomic-op-char.c | 2 +-
gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c | 2 +-
gcc/testsuite/gcc.target/aarch64/atomic-op-imm.c | 2 +-
gcc/testsuite/gcc.target/aarch64/atomic-op-int.c | 2 +-
gcc/testsuite/gcc.target/aarch64/atomic-op-long.c | 2 +-
gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c | 2 +-
gcc/testsuite/gcc.target/aarch64/atomic-op-release.c | 2 +-
gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c | 2 +-
gcc/testsuite/gcc.target/aarch64/atomic-op-short.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sync-comp-swap.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sync-op-acquire.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sync-op-full.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sync-op-release.c | 2 +-
17 files changed, 36 insertions(+), 16 deletions(-)
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unknown user pushed a change to branch gcc-4_9-branch
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from 1aa0574 PR rtl-optimization/67028 * combine.c (simplify_comparison) [...]
new 4cc0b6a PR c++/58063 * tree.c (bot_manip): Remap SAVE_EXPR.
new b4cde57 PR c++/66957 * search.c (protected_accessible_p): Revert fi [...]
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gcc/cp/ChangeLog | 8 ++++++++
gcc/cp/search.c | 2 +-
gcc/cp/tree.c | 23 +++++++++++++++++++++++
gcc/testsuite/g++.dg/conversion/access1.C | 2 +-
gcc/testsuite/g++.dg/inherit/access9.C | 14 ++++++++++++++
gcc/testsuite/g++.dg/overload/defarg10.C | 28 ++++++++++++++++++++++++++++
6 files changed, 75 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/g++.dg/inherit/access9.C
create mode 100644 gcc/testsuite/g++.dg/overload/defarg10.C
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from 35ed5ce [MIPS] Fix register renaming in the interrupt handlers.
new 6189000 PR middle-end/67222 * gimple-low.c (lower_stmt): Don't lowe [...]
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gcc/ChangeLog | 10 ++++++++++
gcc/gimple-low.c | 3 ++-
gcc/testsuite/ChangeLog | 5 +++++
gcc/testsuite/gcc.dg/torture/pr67222.c | 19 +++++++++++++++++++
gcc/tree-ssa-alias.c | 6 +++---
5 files changed, 39 insertions(+), 4 deletions(-)
create mode 100644 gcc/testsuite/gcc.dg/torture/pr67222.c
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new 35ed5ce [MIPS] Fix register renaming in the interrupt handlers.
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gcc/ChangeLog | 8 ++++++
gcc/config/mips/mips-protos.h | 1 +
gcc/config/mips/mips.c | 30 ++++++++++++++++++++++
gcc/config/mips/mips.h | 3 +++
gcc/testsuite/ChangeLog | 4 +++
.../gcc.target/mips/interrupt_handler-bug-1.c | 11 ++++++++
6 files changed, 57 insertions(+)
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