v1/v2: There is only the first patch: RISC-V: Enable cbo.clean/flush in usermode, which mainly removes the enabling of cbo.inval in user mode.
v3: Add the functionality of Expose Zicbom and selftests for Zicbom.
v4: Modify the order of macros, The test_no_cbo_inval function is added separately.
v5: 1. Modify the order of RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE in hwprobe.rst 2. "TEST_NO_ZICBOINVAL" -> "TEST_NO_CBO_INVAL"
Yunhui Cui (3): RISC-V: Enable cbo.clean/flush in usermode RISC-V: hwprobe: Expose Zicbom extension and its block size RISC-V: selftests: Add TEST_ZICBOM into CBO tests
Documentation/arch/riscv/hwprobe.rst | 6 ++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 2 + arch/riscv/kernel/cpufeature.c | 8 +++ arch/riscv/kernel/sys_hwprobe.c | 6 ++ tools/testing/selftests/riscv/hwprobe/cbo.c | 66 +++++++++++++++++---- 6 files changed, 78 insertions(+), 12 deletions(-)
Enabling cbo.clean and cbo.flush in user mode makes it more convenient to manage the cache state and achieve better performance.
Reviewed-by: Andrew Jones ajones@ventanamicro.com Signed-off-by: Yunhui Cui cuiyunhui@bytedance.com --- arch/riscv/kernel/cpufeature.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c0916ed318c2..60d180b98f52 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -30,6 +30,7 @@ #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
static bool any_cpu_has_zicboz; +static bool any_cpu_has_zicbom;
unsigned long elf_hwcap __read_mostly;
@@ -87,6 +88,8 @@ static int riscv_ext_zicbom_validate(const struct riscv_isa_ext_data *data, pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n"); return -EINVAL; } + + any_cpu_has_zicbom = true; return 0; }
@@ -944,6 +947,11 @@ void __init riscv_user_isa_enable(void) current->thread.envcfg |= ENVCFG_CBZE; else if (any_cpu_has_zicboz) pr_warn("Zicboz disabled as it is unavailable on some harts\n"); + + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOM)) + current->thread.envcfg |= ENVCFG_CBCFE; + else if (any_cpu_has_zicbom) + pr_warn("Zicbom disabled as it is unavailable on some harts\n"); }
#ifdef CONFIG_RISCV_ALTERNATIVE
Expose Zicbom through hwprobe and also provide a key to extract its respective block size.
Signed-off-by: Yunhui Cui cuiyunhui@bytedance.com --- Documentation/arch/riscv/hwprobe.rst | 6 ++++++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_hwprobe.c | 6 ++++++ 4 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index 955fbcd19ce9..21323811a206 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -242,6 +242,9 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as defined in version 1.0 of the RISC-V Pointer Masking extensions.
+ * :c:macro:`RISCV_HWPROBE_EXT_ZICBOM`: The Zicbom extension is supported, as + ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was mistakenly classified as a bitmask rather than a value. @@ -293,3 +296,6 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`: Misaligned vector accesses are not supported at all and will generate a misaligned address fault. + +* :c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`: An unsigned int which + represents the size of the Zicbom block in bytes. diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h index 1ce1df6d0ff3..89379f9a2e6e 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -8,7 +8,7 @@
#include <uapi/asm/hwprobe.h>
-#define RISCV_HWPROBE_MAX_KEY 10 +#define RISCV_HWPROBE_MAX_KEY 11
static inline bool riscv_hwprobe_key_is_valid(__s64 key) { diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 3af142b99f77..b15c0bd83ef2 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -73,6 +73,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47) #define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48) #define RISCV_HWPROBE_EXT_SUPM (1ULL << 49) +#define RISCV_HWPROBE_EXT_ZICBOM (1ULL << 50) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) @@ -94,6 +95,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW 2 #define RISCV_HWPROBE_MISALIGNED_VECTOR_FAST 3 #define RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED 4 +#define RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE 11 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
/* Flags */ diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index cb93adfffc48..04150e62f998 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -106,6 +106,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZCA); EXT_KEY(ZCB); EXT_KEY(ZCMOP); + EXT_KEY(ZICBOM); EXT_KEY(ZICBOZ); EXT_KEY(ZICOND); EXT_KEY(ZIHINTNTL); @@ -278,6 +279,11 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOZ)) pair->value = riscv_cboz_block_size; break; + case RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE: + pair->value = 0; + if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOM)) + pair->value = riscv_cbom_block_size; + break; case RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS: pair->value = user_max_virt_addr(); break;
On Wed, Jan 15, 2025 at 10:40:23AM +0800, Yunhui Cui wrote:
Expose Zicbom through hwprobe and also provide a key to extract its respective block size.
Signed-off-by: Yunhui Cui cuiyunhui@bytedance.com
Documentation/arch/riscv/hwprobe.rst | 6 ++++++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_hwprobe.c | 6 ++++++ 4 files changed, 15 insertions(+), 1 deletion(-)
Reviewed-by: Andrew Jones ajones@ventanamicro.com
On 2025-01-14 8:40 PM, Yunhui Cui wrote:
Expose Zicbom through hwprobe and also provide a key to extract its respective block size.
Signed-off-by: Yunhui Cui cuiyunhui@bytedance.com
Documentation/arch/riscv/hwprobe.rst | 6 ++++++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_hwprobe.c | 6 ++++++ 4 files changed, 15 insertions(+), 1 deletion(-)
Reviewed-by: Samuel Holland samuel.holland@sifive.com
Hi Yunhui,
kernel test robot noticed the following build warnings:
[auto build test WARNING on shuah-kselftest/next] [also build test WARNING on shuah-kselftest/fixes linus/master v6.13 next-20250121] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Yunhui-Cui/RISC-V-Enable-cbo-... base: https://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest.git next patch link: https://lore.kernel.org/r/20250115024024.84365-3-cuiyunhui%40bytedance.com patch subject: [PATCH v5 2/3] RISC-V: hwprobe: Expose Zicbom extension and its block size config: riscv-randconfig-r133-20250121 (https://download.01.org/0day-ci/archive/20250121/202501212220.5GHTtuF7-lkp@i...) compiler: clang version 20.0.0git (https://github.com/llvm/llvm-project c23f2417dc5f6dc371afb07af5627ec2a9d373a0) reproduce: (https://download.01.org/0day-ci/archive/20250121/202501212220.5GHTtuF7-lkp@i...)
If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot lkp@intel.com | Closes: https://lore.kernel.org/oe-kbuild-all/202501212220.5GHTtuF7-lkp@intel.com/
All warnings (new ones prefixed by >>):
arch/riscv/kernel/sys_hwprobe.c:284:30: warning: implicit conversion from 'unsigned long long' to 'unsigned long' changes value from 1125899906842624 to 0 [-Wconstant-conversion]
284 | if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOM)) | ~~~~~~~~~~~~~~~~ ^~~~~~~~~~~~~~~~~~~~~~~~ arch/riscv/include/uapi/asm/hwprobe.h:76:41: note: expanded from macro 'RISCV_HWPROBE_EXT_ZICBOM' 76 | #define RISCV_HWPROBE_EXT_ZICBOM (1ULL << 50) | ~~~~~^~~~~ 1 warning generated.
vim +284 arch/riscv/kernel/sys_hwprobe.c
244 245 static void hwprobe_one_pair(struct riscv_hwprobe *pair, 246 const struct cpumask *cpus) 247 { 248 switch (pair->key) { 249 case RISCV_HWPROBE_KEY_MVENDORID: 250 case RISCV_HWPROBE_KEY_MARCHID: 251 case RISCV_HWPROBE_KEY_MIMPID: 252 hwprobe_arch_id(pair, cpus); 253 break; 254 /* 255 * The kernel already assumes that the base single-letter ISA 256 * extensions are supported on all harts, and only supports the 257 * IMA base, so just cheat a bit here and tell that to 258 * userspace. 259 */ 260 case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: 261 pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA; 262 break; 263 264 case RISCV_HWPROBE_KEY_IMA_EXT_0: 265 hwprobe_isa_ext0(pair, cpus); 266 break; 267 268 case RISCV_HWPROBE_KEY_CPUPERF_0: 269 case RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF: 270 pair->value = hwprobe_misaligned(cpus); 271 break; 272 273 case RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF: 274 pair->value = hwprobe_vec_misaligned(cpus); 275 break; 276 277 case RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE: 278 pair->value = 0; 279 if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOZ)) 280 pair->value = riscv_cboz_block_size; 281 break; 282 case RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE: 283 pair->value = 0;
284 if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOM))
285 pair->value = riscv_cbom_block_size; 286 break; 287 case RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS: 288 pair->value = user_max_virt_addr(); 289 break; 290 291 case RISCV_HWPROBE_KEY_TIME_CSR_FREQ: 292 pair->value = riscv_timebase; 293 break; 294 295 /* 296 * For forward compatibility, unknown keys don't fail the whole 297 * call, but get their element key set to -1 and value set to 0 298 * indicating they're unrecognized. 299 */ 300 default: 301 pair->key = -1; 302 pair->value = 0; 303 break; 304 } 305 } 306
On Wed, Jan 15, 2025 at 10:40:23AM +0800, Yunhui Cui wrote:
Expose Zicbom through hwprobe and also provide a key to extract its respective block size.
Signed-off-by: Yunhui Cui cuiyunhui@bytedance.com
Documentation/arch/riscv/hwprobe.rst | 6 ++++++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_hwprobe.c | 6 ++++++ 4 files changed, 15 insertions(+), 1 deletion(-)
As the bot points out, we need to add the following to this patch.
Thanks, drew
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index cb93adfffc48..6b5b24b399c3 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -160,7 +160,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, pair->value &= ~missing; }
-static bool hwprobe_ext0_has(const struct cpumask *cpus, unsigned long ext) +static bool hwprobe_ext0_has(const struct cpumask *cpus, u64 ext) { struct riscv_hwprobe pair;
Hi drew,
On Tue, Jan 21, 2025 at 11:29 PM Andrew Jones ajones@ventanamicro.com wrote:
On Wed, Jan 15, 2025 at 10:40:23AM +0800, Yunhui Cui wrote:
Expose Zicbom through hwprobe and also provide a key to extract its respective block size.
Signed-off-by: Yunhui Cui cuiyunhui@bytedance.com
Documentation/arch/riscv/hwprobe.rst | 6 ++++++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_hwprobe.c | 6 ++++++ 4 files changed, 15 insertions(+), 1 deletion(-)
As the bot points out, we need to add the following to this patch.
OK, I'll update a version and change hwprobe_ext0_has's second param to u64.
Thanks, drew
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index cb93adfffc48..6b5b24b399c3 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -160,7 +160,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, pair->value &= ~missing; }
-static bool hwprobe_ext0_has(const struct cpumask *cpus, unsigned long ext) +static bool hwprobe_ext0_has(const struct cpumask *cpus, u64 ext) { struct riscv_hwprobe pair;
Thanks, Yunhui
Add test for Zicbom and its block size into CBO tests, when Zicbom is present, test that cbo.clean/flush may be issued and works. As the software can't verify the clean/flush functions, we just judged that cbo.clean/flush isn't executed illegally.
Reviewed-by: Andrew Jones ajones@ventanamicro.com Reviewed-by: Samuel Holland samuel.holland@sifive.com Signed-off-by: Yunhui Cui cuiyunhui@bytedance.com --- tools/testing/selftests/riscv/hwprobe/cbo.c | 66 +++++++++++++++++---- 1 file changed, 55 insertions(+), 11 deletions(-)
diff --git a/tools/testing/selftests/riscv/hwprobe/cbo.c b/tools/testing/selftests/riscv/hwprobe/cbo.c index a40541bb7c7d..5e96ef785d0d 100644 --- a/tools/testing/selftests/riscv/hwprobe/cbo.c +++ b/tools/testing/selftests/riscv/hwprobe/cbo.c @@ -50,6 +50,14 @@ static void cbo_clean(char *base) { cbo_insn(base, 1); } static void cbo_flush(char *base) { cbo_insn(base, 2); } static void cbo_zero(char *base) { cbo_insn(base, 4); }
+static void test_no_cbo_inval(void *arg) +{ + ksft_print_msg("Testing cbo.inval instruction remain privileged\n"); + illegal_insn = false; + cbo_inval(&mem[0]); + ksft_test_result(illegal_insn, "No cbo.inval\n"); +} + static void test_no_zicbom(void *arg) { ksft_print_msg("Testing Zicbom instructions remain privileged\n"); @@ -61,10 +69,6 @@ static void test_no_zicbom(void *arg) illegal_insn = false; cbo_flush(&mem[0]); ksft_test_result(illegal_insn, "No cbo.flush\n"); - - illegal_insn = false; - cbo_inval(&mem[0]); - ksft_test_result(illegal_insn, "No cbo.inval\n"); }
static void test_no_zicboz(void *arg) @@ -81,6 +85,30 @@ static bool is_power_of_2(__u64 n) return n != 0 && (n & (n - 1)) == 0; }
+static void test_zicbom(void *arg) +{ + struct riscv_hwprobe pair = { + .key = RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE, + }; + cpu_set_t *cpus = (cpu_set_t *)arg; + __u64 block_size; + long rc; + + rc = riscv_hwprobe(&pair, 1, sizeof(cpu_set_t), (unsigned long *)cpus, 0); + block_size = pair.value; + ksft_test_result(rc == 0 && pair.key == RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE && + is_power_of_2(block_size), "Zicbom block size\n"); + ksft_print_msg("Zicbom block size: %llu\n", block_size); + + illegal_insn = false; + cbo_clean(&mem[block_size]); + ksft_test_result(!illegal_insn, "cbo.clean\n"); + + illegal_insn = false; + cbo_flush(&mem[block_size]); + ksft_test_result(!illegal_insn, "cbo.flush\n"); +} + static void test_zicboz(void *arg) { struct riscv_hwprobe pair = { @@ -129,7 +157,7 @@ static void test_zicboz(void *arg) ksft_test_result_pass("cbo.zero check\n"); }
-static void check_no_zicboz_cpus(cpu_set_t *cpus) +static void check_no_zicbo_cpus(cpu_set_t *cpus, __u64 cbo) { struct riscv_hwprobe pair = { .key = RISCV_HWPROBE_KEY_IMA_EXT_0, @@ -137,6 +165,7 @@ static void check_no_zicboz_cpus(cpu_set_t *cpus) cpu_set_t one_cpu; int i = 0, c = 0; long rc; + char *cbostr;
while (i++ < CPU_COUNT(cpus)) { while (!CPU_ISSET(c, cpus)) @@ -148,10 +177,13 @@ static void check_no_zicboz_cpus(cpu_set_t *cpus) rc = riscv_hwprobe(&pair, 1, sizeof(cpu_set_t), (unsigned long *)&one_cpu, 0); assert(rc == 0 && pair.key == RISCV_HWPROBE_KEY_IMA_EXT_0);
- if (pair.value & RISCV_HWPROBE_EXT_ZICBOZ) - ksft_exit_fail_msg("Zicboz is only present on a subset of harts.\n" - "Use taskset to select a set of harts where Zicboz\n" - "presence (present or not) is consistent for each hart\n"); + cbostr = cbo == RISCV_HWPROBE_EXT_ZICBOZ ? "Zicboz" : "Zicbom"; + + if (pair.value & cbo) + ksft_exit_fail_msg("%s is only present on a subset of harts.\n" + "Use taskset to select a set of harts where %s\n" + "presence (present or not) is consistent for each hart\n", + cbostr, cbostr); ++c; } } @@ -159,7 +191,9 @@ static void check_no_zicboz_cpus(cpu_set_t *cpus) enum { TEST_ZICBOZ, TEST_NO_ZICBOZ, + TEST_ZICBOM, TEST_NO_ZICBOM, + TEST_NO_CBO_INVAL, };
static struct test_info { @@ -169,7 +203,9 @@ static struct test_info { } tests[] = { [TEST_ZICBOZ] = { .nr_tests = 3, test_zicboz }, [TEST_NO_ZICBOZ] = { .nr_tests = 1, test_no_zicboz }, - [TEST_NO_ZICBOM] = { .nr_tests = 3, test_no_zicbom }, + [TEST_ZICBOM] = { .nr_tests = 3, test_zicbom }, + [TEST_NO_ZICBOM] = { .nr_tests = 2, test_no_zicbom }, + [TEST_NO_CBO_INVAL] = { .nr_tests = 1, test_no_cbo_inval }, };
int main(int argc, char **argv) @@ -189,6 +225,7 @@ int main(int argc, char **argv) assert(rc == 0); tests[TEST_NO_ZICBOZ].enabled = true; tests[TEST_NO_ZICBOM].enabled = true; + tests[TEST_NO_CBO_INVAL].enabled = true; }
rc = sched_getaffinity(0, sizeof(cpu_set_t), &cpus); @@ -206,7 +243,14 @@ int main(int argc, char **argv) tests[TEST_ZICBOZ].enabled = true; tests[TEST_NO_ZICBOZ].enabled = false; } else { - check_no_zicboz_cpus(&cpus); + check_no_zicbo_cpus(&cpus, RISCV_HWPROBE_EXT_ZICBOZ); + } + + if (pair.value & RISCV_HWPROBE_EXT_ZICBOM) { + tests[TEST_ZICBOM].enabled = true; + tests[TEST_NO_ZICBOM].enabled = false; + } else { + check_no_zicbo_cpus(&cpus, RISCV_HWPROBE_EXT_ZICBOM); }
for (i = 0; i < ARRAY_SIZE(tests); ++i)
Hi Yunhui,
On Wed, Jan 15, 2025 at 3:40 AM Yunhui Cui cuiyunhui@bytedance.com wrote:
v1/v2: There is only the first patch: RISC-V: Enable cbo.clean/flush in usermode, which mainly removes the enabling of cbo.inval in user mode.
v3: Add the functionality of Expose Zicbom and selftests for Zicbom.
v4: Modify the order of macros, The test_no_cbo_inval function is added separately.
v5:
- Modify the order of RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE in hwprobe.rst
- "TEST_NO_ZICBOINVAL" -> "TEST_NO_CBO_INVAL"
Yunhui Cui (3): RISC-V: Enable cbo.clean/flush in usermode RISC-V: hwprobe: Expose Zicbom extension and its block size RISC-V: selftests: Add TEST_ZICBOM into CBO tests
Documentation/arch/riscv/hwprobe.rst | 6 ++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 2 + arch/riscv/kernel/cpufeature.c | 8 +++ arch/riscv/kernel/sys_hwprobe.c | 6 ++ tools/testing/selftests/riscv/hwprobe/cbo.c | 66 +++++++++++++++++---- 6 files changed, 78 insertions(+), 12 deletions(-)
-- 2.39.2
So a v6 needs to be sent with:
- the fix for hwprobe_ext0_has() reported by kernel test robot - a rebase on top of 6.14 since patch 2 will conflict with RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0
Do you think you can do that soon so that it gets merged in 6.15? The patchset received a lot of RB so it would be too bad to miss this release.
Thanks,
Alex
Hi Alex,
On Tue, Feb 25, 2025 at 9:21 PM Alexandre Ghiti alexghiti@rivosinc.com wrote:
Hi Yunhui,
On Wed, Jan 15, 2025 at 3:40 AM Yunhui Cui cuiyunhui@bytedance.com wrote:
v1/v2: There is only the first patch: RISC-V: Enable cbo.clean/flush in usermode, which mainly removes the enabling of cbo.inval in user mode.
v3: Add the functionality of Expose Zicbom and selftests for Zicbom.
v4: Modify the order of macros, The test_no_cbo_inval function is added separately.
v5:
- Modify the order of RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE in hwprobe.rst
- "TEST_NO_ZICBOINVAL" -> "TEST_NO_CBO_INVAL"
Yunhui Cui (3): RISC-V: Enable cbo.clean/flush in usermode RISC-V: hwprobe: Expose Zicbom extension and its block size RISC-V: selftests: Add TEST_ZICBOM into CBO tests
Documentation/arch/riscv/hwprobe.rst | 6 ++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 2 + arch/riscv/kernel/cpufeature.c | 8 +++ arch/riscv/kernel/sys_hwprobe.c | 6 ++ tools/testing/selftests/riscv/hwprobe/cbo.c | 66 +++++++++++++++++---- 6 files changed, 78 insertions(+), 12 deletions(-)
-- 2.39.2
So a v6 needs to be sent with:
- the fix for hwprobe_ext0_has() reported by kernel test robot
- a rebase on top of 6.14 since patch 2 will conflict with
RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0
Thank you for the reminder. In fact, version 6 was sent out almost a month ago. Reference: https://lore.kernel.org/lkml/20250124035959.45499-1-cuiyunhui@bytedance.com/
Do you think you can do that soon so that it gets merged in 6.15? The patchset received a lot of RB so it would be too bad to miss this release.
Thanks,
Alex
Thanks, Yunhui
On Tue, Feb 25, 2025 at 2:27 PM yunhui cui cuiyunhui@bytedance.com wrote:
Hi Alex,
On Tue, Feb 25, 2025 at 9:21 PM Alexandre Ghiti alexghiti@rivosinc.com wrote:
Hi Yunhui,
On Wed, Jan 15, 2025 at 3:40 AM Yunhui Cui cuiyunhui@bytedance.com wrote:
v1/v2: There is only the first patch: RISC-V: Enable cbo.clean/flush in usermode, which mainly removes the enabling of cbo.inval in user mode.
v3: Add the functionality of Expose Zicbom and selftests for Zicbom.
v4: Modify the order of macros, The test_no_cbo_inval function is added separately.
v5:
- Modify the order of RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE in hwprobe.rst
- "TEST_NO_ZICBOINVAL" -> "TEST_NO_CBO_INVAL"
Yunhui Cui (3): RISC-V: Enable cbo.clean/flush in usermode RISC-V: hwprobe: Expose Zicbom extension and its block size RISC-V: selftests: Add TEST_ZICBOM into CBO tests
Documentation/arch/riscv/hwprobe.rst | 6 ++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 2 + arch/riscv/kernel/cpufeature.c | 8 +++ arch/riscv/kernel/sys_hwprobe.c | 6 ++ tools/testing/selftests/riscv/hwprobe/cbo.c | 66 +++++++++++++++++---- 6 files changed, 78 insertions(+), 12 deletions(-)
-- 2.39.2
So a v6 needs to be sent with:
- the fix for hwprobe_ext0_has() reported by kernel test robot
- a rebase on top of 6.14 since patch 2 will conflict with
RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0
Thank you for the reminder. In fact, version 6 was sent out almost a month ago. Reference: https://lore.kernel.org/lkml/20250124035959.45499-1-cuiyunhui@bytedance.com/
Oh sorry, I missed it somehow!
I think we can fix RISCV_HWPROBE_MAX_KEY when merging the patch.
Sorry again and thanks!
Alex
Do you think you can do that soon so that it gets merged in 6.15? The patchset received a lot of RB so it would be too bad to miss this release.
Thanks,
Alex
Thanks, Yunhui
Hi Alex,
On Tue, Feb 25, 2025 at 10:07 PM Alexandre Ghiti alexghiti@rivosinc.com wrote:
On Tue, Feb 25, 2025 at 2:27 PM yunhui cui cuiyunhui@bytedance.com wrote:
Hi Alex,
On Tue, Feb 25, 2025 at 9:21 PM Alexandre Ghiti alexghiti@rivosinc.com wrote:
Hi Yunhui,
On Wed, Jan 15, 2025 at 3:40 AM Yunhui Cui cuiyunhui@bytedance.com wrote:
v1/v2: There is only the first patch: RISC-V: Enable cbo.clean/flush in usermode, which mainly removes the enabling of cbo.inval in user mode.
v3: Add the functionality of Expose Zicbom and selftests for Zicbom.
v4: Modify the order of macros, The test_no_cbo_inval function is added separately.
v5:
- Modify the order of RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE in hwprobe.rst
- "TEST_NO_ZICBOINVAL" -> "TEST_NO_CBO_INVAL"
Yunhui Cui (3): RISC-V: Enable cbo.clean/flush in usermode RISC-V: hwprobe: Expose Zicbom extension and its block size RISC-V: selftests: Add TEST_ZICBOM into CBO tests
Documentation/arch/riscv/hwprobe.rst | 6 ++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 2 + arch/riscv/kernel/cpufeature.c | 8 +++ arch/riscv/kernel/sys_hwprobe.c | 6 ++ tools/testing/selftests/riscv/hwprobe/cbo.c | 66 +++++++++++++++++---- 6 files changed, 78 insertions(+), 12 deletions(-)
-- 2.39.2
So a v6 needs to be sent with:
- the fix for hwprobe_ext0_has() reported by kernel test robot
- a rebase on top of 6.14 since patch 2 will conflict with
RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0
Thank you for the reminder. In fact, version 6 was sent out almost a month ago. Reference: https://lore.kernel.org/lkml/20250124035959.45499-1-cuiyunhui@bytedance.com/
Oh sorry, I missed it somehow!
I think we can fix RISCV_HWPROBE_MAX_KEY when merging the patch.
Sorry again and thanks!
It's all good. I've rebased a version: https://lore.kernel.org/all/20250226063206.71216-1-cuiyunhui@bytedance.com/. Could you help to merge it? Thanks.
Alex
Do you think you can do that soon so that it gets merged in 6.15? The patchset received a lot of RB so it would be too bad to miss this release.
Thanks,
Alex
Thanks, Yunhui
Thanks, Yunhui
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