Add support for (yet again) more RVA23U64 missing extensions. Add support for Zcmop, Zca, Zcf, Zcd and Zcb extensions isa string parsing, hwprobe and kvm support. Zce, Zcmt and Zcmp extensions have been left out since they target microcontrollers/embedded CPUs and are not needed by RVA23U64
This series is based on the Zimop one [1].
Link: https://lore.kernel.org/linux-riscv/20240404103254.1752834-1-cleger@rivosinc... [1]
--- v2: - Add Zc* dependencies validation in dt-bindings - v1: https://lore.kernel.org/lkml/20240410091106.749233-1-cleger@rivosinc.com/
Clément Léger (12): dt-bindings: riscv: add Zca, Zcf, Zcd and Zcb ISA extension description riscv: dts: enable Zc* extensions when needed dt-bindings: riscv: add Zc* extension rules implied by C extension riscv: add ISA parsing for Zca, Zcf, Zcd and Zcb riscv: hwprobe: export Zca, Zcf, Zcd and Zcb ISA extensions RISC-V: KVM: Allow Zca, Zcf, Zcd and Zcb extensions for Guest/VM KVM: riscv: selftests: Add some Zc* extensions to get-reg-list test dt-bindings: riscv: add Zcmop ISA extension description riscv: add ISA extension parsing for Zcmop riscv: hwprobe: export Zcmop ISA extension RISC-V: KVM: Allow Zcmop extension for Guest/VM KVM: riscv: selftests: Add Zcmop extension to get-reg-list test
Documentation/arch/riscv/hwprobe.rst | 24 ++ .../devicetree/bindings/riscv/cpus.yaml | 8 +- .../devicetree/bindings/riscv/extensions.yaml | 124 +++++++++ arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 4 +- arch/riscv/boot/dts/microchip/mpfs.dtsi | 20 +- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 +- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 20 +- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 20 +- arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 4 +- arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 256 +++++++++--------- arch/riscv/boot/dts/starfive/jh7100.dtsi | 8 +- arch/riscv/boot/dts/starfive/jh7110.dtsi | 20 +- arch/riscv/boot/dts/thead/th1520.dtsi | 16 +- arch/riscv/include/asm/hwcap.h | 5 + arch/riscv/include/uapi/asm/hwprobe.h | 5 + arch/riscv/include/uapi/asm/kvm.h | 5 + arch/riscv/kernel/cpufeature.c | 5 + arch/riscv/kernel/sys_hwprobe.c | 5 + arch/riscv/kvm/vcpu_onereg.c | 10 + .../selftests/kvm/riscv/get-reg-list.c | 20 ++ 20 files changed, 394 insertions(+), 189 deletions(-)
Add description for Zca, Zcf, Zcd and Zcb extensions which are part the Zc* standard extensions for code size reduction. Additional validation rules are added since Zcb depends on Zca, Zcf, depends on Zca and F, Zcd depends on Zca and D and finally, Zcf can not be present on rv64.
Signed-off-by: Clément Léger cleger@rivosinc.com --- .../devicetree/bindings/riscv/extensions.yaml | 78 +++++++++++++++++++ 1 file changed, 78 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 616370318a66..db7daf22b863 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -220,6 +220,38 @@ properties: instructions as ratified at commit 6d33919 ("Merge pull request #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
+ - const: zca + description: | + The Zca extension part of Zc* standard extensions for code size + reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on + RV64 as it contains no instructions") of riscv-code-size-reduction, + merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed + of zc.adoc to src tree."). + + - const: zcb + description: | + The Zcb extension part of Zc* standard extensions for code size + reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on + RV64 as it contains no instructions") of riscv-code-size-reduction, + merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed + of zc.adoc to src tree."). + + - const: zcd + description: | + The Zcd extension part of Zc* standard extensions for code size + reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on + RV64 as it contains no instructions") of riscv-code-size-reduction, + merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed + of zc.adoc to src tree."). + + - const: zcf + description: | + The Zcf extension part of Zc* standard extensions for code size + reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on + RV64 as it contains no instructions") of riscv-code-size-reduction, + merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed + of zc.adoc to src tree."). + - const: zfa description: The standard Zfa extension for additional floating point @@ -489,5 +521,51 @@ properties: Registers in the AX45MP datasheet. https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet....
+ allOf: + # Zcb depends on Zca + - if: + contains: + const: zcb + then: + contains: + const: zca + # Zcd depends on Zca and D + - if: + contains: + const: zcd + then: + allOf: + - contains: + const: zca + - contains: + const: d + # Zcf depends on Zca and F + - if: + contains: + const: zcf + then: + allOf: + - contains: + const: zca + - contains: + const: f + +allOf: + # Zcf extension does not exists on rv64 + - if: + properties: + riscv,isa-extensions: + contains: + const: zcf + riscv,isa-base: + contains: + const: rv64i + then: + properties: + riscv,isa-extensions: + not: + contains: + const: zcf + additionalProperties: true ...
On Thu, Apr 18, 2024 at 02:42:24PM +0200, Clément Léger wrote:
Add description for Zca, Zcf, Zcd and Zcb extensions which are part the Zc* standard extensions for code size reduction. Additional validation rules are added since Zcb depends on Zca, Zcf, depends on Zca and F, Zcd depends on Zca and D and finally, Zcf can not be present on rv64.
+allOf:
- # Zcf extension does not exists on rv64
If there's another version, "exist". Reviewed-by: Conor Dooley conor.dooley@microchip.com
Thanks, Conor.
The Zc* spec states that:
"The C extension is the superset of the following extensions: - Zca - Zcf if F is specified (RV32 only) - Zcd if D is specified As C defines the same instructions as Zca, Zcf and Zcd, the rule is that: - C always implies Zca - C+F implies Zcf (RV32 only)"
Add these extensions to existing device-trees that contains "c" extension in "riscv,isa-extensions".
Signed-off-by: Clément Léger cleger@rivosinc.com --- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 4 +- arch/riscv/boot/dts/microchip/mpfs.dtsi | 20 +- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 +- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 20 +- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 20 +- arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 4 +- arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 256 +++++++++--------- arch/riscv/boot/dts/starfive/jh7100.dtsi | 8 +- arch/riscv/boot/dts/starfive/jh7110.dtsi | 20 +- arch/riscv/boot/dts/thead/th1520.dtsi | 16 +- 10 files changed, 186 insertions(+), 186 deletions(-)
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index 64c3c2e6cbe0..05e0e5f0eed7 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -26,8 +26,8 @@ cpu0: cpu@0 { operating-points-v2 = <&opp_table_cpu>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; #cooling-cells = <2>;
cpu0_intc: interrupt-controller { diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 9883ca3554c5..82ac84afdda7 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -24,8 +24,8 @@ cpu0: cpu@0 { reg = <0>; riscv,isa = "rv64imac"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + riscv,isa-extensions = "i", "m", "a", "c", "zca", "zicntr", "zicsr", + "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; status = "disabled";
@@ -53,8 +53,8 @@ cpu1: cpu@1 { reg = <1>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -84,8 +84,8 @@ cpu2: cpu@2 { reg = <2>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -115,8 +115,8 @@ cpu3: cpu@3 { reg = <3>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -146,8 +146,8 @@ cpu4: cpu@4 { reg = <4>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index f35324b9173c..b5e06fbfdf65 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -26,8 +26,8 @@ cpu0: cpu@0 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xandespmu"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm", "xandespmu"; mmu-type = "riscv,sv39"; i-cache-size = <0x8000>; i-cache-line-size = <0x40>; diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index 156330a9bbf3..2872515dab17 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -31,8 +31,8 @@ cpu0: cpu@0 { reg = <0>; riscv,isa = "rv64imac"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + riscv,isa-extensions = "i", "m", "a", "c", "zca", "zicntr", "zicsr", + "zifencei", "zihpm"; status = "disabled"; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; @@ -57,8 +57,8 @@ cpu1: cpu@1 { reg = <1>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu1_intc: interrupt-controller { @@ -84,8 +84,8 @@ cpu2: cpu@2 { reg = <2>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu2_intc: interrupt-controller { @@ -111,8 +111,8 @@ cpu3: cpu@3 { reg = <3>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu3_intc: interrupt-controller { @@ -138,8 +138,8 @@ cpu4: cpu@4 { reg = <4>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu4_intc: interrupt-controller { diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index 6150f3397bff..4336ed11db9a 100644 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -32,8 +32,8 @@ cpu0: cpu@0 { reg = <0x0>; riscv,isa = "rv64imac"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + riscv,isa-extensions = "i", "m", "a", "c", "zca", "zicntr", "zicsr", + "zifencei", "zihpm"; status = "disabled"; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; @@ -59,8 +59,8 @@ cpu1: cpu@1 { reg = <0x1>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; @@ -86,8 +86,8 @@ cpu2: cpu@2 { reg = <0x2>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; cpu2_intc: interrupt-controller { #interrupt-cells = <1>; @@ -113,8 +113,8 @@ cpu3: cpu@3 { reg = <0x3>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; cpu3_intc: interrupt-controller { #interrupt-cells = <1>; @@ -140,8 +140,8 @@ cpu4: cpu@4 { reg = <0x4>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; cpu4_intc: interrupt-controller { #interrupt-cells = <1>; diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi index 2d6f4a4b1e58..1fa5c57acf48 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -28,8 +28,8 @@ cpu0: cpu@0 { mmu-type = "riscv,sv39"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm";
cpu0_intc: interrupt-controller { compatible = "riscv,cpu-intc"; diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi index b136b6c4128c..6d03076314aa 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -259,8 +259,8 @@ cpu0: cpu@0 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <0>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -284,8 +284,8 @@ cpu1: cpu@1 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <1>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -309,8 +309,8 @@ cpu2: cpu@2 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <2>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -334,8 +334,8 @@ cpu3: cpu@3 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <3>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -359,8 +359,8 @@ cpu4: cpu@4 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <4>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -384,8 +384,8 @@ cpu5: cpu@5 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <5>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -409,8 +409,8 @@ cpu6: cpu@6 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <6>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -434,8 +434,8 @@ cpu7: cpu@7 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <7>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -459,8 +459,8 @@ cpu8: cpu@8 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <8>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -484,8 +484,8 @@ cpu9: cpu@9 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <9>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -509,8 +509,8 @@ cpu10: cpu@10 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <10>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -534,8 +534,8 @@ cpu11: cpu@11 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <11>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -559,8 +559,8 @@ cpu12: cpu@12 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <12>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -584,8 +584,8 @@ cpu13: cpu@13 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <13>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -609,8 +609,8 @@ cpu14: cpu@14 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <14>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -634,8 +634,8 @@ cpu15: cpu@15 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <15>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -659,8 +659,8 @@ cpu16: cpu@16 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <16>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -684,8 +684,8 @@ cpu17: cpu@17 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <17>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -709,8 +709,8 @@ cpu18: cpu@18 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <18>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -734,8 +734,8 @@ cpu19: cpu@19 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <19>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -759,8 +759,8 @@ cpu20: cpu@20 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <20>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -784,8 +784,8 @@ cpu21: cpu@21 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <21>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -809,8 +809,8 @@ cpu22: cpu@22 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <22>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -834,8 +834,8 @@ cpu23: cpu@23 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <23>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -859,8 +859,8 @@ cpu24: cpu@24 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <24>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -884,8 +884,8 @@ cpu25: cpu@25 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <25>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -909,8 +909,8 @@ cpu26: cpu@26 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <26>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -934,8 +934,8 @@ cpu27: cpu@27 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <27>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -959,8 +959,8 @@ cpu28: cpu@28 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <28>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -984,8 +984,8 @@ cpu29: cpu@29 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <29>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1009,8 +1009,8 @@ cpu30: cpu@30 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <30>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1034,8 +1034,8 @@ cpu31: cpu@31 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <31>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1059,8 +1059,8 @@ cpu32: cpu@32 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <32>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1084,8 +1084,8 @@ cpu33: cpu@33 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <33>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1109,8 +1109,8 @@ cpu34: cpu@34 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <34>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1134,8 +1134,8 @@ cpu35: cpu@35 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <35>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1159,8 +1159,8 @@ cpu36: cpu@36 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <36>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1184,8 +1184,8 @@ cpu37: cpu@37 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <37>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1209,8 +1209,8 @@ cpu38: cpu@38 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <38>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1234,8 +1234,8 @@ cpu39: cpu@39 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <39>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1259,8 +1259,8 @@ cpu40: cpu@40 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <40>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1284,8 +1284,8 @@ cpu41: cpu@41 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <41>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1309,8 +1309,8 @@ cpu42: cpu@42 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <42>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1334,8 +1334,8 @@ cpu43: cpu@43 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <43>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1359,8 +1359,8 @@ cpu44: cpu@44 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <44>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1384,8 +1384,8 @@ cpu45: cpu@45 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <45>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1409,8 +1409,8 @@ cpu46: cpu@46 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <46>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1434,8 +1434,8 @@ cpu47: cpu@47 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <47>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1459,8 +1459,8 @@ cpu48: cpu@48 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <48>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1484,8 +1484,8 @@ cpu49: cpu@49 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <49>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1509,8 +1509,8 @@ cpu50: cpu@50 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <50>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1534,8 +1534,8 @@ cpu51: cpu@51 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <51>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1559,8 +1559,8 @@ cpu52: cpu@52 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <52>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1584,8 +1584,8 @@ cpu53: cpu@53 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <53>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1609,8 +1609,8 @@ cpu54: cpu@54 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <54>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1634,8 +1634,8 @@ cpu55: cpu@55 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <55>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1659,8 +1659,8 @@ cpu56: cpu@56 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <56>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1684,8 +1684,8 @@ cpu57: cpu@57 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <57>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1709,8 +1709,8 @@ cpu58: cpu@58 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <58>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1734,8 +1734,8 @@ cpu59: cpu@59 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <59>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1759,8 +1759,8 @@ cpu60: cpu@60 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <60>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1784,8 +1784,8 @@ cpu61: cpu@61 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <61>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1809,8 +1809,8 @@ cpu62: cpu@62 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <62>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1834,8 +1834,8 @@ cpu63: cpu@63 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <63>; i-cache-block-size = <64>; i-cache-size = <65536>; diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 9a2e9583af88..7e53c539c871 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -35,8 +35,8 @@ U74_0: cpu@0 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split;
cpu0_intc: interrupt-controller { @@ -64,8 +64,8 @@ U74_1: cpu@1 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split;
cpu1_intc: interrupt-controller { diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 4a5708f7fcf7..f01024f50561 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -29,8 +29,8 @@ S7_0: cpu@0 { next-level-cache = <&ccache>; riscv,isa = "rv64imac_zba_zbb"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zca", "zicntr", + "zicsr", "zifencei", "zihpm"; status = "disabled";
cpu0_intc: interrupt-controller { @@ -58,8 +58,8 @@ U74_1: cpu@1 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", - "zicsr", "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zca", + "zcd", "zicntr", "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; @@ -91,8 +91,8 @@ U74_2: cpu@2 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", - "zicsr", "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zca", + "zcd", "zicntr", "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; @@ -124,8 +124,8 @@ U74_3: cpu@3 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", - "zicsr", "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zca", + "zcd", "zicntr", "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; @@ -157,8 +157,8 @@ U74_4: cpu@4 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", - "zicsr", "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zca", + "zcd", "zicntr", "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 8b915e206f3a..530355bda7c1 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -21,8 +21,8 @@ c910_0: cpu@0 { device_type = "cpu"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; reg = <0>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -45,8 +45,8 @@ c910_1: cpu@1 { device_type = "cpu"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; reg = <1>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -69,8 +69,8 @@ c910_2: cpu@2 { device_type = "cpu"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; reg = <2>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -93,8 +93,8 @@ c910_3: cpu@3 { device_type = "cpu"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; reg = <3>; i-cache-block-size = <64>; i-cache-size = <65536>;
On Thu, Apr 18, 2024 at 02:42:25PM +0200, Clément Léger wrote:
The Zc* spec states that:
"The C extension is the superset of the following extensions:
- Zca
- Zcf if F is specified (RV32 only)
- Zcd if D is specified
As C defines the same instructions as Zca, Zcf and Zcd, the rule is that:
- C always implies Zca
- C+F implies Zcf (RV32 only)"
Add these extensions to existing device-trees that contains "c" extension in "riscv,isa-extensions".
Signed-off-by: Clément Léger cleger@rivosinc.com
I don't wanna advocate this sort of churn whenever we add extensions that are implied by some other existing extension, and I certainly don't want to /have/ to do it because there'll be dbts_check warnings otherwise. New subsets being defined do not invalidate the old descriptions and they should remain valid.
arch/riscv/boot/dts/microchip/mpfs.dtsi | 20 +- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 20 +- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 20 +- arch/riscv/boot/dts/starfive/jh7100.dtsi | 8 +- arch/riscv/boot/dts/starfive/jh7110.dtsi | 20 +- arch/riscv/boot/dts/thead/th1520.dtsi | 16 +-
NAK for doing it to these 4 subdirs, even if the bindings are changed to not warn about it anymore.
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 4 +-
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 +-
arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 4 +- arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 256 +++++++++---------
These go to other trees, so up to their maintainers what they want :)
Thanks, Conor.
10 files changed, 186 insertions(+), 186 deletions(-)
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index 64c3c2e6cbe0..05e0e5f0eed7 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -26,8 +26,8 @@ cpu0: cpu@0 { operating-points-v2 = <&opp_table_cpu>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr","zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr","zicsr", "zifencei", "zihpm"; #cooling-cells = <2>;cpu0_intc: interrupt-controller { diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 9883ca3554c5..82ac84afdda7 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -24,8 +24,8 @@ cpu0: cpu@0 { reg = <0>; riscv,isa = "rv64imac"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei","zihpm";
riscv,isa-extensions = "i", "m", "a", "c", "zca", "zicntr", "zicsr","zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; status = "disabled";@@ -53,8 +53,8 @@ cpu1: cpu@1 { reg = <1>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr","zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr","zicsr", "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>;@@ -84,8 +84,8 @@ cpu2: cpu@2 { reg = <2>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr","zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr","zicsr", "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>;@@ -115,8 +115,8 @@ cpu3: cpu@3 { reg = <3>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr","zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr","zicsr", "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>;@@ -146,8 +146,8 @@ cpu4: cpu@4 { reg = <4>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr","zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr","zicsr", "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>;diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index f35324b9173c..b5e06fbfdf65 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -26,8 +26,8 @@ cpu0: cpu@0 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm", "xandespmu";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm", "xandespmu"; mmu-type = "riscv,sv39"; i-cache-size = <0x8000>; i-cache-line-size = <0x40>;diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index 156330a9bbf3..2872515dab17 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -31,8 +31,8 @@ cpu0: cpu@0 { reg = <0>; riscv,isa = "rv64imac"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei","zihpm";
riscv,isa-extensions = "i", "m", "a", "c", "zca", "zicntr", "zicsr","zifencei", "zihpm"; status = "disabled"; cpu0_intc: interrupt-controller { #interrupt-cells = <1>;@@ -57,8 +57,8 @@ cpu1: cpu@1 { reg = <1>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr","zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr","zicsr", "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu1_intc: interrupt-controller {@@ -84,8 +84,8 @@ cpu2: cpu@2 { reg = <2>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr","zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr","zicsr", "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu2_intc: interrupt-controller {@@ -111,8 +111,8 @@ cpu3: cpu@3 { reg = <3>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr","zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr","zicsr", "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu3_intc: interrupt-controller {@@ -138,8 +138,8 @@ cpu4: cpu@4 { reg = <4>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr","zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr","zicsr", "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu4_intc: interrupt-controller {diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index 6150f3397bff..4336ed11db9a 100644 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -32,8 +32,8 @@ cpu0: cpu@0 { reg = <0x0>; riscv,isa = "rv64imac"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei","zihpm";
riscv,isa-extensions = "i", "m", "a", "c", "zca", "zicntr", "zicsr","zifencei", "zihpm"; status = "disabled"; cpu0_intc: interrupt-controller { #interrupt-cells = <1>;@@ -59,8 +59,8 @@ cpu1: cpu@1 { reg = <0x1>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr","zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr","zicsr", "zifencei", "zihpm"; tlb-split; cpu1_intc: interrupt-controller { #interrupt-cells = <1>;@@ -86,8 +86,8 @@ cpu2: cpu@2 { reg = <0x2>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr","zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr","zicsr", "zifencei", "zihpm"; tlb-split; cpu2_intc: interrupt-controller { #interrupt-cells = <1>;@@ -113,8 +113,8 @@ cpu3: cpu@3 { reg = <0x3>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr","zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr","zicsr", "zifencei", "zihpm"; tlb-split; cpu3_intc: interrupt-controller { #interrupt-cells = <1>;@@ -140,8 +140,8 @@ cpu4: cpu@4 { reg = <0x4>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr","zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr","zicsr", "zifencei", "zihpm"; tlb-split; cpu4_intc: interrupt-controller { #interrupt-cells = <1>;diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi index 2d6f4a4b1e58..1fa5c57acf48 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -28,8 +28,8 @@ cpu0: cpu@0 { mmu-type = "riscv,sv39"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr","zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr","zicsr", "zifencei", "zihpm";cpu0_intc: interrupt-controller { compatible = "riscv,cpu-intc"; diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi index b136b6c4128c..6d03076314aa 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -259,8 +259,8 @@ cpu0: cpu@0 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <0>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -284,8 +284,8 @@ cpu1: cpu@1 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <1>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -309,8 +309,8 @@ cpu2: cpu@2 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <2>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -334,8 +334,8 @@ cpu3: cpu@3 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <3>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -359,8 +359,8 @@ cpu4: cpu@4 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <4>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -384,8 +384,8 @@ cpu5: cpu@5 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <5>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -409,8 +409,8 @@ cpu6: cpu@6 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <6>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -434,8 +434,8 @@ cpu7: cpu@7 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <7>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -459,8 +459,8 @@ cpu8: cpu@8 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <8>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -484,8 +484,8 @@ cpu9: cpu@9 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <9>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -509,8 +509,8 @@ cpu10: cpu@10 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <10>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -534,8 +534,8 @@ cpu11: cpu@11 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <11>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -559,8 +559,8 @@ cpu12: cpu@12 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <12>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -584,8 +584,8 @@ cpu13: cpu@13 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <13>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -609,8 +609,8 @@ cpu14: cpu@14 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <14>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -634,8 +634,8 @@ cpu15: cpu@15 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <15>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -659,8 +659,8 @@ cpu16: cpu@16 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <16>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -684,8 +684,8 @@ cpu17: cpu@17 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <17>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -709,8 +709,8 @@ cpu18: cpu@18 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <18>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -734,8 +734,8 @@ cpu19: cpu@19 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <19>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -759,8 +759,8 @@ cpu20: cpu@20 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <20>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -784,8 +784,8 @@ cpu21: cpu@21 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <21>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -809,8 +809,8 @@ cpu22: cpu@22 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <22>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -834,8 +834,8 @@ cpu23: cpu@23 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <23>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -859,8 +859,8 @@ cpu24: cpu@24 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <24>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -884,8 +884,8 @@ cpu25: cpu@25 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <25>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -909,8 +909,8 @@ cpu26: cpu@26 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <26>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -934,8 +934,8 @@ cpu27: cpu@27 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <27>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -959,8 +959,8 @@ cpu28: cpu@28 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <28>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -984,8 +984,8 @@ cpu29: cpu@29 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <29>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1009,8 +1009,8 @@ cpu30: cpu@30 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <30>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1034,8 +1034,8 @@ cpu31: cpu@31 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <31>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1059,8 +1059,8 @@ cpu32: cpu@32 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <32>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1084,8 +1084,8 @@ cpu33: cpu@33 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <33>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1109,8 +1109,8 @@ cpu34: cpu@34 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <34>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1134,8 +1134,8 @@ cpu35: cpu@35 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <35>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1159,8 +1159,8 @@ cpu36: cpu@36 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <36>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1184,8 +1184,8 @@ cpu37: cpu@37 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <37>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1209,8 +1209,8 @@ cpu38: cpu@38 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <38>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1234,8 +1234,8 @@ cpu39: cpu@39 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <39>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1259,8 +1259,8 @@ cpu40: cpu@40 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <40>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1284,8 +1284,8 @@ cpu41: cpu@41 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <41>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1309,8 +1309,8 @@ cpu42: cpu@42 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <42>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1334,8 +1334,8 @@ cpu43: cpu@43 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <43>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1359,8 +1359,8 @@ cpu44: cpu@44 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <44>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1384,8 +1384,8 @@ cpu45: cpu@45 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <45>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1409,8 +1409,8 @@ cpu46: cpu@46 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <46>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1434,8 +1434,8 @@ cpu47: cpu@47 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <47>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1459,8 +1459,8 @@ cpu48: cpu@48 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <48>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1484,8 +1484,8 @@ cpu49: cpu@49 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <49>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1509,8 +1509,8 @@ cpu50: cpu@50 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <50>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1534,8 +1534,8 @@ cpu51: cpu@51 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <51>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1559,8 +1559,8 @@ cpu52: cpu@52 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <52>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1584,8 +1584,8 @@ cpu53: cpu@53 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <53>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1609,8 +1609,8 @@ cpu54: cpu@54 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <54>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1634,8 +1634,8 @@ cpu55: cpu@55 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <55>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1659,8 +1659,8 @@ cpu56: cpu@56 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <56>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1684,8 +1684,8 @@ cpu57: cpu@57 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <57>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1709,8 +1709,8 @@ cpu58: cpu@58 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <58>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1734,8 +1734,8 @@ cpu59: cpu@59 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <59>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1759,8 +1759,8 @@ cpu60: cpu@60 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <60>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1784,8 +1784,8 @@ cpu61: cpu@61 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <61>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1809,8 +1809,8 @@ cpu62: cpu@62 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <62>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -1834,8 +1834,8 @@ cpu63: cpu@63 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei","zihpm";
"zca", "zcd", "zicntr", "zicsr","zifencei", "zihpm"; reg = <63>; i-cache-block-size = <64>; i-cache-size = <65536>;diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 9a2e9583af88..7e53c539c871 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -35,8 +35,8 @@ U74_0: cpu@0 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr","zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr","zicsr", "zifencei", "zihpm"; tlb-split;cpu0_intc: interrupt-controller { @@ -64,8 +64,8 @@ U74_1: cpu@1 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr","zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr","zicsr", "zifencei", "zihpm"; tlb-split;cpu1_intc: interrupt-controller { diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 4a5708f7fcf7..f01024f50561 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -29,8 +29,8 @@ S7_0: cpu@0 { next-level-cache = <&ccache>; riscv,isa = "rv64imac_zba_zbb"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr","zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zca", "zicntr","zicsr", "zifencei", "zihpm"; status = "disabled";cpu0_intc: interrupt-controller { @@ -58,8 +58,8 @@ U74_1: cpu@1 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr","zicsr", "zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zca","zcd", "zicntr", "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;@@ -91,8 +91,8 @@ U74_2: cpu@2 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr","zicsr", "zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zca","zcd", "zicntr", "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;@@ -124,8 +124,8 @@ U74_3: cpu@3 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr","zicsr", "zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zca","zcd", "zicntr", "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;@@ -157,8 +157,8 @@ U74_4: cpu@4 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr","zicsr", "zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zca","zcd", "zicntr", "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 8b915e206f3a..530355bda7c1 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -21,8 +21,8 @@ c910_0: cpu@0 { device_type = "cpu"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr","zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr","zicsr", "zifencei", "zihpm"; reg = <0>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -45,8 +45,8 @@ c910_1: cpu@1 { device_type = "cpu"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr","zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr","zicsr", "zifencei", "zihpm"; reg = <1>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -69,8 +69,8 @@ c910_2: cpu@2 { device_type = "cpu"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr","zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr","zicsr", "zifencei", "zihpm"; reg = <2>; i-cache-block-size = <64>; i-cache-size = <65536>;@@ -93,8 +93,8 @@ c910_3: cpu@3 { device_type = "cpu"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr","zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr","zicsr", "zifencei", "zihpm"; reg = <3>; i-cache-block-size = <64>; i-cache-size = <65536>;-- 2.43.0
As stated by Zc* spec:
"As C defines the same instructions as Zca, Zcf and Zcd, the rule is that: - C always implies Zca - C+F implies Zcf (RV32 only) - C+D implies Zcd"
Add additionnal validation rules to enforce this in dts.
Signed-off-by: Clément Léger cleger@rivosinc.com --- .../devicetree/bindings/riscv/cpus.yaml | 8 +++-- .../devicetree/bindings/riscv/extensions.yaml | 34 +++++++++++++++++++ 2 files changed, 39 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d87dd50f1a4b..c4e2c65437b1 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -168,7 +168,7 @@ examples: i-cache-size = <16384>; reg = <0>; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "c"; + riscv,isa-extensions = "i", "m", "a", "c", "zca";
cpu_intc0: interrupt-controller { #interrupt-cells = <1>; @@ -194,7 +194,8 @@ examples: reg = <1>; tlb-split; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", + "zcd";
cpu_intc1: interrupt-controller { #interrupt-cells = <1>; @@ -215,7 +216,8 @@ examples: compatible = "riscv"; mmu-type = "riscv,sv48"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", + "zcd";
interrupt-controller { #interrupt-cells = <1>; diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index db7daf22b863..0172cbaa13ca 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -549,6 +549,23 @@ properties: const: zca - contains: const: f + # C extension implies Zca + - if: + contains: + const: c + then: + contains: + const: zca + # C extension implies Zcd if d + - if: + allOf: + - contains: + const: c + - contains: + const: d + then: + contains: + const: zcd
allOf: # Zcf extension does not exists on rv64 @@ -566,6 +583,23 @@ allOf: not: contains: const: zcf + # C extension implies Zcf if f on rv32 only + - if: + properties: + riscv,isa-extensions: + allOf: + - contains: + const: c + - contains: + const: f + riscv,isa-base: + contains: + const: rv32i + then: + properties: + riscv,isa-extensions: + contains: + const: zcf
additionalProperties: true ...
On Thu, Apr 18, 2024 at 02:42:26PM +0200, Clément Léger wrote:
As stated by Zc* spec:
"As C defines the same instructions as Zca, Zcf and Zcd, the rule is that:
- C always implies Zca
- C+F implies Zcf (RV32 only)
- C+D implies Zcd"
Add additionnal validation rules to enforce this in dts.
I'll get it out of the way: NAK, and the dts patch is the perfect example of why. I don't want us to have to continually update devicetrees. If these are implied due to being subsets of other extensions, then software should be able to enable them when that other extension is present.
My fear is that, and a quick look at the "add probing" commit seemed to confirm it, new subsets would require updates to the dts, even though the existing extension is perfectly sufficient to determine presence.
I definitely want to avoid continual updates to the devicetree for churn reasons whenever subsets are added, but not turning on the likes of Zca when C is present because "the bindings were updated to enforce this" is a complete blocker. I do concede that having two parents makes that more difficult and will likely require some changes to how we probe - do we need to have a "second round" type thing? Taking Zcf as an example, maybe something like making both of C and F into "standard" supersets and adding a case to riscv_isa_extension_check() that would mandate that Zca and F are enabled before enabling it, and we would ensure that C implies Zca before it implies Zcf?
Given we'd be relying on ordering, we have to perform the same implication for both F and C and make sure that the "implies" struct has Zca before Zcf. I don't really like that suggestion, hopefully there's a nicer way of doing that, but I don't like the dt stuff here.
Thanks, Conor.
Signed-off-by: Clément Léger cleger@rivosinc.com
.../devicetree/bindings/riscv/cpus.yaml | 8 +++-- .../devicetree/bindings/riscv/extensions.yaml | 34 +++++++++++++++++++ 2 files changed, 39 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d87dd50f1a4b..c4e2c65437b1 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -168,7 +168,7 @@ examples: i-cache-size = <16384>; reg = <0>; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "c";
riscv,isa-extensions = "i", "m", "a", "c", "zca";cpu_intc0: interrupt-controller { #interrupt-cells = <1>; @@ -194,7 +194,8 @@ examples: reg = <1>; tlb-split; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca","zcd";cpu_intc1: interrupt-controller { #interrupt-cells = <1>; @@ -215,7 +216,8 @@ examples: compatible = "riscv"; mmu-type = "riscv,sv48"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca","zcd";interrupt-controller { #interrupt-cells = <1>; diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index db7daf22b863..0172cbaa13ca 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -549,6 +549,23 @@ properties: const: zca - contains: const: f
# C extension implies Zca- if:contains:const: cthen:contains:const: zca# C extension implies Zcd if d- if:allOf:- contains:const: c- contains:const: dthen:contains:const: zcdallOf: # Zcf extension does not exists on rv64 @@ -566,6 +583,23 @@ allOf: not: contains: const: zcf
- # C extension implies Zcf if f on rv32 only
- if:
properties:riscv,isa-extensions:allOf:- contains:const: c- contains:const: friscv,isa-base:contains:const: rv32i- then:
properties:riscv,isa-extensions:contains:const: zcfadditionalProperties: true ... -- 2.43.0
On 19/04/2024 17:49, Conor Dooley wrote:
On Thu, Apr 18, 2024 at 02:42:26PM +0200, Clément Léger wrote:
As stated by Zc* spec:
"As C defines the same instructions as Zca, Zcf and Zcd, the rule is that:
- C always implies Zca
- C+F implies Zcf (RV32 only)
- C+D implies Zcd"
Add additionnal validation rules to enforce this in dts.
I'll get it out of the way: NAK, and the dts patch is the perfect example of why. I don't want us to have to continually update devicetrees. If these are implied due to being subsets of other extensions, then software should be able to enable them when that other extension is present.
Acked.
My fear is that, and a quick look at the "add probing" commit seemed to confirm it, new subsets would require updates to the dts, even though the existing extension is perfectly sufficient to determine presence.
I definitely want to avoid continual updates to the devicetree for churn reasons whenever subsets are added, but not turning on the likes of Zca when C is present because "the bindings were updated to enforce this" is a complete blocker. I do concede that having two parents makes that more difficult and will likely require some changes to how we probe - do we need to have a "second round" type thing?
Yeah, I understand. At first, I actually did the modifications in the ISA probing loop with some dependency probing (ie loop while we don't have a stable extension state). But I thought that it was not actually our problem but rather the ISA string provider. For instance, Qemu provides them.
Taking Zcf as an example, maybe something like making both of C and F into "standard" supersets and adding a case to riscv_isa_extension_check() that would mandate that Zca and F are enabled before enabling it, and we would ensure that C implies Zca before it implies Zcf?
I'm afraid that riscv_isa_extension_check() will become a rat nest so rather than going that way, I would be in favor of adding a validation callback for the extensions if needed.
Given we'd be relying on ordering, we have to perform the same implication for both F and C and make sure that the "implies" struct has Zca before Zcf. I don't really like that suggestion, hopefully there's a nicer way of doing that, but I don't like the dt stuff here.
I guess the "cleanest" way would be to have some "defered-like" mechanism in ISA probing which would allow to handle ordering as well as dependencies/implies for extensions. For Zca, Zcf, we actually do not have ordering problems but I think it would be a bit broken not to support that as well.
I can actually revive the work mentioned above to handle that and see if it works ok.
Clément
Thanks, Conor.
Signed-off-by: Clément Léger cleger@rivosinc.com
.../devicetree/bindings/riscv/cpus.yaml | 8 +++-- .../devicetree/bindings/riscv/extensions.yaml | 34 +++++++++++++++++++ 2 files changed, 39 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d87dd50f1a4b..c4e2c65437b1 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -168,7 +168,7 @@ examples: i-cache-size = <16384>; reg = <0>; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "c";
riscv,isa-extensions = "i", "m", "a", "c", "zca";cpu_intc0: interrupt-controller { #interrupt-cells = <1>; @@ -194,7 +194,8 @@ examples: reg = <1>; tlb-split; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca","zcd";cpu_intc1: interrupt-controller { #interrupt-cells = <1>; @@ -215,7 +216,8 @@ examples: compatible = "riscv"; mmu-type = "riscv,sv48"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca","zcd";interrupt-controller { #interrupt-cells = <1>; diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index db7daf22b863..0172cbaa13ca 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -549,6 +549,23 @@ properties: const: zca - contains: const: f
# C extension implies Zca- if:contains:const: cthen:contains:const: zca# C extension implies Zcd if d- if:allOf:- contains:const: c- contains:const: dthen:contains:const: zcdallOf: # Zcf extension does not exists on rv64 @@ -566,6 +583,23 @@ allOf: not: contains: const: zcf
- # C extension implies Zcf if f on rv32 only
- if:
properties:riscv,isa-extensions:allOf:- contains:const: c- contains:const: friscv,isa-base:contains:const: rv32i- then:
properties:riscv,isa-extensions:contains:const: zcfadditionalProperties: true ... -- 2.43.0
On Mon, Apr 22, 2024 at 10:53:04AM +0200, Clément Léger wrote:
On 19/04/2024 17:49, Conor Dooley wrote:
On Thu, Apr 18, 2024 at 02:42:26PM +0200, Clément Léger wrote:
As stated by Zc* spec:
"As C defines the same instructions as Zca, Zcf and Zcd, the rule is that:
- C always implies Zca
- C+F implies Zcf (RV32 only)
- C+D implies Zcd"
Add additionnal validation rules to enforce this in dts.
I'll get it out of the way: NAK, and the dts patch is the perfect example of why. I don't want us to have to continually update devicetrees. If these are implied due to being subsets of other extensions, then software should be able to enable them when that other extension is present.
Acked.
My fear is that, and a quick look at the "add probing" commit seemed to confirm it, new subsets would require updates to the dts, even though the existing extension is perfectly sufficient to determine presence.
I definitely want to avoid continual updates to the devicetree for churn reasons whenever subsets are added, but not turning on the likes of Zca when C is present because "the bindings were updated to enforce this" is a complete blocker. I do concede that having two parents makes that more difficult and will likely require some changes to how we probe - do we need to have a "second round" type thing?
Yeah, I understand. At first, I actually did the modifications in the ISA probing loop with some dependency probing (ie loop while we don't have a stable extension state). But I thought that it was not actually our problem but rather the ISA string provider. For instance, Qemu provides them.
A newer version of QEMU might, but not all do, so I'm not sure that using it is a good example. My expectations is that a devicetree will be written to the standards of the day and not be updated as subsets are released.
If this were the first instance of a superset/bundle I'd be prepared to accept an argument that we should not infer anything - but it's not and we'd be introducing inconsistency with the crypto stuff. I know that both scenarios are different in terms of extension history given that this is splitting things into a subset and that was a superset/bundle created at the same time, but they're not really that different in terms of the DT/ACPI to user "interface".
Taking Zcf as an example, maybe something like making both of C and F into "standard" supersets and adding a case to riscv_isa_extension_check() that would mandate that Zca and F are enabled before enabling it, and we would ensure that C implies Zca before it implies Zcf?
I'm afraid that riscv_isa_extension_check() will become a rat nest so rather than going that way, I would be in favor of adding a validation callback for the extensions if needed.
IOW, extension check split out per extension moving to be a callback?
Given we'd be relying on ordering, we have to perform the same implication for both F and C and make sure that the "implies" struct has Zca before Zcf. I don't really like that suggestion, hopefully there's a nicer way of doing that, but I don't like the dt stuff here.
I guess the "cleanest" way would be to have some "defered-like" mechanism in ISA probing which would allow to handle ordering as well as dependencies/implies for extensions. For Zca, Zcf, we actually do not have ordering problems but I think it would be a bit broken not to support that as well.
We could, I suppose, enable all detected extensions on a CPU and run the aforemention callback, disabling them if conditions are not met?
Is that something like what you're suggesting?
On 22/04/2024 13:19, Conor Dooley wrote:
On Mon, Apr 22, 2024 at 10:53:04AM +0200, Clément Léger wrote:
On 19/04/2024 17:49, Conor Dooley wrote:
On Thu, Apr 18, 2024 at 02:42:26PM +0200, Clément Léger wrote:
As stated by Zc* spec:
"As C defines the same instructions as Zca, Zcf and Zcd, the rule is that:
- C always implies Zca
- C+F implies Zcf (RV32 only)
- C+D implies Zcd"
Add additionnal validation rules to enforce this in dts.
I'll get it out of the way: NAK, and the dts patch is the perfect example of why. I don't want us to have to continually update devicetrees. If these are implied due to being subsets of other extensions, then software should be able to enable them when that other extension is present.
Acked.
My fear is that, and a quick look at the "add probing" commit seemed to confirm it, new subsets would require updates to the dts, even though the existing extension is perfectly sufficient to determine presence.
I definitely want to avoid continual updates to the devicetree for churn reasons whenever subsets are added, but not turning on the likes of Zca when C is present because "the bindings were updated to enforce this" is a complete blocker. I do concede that having two parents makes that more difficult and will likely require some changes to how we probe - do we need to have a "second round" type thing?
Yeah, I understand. At first, I actually did the modifications in the ISA probing loop with some dependency probing (ie loop while we don't have a stable extension state). But I thought that it was not actually our problem but rather the ISA string provider. For instance, Qemu provides them.
A newer version of QEMU might, but not all do, so I'm not sure that using it is a good example. My expectations is that a devicetree will be written to the standards of the day and not be updated as subsets are released.
If this were the first instance of a superset/bundle I'd be prepared to accept an argument that we should not infer anything - but it's not and we'd be introducing inconsistency with the crypto stuff. I know that both scenarios are different in terms of extension history given that this is splitting things into a subset and that was a superset/bundle created at the same time, but they're not really that different in terms of the DT/ACPI to user "interface".
Taking Zcf as an example, maybe something like making both of C and F into "standard" supersets and adding a case to riscv_isa_extension_check() that would mandate that Zca and F are enabled before enabling it, and we would ensure that C implies Zca before it implies Zcf?
I'm afraid that riscv_isa_extension_check() will become a rat nest so rather than going that way, I would be in favor of adding a validation callback for the extensions if needed.
IOW, extension check split out per extension moving to be a callback?
Given we'd be relying on ordering, we have to perform the same implication for both F and C and make sure that the "implies" struct has Zca before Zcf. I don't really like that suggestion, hopefully there's a nicer way of doing that, but I don't like the dt stuff here.
I guess the "cleanest" way would be to have some "defered-like" mechanism in ISA probing which would allow to handle ordering as well as dependencies/implies for extensions. For Zca, Zcf, we actually do not have ordering problems but I think it would be a bit broken not to support that as well.
We could, I suppose, enable all detected extensions on a CPU and run the aforemention callback, disabling them if conditions are not met?
Is that something like what you're suggesting?
Yep, exactly. First parse the ISA blindly in a bitmap, (either from riscv,isa string, riscv,isa-extensions, or ACPI). Then in a second time, verify the ISA extensions by validating extension and looping until we reach a stable set.
Clément
The Zc* standard extension for code reduction introduces new extensions. This patch adds support for Zca, Zcf, Zcd and Zcb. Zce, Zcmt and Zcmp are left out of this patch since they are targeting microcontrollers/ embedded CPUs instead of application processors.
Signed-off-by: Clément Léger cleger@rivosinc.com --- arch/riscv/include/asm/hwcap.h | 4 ++++ arch/riscv/kernel/cpufeature.c | 4 ++++ 2 files changed, 8 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 543e3ea2da0e..b7551bad341b 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -82,6 +82,10 @@ #define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_XANDESPMU 74 #define RISCV_ISA_EXT_ZIMOP 75 +#define RISCV_ISA_EXT_ZCA 76 +#define RISCV_ISA_EXT_ZCB 77 +#define RISCV_ISA_EXT_ZCD 78 +#define RISCV_ISA_EXT_ZCF 79
#define RISCV_ISA_EXT_XLINUXENVCFG 127
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 115ba001f1bc..09dee071274d 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -261,6 +261,10 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), + __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA), + __RISCV_ISA_EXT_DATA(zcb, RISCV_ISA_EXT_ZCB), + __RISCV_ISA_EXT_DATA(zcd, RISCV_ISA_EXT_ZCD), + __RISCV_ISA_EXT_DATA(zcf, RISCV_ISA_EXT_ZCF), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
On Thu, Apr 18, 2024 at 02:42:27PM +0200, Clément Léger wrote:
The Zc* standard extension for code reduction introduces new extensions. This patch adds support for Zca, Zcf, Zcd and Zcb. Zce, Zcmt and Zcmp are left out of this patch since they are targeting microcontrollers/ embedded CPUs instead of application processors.
Signed-off-by: Clément Léger cleger@rivosinc.com
arch/riscv/include/asm/hwcap.h | 4 ++++ arch/riscv/kernel/cpufeature.c | 4 ++++ 2 files changed, 8 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 543e3ea2da0e..b7551bad341b 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -82,6 +82,10 @@ #define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_XANDESPMU 74 #define RISCV_ISA_EXT_ZIMOP 75 +#define RISCV_ISA_EXT_ZCA 76 +#define RISCV_ISA_EXT_ZCB 77 +#define RISCV_ISA_EXT_ZCD 78 +#define RISCV_ISA_EXT_ZCF 79 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 115ba001f1bc..09dee071274d 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -261,6 +261,10 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
- __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA),
- __RISCV_ISA_EXT_DATA(zcb, RISCV_ISA_EXT_ZCB),
- __RISCV_ISA_EXT_DATA(zcd, RISCV_ISA_EXT_ZCD),
- __RISCV_ISA_EXT_DATA(zcf, RISCV_ISA_EXT_ZCF), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
Ye, this looks exactly like what I "feared".
On 19/04/2024 17:51, Conor Dooley wrote:
On Thu, Apr 18, 2024 at 02:42:27PM +0200, Clément Léger wrote:
The Zc* standard extension for code reduction introduces new extensions. This patch adds support for Zca, Zcf, Zcd and Zcb. Zce, Zcmt and Zcmp are left out of this patch since they are targeting microcontrollers/ embedded CPUs instead of application processors.
Signed-off-by: Clément Léger cleger@rivosinc.com
arch/riscv/include/asm/hwcap.h | 4 ++++ arch/riscv/kernel/cpufeature.c | 4 ++++ 2 files changed, 8 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 543e3ea2da0e..b7551bad341b 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -82,6 +82,10 @@ #define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_XANDESPMU 74 #define RISCV_ISA_EXT_ZIMOP 75 +#define RISCV_ISA_EXT_ZCA 76 +#define RISCV_ISA_EXT_ZCB 77 +#define RISCV_ISA_EXT_ZCD 78 +#define RISCV_ISA_EXT_ZCF 79 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 115ba001f1bc..09dee071274d 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -261,6 +261,10 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
- __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA),
- __RISCV_ISA_EXT_DATA(zcb, RISCV_ISA_EXT_ZCB),
- __RISCV_ISA_EXT_DATA(zcd, RISCV_ISA_EXT_ZCD),
- __RISCV_ISA_EXT_DATA(zcf, RISCV_ISA_EXT_ZCF), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
Ye, this looks exactly like what I "feared".
Ok but for instance, Qemu actually set Zc* based on C/F/D. So the ISA string containing theses dependencies should actually also be allowed. So should we simply ignore them in the ISA string and always do our own "post-processing" based on C/F/D ?
Thanks,
Clément
On Mon, Apr 22, 2024 at 10:53:10AM +0200, Clément Léger wrote:
On 19/04/2024 17:51, Conor Dooley wrote:
On Thu, Apr 18, 2024 at 02:42:27PM +0200, Clément Léger wrote:
The Zc* standard extension for code reduction introduces new extensions. This patch adds support for Zca, Zcf, Zcd and Zcb. Zce, Zcmt and Zcmp are left out of this patch since they are targeting microcontrollers/ embedded CPUs instead of application processors.
Signed-off-by: Clément Léger cleger@rivosinc.com
arch/riscv/include/asm/hwcap.h | 4 ++++ arch/riscv/kernel/cpufeature.c | 4 ++++ 2 files changed, 8 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 543e3ea2da0e..b7551bad341b 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -82,6 +82,10 @@ #define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_XANDESPMU 74 #define RISCV_ISA_EXT_ZIMOP 75 +#define RISCV_ISA_EXT_ZCA 76 +#define RISCV_ISA_EXT_ZCB 77 +#define RISCV_ISA_EXT_ZCD 78 +#define RISCV_ISA_EXT_ZCF 79 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 115ba001f1bc..09dee071274d 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -261,6 +261,10 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
- __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA),
- __RISCV_ISA_EXT_DATA(zcb, RISCV_ISA_EXT_ZCB),
- __RISCV_ISA_EXT_DATA(zcd, RISCV_ISA_EXT_ZCD),
- __RISCV_ISA_EXT_DATA(zcf, RISCV_ISA_EXT_ZCF), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
Ye, this looks exactly like what I "feared".
Ok but for instance, Qemu actually set Zc* based on C/F/D. So the ISA string containing theses dependencies should actually also be allowed. So should we simply ignore them in the ISA string and always do our own "post-processing" based on C/F/D?
I'm not familiar with the contents of all of these extensions, but I assume the reasoning for splitting them out is that you can implement them but not maybe not implement C (or something similar)? If that's the case, you cannot always imply.
On 22/04/2024 11:35, Conor Dooley wrote:
On Mon, Apr 22, 2024 at 10:53:10AM +0200, Clément Léger wrote:
On 19/04/2024 17:51, Conor Dooley wrote:
On Thu, Apr 18, 2024 at 02:42:27PM +0200, Clément Léger wrote:
The Zc* standard extension for code reduction introduces new extensions. This patch adds support for Zca, Zcf, Zcd and Zcb. Zce, Zcmt and Zcmp are left out of this patch since they are targeting microcontrollers/ embedded CPUs instead of application processors.
Signed-off-by: Clément Léger cleger@rivosinc.com
arch/riscv/include/asm/hwcap.h | 4 ++++ arch/riscv/kernel/cpufeature.c | 4 ++++ 2 files changed, 8 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 543e3ea2da0e..b7551bad341b 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -82,6 +82,10 @@ #define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_XANDESPMU 74 #define RISCV_ISA_EXT_ZIMOP 75 +#define RISCV_ISA_EXT_ZCA 76 +#define RISCV_ISA_EXT_ZCB 77 +#define RISCV_ISA_EXT_ZCD 78 +#define RISCV_ISA_EXT_ZCF 79 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 115ba001f1bc..09dee071274d 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -261,6 +261,10 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
- __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA),
- __RISCV_ISA_EXT_DATA(zcb, RISCV_ISA_EXT_ZCB),
- __RISCV_ISA_EXT_DATA(zcd, RISCV_ISA_EXT_ZCD),
- __RISCV_ISA_EXT_DATA(zcf, RISCV_ISA_EXT_ZCF), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
Ye, this looks exactly like what I "feared".
Ok but for instance, Qemu actually set Zc* based on C/F/D. So the ISA string containing theses dependencies should actually also be allowed. So should we simply ignore them in the ISA string and always do our own "post-processing" based on C/F/D?
I'm not familiar with the contents of all of these extensions, but I assume the reasoning for splitting them out is that you can implement them but not maybe not implement C (or something similar)? If that's the case, you cannot always imply.
Yeah, they can be implemented independently so we need to be able to parse them independently. However, the kernel currently requires C so we should always have Zca/Zcf/Zcd. But if that changes in the future, then, that won't be true anymore. Better keep it generic probably
Clément
On Mon, Apr 22, 2024 at 01:14:26PM +0200, Clément Léger wrote:
On 22/04/2024 11:35, Conor Dooley wrote:
On Mon, Apr 22, 2024 at 10:53:10AM +0200, Clément Léger wrote:
On 19/04/2024 17:51, Conor Dooley wrote:
On Thu, Apr 18, 2024 at 02:42:27PM +0200, Clément Léger wrote:
The Zc* standard extension for code reduction introduces new extensions. This patch adds support for Zca, Zcf, Zcd and Zcb. Zce, Zcmt and Zcmp are left out of this patch since they are targeting microcontrollers/ embedded CPUs instead of application processors.
Signed-off-by: Clément Léger cleger@rivosinc.com
arch/riscv/include/asm/hwcap.h | 4 ++++ arch/riscv/kernel/cpufeature.c | 4 ++++ 2 files changed, 8 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 543e3ea2da0e..b7551bad341b 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -82,6 +82,10 @@ #define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_XANDESPMU 74 #define RISCV_ISA_EXT_ZIMOP 75 +#define RISCV_ISA_EXT_ZCA 76 +#define RISCV_ISA_EXT_ZCB 77 +#define RISCV_ISA_EXT_ZCD 78 +#define RISCV_ISA_EXT_ZCF 79 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 115ba001f1bc..09dee071274d 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -261,6 +261,10 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
- __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA),
- __RISCV_ISA_EXT_DATA(zcb, RISCV_ISA_EXT_ZCB),
- __RISCV_ISA_EXT_DATA(zcd, RISCV_ISA_EXT_ZCD),
- __RISCV_ISA_EXT_DATA(zcf, RISCV_ISA_EXT_ZCF), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
Ye, this looks exactly like what I "feared".
Ok but for instance, Qemu actually set Zc* based on C/F/D. So the ISA string containing theses dependencies should actually also be allowed. So should we simply ignore them in the ISA string and always do our own "post-processing" based on C/F/D?
I'm not familiar with the contents of all of these extensions, but I assume the reasoning for splitting them out is that you can implement them but not maybe not implement C (or something similar)? If that's the case, you cannot always imply.
Yeah, they can be implemented independently so we need to be able to parse them independently.
However, the kernel currently requires C
No it doesn't! There's a Kconfig option that controls whether or not we build with compressed instructions.
so we should always have Zca/Zcf/Zcd. But if that changes in the future, then, that won't be true anymore. Better keep it generic probably
On 22/04/2024 13:36, Conor Dooley wrote:
On Mon, Apr 22, 2024 at 01:14:26PM +0200, Clément Léger wrote:
On 22/04/2024 11:35, Conor Dooley wrote:
On Mon, Apr 22, 2024 at 10:53:10AM +0200, Clément Léger wrote:
On 19/04/2024 17:51, Conor Dooley wrote:
On Thu, Apr 18, 2024 at 02:42:27PM +0200, Clément Léger wrote:
The Zc* standard extension for code reduction introduces new extensions. This patch adds support for Zca, Zcf, Zcd and Zcb. Zce, Zcmt and Zcmp are left out of this patch since they are targeting microcontrollers/ embedded CPUs instead of application processors.
Signed-off-by: Clément Léger cleger@rivosinc.com
arch/riscv/include/asm/hwcap.h | 4 ++++ arch/riscv/kernel/cpufeature.c | 4 ++++ 2 files changed, 8 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 543e3ea2da0e..b7551bad341b 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -82,6 +82,10 @@ #define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_XANDESPMU 74 #define RISCV_ISA_EXT_ZIMOP 75 +#define RISCV_ISA_EXT_ZCA 76 +#define RISCV_ISA_EXT_ZCB 77 +#define RISCV_ISA_EXT_ZCD 78 +#define RISCV_ISA_EXT_ZCF 79 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 115ba001f1bc..09dee071274d 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -261,6 +261,10 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
- __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA),
- __RISCV_ISA_EXT_DATA(zcb, RISCV_ISA_EXT_ZCB),
- __RISCV_ISA_EXT_DATA(zcd, RISCV_ISA_EXT_ZCD),
- __RISCV_ISA_EXT_DATA(zcf, RISCV_ISA_EXT_ZCF), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
Ye, this looks exactly like what I "feared".
Ok but for instance, Qemu actually set Zc* based on C/F/D. So the ISA string containing theses dependencies should actually also be allowed. So should we simply ignore them in the ISA string and always do our own "post-processing" based on C/F/D?
I'm not familiar with the contents of all of these extensions, but I assume the reasoning for splitting them out is that you can implement them but not maybe not implement C (or something similar)? If that's the case, you cannot always imply.
Yeah, they can be implemented independently so we need to be able to parse them independently.
However, the kernel currently requires C
No it doesn't! There's a Kconfig option that controls whether or not we build with compressed instructions.
Acked, missed that. That is then advocating to keep separate Zc* extensions.
so we should always have Zca/Zcf/Zcd. But if that changes in the future, then, that won't be true anymore. Better keep it generic probably
Export Zca, Zcf, Zcd and Zcb ISA extension through hwprobe.
Signed-off-by: Clément Léger cleger@rivosinc.com --- Documentation/arch/riscv/hwprobe.rst | 20 ++++++++++++++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 4 ++++ arch/riscv/kernel/sys_hwprobe.c | 4 ++++ 3 files changed, 28 insertions(+)
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index 9ca5b093b6d5..bf96b4e8ba3b 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -192,6 +192,26 @@ The following keys are defined: supported as defined in the RISC-V ISA manual starting from commit 58220614a5f ("Zimop is ratified/1.0").
+ * :c:macro:`RISCV_HWPROBE_EXT_ZCA`: The Zca extension part of Zc* standard + extensions for code size reduction, as ratified in commit 8be3419c1c0 + ("Zcf doesn't exist on RV64 as it contains no instructions") of + riscv-code-size-reduction. + + * :c:macro:`RISCV_HWPROBE_EXT_ZCB`: The Zcb extension part of Zc* standard + extensions for code size reduction, as ratified in commit 8be3419c1c0 + ("Zcf doesn't exist on RV64 as it contains no instructions") of + riscv-code-size-reduction. + + * :c:macro:`RISCV_HWPROBE_EXT_ZCD`: The Zcd extension part of Zc* standard + extensions for code size reduction, as ratified in commit 8be3419c1c0 + ("Zcf doesn't exist on RV64 as it contains no instructions") of + riscv-code-size-reduction. + + * :c:macro:`RISCV_HWPROBE_EXT_ZCF`: The Zcf extension part of Zc* standard + extensions for code size reduction, as ratified in commit 8be3419c1c0 + ("Zcf doesn't exist on RV64 as it contains no instructions") of + riscv-code-size-reduction. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index ac6874ab743a..dd4ad77faf49 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -60,6 +60,10 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34) #define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35) #define RISCV_HWPROBE_EXT_ZIMOP (1ULL << 36) +#define RISCV_HWPROBE_EXT_ZCA (1ULL << 37) +#define RISCV_HWPROBE_EXT_ZCB (1ULL << 38) +#define RISCV_HWPROBE_EXT_ZCD (1ULL << 39) +#define RISCV_HWPROBE_EXT_ZCF (1ULL << 40) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index c99a4cf231c5..2ffa0fe5101e 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -112,6 +112,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZACAS); EXT_KEY(ZICOND); EXT_KEY(ZIMOP); + EXT_KEY(ZCA); + EXT_KEY(ZCB);
if (has_vector()) { EXT_KEY(ZVBB); @@ -132,6 +134,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZFH); EXT_KEY(ZFHMIN); EXT_KEY(ZFA); + EXT_KEY(ZCD); + EXT_KEY(ZCF); } #undef EXT_KEY }
Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zca, Zcf, Zcd and Zcb extensions for Guest/VM.
Signed-off-by: Clément Léger cleger@rivosinc.com --- arch/riscv/include/uapi/asm/kvm.h | 4 ++++ arch/riscv/kvm/vcpu_onereg.c | 8 ++++++++ 2 files changed, 12 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 35a12aa1953e..57db3fea679f 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -168,6 +168,10 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZTSO, KVM_RISCV_ISA_EXT_ZACAS, KVM_RISCV_ISA_EXT_ZIMOP, + KVM_RISCV_ISA_EXT_ZCA, + KVM_RISCV_ISA_EXT_ZCB, + KVM_RISCV_ISA_EXT_ZCD, + KVM_RISCV_ISA_EXT_ZCF, KVM_RISCV_ISA_EXT_MAX, };
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 12436f6f0d20..a2747a6dbdb6 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -48,6 +48,10 @@ static const unsigned long kvm_isa_ext_arr[] = { KVM_ISA_EXT_ARR(ZBKC), KVM_ISA_EXT_ARR(ZBKX), KVM_ISA_EXT_ARR(ZBS), + KVM_ISA_EXT_ARR(ZCA), + KVM_ISA_EXT_ARR(ZCB), + KVM_ISA_EXT_ARR(ZCD), + KVM_ISA_EXT_ARR(ZCF), KVM_ISA_EXT_ARR(ZFA), KVM_ISA_EXT_ARR(ZFH), KVM_ISA_EXT_ARR(ZFHMIN), @@ -128,6 +132,10 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) case KVM_RISCV_ISA_EXT_ZBKC: case KVM_RISCV_ISA_EXT_ZBKX: case KVM_RISCV_ISA_EXT_ZBS: + case KVM_RISCV_ISA_EXT_ZCA: + case KVM_RISCV_ISA_EXT_ZCB: + case KVM_RISCV_ISA_EXT_ZCD: + case KVM_RISCV_ISA_EXT_ZCF: case KVM_RISCV_ISA_EXT_ZFA: case KVM_RISCV_ISA_EXT_ZFH: case KVM_RISCV_ISA_EXT_ZFHMIN:
On Thu, Apr 18, 2024 at 6:14 PM Clément Léger cleger@rivosinc.com wrote:
Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zca, Zcf, Zcd and Zcb extensions for Guest/VM.
Signed-off-by: Clément Léger cleger@rivosinc.com
LGTM.
Reviewed-by: Anup Patel anup@brainfault.org Acked-by: Anup Patel anup@brainfault.org
Thanks, Anup
arch/riscv/include/uapi/asm/kvm.h | 4 ++++ arch/riscv/kvm/vcpu_onereg.c | 8 ++++++++ 2 files changed, 12 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 35a12aa1953e..57db3fea679f 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -168,6 +168,10 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZTSO, KVM_RISCV_ISA_EXT_ZACAS, KVM_RISCV_ISA_EXT_ZIMOP,
KVM_RISCV_ISA_EXT_ZCA,KVM_RISCV_ISA_EXT_ZCB,KVM_RISCV_ISA_EXT_ZCD,KVM_RISCV_ISA_EXT_ZCF, KVM_RISCV_ISA_EXT_MAX,};
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 12436f6f0d20..a2747a6dbdb6 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -48,6 +48,10 @@ static const unsigned long kvm_isa_ext_arr[] = { KVM_ISA_EXT_ARR(ZBKC), KVM_ISA_EXT_ARR(ZBKX), KVM_ISA_EXT_ARR(ZBS),
KVM_ISA_EXT_ARR(ZCA),KVM_ISA_EXT_ARR(ZCB),KVM_ISA_EXT_ARR(ZCD),KVM_ISA_EXT_ARR(ZCF), KVM_ISA_EXT_ARR(ZFA), KVM_ISA_EXT_ARR(ZFH), KVM_ISA_EXT_ARR(ZFHMIN),@@ -128,6 +132,10 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) case KVM_RISCV_ISA_EXT_ZBKC: case KVM_RISCV_ISA_EXT_ZBKX: case KVM_RISCV_ISA_EXT_ZBS:
case KVM_RISCV_ISA_EXT_ZCA:case KVM_RISCV_ISA_EXT_ZCB:case KVM_RISCV_ISA_EXT_ZCD:case KVM_RISCV_ISA_EXT_ZCF: case KVM_RISCV_ISA_EXT_ZFA: case KVM_RISCV_ISA_EXT_ZFH: case KVM_RISCV_ISA_EXT_ZFHMIN:-- 2.43.0
The KVM RISC-V allows Zca, Zcf, Zcd and Zcb extensions for Guest/VM so add these extensions to get-reg-list test.
Signed-off-by: Clément Léger cleger@rivosinc.com --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 40107bb61975..61cad4514197 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -55,6 +55,10 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKC: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKX: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBS: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCA: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCB: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCD: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCF: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFA: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN: @@ -421,6 +425,10 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off) KVM_ISA_EXT_ARR(ZBKC), KVM_ISA_EXT_ARR(ZBKX), KVM_ISA_EXT_ARR(ZBS), + KVM_ISA_EXT_ARR(ZCA), + KVM_ISA_EXT_ARR(ZCB), + KVM_ISA_EXT_ARR(ZCD), + KVM_ISA_EXT_ARR(ZCF), KVM_ISA_EXT_ARR(ZFA), KVM_ISA_EXT_ARR(ZFH), KVM_ISA_EXT_ARR(ZFHMIN), @@ -945,6 +953,10 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zbkb, ZBKB); KVM_ISA_EXT_SIMPLE_CONFIG(zbkc, ZBKC); KVM_ISA_EXT_SIMPLE_CONFIG(zbkx, ZBKX); KVM_ISA_EXT_SIMPLE_CONFIG(zbs, ZBS); +KVM_ISA_EXT_SIMPLE_CONFIG(zca, ZCA), +KVM_ISA_EXT_SIMPLE_CONFIG(zcb, ZCB), +KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD), +KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF), KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA); KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH); KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN); @@ -1001,6 +1013,10 @@ struct vcpu_reg_list *vcpu_configs[] = { &config_zbkc, &config_zbkx, &config_zbs, + &config_zca, + &config_zcb, + &config_zcd, + &config_zcf, &config_zfa, &config_zfh, &config_zfhmin,
On Thu, Apr 18, 2024 at 6:14 PM Clément Léger cleger@rivosinc.com wrote:
The KVM RISC-V allows Zca, Zcf, Zcd and Zcb extensions for Guest/VM so add these extensions to get-reg-list test.
Signed-off-by: Clément Léger cleger@rivosinc.com
LGTM.
Reviewed-by: Anup Patel anup@brainfault.org Acked-by: Anup Patel anup@brainfault.org
Thanks, Anup
tools/testing/selftests/kvm/riscv/get-reg-list.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 40107bb61975..61cad4514197 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -55,6 +55,10 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKC: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKX: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBS:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCA:case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCB:case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCD:case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCF: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFA: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN:@@ -421,6 +425,10 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off) KVM_ISA_EXT_ARR(ZBKC), KVM_ISA_EXT_ARR(ZBKX), KVM_ISA_EXT_ARR(ZBS),
KVM_ISA_EXT_ARR(ZCA),KVM_ISA_EXT_ARR(ZCB),KVM_ISA_EXT_ARR(ZCD),KVM_ISA_EXT_ARR(ZCF), KVM_ISA_EXT_ARR(ZFA), KVM_ISA_EXT_ARR(ZFH), KVM_ISA_EXT_ARR(ZFHMIN),@@ -945,6 +953,10 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zbkb, ZBKB); KVM_ISA_EXT_SIMPLE_CONFIG(zbkc, ZBKC); KVM_ISA_EXT_SIMPLE_CONFIG(zbkx, ZBKX); KVM_ISA_EXT_SIMPLE_CONFIG(zbs, ZBS); +KVM_ISA_EXT_SIMPLE_CONFIG(zca, ZCA), +KVM_ISA_EXT_SIMPLE_CONFIG(zcb, ZCB), +KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD), +KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF), KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA); KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH); KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN); @@ -1001,6 +1013,10 @@ struct vcpu_reg_list *vcpu_configs[] = { &config_zbkc, &config_zbkx, &config_zbs,
&config_zca,&config_zcb,&config_zcd,&config_zcf, &config_zfa, &config_zfh, &config_zfhmin,-- 2.43.0
Add description for the Zcmop (Compressed May-Be-Operations) ISA extension which was ratified in commit c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual.
Signed-off-by: Clément Léger cleger@rivosinc.com --- .../devicetree/bindings/riscv/extensions.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 0172cbaa13ca..a0113cb46893 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -252,6 +252,11 @@ properties: merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed of zc.adoc to src tree.").
+ - const: zcmop + description: + The standard Zcmop extension version 1.0, as ratified in commit + c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual. + - const: zfa description: The standard Zfa extension for additional floating point @@ -566,6 +571,13 @@ properties: then: contains: const: zcd + # Zcmop depends on Zca + - if: + contains: + const: zcmop + then: + contains: + const: zca
allOf: # Zcf extension does not exists on rv64
On Thu, Apr 18, 2024 at 02:42:31PM +0200, Clément Léger wrote:
Add description for the Zcmop (Compressed May-Be-Operations) ISA extension which was ratified in commit c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual.
Acked-by: Conor Dooley conor.dooley@microchip.com
Add parsing for Zcmop ISA extension which was ratified in commit b854a709c00 ("Zcmop is ratified/1.0") of the riscv-isa-manual.
Signed-off-by: Clément Léger cleger@rivosinc.com --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index b7551bad341b..cff7660de268 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -86,6 +86,7 @@ #define RISCV_ISA_EXT_ZCB 77 #define RISCV_ISA_EXT_ZCD 78 #define RISCV_ISA_EXT_ZCF 79 +#define RISCV_ISA_EXT_ZCMOP 80
#define RISCV_ISA_EXT_XLINUXENVCFG 127
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 09dee071274d..f1450cd7231e 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -265,6 +265,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zcb, RISCV_ISA_EXT_ZCB), __RISCV_ISA_EXT_DATA(zcd, RISCV_ISA_EXT_ZCD), __RISCV_ISA_EXT_DATA(zcf, RISCV_ISA_EXT_ZCF), + __RISCV_ISA_EXT_DATA(zcmop, RISCV_ISA_EXT_ZCMOP), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
Export Zcmop ISA extension through hwprobe.
Signed-off-by: Clément Léger cleger@rivosinc.com --- Documentation/arch/riscv/hwprobe.rst | 4 ++++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_hwprobe.c | 1 + 3 files changed, 6 insertions(+)
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index bf96b4e8ba3b..e3187659a077 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -212,6 +212,10 @@ The following keys are defined: ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction.
+ * :c:macro:`RISCV_HWPROBE_EXT_ZCMOP`: The Zcmop May-Be-Operations extension is + supported as defined in the RISC-V ISA manual starting from commit + c732a4f39a4 ("Zcmop is ratified/1.0"). + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index dd4ad77faf49..d97ac5436447 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -64,6 +64,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZCB (1ULL << 38) #define RISCV_HWPROBE_EXT_ZCD (1ULL << 39) #define RISCV_HWPROBE_EXT_ZCF (1ULL << 40) +#define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 41) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index 2ffa0fe5101e..9457231bd1c0 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -114,6 +114,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZIMOP); EXT_KEY(ZCA); EXT_KEY(ZCB); + EXT_KEY(ZCMOP);
if (has_vector()) { EXT_KEY(ZVBB);
Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zcmop extension for Guest/VM.
Signed-off-by: Clément Léger cleger@rivosinc.com --- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu_onereg.c | 2 ++ 2 files changed, 3 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 57db3fea679f..0366389a0bae 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -172,6 +172,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZCB, KVM_RISCV_ISA_EXT_ZCD, KVM_RISCV_ISA_EXT_ZCF, + KVM_RISCV_ISA_EXT_ZCMOP, KVM_RISCV_ISA_EXT_MAX, };
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index a2747a6dbdb6..77a0d337faeb 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -52,6 +52,7 @@ static const unsigned long kvm_isa_ext_arr[] = { KVM_ISA_EXT_ARR(ZCB), KVM_ISA_EXT_ARR(ZCD), KVM_ISA_EXT_ARR(ZCF), + KVM_ISA_EXT_ARR(ZCMOP), KVM_ISA_EXT_ARR(ZFA), KVM_ISA_EXT_ARR(ZFH), KVM_ISA_EXT_ARR(ZFHMIN), @@ -136,6 +137,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) case KVM_RISCV_ISA_EXT_ZCB: case KVM_RISCV_ISA_EXT_ZCD: case KVM_RISCV_ISA_EXT_ZCF: + case KVM_RISCV_ISA_EXT_ZCMOP: case KVM_RISCV_ISA_EXT_ZFA: case KVM_RISCV_ISA_EXT_ZFH: case KVM_RISCV_ISA_EXT_ZFHMIN:
On Thu, Apr 18, 2024 at 6:14 PM Clément Léger cleger@rivosinc.com wrote:
Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zcmop extension for Guest/VM.
Signed-off-by: Clément Léger cleger@rivosinc.com
LGTM.
Reviewed-by: Anup Patel anup@brainfault.org Acked-by: Anup Patel anup@brainfault.org
Thanks, Anup
arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu_onereg.c | 2 ++ 2 files changed, 3 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 57db3fea679f..0366389a0bae 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -172,6 +172,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZCB, KVM_RISCV_ISA_EXT_ZCD, KVM_RISCV_ISA_EXT_ZCF,
KVM_RISCV_ISA_EXT_ZCMOP, KVM_RISCV_ISA_EXT_MAX,};
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index a2747a6dbdb6..77a0d337faeb 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -52,6 +52,7 @@ static const unsigned long kvm_isa_ext_arr[] = { KVM_ISA_EXT_ARR(ZCB), KVM_ISA_EXT_ARR(ZCD), KVM_ISA_EXT_ARR(ZCF),
KVM_ISA_EXT_ARR(ZCMOP), KVM_ISA_EXT_ARR(ZFA), KVM_ISA_EXT_ARR(ZFH), KVM_ISA_EXT_ARR(ZFHMIN),@@ -136,6 +137,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) case KVM_RISCV_ISA_EXT_ZCB: case KVM_RISCV_ISA_EXT_ZCD: case KVM_RISCV_ISA_EXT_ZCF:
case KVM_RISCV_ISA_EXT_ZCMOP: case KVM_RISCV_ISA_EXT_ZFA: case KVM_RISCV_ISA_EXT_ZFH: case KVM_RISCV_ISA_EXT_ZFHMIN:-- 2.43.0
The KVM RISC-V allows Zcmop extension for Guest/VM so add this extension to get-reg-list test.
Signed-off-by: Clément Léger cleger@rivosinc.com --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 61cad4514197..9604c8ece787 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -59,6 +59,7 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCB: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCD: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCF: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCMOP: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFA: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN: @@ -429,6 +430,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off) KVM_ISA_EXT_ARR(ZCB), KVM_ISA_EXT_ARR(ZCD), KVM_ISA_EXT_ARR(ZCF), + KVM_ISA_EXT_ARR(ZCMOP), KVM_ISA_EXT_ARR(ZFA), KVM_ISA_EXT_ARR(ZFH), KVM_ISA_EXT_ARR(ZFHMIN), @@ -957,6 +959,7 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zca, ZCA), KVM_ISA_EXT_SIMPLE_CONFIG(zcb, ZCB), KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD), KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF), +KVM_ISA_EXT_SIMPLE_CONFIG(zcmop, ZCMOP); KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA); KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH); KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN); @@ -1017,6 +1020,7 @@ struct vcpu_reg_list *vcpu_configs[] = { &config_zcb, &config_zcd, &config_zcf, + &config_zcmop, &config_zfa, &config_zfh, &config_zfhmin,
On Thu, Apr 18, 2024 at 6:14 PM Clément Léger cleger@rivosinc.com wrote:
The KVM RISC-V allows Zcmop extension for Guest/VM so add this extension to get-reg-list test.
Signed-off-by: Clément Léger cleger@rivosinc.com
LGTM.
Reviewed-by: Anup Patel anup@brainfault.org Acked-by: Anup Patel anup@brainfault.org
Thanks, Anup
tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 61cad4514197..9604c8ece787 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -59,6 +59,7 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCB: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCD: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCF:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCMOP: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFA: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN:@@ -429,6 +430,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off) KVM_ISA_EXT_ARR(ZCB), KVM_ISA_EXT_ARR(ZCD), KVM_ISA_EXT_ARR(ZCF),
KVM_ISA_EXT_ARR(ZCMOP), KVM_ISA_EXT_ARR(ZFA), KVM_ISA_EXT_ARR(ZFH), KVM_ISA_EXT_ARR(ZFHMIN),@@ -957,6 +959,7 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zca, ZCA), KVM_ISA_EXT_SIMPLE_CONFIG(zcb, ZCB), KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD), KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF), +KVM_ISA_EXT_SIMPLE_CONFIG(zcmop, ZCMOP); KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA); KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH); KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN); @@ -1017,6 +1020,7 @@ struct vcpu_reg_list *vcpu_configs[] = { &config_zcb, &config_zcd, &config_zcf,
&config_zcmop, &config_zfa, &config_zfh, &config_zfhmin,-- 2.43.0
Hi Palmer,
On Thu, Apr 18, 2024 at 6:13 PM Clément Léger cleger@rivosinc.com wrote:
Add support for (yet again) more RVA23U64 missing extensions. Add support for Zcmop, Zca, Zcf, Zcd and Zcb extensions isa string parsing, hwprobe and kvm support. Zce, Zcmt and Zcmp extensions have been left out since they target microcontrollers/embedded CPUs and are not needed by RVA23U64
This series is based on the Zimop one [1].
Link: https://lore.kernel.org/linux-riscv/20240404103254.1752834-1-cleger@rivosinc... [1]
v2:
- Add Zc* dependencies validation in dt-bindings
- v1: https://lore.kernel.org/lkml/20240410091106.749233-1-cleger@rivosinc.com/
Clément Léger (12): dt-bindings: riscv: add Zca, Zcf, Zcd and Zcb ISA extension description riscv: dts: enable Zc* extensions when needed dt-bindings: riscv: add Zc* extension rules implied by C extension riscv: add ISA parsing for Zca, Zcf, Zcd and Zcb riscv: hwprobe: export Zca, Zcf, Zcd and Zcb ISA extensions RISC-V: KVM: Allow Zca, Zcf, Zcd and Zcb extensions for Guest/VM KVM: riscv: selftests: Add some Zc* extensions to get-reg-list test dt-bindings: riscv: add Zcmop ISA extension description riscv: add ISA extension parsing for Zcmop riscv: hwprobe: export Zcmop ISA extension RISC-V: KVM: Allow Zcmop extension for Guest/VM KVM: riscv: selftests: Add Zcmop extension to get-reg-list test
Documentation/arch/riscv/hwprobe.rst | 24 ++ .../devicetree/bindings/riscv/cpus.yaml | 8 +- .../devicetree/bindings/riscv/extensions.yaml | 124 +++++++++ arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 4 +- arch/riscv/boot/dts/microchip/mpfs.dtsi | 20 +- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 +- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 20 +- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 20 +- arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 4 +- arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 256 +++++++++--------- arch/riscv/boot/dts/starfive/jh7100.dtsi | 8 +- arch/riscv/boot/dts/starfive/jh7110.dtsi | 20 +- arch/riscv/boot/dts/thead/th1520.dtsi | 16 +- arch/riscv/include/asm/hwcap.h | 5 + arch/riscv/include/uapi/asm/hwprobe.h | 5 + arch/riscv/include/uapi/asm/kvm.h | 5 + arch/riscv/kernel/cpufeature.c | 5 + arch/riscv/kernel/sys_hwprobe.c | 5 + arch/riscv/kvm/vcpu_onereg.c | 10 + .../selftests/kvm/riscv/get-reg-list.c | 20 ++ 20 files changed, 394 insertions(+), 189 deletions(-)
-- 2.43.0
Most likely the KVM RISC-V related changes in this series will conflict with the KVM RISC-V repo.
I will provide a shared tag based on 6.9-rc3 tomorrow or early next week.
Regards, Anup
linux-kselftest-mirror@lists.linaro.org
-
Anup Patel -
Clément Léger -
Conor Dooley -
Conor Dooley