[CI-NOTIFY]: TCWG Bisect tcwg_gcc_bootstrap/master-arm-bootstrap_O3 - Build # 2 - Successful! - linaro-toolchain

2 Sep 2021

Successfully identified regression in *gcc* in CI configuration tcwg_gcc_bootstrap/master-arm-bootstrap_O3.  So far, this commit has regressed CI configurations:
 - tcwg_gcc_bootstrap/master-arm-bootstrap_O3
Culprit:
<cut>
commit cad36f38576a6a781e3c62ab061c68f5b8dab13a
Author: Roger Sayle roger@nextmovesoftware.com
Date:   Tue Aug 31 11:45:07 2021 +0100
Preserve SUBREG_PROMOTED_VAR_P on (extend:HI (subreg/s:QI (reg:SI))).
SUBREG_PROMOTED_VAR_P is a mechanism for tracking that a partial subreg
    is correctly zero-extended or sign-extended in the parent register.  For
    example, the RTL (subreg/s/v:QI (reg/v:SI 23 [ x ]) 0) indicates that the
    byte x is zero extended in reg:SI 23, which is useful for optimization.
    An example is that zero extending the above QImode value to HImode can
    simply use a wider subreg, i.e. (subreg:HI (reg/v:SI 23 [ x ]) 0).
This patch addresses the oversight/missed optimization opportunity that
    the new HImode subreg above should retain its SUBREG_PROMOTED_VAR_P
    annotation as its value is guaranteed to be correctly extended in the
    SImode parent.  The code below to preserve SUBREG_PROMOTED_VAR_P is already
    present in the middle-end (e.g. simplify-rtx.c:7232-7242) but missing
    from one or two (precisely three) places that (accidentally) strip it.
Whilst there I also added another optimization.  If we need to extend
    the above QImode value beyond the SImode register holding it, say to
    DImode, we can eliminate the SUBREG and simply extend from the SImode
    register to DImode.
2021-08-31  Roger Sayle  roger@nextmovesoftware.com
gcc/ChangeLog
            * expr.c (convert_modes): Preserve SUBREG_PROMOTED_VAR_P when
            creating a (wider) partial subreg from a SUBREG_PROMOTED_VAR_P
            subreg.
            * simplify-rtx.c (simplify_unary_operation_1) [SIGN_EXTEND]:
            Likewise, preserve SUBREG_PROMOTED_VAR_P when creating a (wider)
            partial subreg from a SUBREG_PROMOTED_VAR_P subreg.  Generate
            SIGN_EXTEND of the SUBREG_REG when a subreg would be paradoxical.
            [ZERO_EXTEND]: Likewise, preserve SUBREG_PROMOTED_VAR_P when
            creating a (wider) partial subreg from a SUBREG_PROMOTED_VAR_P
            subreg.  Generate ZERO_EXTEND of the SUBREG_REG when a subreg
            would be paradoxical.
</cut>
Results regressed to (for first_bad == cad36f38576a6a781e3c62ab061c68f5b8dab13a)
# reset_artifacts:
-10
# true:
0
# build_abe binutils:
1
# First few build errors in logs:
from (for last_good == 0960d937d9bee3c831d0b64a9c828c263a58ff89)
# reset_artifacts:
-10
# true:
0
# build_abe binutils:
1
# build_abe bootstrap_O3:
2
Artifacts of last_good build: https://ci.linaro.org/job/tcwg_gcc_bootstrap-bisect-master-arm-bootstrap_O3/...
Artifacts of first_bad build: https://ci.linaro.org/job/tcwg_gcc_bootstrap-bisect-master-arm-bootstrap_O3/...
Build top page/logs: https://ci.linaro.org/job/tcwg_gcc_bootstrap-bisect-master-arm-bootstrap_O3/...
Configuration details:
Reproduce builds:
<cut>
mkdir investigate-gcc-cad36f38576a6a781e3c62ab061c68f5b8dab13a
cd investigate-gcc-cad36f38576a6a781e3c62ab061c68f5b8dab13a
git clone https://git.linaro.org/toolchain/jenkins-scripts
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_gcc_bootstrap-bisect-master-arm-bootstrap_O3/... --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_gcc_bootstrap-bisect-master-arm-bootstrap_O3/... --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_gcc_bootstrap-bisect-master-arm-bootstrap_O3/... --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_gnu-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /gcc/ ./ ./bisect/baseline/
cd gcc
# Reproduce first_bad build
git checkout --detach cad36f38576a6a781e3c62ab061c68f5b8dab13a
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach 0960d937d9bee3c831d0b64a9c828c263a58ff89
../artifacts/test.sh
cd ..
</cut>
History of pending regressions and results: https://git.linaro.org/toolchain/ci/base-artifacts.git/log/?h=linaro-local/c...
Artifacts: https://ci.linaro.org/job/tcwg_gcc_bootstrap-bisect-master-arm-bootstrap_O3/...
Build log: https://ci.linaro.org/job/tcwg_gcc_bootstrap-bisect-master-arm-bootstrap_O3/...
Full commit (up to 1000 lines):
<cut>
commit cad36f38576a6a781e3c62ab061c68f5b8dab13a
Author: Roger Sayle roger@nextmovesoftware.com
Date:   Tue Aug 31 11:45:07 2021 +0100
Preserve SUBREG_PROMOTED_VAR_P on (extend:HI (subreg/s:QI (reg:SI))).
SUBREG_PROMOTED_VAR_P is a mechanism for tracking that a partial subreg
    is correctly zero-extended or sign-extended in the parent register.  For
    example, the RTL (subreg/s/v:QI (reg/v:SI 23 [ x ]) 0) indicates that the
    byte x is zero extended in reg:SI 23, which is useful for optimization.
    An example is that zero extending the above QImode value to HImode can
    simply use a wider subreg, i.e. (subreg:HI (reg/v:SI 23 [ x ]) 0).
This patch addresses the oversight/missed optimization opportunity that
    the new HImode subreg above should retain its SUBREG_PROMOTED_VAR_P
    annotation as its value is guaranteed to be correctly extended in the
    SImode parent.  The code below to preserve SUBREG_PROMOTED_VAR_P is already
    present in the middle-end (e.g. simplify-rtx.c:7232-7242) but missing
    from one or two (precisely three) places that (accidentally) strip it.
Whilst there I also added another optimization.  If we need to extend
    the above QImode value beyond the SImode register holding it, say to
    DImode, we can eliminate the SUBREG and simply extend from the SImode
    register to DImode.
2021-08-31  Roger Sayle  roger@nextmovesoftware.com
gcc/ChangeLog
            * expr.c (convert_modes): Preserve SUBREG_PROMOTED_VAR_P when
            creating a (wider) partial subreg from a SUBREG_PROMOTED_VAR_P
            subreg.
            * simplify-rtx.c (simplify_unary_operation_1) [SIGN_EXTEND]:
            Likewise, preserve SUBREG_PROMOTED_VAR_P when creating a (wider)
            partial subreg from a SUBREG_PROMOTED_VAR_P subreg.  Generate
            SIGN_EXTEND of the SUBREG_REG when a subreg would be paradoxical.
            [ZERO_EXTEND]: Likewise, preserve SUBREG_PROMOTED_VAR_P when
            creating a (wider) partial subreg from a SUBREG_PROMOTED_VAR_P
            subreg.  Generate ZERO_EXTEND of the SUBREG_REG when a subreg
            would be paradoxical.
---
 gcc/expr.c         | 19 ++++++++++++++++++-
 gcc/simplify-rtx.c | 52 ++++++++++++++++++++++++++++++++++++++++++----------
 2 files changed, 60 insertions(+), 11 deletions(-)

diff --git a/gcc/expr.c b/gcc/expr.c
index 096c0315ecc..5dd98a9bccc 100644
--- a/gcc/expr.c
+++ b/gcc/expr.c
@@ -688,7 +688,24 @@ convert_modes (machine_mode mode, machine_mode oldmode, rtx x, int unsignedp)
       && (GET_MODE_PRECISION (subreg_promoted_mode (x))
      >= GET_MODE_PRECISION (int_mode))
       && SUBREG_CHECK_PROMOTED_SIGN (x, unsignedp))
-    x = gen_lowpart (int_mode, SUBREG_REG (x));
+    {
+      scalar_int_mode int_orig_mode;
+      machine_mode orig_mode = GET_MODE (x);
+      x = gen_lowpart (int_mode, SUBREG_REG (x));
+
+      /* Preserve SUBREG_PROMOTED_VAR_P if the new mode is wider than
+	 the original mode, but narrower than the inner mode.  */
+      if (GET_CODE (x) == SUBREG
+	  && GET_MODE_PRECISION (subreg_promoted_mode (x))
+	     > GET_MODE_PRECISION (int_mode)
+	  && is_a <scalar_int_mode> (orig_mode, &int_orig_mode)
+	  && GET_MODE_PRECISION (int_mode)
+	     > GET_MODE_PRECISION (int_orig_mode))
+	{
+	  SUBREG_PROMOTED_VAR_P (x) = 1;
+	  SUBREG_PROMOTED_SET (x, unsignedp);
+	}
+    }
if (GET_MODE (x) != VOIDmode)
     oldmode = GET_MODE (x);
diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index e431e0c19d7..ebad5cb5a79 100644
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -1512,12 +1512,28 @@ simplify_context::simplify_unary_operation_1 (rtx_code code, machine_mode mode,
     target mode is the same as the variable's promotion.  */
       if (GET_CODE (op) == SUBREG
      && SUBREG_PROMOTED_VAR_P (op)
-	  && SUBREG_PROMOTED_SIGNED_P (op)
-	  && !paradoxical_subreg_p (mode, GET_MODE (SUBREG_REG (op))))
+	  && SUBREG_PROMOTED_SIGNED_P (op))
    {
-	  temp = rtl_hooks.gen_lowpart_no_emit (mode, SUBREG_REG (op));
-	  if (temp)
-	    return temp;
+	  rtx subreg = SUBREG_REG (op);
+	  machine_mode subreg_mode = GET_MODE (subreg);
+	  if (!paradoxical_subreg_p (mode, subreg_mode))
+	    {
+	      temp = rtl_hooks.gen_lowpart_no_emit (mode, subreg);
+	      if (temp)
+		{
+		  /* Preserve SUBREG_PROMOTED_VAR_P.  */
+		  if (partial_subreg_p (temp))
+		    {
+		      SUBREG_PROMOTED_VAR_P (temp) = 1;
+		      SUBREG_PROMOTED_SET (temp, 1);
+		    }
+		  return temp;
+		}
+	    }
+	  else
+	    /* Sign-extending a sign-extended subreg.  */
+	    return simplify_gen_unary (SIGN_EXTEND, mode,
+				       subreg, subreg_mode);
    }
/* (sign_extend:M (sign_extend:N <X>)) is (sign_extend:M <X>).
@@ -1631,12 +1647,28 @@ simplify_context::simplify_unary_operation_1 (rtx_code code, machine_mode mode,
     target mode is the same as the variable's promotion.  */
       if (GET_CODE (op) == SUBREG
      && SUBREG_PROMOTED_VAR_P (op)
-	  && SUBREG_PROMOTED_UNSIGNED_P (op)
-	  && !paradoxical_subreg_p (mode, GET_MODE (SUBREG_REG (op))))
+	  && SUBREG_PROMOTED_UNSIGNED_P (op))
    {
-	  temp = rtl_hooks.gen_lowpart_no_emit (mode, SUBREG_REG (op));
-	  if (temp)
-	    return temp;
+	  rtx subreg = SUBREG_REG (op);
+	  machine_mode subreg_mode = GET_MODE (subreg);
+	  if (!paradoxical_subreg_p (mode, subreg_mode))
+	    {
+	      temp = rtl_hooks.gen_lowpart_no_emit (mode, subreg);
+	      if (temp)
+		{
+		  /* Preserve SUBREG_PROMOTED_VAR_P.  */
+		  if (partial_subreg_p (temp))
+		    {
+		      SUBREG_PROMOTED_VAR_P (temp) = 1;
+		      SUBREG_PROMOTED_SET (temp, 0);
+		    }
+		  return temp;
+		}
+	    }
+	  else
+	    /* Zero-extending a zero-extended subreg.  */
+	    return simplify_gen_unary (ZERO_EXTEND, mode,
+				       subreg, subreg_mode);
    }
/* Extending a widening multiplication should be canonicalized to
</cut>

    