== Progress ==

* Zero/sign extension elimination (TCWG-15) (2/10) - Posted patch for comment

* benchmarking (TCWG-468) (1/10) - Ran a53 benchmarks

* regressions (7/10) - THUMB1 regression for ARM fenv * Issue due to thumb1 not supporting mrc/mcr. Patch to fix this is posted for review. - Regression when allocating 128bit integer to VFP register * When LRA assigns DImode value to TImode register, it is not setting up it in the right place of TImode. Due to this, one of the moves becomes dead. Patterns needs to be checked. * VFP registers store big-endian values in little-endian format. Hence, subreg for mode greater than word has to be aware of this. As it is, aarch64_cannot_change_mode_class will need the fix like done in ARM.

== Plan == * Benchmarking. * Upstream zero/sign extension elimination activities.