Note this patch can cause wrong code in some cases due to the load pair converting: ldr x0, [x0] ldr x1, [x0, 8] into ldp x0, x1, [x0].

I have a fixed up patch which combines what Naveen did and enhances it some more to handle reg-size,reg. I can provide a version if you want to start with my version.

It does not handle store pairs where one or both are zeros.

That is: void f(int a, int *b) { b[0] = 0; b[1] = a; } void f1(int a, int *b) { b[1] = 0; b[0] = a; }

It also does not handle vector modes, zero-extended or sign-extended SImode (LDPSW) loads.

It would be better if there was a pass which does the combing instead of the peepholes like: https://gcc.gnu.org/ml/gcc-patches/2014-05/msg01151.html

Thanks, Andrew Pinski ________________________________________ From: linaro-toolchain-bounces@lists.linaro.org linaro-toolchain-bounces@lists.linaro.org on behalf of Kugan kugan.vivekanandarajah@linaro.org Sent: Sunday, June 29, 2014 7:30 PM To: Michael Collison; linaro-toolchain@lists.linaro.org Subject: Re: [Weekly] 23-27 JUNE 2014

• Provide ldp/stp peephole optimization for Aarch64 [TCWG-446] [2/10]

In case you are not aware of, there was an earlier attempt for this and the patch was posted here: https://gcc.gnu.org/ml/gcc-patches/2013-03/msg01051.html

Thanks, Kugan

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