Hi there. Mounir and I have been looking at the work for next cycle. A summary spreadsheet with notes is available here: https://spreadsheets0.google.com/ccc?key=ty1c-H56f0GxnL1Hk9LCmRg
I'm very interested in feedback, especially on the time estimates and extra topics we should suggest to the TSC. See the notes at the top and feel free to add items or estimates straight into the sheet - anyone can view and anyone at Linaro should be able to edit.
-- Michael
Michael Hope michael.hope@linaro.org writes:
Hi there. Mounir and I have been looking at the work for next cycle. A summary spreadsheet with notes is available here: https://spreadsheets0.google.com/ccc?key=ty1c-H56f0GxnL1Hk9LCmRg
I'm very interested in feedback, especially on the time estimates and extra topics we should suggest to the TSC. See the notes at the top and feel free to add items or estimates straight into the sheet - anyone can view and anyone at Linaro should be able to edit.
For T1.4 (Better Intrinsics):
TBH, I'm hoping the work we've done for the May release will fix the known problems (or at least the problems known to me). The main patches were:
* Allowing RTL mode changes for values stored in VFP registers. Approved and applied upstream a while ago.
* Reworking the RTL representation of the built-in functions. This was approved and applied yesterday.
* Allowing arrays of vectors to have an RTL mode, and therefore be stored in registers. There seemed to be agreement in principle, although Richard Guenther understandably wanted to see the main vectoriser patches before giving a final verdict. I posted those patches yesterday.
The patch also exposed more instances of PR target/46329, so there was a fourth item:
* Fix PR target/46329. I submitted patches for this last week and pinged them yesterday.
It's really the last item that's stopping me from doing a merge request.
Of course, if anyone notices poor code even after these changes, we should fix that. I doubt it would take 1 month though.
Richard
On Wed, Apr 13, 2011 at 8:54 PM, Richard Sandiford richard.sandiford@linaro.org wrote:
Michael Hope michael.hope@linaro.org writes:
Hi there. Mounir and I have been looking at the work for next cycle. A summary spreadsheet with notes is available here: https://spreadsheets0.google.com/ccc?key=ty1c-H56f0GxnL1Hk9LCmRg
I'm very interested in feedback, especially on the time estimates and extra topics we should suggest to the TSC. See the notes at the top and feel free to add items or estimates straight into the sheet - anyone can view and anyone at Linaro should be able to edit.
For T1.4 (Better Intrinsics):
TBH, I'm hoping the work we've done for the May release will fix the known problems (or at least the problems known to me).
I haven't thought this one through so please correct me. My feeling is that we should promote NEON intrinsics over hand-written assembler as it's more maintainable, might perform better due to register allocation and scheduling, and is more portable across the Cortex-A* cores. To do this you need full access to all of the NEON instructions via intrinsics and they need to work well.
You patches should cover the 'work well'. I don't think we have full coverage as there are some instructions such as vld1.8 {d0,d1,d2,d3}, [rn] that are missing.
The proof would be to take some existing hand-written backends such as ffmpeg, do them in intrinsics, and have the code run as well or better.
-- Michael
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