The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2017.02 snapshot of both Linaro GCC 5 and Linaro GCC 6 source packages.

Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.3+svn245201 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the 2017.05 stable[2] quarterly release.

This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.02/

Interesting changes in this GCC source package snapshot include:

* Updates to GCC 6.3+svn245201 * Linaro BZ #2562: [PR target/78253] Call weak function instead of strong when called through pointer * Backport of [Bugfix] [AArch32] PR target/71270 Fix neon_valid_immediate for big-endian * Backport of [Bugfix] [AArch32] PR target/77439 Wrong code for sibcall with longcall, APCS frame and VFP * Backport of [Bugfix] [AArch32] PR target/78364 Add proper restrictions to zero and sign_extract patterns operands * Backport of [Bugfix] [AArch32] PR target/78694 Avoid invalid RTL sharing in minipool code * Backport of [Bugfix] [AArch32] PR target/79145 Fix xordi3 expander for immediate operands in iWMMXt * Backport of [Bugfix] [AArch64] PR target/78362 Make sure to only take REGNO of a register * Backport of [Bugfix] PR rtl-optimization/79121 Incorrect expansion of extend plus left shift * Backport of [AArch32] 1/2 Use generic_extra_costs in all remaining tuning structs * Backport of [AArch32] 2/2 Remove old rtx costs * Backport of [AArch32] arm_neon.h: Add artificial and gnu_inline * Backport of [AArch32] Improve Cortex-a53 integer scheduler * Backport of [AArch32] Improve Thumb allocation order * Backport of [AArch32] Merge negdi2 patterns * Backport of [AArch64] 1/2 Add bfx attribute * Backport of [AArch64] 2/2 Add bfx attribute * Backport of [AArch64] Fix bootstrap on aarch64-*-freebsd * Backport of [AArch64] Improve SHA1 scheduling * Backport of [AArch64] Purge leftover occurrences of aarch64_nopcrelative_literal_loads * Backport of [AArch64] Split X-reg UBFIZ into W-reg LSL when possible * Backport of [AArch64] Split X-reg UBFX into W-reg LSR when possible * Backport of [AArch64] Tweak Cortex-A57 vector cost * Backport of [Testsuite] [AArch64] PR target/77634 some vectorized testcases fail with -mcpu=thunderx * Backport of [Testsuite] [AArch64] PR target/77635 load/store pair testcases need to use -mcpu=generic * Backport of [Testsuite] Fix format string in AdvSIMD tests * Backport of [Testsuite] Require shared effective target for some lto.exp tests

Linaro GCC 5 monthly snapshot[1] is based on FSF GCC 5.4+svn245200 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the next maintenance release.

This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.4-2017.02/

Interesting changes in this GCC source package snapshot include:

* Updates to GCC 5.4+svn245200 * Linaro BZ #2785: PR target/66785 Internal compiler error in record_operand_use * Linaro BZ #2562: [PR target/78253] Call weak function instead of strong when called through pointer

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