Hi Andrew. gcc-4.7~svn183693 just finished running through the auto
builders and builds and tests in the ARM, Cortex-A9, i686, and x86_64
configurations.
You could base the Linaro 4.7 branch off that. It's r114897 in bzr
and, suitably, Sandra is the author.
-- Michael
For your records:
Loïc wrote a script that pushes the revisions from a GCC branch into
the current development focus. This makes branching on a shared
repository much faster. The script is here:
http://bazaar.launchpad.net/~linaro-toolchain-dev/cbuild/tools/view/head:/e…
and it runs daily on a cronjob as the cbuild user on the 'apus' EC2
instance (phew).
We'll need to update this when 4.7 comes along.
-- Michael
I've gone through the documentation on the wiki about how to get
going with KVM on Fast Models, to clean it up and reorganise it
and add some of the missing bits (notably how to set up a KVM
guest kernel and filesystem). It's now at:
https://wiki.linaro.org/PeterMaydell/KVM/HowTo
The only minor point I'd still like to address is that at the
moment we document the old-style "build your kernel and arguments
into an .axf file" boot-wrapper, because my changes to support
specifying them at model runtime haven't yet gone into the
boot-wrapper git repo. When they do land I'll update the wiki.
(Yes, technically TCWG2011-A15-KVM says "one page summary" but
I thought splitting it into four pages was much clearer :-))
-- PMM
Ken, Åsa: could you add a -O0 and -O1 build to the size and benchmark
results? I'm looking at the writeup and it would be interesting to
contrast the speed/size of -O0 with -O2.
Ta,
-- Michael
Continued work on 64-bit shifts in core registers. This has now been
posted to gcc-patches, and is awaiting review.
64-bit shifts in NEON are also working correctly, but the register
allocator chooses not to use them most of the time. I've begun trying to
work out why, but it's quite involved in ira-costs.c and will take some
unpicking, I think.
Attempted to create a Linaro GCC 4.7 branch, but my test build failed,
so that'll have to wait until it's stabilized a little.
Hi Marcin, Ricardo. How is the work on pre-built sysroots coming
along? I'd like to use/reference them in the next binary toolchain
release.
I'm looking for:
* Scripts that produce the sysroots
* A README that covers what they contain and how to reproduce them
* Test plan
* An official tagged branch holding the above
* A tarball release of the above
* A tarball release of the different sysroots
* Done in a way so they easily integrate with the binary builds[1]
and are useful to others as a sysroot
* Relocatable
* Usable on win32 and Linux
all hosted somewhere. Zhenqiang and I can test and give you feedback.
For reference, here's the README for the binary builds:
http://launchpadlibrarian.net/90998258/README.txt
Here's the simple script I used to make a libc only sysroot:
http://bazaar.launchpad.net/~linaro-toolchain-dev/crosstool-ng/linaro/view/…
I used chdist as I don't know multistrap. I guessed and added
build-dep support to download the build dependencies. It also fixes
up the absolute symlinks to relative.
-- Michael
[1] https://launchpad.net/linaro-toolchain-binaries
==Progress===
* Fixed PR48308 on FSF trunk. Needs backporting to FSF GCC 4.6 branch
* Fixed a number of failing testcases on trunk.
* Read up on Partial-partial PRE . Slow progress but getting a handle
on the theory now. A couple of approaches being benchmarked . Still
slow progress.
* Debugged Andrew's issues with 64 bit shifts. Nice that skype screen
sharing works well on Ubuntu.
* Started notes for Connect 2012.q1.
* Looked into the strd / strexd failure on the testcase in trunk.
Looked at a small patch to implement sync_lock_releasedi for ARM but
needs some more time and effort. Filed issue
https://bugs.launchpad.net/gcc-linaro/+bug/922474
=== Plans ===
* Finish 1x AFDS
* Continue with partial-partial PRE .
* Finish backport of fix for PR50313 to appropriate branches
* Start preparing for Connect 2012.q1
* Do something about the PGO and ABI patches next week.
Absences.
* Feb 6-10 : Linaro Connect Q1.12.
* Feb 13- 18 : Holiday.
Hi,
* libunwind
* reviewed small patch from T. R. of Nokia who provided a
bugfix in case unwind instructions are popping VFP registers
* exchanged mails with P. W. from Bosch who encountered a crash
in case DWARF info is involved
* OpenEmbedded
* changed Qt build to respect the optimization flags
* wrote a script around QEMU to measure the memory footprint
using named pipes to communicate with the serial console of the guest
* rebuilt the minimal, sato and qt4e images using the
gcc-linaro-arm-linux-gnueabi-2012.01-20120125_linux
(optimization levels: -O2, -O3 -fno-tree-vectorize and -O3)
* collected/updated the ELF size and memory footprint results:
*
https://docs.google.com/spreadsheet/ccc?key=0AmsCLxCMnnISdDNQSEM2ZHIxd3dVNj…
*
https://docs.google.com/spreadsheet/ccc?key=0AmsCLxCMnnISdHFtZll0OWdiTlhpdj…
* uploaded the image packs to: http://people.linaro.org/~kwerner/oe-core/
* prepared the environment to build the images using -O1
Regards,
Ken
== GDB ==
* Committed follow-on patch to fix cosmetic issues resulting from
the remote "info proc" patch set.
== GCC ==
* Created 4.6 backport branch including Richard's subreg forward-
propagation branch, the modes-tieable patch, and the combine.c
regression fix, and evaluated for correctness and performance.
Investigation of performance regressions uncovered a problem in
the register allocator: tied subregs (validly) cause somewhat
larger register pressure in certain cases, and this caused the
4.6 IRA to generate spills. Note that the 4.7 IRA is still
able to allocate every pseudo in the very same code; this is
a result of Vladmir's significant IRA rewrite in 4.7 ...
* Investigated Ramana's vld1 patches, and a problem with excessive
vmov's in the PR 51819 test case pointed out by Ramana. It turns
out that when we extract a lane from a vector to memory using an
offsetted address, we move the value through a core register
instead of simply computing the address and using vst1.
I'm working on a patch to address this.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
