Hi,
I have a few armv7 assembly tests. I'm trying to compile these using the linaro aarch64 toolchain and I'm getting errors.
Is there any specific flag that I have to pass to enable backward compatibility to allow v7 assembly to be compiled for a v8 model?
reset.s: Assembler messages:
reset.s:32: Error: operand 1 should be an integer register -- `mov r0,#0'
reset.s:33: Error: unknown mnemonic `mcr' -- `mcr p15,0,R0,C13,c0,1'
reset.s:36: Error: unknown mnemonic `mrc' -- `mrc p15,0,r0,c1,c0,0'
reset.s:40: Error: operand 1 should be a SIMD vector register -- `orr r0,r0,#0x00001000'
....
Relevant assembly code:
....
_reset:
// init Context ID Register
MOV r0, #0
MCR p15, 0, R0, C13, c0, 1
// Enable Instruction cache
mrc p15, 0, r0, c1, c0, 0
/* set bits:
12 = I i-cache
*/
orr r0, r0, #0x00001000
mcr p15, 0, r0, c1, c0, 0
.....
This is my assembler command: aarch64-linux-gnu-as -march=armv8-a+fp --keep-locals -o "reset.o" "reset.s"
Thanks,
Kalai
== Progress ==
* 64-bits ops in Neon: waiting for upstream.
* vectorizer cost model: initial activation with unaligned load/store
cost equal to aligned ones; benchmarking shows no significant
difference.
* smin-umin: a few benchmarks show a few unexpected regressions (10-15%).
* setting up spec2k on local board
* tcpanda heat problems: GCC built OK. Don't know how hot it became.
== Next ==
* handle 64-bits bitops in Neon feedback from upstream if any.
* analyze regressions in smin-umin
* check if more tuning of the vectorizer cost model is desirable.
* finish local board setup
* tcpanda: run gcc testsuite to check heat
== Progress ==
* Boehm GC AArch64 support:
- Tested on Foundation model
- Patches sent to mailing list
- Boehm GC has been accepted and merged into mainline
- Libatomic_ops under review, some improvements are needed.
== Next ==
* Boehm GC AArch64 support:
- Fix libatomic_ops for mainline merge
* Start gc sections support for AArch64 binutils
* Review roster
Summary:
* Investigate Automotive benchmark performance on different branch cost.
Details:
1. Automotive benchmark performance analysis for different branch cost
on Pardaboard ES.
* Design small test cases to simulate bitmnp01 to compare the
performance between ITTT and conditional branch. Test results show
- If branch prediction does not work (put the codes in a
function), ITTT is always better than conditional branch.
- If branch prediction works (inline the codes t in the loop
body), for most cases, conditional branch is better than ITTT.
* Code alignment has big impact for tblook01. By default IT block
has better performance. When adding __attribute__((aligned (16))) for
function t_run_test, performance of conditional branch is better than
IT block.
2. Prepare Linaro toolchain binary release.
* Update Linaro crosstool-ng local patches due to the fix of
lp:1067766 in source package.
* Spawn all builds and smoke tests.
Plan:
* Investigate SPEC2k performance for different branch costs.
* Work with Bero for 2013.01 toolchain binary release .
Planed leaves:
* Feb. 9 - 15: Chinese Spring Festival.
Best Regards!
-Zhenqiang
== Progress ==
* Buildbot
- Taking buildbot to Linaro
- Had wireless/GPU overheating, disabled kernel modules
- Running smooth again (most of the time)
- Debugging errors that only appear on ARM.
* Building and Testing LLVM
- Compiling on Intel with only the ARM backend helps a lot
- Sent a call for Action to people clean up cross-compilation failures
* LAVA
- Progress on LAVA LLVM job
- Got it checking out, configuring and building
- Got PASS/FAIL/SKIP patterns working
- https://validation.linaro.org/lava-server/scheduler/job/46027
- Need to get a patch from a specific place to apply
* Cost Model
- Re-wrote table lookup patch a few times, finally in for good
- http://llvm.org/viewvc/llvm-project?rev=173382&view=rev
- Studying costs of instructions, all seem good enough
- Better approach now is to change the target description (less code, more
gain)
* EuroLLVM
- 136 people so far
== Plan ==
* Test distcc (or similar) on Pandas
* Get a buildbot running with cross-compilation
* Internal git repository for LAVA LLVM job
* Confirm Linaro's sponsorship for EuroLLVM
* Continue cost model changes in between
== Background ==
* Monitor list for ARM changes
* Monitor buildbot for failures
Activity:
* calls and meetings (about 20% of my working week this week ;-))
* finished rebasing and testing the KVM QEMU patches (thanks
to Pawel for getting me an updated RTSM device tree), sent
out updated version to go with -v17 kernel
* minor qemu maintenance patches (including a minor cfi01
flash model bugfix)
* trying to track down issues running a 3.8-rc4 vexpress
kernel on QEMU. Among other things:
* looks like we need to emulate some more of the oscillator
and voltage config registers now (if only to make the
kernel a bit quieter)
* the kernel doesn't like the way qemu's boot loader puts
the DTB blob after the initrd but beginning in the same
page as the initrd ends [free_initrd_mem will trash memory
outside the initrd proper but inside that last page]
* a15 reports the wrong board model number
-- PMM
Dear All,
Is it possible to compile ARCH "AArch64 " for 32 mode, like if I have
x86 64 bit machine and I install 32 bit OS on it, and machine is
compatible with 32 bit binary.
So is it possible to use AARCH64 (Cortex-V8) with installation of
kernel 32 bit and use 32 bit tool chain.
If answer is yes, can I build tool chain or is there option available
in linaro cross-compile available from
https://launchpad.net/linaro-toolchain-binaries/+milestone/2012.12
Thanks
Activity:
* usual set of calls and meetings (and there is another
KVM related weekly meeting in the pipeline...)
* reviewed virtio patches
* rebased qemu-linaro on upstream
* rebased KVM patches; couldn't get updated kernel to run
on RTSM (probably a device tree or config issue; need to
attack problem again this week)
NB: I'm currently working a reduced set of hours due to RSI,
though I am trying to remain responsive to email etc.
-- PMM
== Progress ==
* Prepared Venkat on-boarding.
* Aarch64 porting meeting:
- libunwind is in the pipe
* Boehm GC AArch64 support:
- basic port done, test on-going
== Next ==
* Boehm GC AArch64 support:
- test and ask for up stream review.
Summary:
* Investigate automotive benchmark.
* Linaro gcc 4.6 release
Details:
1. Automotive benchmark performance analysis for different branch cost
for Cortex-A9.
* Debug function WriteOut, which is called 12 times on average,
leads common performance issue since the IF-THEN in the function is
converted to IT block, which TRUE probability is less than 4%.
* Identify the root cause of performance regression with IT block
for bitmnp01, rspeed01, pntrch01 and ttsprk01. Overall,
- The performance of a taken bpl is better than an ITTT. If this
is a common sense, for IF-THEN, we'd set branch-cost to 1.
- For IF-THEN-ELSE, we'd take branch probability into account when
converting it to IT block.
- ifcvt might generate useless IT block.
2. Try to do Linaro GCC release. But meet several issues:
* Can not branch a clean lp:gcc-linaro/4.7. As a workaround, I had
downloaded a clean bzr tree from other site. For next release, I can
use the local tree to create the release tarball.
* All a9hf-builder ubutests fail due to test environment issue.
Plan:
* Investigate more benchmarks for different branch costs.
Planed leaves:
* Feb. 9 - 15: Chinese Spring Festival.
Best Regards!
-Zhenqiang
