Hi,
I have being trying to persuade gcc to generate the ldp instruction without success. I have tried many combinations, below is an example.
--- cut here ---
#define LDP(x,y,p) { \
struct vec { long x, y; } data; \
data = *(struct vec *)p; p += 2; \
x = data.x; y = data.y; \
}
long testp(long *p) {
long x, y;
LDP(x, y, p);
return x+y;
}
--- cut here ---
$ gcc --version
gcc (GCC) 4.9.1
Copyright (C) 2014 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
$ gcc -S -O3 ldp.c
$ cat ldp.s
.cpu generic+fp+simd
.file "ldp.c"
.text
.align 2
.global testp
.type testp, %function
testp:
ldr x1, [x0,8] ;; why not ldp?????
ldr x0, [x0]
add x0, x1, x0
ret
.size testp, .-testp
.ident "GCC: (GNU) 4.9.1"
What can I do do make it generate ldp?
Ed.
== Progress ==
Bug triage [2/10]
Bug 1199 analysis [4/10]
reproduced, studied IRA dumps for a while, will have to report this upstream
Backports + BackFLiP enhancement [3/10]
Misc [1/10]
meetings, git training presentation, mailing lists
== Plans ==
benchmark 2015.02 release
more bugs
== Progress ==
LLDB development
-- Some code sniffing and created JIRA cards with some task estimation [2/10]
-- Trying AArch64 cross build and update howto [1/10]
-- Trying Arm cross build and update howto [2/10]
GDB patch updates and test cases for ARM record-replay instruction
recording [4/10]
Miscellaneous [1/10]
-- 96board with custom kernel no success with getting ethernet
working on it yet
== Plan ==
Wind up all pending gdb patches
== Issue ==
* none
== Progress ==
* Release and Backports (6/10)
- Supported backporting activity
- Added new feature to Backflip
- Discussed redefinition of release/maintenance policy
* Misc (4/10)
- Various meetings
- Catch up with mails
- Updated GCC release process in collaborate
- HiKey
== Plan ==
* Release and backport support
== This week ==
Short week - 3 days. Took Sat, Sun off due to health issues, severe
ear infection -:(
* Modularization project
a) TCWG-637: Applied TLC to parser in include-remove tool
b) TCWG-621: Began refactoring rtl.h
c) TCWG-628.
* TCWG-619:
- Started going through LTO documentation.
* Bugs
1178: Found a possible fix, prevents the ICE for the test-case.
== Next week ==
* TCWG-619
* Submit fix to 1178 upstream
* TCWG-628
== This week ==
* GCC Modularization project
- TCWG-621: Refactoring rtl.h almost completed.
- TCWG-639: Working on rewriting the tool in python.
- TCWG-637: Working on basing the tool on rtags instead of ctags.
- TCWG-629: Continue target-hook conversion.
* Backports:
- Submitted following backports for review:
r215612, r215722, r219656, r219657, r219659, r219661
== Issues ==
- Building chromium dependencies.
- Cannot log in to NX session on tcwg-env-05.
== Next Week ==
- Chromium LTO build (TCWG-619)
- Validate and commit backports.
== Progress ==
* compiler-pass to widen computation (TCWG-547) - (7/10)
- ran into -std=gnu90 issue in compiling spec2k/2006 with the trunk
using the new infrastructure
- ran benchmarking but the results are not much different
- tried with -save-temps but the intermediates are gone. Not sure if
infrastructure cleans it
- setting up spec2k in nx aarch64 chroot for easy comparison of
intermediate values (asm and tree dumps)
- also plan to try benchmarking with widening pass enabled only for
unsigned type where BIT_AND_EXPR (zero_extend) is optimized well as
compared to new middle-end ZEXT_EXPR (which is not handled well yet) to
see if the difference is there.
* Improve register allocation for AArch64 (TCWG-620) - (1/10)
- Looked at the relevant patches and code
* https://bugs.linaro.org/show_bug.cgi?id=1291 (1/10)
* Misc (1/10)
== Plan ==
* TCWG-620 and TCWG-547
* https://bugs.linaro.org/show_bug.cgi?id=1291
